Channel anomaly detection method and system adapted for chisel environment

Abstract

The application relates to a channel anomaly detection method and system suitable for a Chisel environment. The method comprises the following steps: obtaining a target Chisel source code file, tracking and marking the compiling behavior of the target Chisel source code file based on the integrated anomaly existing after integration, obtaining a channel marker Chisel source path related to the channel anomaly after tracking and marking, integrating and marking the compiling process of the communication anomaly signal based on the generated channel marker Chisel source path, obtaining a corresponding channel detection marker path after marking, performing anomaly signal source analysis and tracking based on the channel detection marker path, generating anomaly signal source marker information after analysis and tracking, and detecting and processing the anomaly signal source marker information by using an integration tool. The application can effectively realize detection of channel anomaly in a bus protocol and improve the reliability of channel anomaly detection.

Description

TECHNICAL FIELD

[0001] The application relates to a channel anomaly detection method and system, in particular to a channel anomaly detection method and system suitable for a Chisel environment. BACKGROUND

[0002] Chisel (Constructed Hardware in Scala Embedded Language) is a Scala library used for constructing high-level, synthesizable, modular hardware design, which allows designers to define the behavior of hardware at a high level and then converts it into low-level Verilog code or VHDL code through a series of conversion steps, which enables designers to focus on implementing the functionality of hardware without worrying about the underlying details; the Chisel environment has the following characteristics:

[0003] 1) High-level abstraction: the Chisel environment allows developers to use high-level Scala language features to describe hardware circuits, which makes the hardware design process more flexible and easy to maintain. Through high-level abstraction, designers can think and work at a higher level without worrying too much about the underlying details.

[0004] 2) Reusability: the Chisel environment supports modular design, which means that hardware circuits can be broken down into multiple reusable modules, which not only improves code reuse, but also enhances design scalability, making it more efficient when building complex systems.

[0005] 3) Static type checking: the Chisel environment performs static type checking at compile time, which helps developers find potential errors at an early stage, which can significantly improve development efficiency and code quality, reducing the workload of later debugging and modification.

[0006] 4) Verilog code generation: the Chisel environment can convert high-level hardware descriptions into corresponding Verilog code, providing convenience for subsequent synthesis and layout, which makes the Chisel environment a bridge between high-level abstraction and actual hardware implementation.

[0007] Scala language has many features suitable for describing circuits, such as being a static language, compiler-based, suitable for converting to Verilog code / VHDL code; and features such as operators, currying, pure object-oriented, powerful pattern matching, convenient generic programming, trait mixing, functional programming, etc. make it easy to develop DSL with Scala language.

[0008] For the circuit described by Scala language, the Chisel file can be converted into firrtl file by firrtl compiler, which is a standard intermediate exchange format, that is, a medium for various high-level languages to be conveniently converted into Verilog code / VHDL code, but it actually belongs to the same level as verilog code / VHDL code. Here, the Chisel environment chooses to compromise and does not directly generate the circuit, but relies on Verilog.

[0009] In the process of converting the Chisel file into the Verilog code, some non-synthesizable syntax is not used, so when writing the Chisel file, there is no need to worry about the inability to generate the circuit, which is extremely convenient for hardware beginners. For example, the reg of the Verilog code does not necessarily refer to the register, which is often misunderstood by beginners, and the Reg in the Chisel environment is the register, which has no ambiguity. Finally, by using the pattern matching, trait mixing and class inheritance of Scala language, the circuit structure can be quickly changed.

[0010] From the above description, it can be seen that in the whole process of converting the Chisel file into the Verilog code, if the syntax differences and optimization process are not familiar, ambiguities and communication exceptions often occur, especially for relatively complex bus protocols, and how to effectively detect the abnormal channel in the bus protocol is a technical problem that needs to be solved urgently. SUMMARY

[0011] The purpose of the present application is to overcome the deficiencies in the prior art, and provide a channel exception detection method and system suitable for Chisel environment, which can effectively detect the channel exception in the bus protocol and improve the ability and reliability of channel exception detection.

[0012] According to the technical scheme provided by the present application, a channel exception detection method suitable for Chisel environment is used to detect the channel exception of the target Chisel source code file whose source code syntax check state is normal source code but has synthesis exception after synthesis, wherein the target Chisel source code file includes a bus protocol designed in the Chisel environment, and the synthesis exception after synthesis at least includes a channel exception existing in the bus protocol.

[0013] When the channel exception detection is performed, the following steps are included:

[0014] The target Chisel source code file is obtained, and the compilation behavior of the target Chisel source code file based on the synthesis exception found after synthesis is tracked and marked, so as to obtain the channel marker Chisel source file related to the channel exception after tracking and marking.

[0015] The generated channel marking Chisel source path is used to integrate and mark the compiling process of the communication abnormal signal, so that a corresponding channel detection marking path is obtained after marking, wherein the channel detection marking path includes a communication path contained in a target bus protocol, and the target bus protocol is a bus protocol in which the channel abnormality occurs;

[0016] Based on the above-mentioned channel detection marking path, abnormal signal source analysis and tracking are performed to generate abnormal signal source marking information after analysis and tracking, wherein the abnormal signal source marking information includes a probe marking signal and a communication link corresponding to the probe marking signal;

[0017] The above-mentioned abnormal signal source marking information is detected and processed by using a synthesis tool, wherein when the abnormal signal source marking information is detected and processed, at least a channel comparison is performed between the probe marking signal and the marking original signal corresponding to the probe marking signal, and the abnormal state of the probe marking signal is determined according to the comparison result, and the abnormal state of the probe marking signal includes abnormality or non-abnormality.

[0018] When the compiling behavior of the target Chisel source code file is tracked and marked based on the synthesis abnormality found after synthesis, it includes:

[0019] The target Chisel source code file is compiled to generate a target fir format file after compilation;

[0020] Based on the synthesis abnormality found after synthesis, the Chisel source path related to the synthesis abnormality is marked in the target fir format file to generate a channel marking Chisel source path after marking.

[0021] When the compiling process of the communication abnormal signal is integrated and marked for the generated channel marking Chisel source path, it includes:

[0022] Based on the channel abnormality in the synthesis abnormality, a target bus protocol corresponding to the channel abnormality is determined in the target Chisel source code file;

[0023] In the target Chisel source code file, the integrated path corresponding to the target bus protocol of each channel marking Chisel source path is determined, and the determined integrated path is marked to generate a channel detection marking path after marking.

[0024] When the abnormal signal source analysis and tracking are performed based on the channel detection marking path, it includes:

[0025] A Chisel probe is added to each channel detection marking path in the target Chisel source code file;

[0026] A probe driving signal is loaded to the Chisel probe, and a path output signal under the probe driving signal is captured, when the captured path output signal is inconsistent with the probe driving signal, an abnormal signal source mark is marked to the channel detection mark path, and abnormal signal source mark information is generated after the abnormal signal source mark.

[0027] When the abnormal state of the probe mark signal is non-abnormal, the position of the Chisel probe is adjusted, and the abnormal signal source mark information is regenerated;

[0028] The regenerated abnormal signal source mark information is detected by using a synthesis tool to determine the abnormal state of the probe mark signal in the currently regenerated abnormal signal source mark information.

[0029] When the abnormal signal source mark information is detected by using the synthesis tool, it includes:

[0030] The channel mark Chisel source path where the abnormal signal source mark information is located is converted by using the synthesis tool, to convert and generate the corresponding gate level form channel Chisel source path;

[0031] In the converted gate level form channel Chisel source path, the probe mark signal is compared with the mark original signal corresponding to the probe mark signal, wherein when the probe mark signal is consistent with the mark original signal, the abnormal state of the probe mark signal is non-abnormal, otherwise, the abnormal state of the probe mark signal is abnormal.

[0032] The synthesis tool includes a vivado tool, a synopsys tool or a Cadence tool;

[0033] In the gate level form channel Chisel source path, the signal name of the probe mark signal is different from the signal name of the mark original signal;

[0034] When the probe mark signal and the mark original signal are compared, the comparison method includes signal value and / or signal bit width.

[0035] When the target Chisel source code file is detected by using the source code syntax detection, the source code syntax detection state further includes that the source code normal function result is consistent, wherein,

[0036] When the source code syntax detection state is that the source code normal function result is consistent, the target Chisel source code file is checked by using a tool flow detection method, and when the tool flow detection method is executed, the syntax usage abnormality existing in the target Chisel source code file is checked, wherein,

[0037] The tool flow detection method comprises sbt compiler checking step, Treadle interpreter checking step and waveform viewer checking step in sequence, wherein,

[0038] When the sbt compiler checking step is executed, consistency checking is performed on the library file used by the target Chisel source code file, the sbt compiler and / or the version of the compilation environment, and when the sbt compiler checking step passes, the Treadle interpreter checking step is executed;

[0039] When the Treadle interpreter checking step is executed, fir format file to waveform file generated in the compilation process of the target Chisel source code file is checked, and when the Treadle interpreter checking step passes, the waveform viewer checking step is executed;

[0040] When the waveform viewer checking step is executed, the waveform viewer checking is performed.

[0041] When there is a synthesis exception after the synthesis of the target Chisel source code file, at least the synthesized logic circuit generated based on the target Chisel source code file is inconsistent with the expected logic function of the target Chisel source code file, and / or the waveform file obtained by simulating the synthesized logic circuit is inconsistent with the waveform file obtained by simulating the target Chisel source code file, wherein,

[0042] When the channel exception is a signal setting exception, the channel exception comprises bit width exception and / or connection exception.

[0043] A channel exception detection system suitable for Chisel environment comprises a channel exception detection terminal, wherein for any target Chisel source code file whose source code syntax checking state is source code normal but communication exception, the channel exception detection terminal performs channel exception detection by using the channel exception detection described above.

[0044] The present application has the advantages that: the target Chisel source code file whose source code syntax checking state is source code normal but has a synthesis exception after synthesis is subjected to channel exception detection, and the compilation behavior tracking mark, integrated channel confirmation mark, abnormal signal source analysis tracking and synthesis tool detection processing are performed in sequence to determine the channel exception in the bus protocol for detection, thereby improving the ability and reliability of channel exception detection. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 It is an embodiment flowchart of the channel exception detection of the present application.

[0046] Figure 2 It is an embodiment flowchart of the channel exception detection of the present application.

[0047] Figure 3 An embodiment flowchart for generating a bit stream file from processing a Chisel source code file. DETAILED DESCRIPTION

[0048] The application will be further described below in conjunction with specific drawings and embodiments.

[0049] In order to effectively realize the detection of channel abnormalities in the bus protocol and improve the ability and reliability of channel abnormality detection, the application provides a channel abnormality detection method suitable for a Chisel environment. Specifically, the method is used for channel abnormality detection on a target Chisel source code file whose syntax checking state is normal but which has a comprehensive abnormality after synthesis, wherein the target Chisel source code file includes a bus protocol designed in a Chisel environment, and the comprehensive abnormality after synthesis at least includes a channel abnormality existing in the bus protocol.

[0050] When performing channel abnormality detection, the following steps are included:

[0051] Step S1, the target Chisel source code file is obtained, and the compilation behavior of the target Chisel source code file based on the comprehensive abnormality after synthesis is tracked and marked to obtain a channel marked Chisel source path related to the channel abnormality after tracking and marking;

[0052] Step S2, the generated channel marked Chisel source path is integrated with the communication abnormality signal to confirm and mark the communication path, to obtain a corresponding channel detection marked path after marking, wherein the channel detection marked path includes a communication path included in a target bus protocol, and the target bus protocol is a bus protocol having a channel abnormality;

[0053] Step S3, based on the channel detection marked path, abnormal signal source analysis tracking is performed to generate abnormal signal source marked information after analysis and tracking, wherein the abnormal signal source marked information includes a probe marked signal and a communication link corresponding to the probe marked signal;

[0054] Step S4, the abnormal signal source marked information is detected and processed by using a synthesis tool, wherein when the abnormal signal source marked information is detected and processed, at least a channel comparison is performed between the probe marked signal and a marked original signal corresponding to the probe marked signal, and an abnormal state of the probe marked signal is determined according to a comparison result, wherein the abnormal state of the probe marked signal includes abnormality or non-abnormality.

[0055] It should be noted that the Chisel environment specifically refers to the Chisel language environment mentioned in the background art, and the Chisel source code file required can be designed and generated under the Chisel environment, and the Chisel source code file can be converted into corresponding low-level Verilog code or VHDL code; specifically, the process of designing and generating the Chisel source code file and converting it into Verilog code or VHDL code can be consistent with the prior art, and will not be repeated here. The channel anomaly detection of the application specifically refers to checking and confirming the existence of an abnormal channel in the Chisel source code file, therefore, the target Chisel source code file is the Chisel source code file to be subjected to channel anomaly detection. It should be noted that the abnormal channel can include at least one transmission signal path anomaly, or at least one transmission signal path exists a signal setting anomaly.

[0056] The target Chisel source code file of the application specifically refers to a Chisel source code file whose source code syntax checking state should be normal, but which has a synthesis anomaly after synthesis, wherein the normal source code specifically refers to the case that there is no syntax ambiguity or incorrect usage in the target Chisel source code file, that is, the target Chisel source code file has no syntax anomaly. In an embodiment of the application, the synthesis anomaly after synthesis at least includes that the synthesized logic circuit generated based on the target Chisel source code file is inconsistent with the expected logic function of the target Chisel source code file, and / or the waveform file obtained by simulating the synthesized logic circuit is inconsistent with the waveform file obtained by simulating the target Chisel source code file, that is, when the synthesized logic circuit is inconsistent with the expected logic function and / or the waveform file, it should be considered that there is a synthesis anomaly. As can be seen, the normal source code but the synthesis anomaly after synthesis specifically refers to the case that the state of the target Chisel source code file is no error in the source code, but the function is incorrect, wherein the incorrect function specifically refers to the case that the function of the current logic circuit is inconsistent with the expected circuit function.

[0057] In a specific implementation, the logic circuit refers to automatically converting a high-level description source code file into a corresponding logic gate circuit by using a computer-aided logic synthesis tool, that is, forming a complete functional circuit by tool conversion; the waveform file shows high and low level changes and is used to understand the timing logic of a signal. For a certain target Chisel source code file, the corresponding logic circuit and waveform file can be generated by using the prior art, and the relationship between the logic circuit and the code logic and the waveform file can be determined, that is, the manner and means for judging the synthesis exception after synthesis can be consistent with the prior art, for example, the data, handshake and other signals in the communication process (here, the high and low levels of the signals can be shown as 1 and 0) can be used to judge whether they are consistent with the expected result, if not, it is an exception, otherwise, it is a non-exception.

[0058] From the above description, it can be known that, for the target Chisel source code file, before the channel exception detection, the source code syntax checking and the exception judgment after synthesis should be performed. It should be noted that the Chisel source code file can generate synthesizable Verilog code, the main principle is to call the special sacla library of chisel3, and the entry of the Scala program is the main function. Therefore, the program for generating Verilog code needs to instantiate the module to be compiled in the main function, and then run the main function, and the instantiation of the module to be compiled needs a special method call, mainly using the singleton object Driver in the library, which contains a method execute and accepts two parameters for calling.

[0059] Based on the above principle of generating synthesizable Verilog code from the Chisel source code file, the person skilled in the art can obtain that if there is an incorrect call or incorrect parameter setting in the Chisel source code file, in most cases, the Verilog code cannot be generated, and if the Verilog code is generated, there will be a serious warning, but if the warning is ignored and the code function is directly verified, an exception phenomenon of correct source code and incorrect function will be obtained (this phenomenon can also occur in other scenes), therefore, the source code syntax checking of the Chisel source code file is extremely important.

[0060] In an embodiment of the present application, when the source code syntax detection state of the target Chisel source code file is correct, the source code syntax detection state further includes a correct function result consistent with the source code, wherein,

[0061] When the source code syntax detection state is a correct function result consistent with the source code, the target Chisel source code file is checked by using a tool stream detection method, and when the tool stream detection method is executed, the syntax usage exception existing in the target Chisel source code file is checked, wherein,

[0062] The tool flow detection method comprises sbt compiler checking step, Treadle interpreter checking step and waveform viewer checking step in sequence, wherein,

[0063] When the sbt compiler checking step is executed, consistency checking is performed on the library file used by the target Chisel source code file, the sbt compiler and / or the version of the compilation environment, and when the sbt compiler checking step passes, the Treadle interpreter checking step is executed;

[0064] When the Treadle interpreter checking step is executed, fir format file to waveform file generated in the compilation process of the target Chisel source code file is checked, and when the Treadle interpreter checking step passes, the waveform viewer checking step is executed;

[0065] When the waveform viewer checking step is executed, the waveform viewer checking is performed.

[0066] Specifically, when the source code syntax detection state is normal source code and the function result is consistent, the general tool flow detection method can be used for anomaly detection, Figure 2 An embodiment of the tool flow detection method is shown in FIG. 1, and it can be seen from the figure that the tool flow detection method mainly comprises sbt compiler checking step, Treadle interpreter checking step and waveform viewer checking.

[0067] It should be noted that the function result consistent means that the source code function is consistent with the expected function result, which is specifically manifested as follows: for the source code of communication function, certain communication signals can be obtained (whether correct or not); for the source code of calculation function, certain calculation results can be given (whether correct or not). When the source code syntax detection is performed on the target Chisel source code file, the syntax of the target Chisel source code file and whether the version of the compilation tool is correct are mainly checked, and if there is an error in the compilation process of the target Chisel source code file, the tool flow detection method can be used for detection. It can be seen that the function result consistent generally means that the expected reply function (and the source code type) is consistent, and it is not strictly required to be completely consistent.

[0068] The sbt compiler checking mainly aims at the sbt compiler, the library file used by the sbt compiler and / or the version of the sbt compiler. Figure 1The shown scala file to fir intermediate file process, that is, the sbt compiler of Scala generates Java class files *.class, that is, bytecode files based on Chisel, Scala library, and Chisel driver executes the bytecode file to generate FIRRTL (Flexible Intermediate Representation for RTL, that is, the variable intermediate representation of RTL) file *.fir. The main sbt compiler check is performed by tools such as compilers, and the main check is the consistency of the *.lib library file, the sbt compiler, and the version of the compilation environment. During the detection process, if the sbt compiler and / or the compilation environment version is inconsistent, log information can be output. The Treadle interpreter detection mainly aims at the *.fir intermediate file to *.vcd process, which can be used for debugging and testing Chisel source code files in cooperation with the Chisel tester. According to the output assertion information, the test result can be obtained. The Treadle interpreter can also generate a waveform file, that is, Hello.vcd, which can be viewed by a waveform viewer, such as GTKWare or Modelsim. When viewed by a waveform viewer, it can be determined whether the final result is completely consistent, that is, the source of the channel error can be tracked through the waveform.

[0069] Specifically, the Treadle interpreter is a prior art, and the Treadle interpreter is a FIRRTL interpreter for simulating circuits. The Treadle interpreter can be used together with the Chisel Tester for debugging and testing Chisel source code files. Specifically, when the Treadle interpreter is used for inspection, there are various forms of inspection, which can be selected to directly output waveform results or only output log information. The specific selection can be made according to the needs, and will not be enumerated and described here.

[0070] In specific implementation, the target Chisel source code file should also include a bus protocol, which can be designed and formed in the Chisel environment by using existing common technical means. The bus protocol in the target Chisel source code file can be one or more, which is related to the function of the logic circuit formed based on the Chisel source code file. When the bus protocol exists in the target Chisel source code file, there is a synthesis exception, and the channel exception including the bus protocol can be included. When the channel exception is a signal setting exception, the channel exception includes a bit width exception and / or a connection exception.

[0071] Figure 1An embodiment flow chart of the present application for channel anomaly detection is shown in the figure, in which, when performing channel anomaly detection, the compilation behavior of the target Chisel source code file needs to be tracked and marked first, wherein the compilation behavior of the target Chisel source code file generally refers to the compilation behavior of the target Chisel source code file to the fir format file, and at this time, one or more channel marked Chisel source paths can be obtained. The way of obtaining the channel anomaly related channel marked Chisel source path after tracking and marking is described in detail below.

[0072] In an embodiment of the present application, when generating the channel marked Chisel source path, it includes:

[0073] Compiling the target Chisel source code file to obtain the target fir format file generated after the compiled target Chisel source code file;

[0074] Based on the synthesis anomaly found after synthesis, the Chisel source path related to the synthesis anomaly in the target fir format file is marked to generate a channel marked Chisel source path after marking.

[0075] Specifically, the target Chisel source code file is generally a scala format file, such as Hello.scala in Figure 3 which is a Chisel source code file. The target Chisel source code file can be compiled in a manner commonly used in the technical field to generate a target fir format file after compilation, and the target fir format file is a fir format file, Figure 3 Hello.fir in Figure 3 is the target fir format file, Figure 3 Hello is the file name. In addition, Figure 3 In , the rectangular box refers to the compilation environment or software tool, such as scalac, Chisel JVM, Chisel Tester JVM, FIRRTL JVM and other JVMs (Java Virtual Machine), the cylindrical box refers to the library file, such as chisel3.lib and scala.lib, which refers to the library file used during compilation, the flat top and wavy bottom box refers to the specific file name, named Hello.+ various suffixes to indicate file types, and the arrow refers to various interaction relationships, Figure 3 In , the process of processing the Chisel source code file to generate the bit stream file is consistent with the prior art, and specific reference can be made to and the above description, which will not be repeated here.

[0076] As can be known from the above description, after the target Chisel source file is synthesized, the logic circuit can be generated, and the synthesis exception can be found based on the generated logic circuit, so that the synthesis exception can be determined in advance when the channel exception detection is performed. Then, the Chisel source path related to the synthesis exception can be marked in the target fir format file based on the determined channel exception, so that the channel marked Chisel source path can be generated after the marking. It should be noted that the process of marking the channel marked Chisel source path, that is, the corresponding Figure 2 fir source path in Figure 3 is the reverse tracking of the target Chisel source file in

[0077] It should be noted that the code logic of the fir format file is completely consistent with the code logic of the target Chisel source file, the fir format file includes a large number of intermediate variable declarations, and the corresponding intermediate variable declarations are annotated to indicate the corresponding Chisel source path. The Chisel source path is the Chisel module in the target Chisel source file, so that the Chisel source path related to the channel exception can be determined from the intermediate variable declaration for the determined channel exception, and the channel marked Chisel source path can be generated after the tracking and marking. Specifically, when the channel exception is tracked, the source and running process of the abnormal signal of the channel exception can be tracked, so that the Chisel source path related to the channel exception can be determined. Then, the Chisel source path corresponding to the channel exception can be marked by using the existing common method. The abnormal tracking and the marking method after the tracking can be consistent with the prior art, for example, the marking can be performed by using the annotation, and the marking method can be selected as needed, which will not be described here.

[0078] As can be known from Figure 1 , after the channel marked Chisel source path is generated, the integration path confirmation and marking of the communication exception signal compilation process are still required, so that the corresponding channel detection marked path can be obtained after the marking. Specifically, the steps of generating the channel detection marked path correspond to the integration path confirmation steps in Figure 2 . The method and process of the integration path confirmation and the generation of the channel detection marked path will be described in detail below.

[0079] In an embodiment of the present application, when the channel detection marked path is generated, the following steps are included:

[0080] Based on the channel exception in the synthesis exception, the target bus protocol corresponding to the channel exception is determined in the target Chisel source file;

[0081] In the target Chisel source file, determine the integrated path of each channel marker Chisel source path corresponding to the target bus protocol, and mark the determined integrated path to generate a channel detection marker path after marking.

[0082] As can be seen from the above description, there is one or more bus protocols in the target Chisel source file, and the target bus protocol is a protocol in the target Chisel source file, that is, the target protocol file is a bus protocol that may have a channel exception. Since the comprehensive exception condition can be determined in advance, the corresponding bus protocol can be determined according to the determined comprehensive exception condition by using the commonly used manner in the technical field, and thus the target bus protocol in the target Chisel source file can be determined.

[0083] After determining the target protocol file and the channel marker Chisel source path, the integrated path of each channel marker Chisel source path corresponding to the target bus protocol can be determined, that is, the path of the channel marker Chisel source path in the target bus protocol or the engineering integration. In specific implementation, when generating the channel detection marker path, a feasible way is to mark all the paths of the channel marker Chisel source path in the target bus protocol or the engineering integration. It should be noted that engineering integration generally refers to a relationship tree between similar files, which is used to determine the functional interconnection relationship between source codes to reflect the interaction and influence between source codes. The engineering integration condition is consistent with the existing one, and thus the commonly used technical means in the technical field can be used to mark all the paths of the engineering integration.

[0084] It should be noted that after obtaining the channel detection marker path, the abnormal signal source analysis can be performed based on the channel detection marker path to generate abnormal signal source marker information. Specifically, in an embodiment of the present application, when generating the abnormal signal source marker information, it includes:

[0085] In the target Chisel source file, a Chisel probe is added to each channel detection marker path;

[0086] A probe driving signal is loaded to the Chisel probe, and a path output signal under the probe driving signal is captured. When the captured path output signal is inconsistent with the probe driving signal, the channel detection marker path is marked as an abnormal signal source, and the abnormal signal source marker information is generated after the abnormal signal source is marked.

[0087] Specifically, when the Chisel probe is added to generate the abnormal signal source marker information, that is, Figure 2corresponding to the adding Chisel probe step in the target Chisel source file, the Chisel probe can be added in a manner commonly used in the technical field, wherein the process of adding the Chisel probe is to insert the code for capturing the signal, and the added code is used to capture the operation of detecting the signal; generally, after adding the Chisel probe, a driving signal different from the original driving signal needs to be loaded to the channel detection mark path through the Chisel probe, the added driving signal is the probe driving signal, and thereafter, the output of the current probe driving signal is captured to obtain the path output signal.

[0088] In specific implementation, the path output signal is inconsistent with the probe driving signal, specifically, the path output signal is inconsistent with the expected output under the driving of the probe driving signal, and the path output signal can be captured in a manner commonly used at present, such as using the REG type and D flip-flop delay that can be probed by a synthesis tool to capture the signal, so as to capture the path output signal. Specifically, the commonly used synthesis tools include Design Compiler of Synopsys Company, RTLComplier of Cadence Company, RTL Blaster of Magma Company, etc., and the type of the synthesis tool can be selected according to the need.

[0089] It can be understood that the manner of capturing the path output signal by using the synthesis tool should be related to the used synthesis tool and Chisel environment, for example, in a waveform file, the suspicious signal at a certain time point can be saved by adding a new REG to regenerate a new waveform file, and the path output signal and the probe driving signal are observed in the generated waveform file; for example, when the synthesis tool uses vivado, the ip of ila can be added in the verilog generated by compiling (the corresponding signal relationship in the chisel source code and the verilog file needs to be clear) to realize the observation of the path output signal and the probe driving signal; for example, the data signal of the result and the handshake signal for a long time can be observed by any tool for observing specific levels.

[0090] It should be noted that the logic circuit synthesized by the synthesis tool is optimized and close to the real logic circuit, and the possible abnormal signal source is marked using the observable Chisel probe, and the corresponding channel mark Chisel source path on each channel detection mark path is uniformly marked, so that the process of abnormal signal generation and the communication link are marked. It can be understood that the logic circuit synthesized by the synthesis tool is generally very close to the final logic circuit, but there may be slight differences, such as process differences from the real flow piece. Specifically, uniform marking, specifically referring to marking records or uniformly recording (annotating or other recording methods) abnormal signal source marks with a tool, and then connecting these uniform records into an error communication link according to the results, thereby generating abnormal signal source mark information.

[0091] By Figure 1 It can be known that after obtaining the abnormal signal source mark information, the synthesis tool can be used to detect and process the above-mentioned abnormal signal source mark information. In an embodiment of the present application, when the synthesis tool is used to detect and process the abnormal signal source mark information, it includes:

[0092] The channel mark Chisel source path where the abnormal signal source mark information is located is converted by using the synthesis tool to convert and generate the corresponding gate-level form channel Chisel source path;

[0093] In the gate-level form channel Chisel source path converted and generated, the probe mark signal is compared with the mark original signal corresponding to the probe mark signal, wherein when the probe mark signal is consistent with the mark original signal, the abnormal state of the probe mark signal is non-abnormal, otherwise, the abnormal state of the probe mark signal is abnormal.

[0094] Specifically, the synthesis tool can adopt the existing common form, such as the synthesis tool can be a vivado tool, a synopsys tool or a Cadence tool. The module described at the behavior level is automatically converted into a gate-level form pattern by the logic netlist through the synthesis tool, that is, the gate-level form channel Chisel source path can be obtained. At this time, translation, logic optimization and gate-level mapping are realized, and the generated module can correspond to the basic elements of a certain process one by one, so it can reflect the final implemented logic circuit better than the target fir format file and the verilog file.

[0095] After the conversion to form the gate-level form channel Chisel source path, the probe mark signal can be renamed in the synthesis tool, that is, in the gate-level form channel Chisel source path, the signal name of the probe mark signal is different from the signal name of the mark original signal; therefore, the probe mark signal and the mark original signal corresponding to the probe mark signal can be better compared and changed, and the channel comparison mode includes signal value and / or signal bit width. When comparing, the result in the synthesis tool can be observed, when the probe mark signal is consistent with the mark original signal, the abnormal state of the probe mark signal is non-abnormal, otherwise, the abnormal state of the probe mark signal is abnormal; wherein the probe mark signal is consistent with the mark original signal, specifically, the signal value and the signal bit width are consistent.

[0096] In an embodiment of the application, when the abnormal state of the probe mark signal is non-abnormal, the position of the Chisel probe is adjusted, and the abnormal signal source mark information is regenerated;

[0097] The regenerated abnormal signal source mark information is detected and processed by the synthesis tool to determine the abnormal state of the probe mark signal in the current regenerated abnormal signal source mark information.

[0098] It can be understood that when the abnormal state of the probe mark signal is non-abnormal, it indicates that the current probe mark signal is not an abnormal signal, and the position of the Chisel probe needs to be adjusted, and the abnormal signal source mark information is regenerated in the above-mentioned manner, and then the synthesis tool is used for detection and processing, as shown in Figure 2 As shown in the figure, during implementation, there is a cycle of synthesis tool detection and Chisel probe adding steps, and the cycle ends when it is found that the abnormal state of the probe mark signal is abnormal, or after adjusting the Chisel probe, the abnormal state of all probe mark signals is non-abnormal.

[0099] The channel abnormality detection method of the application will be described in detail below with reference to specific embodiments.

[0100] For a Chisel source code file with an axi bus protocol, the bit width of two signals changes during synthesis, and the fir format file and the verilog code are normal. In addition, since the axi bus protocol can be normally used in other modules, the general tool flow detection method cannot find the bit width change of the abnormal signal (the bit width change is exchanged through different modules, such as a5 bit b12 bit in this module, and a12 bit b7 bit in the next module), wherein the axi bus protocol can be normally used in other modules, specifically, the source code of the other modules has a normal use function after integration and interconnection.

[0101] TheFigure 2 And the above detection method, after adding Chisel probe signal, it is found that another clock domain crossing processing signal is also changed in the help of integrated tool, finally the reason of communication abnormality is detected that the clock crossing processing requirement in Chisel source file is inconsistent, specifically, another clock domain crossing processing signal, specifically refers to a part of signal of axi bus in Chisel source file needs to pass through another clock domain crossing processing. In addition, the channel abnormality detection method of the application can find that the corresponding probe mark signal is deliberately added through the detection of tilelink bus protocol and wishbone protocol, that is, the effectiveness of the probe mark signal can be determined.

[0102] From the above description, a channel abnormality detection system suitable for Chisel environment can be obtained, specifically comprising a channel abnormality detection terminal, wherein for any pair of source code syntax check state is normal source code but communication abnormality target Chisel source file, the channel abnormality detection terminal adopts the above-mentioned channel abnormality detection to detect channel abnormality.

[0103] Specifically, the channel abnormality detection terminal can be a commonly used computer device, and the Chisel environment should be installed in the channel abnormality detection terminal, and the detection of channel abnormality is realized by using the above-mentioned method. The method and process of channel abnormality detection can refer to the above description, which will not be repeated here.

Claims

1. A method for detecting channel anomalies suitable for a Chisel environment, characterized in that, The application relates to a channel exception detection method for a target Chisel source code file with a source code syntax checking state of normal source code but with a comprehensive exception after comprehensive processing, wherein the target Chisel source code file comprises a bus protocol designed in a Chisel environment, and the comprehensive exception after the comprehensive processing at least comprises a channel exception existing in the bus protocol. The method comprises the following steps: acquiring the target Chisel source code file and tracking and marking a compiling behavior of the target Chisel source code file based on the comprehensive exception existing after the comprehensive processing to obtain a channel marked Chisel source path related to the channel exception after the tracking and marking; integrating and marking a compiling process of a communication exception signal based on the generated channel marked Chisel source path to obtain a corresponding channel detection marked path after the marking, wherein the channel detection marked path comprises a communication path of a target bus protocol, and the target bus protocol is a bus protocol with the channel exception; performing abnormal signal source analysis and tracking based on the channel detection marked path to generate abnormal signal source marked information after the analysis and tracking, wherein the abnormal signal source marked information comprises a probe marked signal and a communication link corresponding to the probe marked signal; detecting and processing the abnormal signal source marked information by using a comprehensive tool, wherein the detection and processing of the abnormal signal source marked information comprises at least a channel comparison between the probe marked signal and a marked original signal corresponding to the probe marked signal, and an abnormal state of the probe marked signal is determined according to a comparison result, wherein the abnormal state of the probe marked signal comprises an exception or a non-exception.

2. The channel anomaly detection method suitable for Chisel environment according to claim 1, characterized in that, The method comprises the following steps: compiling the target Chisel source code file to generate a target fir format file after the compiling; marking a Chisel source path related to the comprehensive exception in the target fir format file based on the comprehensive exception existing after the comprehensive processing to generate the channel marked Chisel source path after the marking.

3. The method of claim 1, wherein the method is adapted for a Chisel environment. The method comprises the following steps: determining a target bus protocol corresponding to the channel exception in the target Chisel source code file based on the channel exception in the comprehensive exception; determining an integrated path corresponding to the target bus protocol of each channel marked Chisel source path in the target Chisel source code file and marking the determined integrated path to generate the channel detection marked path after the marking.

4. The method of channel anomaly detection suitable for Chisel environment according to claim 1, characterized in that, The method comprises the following steps: adding a Chisel probe to each channel detection marked path in the target Chisel source code file. A probe driving signal is loaded to the Chisel probe, and a path output signal under the probe driving signal is captured, when the captured path output signal is inconsistent with the probe driving signal, an abnormal signal source mark is marked to the channel detection mark path, and abnormal signal source mark information is generated after the abnormal signal source mark.

5. The method of channel anomaly detection suitable for Chisel environment according to claim 4, characterized in that, When the abnormal state of the probe mark signal is non-abnormal, the position of the Chisel probe is adjusted, and the abnormal signal source mark information is regenerated; The regenerated abnormal signal source mark information is detected by using a synthesis tool to determine the abnormal state of the probe mark signal in the currently regenerated abnormal signal source mark information.

6. The method for detecting channel anomalies suitable for Chisel environment according to any one of claims 1 to 5, characterized in that, When the abnormal signal source mark information is detected by using the synthesis tool, it includes: The channel mark Chisel source path where the abnormal signal source mark information is located is converted by using the synthesis tool to convert and generate the corresponding gate level form channel Chisel source path; In the converted gate level form channel Chisel source path, the probe mark signal is compared with the mark original signal corresponding to the probe mark signal, wherein when the probe mark signal is consistent with the mark original signal, the abnormal state of the probe mark signal is non-abnormal, otherwise, the abnormal state of the probe mark signal is abnormal.

7. The method of channel anomaly detection suitable for Chisel environment according to claim 6, characterized in that, The synthesis tool includes a vivado tool, a synopsys tool or a Cadence tool; In the gate level form channel Chisel source path, the signal name of the probe mark signal is different from the signal name of the mark original signal; When the channel comparison is performed between the probe mark signal and the mark original signal, the channel comparison mode includes signal value and / or signal bit width.

8. The method of channel anomaly detection suitable for Chisel environment according to any one of claims 1 to 5, characterized in that, When the source code syntax detection state is consistent with the normal function result of the source code, the target Chisel source code file is checked by using a tool flow detection method, and when the tool flow detection method is executed, the syntax usage abnormality existing in the target Chisel source code file is checked, wherein The tool flow detection method includes sbt compiler checking step, Treadle interpreter checking step and waveform viewer checking step in sequence, wherein When the sbt compiler checking step is executed, the consistency of the library file used by the target Chisel source code file, the sbt compiler and / or the compilation environment version is checked, and when the sbt compiler checking step passes, the Treadle interpreter checking step is executed; When the Treadle interpreter checking step is executed, the fir format file generated in the compilation process of the target Chisel source code file to the waveform file is checked, and after the Treadle interpreter checking step passes, the waveform viewer checking is executed; When the waveform viewer checking is executed, the waveform viewer checking is executed. ​ 9. The method of channel anomaly detection suitable for Chisel environment according to any one of claims 1 to 5, characterized in that, When a synthesis exception exists after the target Chisel source code file is synthesized, at least including that the synthesized logic circuit generated based on the target Chisel source code file is inconsistent with the logical function expected by the target Chisel source code file, and / or the waveform file obtained by simulating the synthesized logic circuit is inconsistent with the waveform file obtained by simulating the target Chisel source code file, wherein, When the channel exception is a signal setting exception, the channel exception includes a bit width exception and / or a connection exception.

10. A channel anomaly detection system adapted for a Chisel environment, characterized in that, The channel exception detection terminal includes the channel exception detection of any one of claims 1-9, wherein, for any target Chisel source code file whose source code syntax check state is source code normal but communication exception, the channel exception detection terminal performs channel exception detection.

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