USB measurement and control system collaborative verification platform building method based on System Verilog in combination with C language
The collaborative verification platform combining System Verilog and C language solves the problems of low efficiency and poor flexibility in FPGA verification, and realizes efficient and flexible USB telemetry and control system verification, which is suitable for spacecraft telemetry and control communication systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-10
- Publication Date
- 2026-03-13
AI Technical Summary
Existing FPGA verification methods suffer from problems such as cumbersome processes, poor flexibility, low efficiency, high cost, and poor debugging visibility, making it difficult to meet the high reliability and real-time requirements of spacecraft telemetry and communication systems.
A collaborative verification platform based on System Verilog and C language is adopted, and a hierarchical tree topology architecture is constructed, including an RTL design layer, a TB test platform layer, and a verification test case set. Signal generation and simulation are realized through mixed programming of System Verilog interface files and C language, supporting parameterized real-time signal generation and dynamic fast response.
It improves verification efficiency and debugging convenience, reduces configuration complexity, and achieves efficient and flexible FPGA verification. It is highly adaptable and suitable for different models of USB measurement and control systems.
Smart Images
Figure CN121659863A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of FPGA testing technology, and in particular to a method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language. Background Technology
[0002] With the continuous development of my country's deep space exploration, higher requirements are being placed on the reliability and real-time performance of spacecraft telemetry, tracking, and command (TT&C) systems. The Unified S-band (USB) TT&C system, as a core component for realizing remote control, telemetry, and ranging functions between space and ground, typically uses FPGAs for its baseband processing. Therefore, the implementation and simulation verification of the USB baseband processing FPGA functions and performance are particularly important.
[0003] In FPGA verification methods, traditional simulation verification techniques have obvious limitations: MATLAB-based pre-generated signal methods can achieve high-precision signal modeling, but suffer from cumbersome processes, poor flexibility, and efficiency bottlenecks caused by file throughput; UVM verification methodology has the advantage of automation, but its steep learning curve and heavy environment setup costs make it difficult to deploy quickly, and it lacks efficient reusability; formal verification can achieve exhaustive testing, but it is prone to state space explosion problems for complex data processing units; physical board-level testing, as the final verification method, is limited by inherent defects such as long iteration cycles, poor debugging visibility, and high hardware costs. Summary of the Invention
[0004] This application addresses the aforementioned problems and aims to provide a method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language, thereby resolving the issues raised in the background section. To achieve the above objectives, the present invention provides the following technical solution: a method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language. The method constructs a hierarchical tree-topology verification platform based on the Cadence IES simulation environment. This verification platform is independent of the design engineering file under test and adopts a three-level architecture, including: RTL design layer: Stores the source code files of the baseband processing FPGA of the USB test and control system under test, which is described using register transfer level; The tb test platform layer adopts a modular design, including a dut_if interface definition module, a dut_wrap design and encapsulation module, a tb test control module, and a tb_top top-level integration module. The dut_if interface definition module implements standardized encapsulation of the top-level signals of the DUT through System Verilog interface files. The dut_wrap design and encapsulation module realizes the instantiation of the top-level design. The tb test control module coordinates the SV driver files of each peripheral interface. The tb_top top-level integration module completes the structured interconnection of each component. Verification test case set: includes library configuration file, flow control file, test case file and module driver file. The module driver file adopts a mixed programming architecture of System Verilog and C language, and realizes cross-language co-simulation by calling C functions through import declarations in SV modules.
[0005] Furthermore, the module driver files in the tb test platform layer include ad_mod, clk_mod, and fp_mod, wherein: The ad_mod module generates an intermediate frequency signal source for the USB measurement and control system by calling the C module. The clk_mod function generates the clock signal. The fp_mod function enables the printing of demodulation results and data comparison.
[0006] Furthermore, the process of generating an intermediate frequency signal source using ad_mod includes the following steps: Parameter initialization phase: Configure AD sampling frequency, symbol bit width, main carrier frequency, remote control subcarrier parameters, remote control code rate, and ranging tone characteristic parameters; Frequency synthesis control stage: Based on the principle of direct digital frequency synthesis, the frequency control words corresponding to the main carrier, remote control subcarrier and ranging tone are calculated. The frequency control words are calculated by the formula ∆=2³²×fc / fs, where fc is the main carrier frequency and fs is the sampling rate. Multi-domain signal synthesis stage: Call the C language modulation program to modulate the BPSK modulated subcarrier and the configurable ranging tone component onto the phase domain of the main carrier to generate a composite PM signal; Signal post-processing stage: Amplitude normalization and dynamic range adjustment are performed on the synthesized signal; Timing alignment stage: Generate an enable signal sequence synchronized with the AD sampling clock; Signal injection stage: The digital intermediate frequency signal is transmitted to the input terminal of the DUT according to the AD interface protocol.
[0007] Furthermore, the implementation process of the method includes: Verification environment initialization configuration: Automatically scan and extract RTL level code, identify the library resources required for simulation, and establish a simulation library mapping relationship in the library configuration file corresponding to the target device model and development environment version; Layered testing platform architecture construction: Automatically generate dut_if interface definition files and dut_wrap encapsulation files, build dedicated test cases in tb test control files, and complete system integration through tb_top top-level files; In-depth development of the excitation model: Based on the specification documents, a simulation model of the peripheral interface is constructed, and the intermediate frequency signal source is generated by ad_mod; Real-time waveform diagnostic analysis: Monitor the time-domain characteristics and integrity indicators of signals using a simulation tool such as a waveform viewer.
[0008] Furthermore, the verification platform implements dynamic testing in multiple scenarios through a set of verification test cases, including primary carrier lock verification, remote control subcarrier lock verification, bit synchronization verification, code stream output verification, ranging tone energy detection and forwarding verification, loss-of-lock recapture verification, modulation error tolerance testing, remote control code rate adaptability testing, and Doppler frequency shift impact testing.
[0009] Furthermore, the reacquisition verification includes: simulating primary carrier acquisition loss and tracking loss by setting Doppler frequency shift error and its rate of change error scenarios, or setting subcarrier frequency abnormality scenarios, to verify the DUT's reacquisition capability after the communication link returns to normal.
[0010] Furthermore, the library configuration file is cds.lib, and the flow control file is run.f. The flow control file is responsible for coordinating RTL code compilation, test stimulus compilation, and coverage collection configuration.
[0011] Furthermore, the remote control interface of the design under test conforms to the three-wire serial port standard, including remote control interface clock, data and gating signal, the gating signal being driven by a bit synchronization lock flag.
[0012] Compared with existing technologies, this invention has the following advantages: it breaks through the limitations of traditional methods by collaboratively constructing a real-time interaction channel between the System Verilog testing framework and the C language algorithm module. This retains the flexibility of C language in implementing complex algorithms while leveraging the advantages of System Verilog in hardware modeling and test process control. This collaborative architecture platform supports parameterized real-time signal generation, enabling the verification process to have dynamic and rapid response capabilities. Simultaneously, the collaboratively constructed real-time interaction channel between the System Verilog testing framework and the C language algorithm module provides complete signal visibility for online debugging, significantly improving verification efficiency and debugging convenience. It provides a verification solution for complex digital systems such as USB measurement and control systems that combines high efficiency, flexibility, and maintainability. The automated scripting system enables intelligent generation of the verification environment, significantly reducing configuration complexity. Its parameterized configuration mechanism allows for rapid adaptation to different USB telemetry and control systems, demonstrating excellent adaptability. Based on a hybrid architecture of SystemVerilog and C, it combines the accuracy of hardware timing modeling with the flexibility of advanced algorithms, effectively overcoming the rigidity of traditional MATLAB methods while avoiding the long development cycles of pure hardware test platforms. This provides an efficient and reliable verification solution for the aerospace telemetry and control field. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments of this drawing or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this drawing. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0014] Figure 1 This is the verification tree for the USB measurement and control system of the present invention; Figure 2 This is a diagram of the collaborative simulation verification platform architecture for the USB measurement and control system of the present invention. Figure 3 This is a step diagram of the collaborative simulation verification platform for the USB measurement and control system of the present invention; Figure 4 This is a waveform diagram of the intermediate frequency signal source of the present invention; Figure 5 The following are waveforms of the simulation results for subcarrier locking, bit locking, and master carrier locking in this invention; Figure 6 The following are detailed waveform diagrams of the simulation results for subcarrier locking, bit locking, and master carrier locking in this invention; Figure 7 This is a simulation waveform diagram of the Doppler frequency offset of this invention; Figure 8 This is a simulation waveform diagram of the recapture after lock-off in this invention.
[0015] The purpose, features, and advantages of this accompanying drawing will be further explained in conjunction with the embodiments and with reference to the accompanying drawing. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following description and illustration are provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.
[0017] Obviously, the following description is merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios without any inventive effort. Furthermore, it is understood that although the effort involved in such development may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.
[0018] Unless otherwise specified, the terms "comprising" and "including" as used in this application can be open-ended or closed-ended. For example, "comprising" and "including" can mean that other components not listed may also be included, or that only the listed components may be included.
[0019] The technical solution of this invention is: a method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language. The core research and development goal of this invention is to verify the demodulation function and performance of the FPGA baseband processing of the USB measurement and control system. In the process of functional verification for this type of FPGA Design Under Test (DUT), the main technical difficulty lies in how to adaptively configure and generate the intermediate frequency excitation signal source according to the corresponding modulation scheme.
[0020] Therefore, the collaborative simulation verification platform of this invention runs in the Cadence IES (Incisive Enterprise Simulator) simulation environment. The simulation platform is independent of the design engineering file under test and is constructed using a hierarchical tree topology architecture, such as... Figure 1 As shown, it is characterized by the following hierarchical structure.
[0021] The verification architecture is based on the sim module. Through a strict hierarchical connection relationship, it realizes the separation and control of test incentives and design responses, and provides infrastructure support for the rapid iteration of verification test cases and the systematic improvement of coverage. Its feature is that it adopts a three-level architecture to realize the entire systematic verification.
[0022] 1) RTL design layer: contains the hardware description of the design under test using register transfer level description, constitutes the main test module of the verification target, and stores the basic source code file of the design under test (.v or .vhd). 2) tb Test Platform Layer: As the foundational support for the verification architecture, it is built using a modular design concept. Its core components include the following four key components and auxiliary driving units: a. dut_if interface definition module: Implemented through the System Verilog interface file dut_if.sv, it uses an interface structure to standardize and encapsulate the top-level signals of the DUT, establishing a standardized channel for signal transmission.
[0023] b. dut_wrap design encapsulation module: The top-level design is instantiated through the dut_wrap.sv file, which builds a physical connection bridge between the test environment and the design under test, ensuring the correct mapping of signal paths.
[0024] c. tb test control module: Implements the instantiation and scheduling of test cases in tb.sv, is responsible for coordinating the SV driver files connecting various external interfaces, and realizes unified management of multiple test incentive modes.
[0025] d. tb_top top-level integration module: The system-level integration is completed through tb_top.sv, which interconnects components such as interface definition, design instantiation, and stimulus driving in a structured manner to build a complete verification environment framework.
[0026] 3) Verification Test Case Set: As the core trunk of the verification tree, it has good scalability and can flexibly expand the verification scenarios according to actual verification needs. Based on this trunk, functional module branches (mod) and underlying component leaves (cds.lib, run.f, testcase.sv) are further derived, while the SV driver file simulating the external interface of the design under test serves as the terminal leaf of the mod branch, thus completing the construction of the complete verification tree.
[0027] The structure of the leaves in each underlying component is as follows: a. Library configuration file (cds.lib): As the basic environment configuration file, its contents strictly correspond to the specific development environment version and target device model. This invention can automatically generate it through the development environment to ensure the consistency between the verification environment and the design environment.
[0028] b. Process Control File (run.f): Serving as the central hub for the verification process, this file establishes a complete working environment by systematically importing RTL design code, test stimulus components, and related library files. It oversees the compilation process, including RTL code compilation and test stimulus compilation, and configures quality assurance mechanisms such as coverage collection.
[0029] c. Test case file (testcase.sv): As the specific implementation of the verification scenario, it instantiates the SV driver file that connects all external interfaces and precisely specifies the execution order and interaction method of each driver component, thereby achieving targeted verification of different functional characteristics and performance indicators.
[0030] d. Module Driver Files (mods): As a key terminal component of the verification tree, these SV driver files need to accurately simulate the behavior of external modules interacting with the device under test, according to interface timing parameters, positional relationships, data flow, etc. For this USB measurement and control system verification platform, an innovative hybrid programming co-simulation architecture of System Verilog and C languages is adopted: the SV module is responsible for interface protocol implementation and simulation flow control, while the C language sub-module focuses on completing low-level algorithm calculations such as carrier modulation. Cross-language co-simulation is achieved by calling C functions through import declarations in the SV module, ultimately constructing a complete verification system capable of generating compliant intermediate frequency signal data in real time. Its specific architecture is shown in Figure 2.
[0031] The USB measurement and control system co-simulation verification platform can automatically calculate the corresponding carrier control word based on the set phase 1, phase 2, ..., phasen, and phasecode using the following formula:
[0032] Combination Figure 1 and Figure 2 ad_mod generates the signal source for the USB measurement and control system by calling the c module, clk_mod generates the clock signal, and fp_mod prints the demodulation results and compares the data, thus enabling the construction of a verification platform for the USB measurement and control system.
[0033] The intermediate frequency signal generated according to the above process, while adhering to the corresponding AD interface timing specifications, serves as the key signal source excitation for the entire USB measurement and control system co-simulation verification platform, and is applied to the design under test (DUT). The receiving module is responsible for processing the remote control data output by the DUT after demodulation. The remote control interface generally follows the three-wire serial port standard, consisting of a remote control interface clock, data, and a gating signal (driven by a bit synchronization lock flag). This module automatically records the interface remote control code data and compares it with the original code to determine the correctness of the DUT's remote control code demodulation function.
[0034] The implementation process follows the structured verification strategy shown in Figure 3, and the specific process is as follows.
[0035] 1) Verify the initial configuration of the environment This step automates the basic construction of the verification environment: First, it automatically scans and extracts the complete RTL-level code description from the design engineering of the device under test (DUT), intelligently identifying the cell and process library resources required for simulation. Then, the system automatically establishes a precise simulation library mapping relationship in the cds.lib configuration file, corresponding to the target device model and development environment version. This process ensures the consistency of the simulation environment configuration with the actual design environment through a built-in version matching engine, achieving optimal setting of environment parameters without manual intervention.
[0036] 2) Construction of Layered Testing Platform Architecture This step employs a construction strategy that combines automated generation with specialized design: the built-in parsing code automatically completes the standardized encapsulation of the dut_if interface definition file and the precise mapping of the dut_wrap encapsulation file, establishing a type-safe signal transmission channel and physical connection bridge; at the same time, for specific FPGA design characteristics, dedicated instantiated test cases are built in the tb test control file and verification correlations are established; finally, the system integration of each functional component is completed through the tb_top top-level file, forming a complete verification framework.
[0037] 3) In-depth development of incentive models Based on the requirements document, technical protocol, and chip manual of the FPGA design under test, a high-precision peripheral interface simulation model is constructed. Specifically, the AD modulation module (ad_mod) adopts the following multi-stage implementation scheme: a. Parameter initialization phase: Configure AD sampling frequency, define symbol bit width, and set basic system parameters such as main carrier frequency, remote control subcarrier parameters, remote control code rate, and ranging tone characteristics; b. Frequency synthesis control stage: Based on the principle of direct digital frequency synthesis, the frequency control words corresponding to the main carrier (phase1), remote control subcarrier (phase2), and ranging tone (phase3) are accurately calculated; c. Multi-domain signal synthesis stage: The C language modulation program is activated through a cross-language calling mechanism to accurately modulate the BPSK-modulated subcarrier and the configurable ranging tone component onto the phase domain of the main carrier, generating a standard-compliant composite PM signal; d. Signal post-processing stage: Amplitude normalization and dynamic range adjustment are performed on the synthesized signal to ensure that the signal characteristics are fully matched with the electrical specifications of the AD interface; e. Timing alignment stage: Generate an enable signal sequence that is strictly synchronized with the AD sampling clock to ensure the timing accuracy of data acquisition; f. Signal injection stage: The digital intermediate frequency signal is transmitted to the DUT input terminal through the verification platform according to the AD interface protocol specification; 4) Real-time waveform diagnostic analysis By using the waveform viewer of the integrated simulation tool, the time-domain characteristics of the bpsk_s signal are monitored in real time, with a focus on verifying its phase reversal characteristics and signal integrity indicators.
[0038] Once the collaborative verification platform described above is built, the project is complete. Figure 1 The topology shown is a complete USB measurement and control system verification tree, which can initiate the full system simulation process.
[0039] According to the scheme in Section 3.2, the platform implements the verification environment construction through an automated process: automatically scanning and extracting RTL code and identifying simulation library resources, and automatically creating a configuration in cds.lib that precisely matches the device model and development version. An architecture construction strategy combining automation and specialized design is adopted, automatically generating the dut_if interface definition and dut_wrap wrapper file to establish standardized signal channels; simultaneously, specific test cases are built in the tb test control file according to the characteristics of the specific FPGA design, and finally, system integration is completed through tb_top.
[0040] The AD modulation module (ad_mod) is implemented in stages: parameter initialization, configuring the AD sampling frequency, symbol width, and carrier parameters; then calculating the frequency control words for each component based on the DDS principle; finally, by calling the C modulation program across languages, the BPSK-modulated subcarrier and ranging tone are synthesized into the main carrier phase to generate a standard composite PM signal. The following details the entire process of parameter configuration, simulation, and results for the USB measurement and control system collaborative verification platform under three scenarios: basic carrier locking, superimposed Doppler frequency shift, and loss-of-lock reacquisition.
[0041] 1) Based on the system parameters shown in Table 1, this platform automatically completes the calculation and configuration of the DDS control word, realizes the parameterized generation of the signal source, and executes IES simulation to verify the subcarrier, bit locking and master carrier locking functions.
[0042]
[0043] The simulation results are shown in Figures 5 and 6. Around 12.8ms, the scarrier_detect_flag signal of the DUT is active low, achieving subcarrier locking. Around 164.635ms, the bit_lock1 and bit_lock2 signals are active low, achieving bit locking and outputting bpsk_s code stream data. Around 424ms, the mcarrier_lock_flag signal is active high, achieving master carrier locking.
[0044] 2) Based on the above verification, to test the dynamic frequency tracking performance of the system, an additional 460 kHz Doppler frequency shift was introduced. The frequency offset telemetry value in the demodulation results was observed to verify the platform's detection accuracy and response characteristics for a specific frequency shift. The simulation results are shown in Figure 7. A Doppler frequency shift error scenario was set in the verification platform. The simulation results show that the detection function of the uplink Doppler frequency offset telemetry signal is correctly implemented. Under the condition of limited simulation accuracy, the detected Doppler frequency offset signal up_doppler_tc fluctuates between 459 and 460.
[0045] 3) Building upon the subcarrier, bit locking, and primary carrier locking implementation in Scenario 1, the re-acquisition performance was tested by adjusting the uplink primary carrier frequency control word. The carrier frequency was first pulled outside the lock-out threshold and then restored to the normal Doppler frequency offset range to verify whether the DUT could re-acquire the carrier after lock-out during this process. The simulation results are shown in Figure 8. Using the platform settings to pull the subcarrier outside the lock-out threshold, the `scarrier_detect_flag` signal became invalid at high level around 612ms, resulting in subcarrier lock-out, which was re-acquired approximately 90ms later. Then, using the platform settings to pull the primary carrier outside the lock-out threshold, the `mcarrier_lock_flag` signal became invalid at low level around 1053ms, resulting in primary carrier lock-out, which was re-acquired approximately 420ms later. This meets the functional requirements and response time performance indicators for carrier re-acquisition in the communication link.
[0046] It should be noted that this application is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments with the same structure and effect as the technical concept within the scope of this application are included in the technical scope of this application. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of this application, are also included in the scope of this application.
Claims
1. A method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language, characterized in that: The method describes a verification platform based on a hierarchical tree topology architecture built using the Cadence IES simulation environment. This verification platform is independent of the design project file under test and employs a three-level architecture, including: RTL design layer: Stores the source code files of the baseband processing FPGA of the USB test and control system under test, described using register transfer level; The tb test platform layer adopts a modular design, including a dut_if interface definition module, a dut_wrap design and encapsulation module, a tb test control module, and a tb_top top-level integration module. The dut_if interface definition module implements standardized encapsulation of the DUT top-level signals through SystemVerilog interface files. The dut_wrap design and encapsulation module realizes the instantiation of the top-level design. The tb test control module coordinates the SV driver files of each peripheral interface. The tb_top top-level integration module completes the structured interconnection of each component. Verification test case set: includes library configuration file, flow control file, test case file and module driver file. The module driver file adopts a mixed programming architecture of System Verilog and C language, and realizes cross-language co-simulation by calling C functions through import declarations in SV modules.
2. The method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language according to claim 1, characterized in that: The module driver files in the tb test platform layer include ad_mod, clk_mod, and fp_mod, where: The ad_mod module generates an intermediate frequency signal source for the USB measurement and control system by calling the C module. The clk_mod function generates the clock signal. The fp_mod function enables the printing of demodulation results and data comparison.
3. The method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language according to claim 2, characterized in that: The process of generating an intermediate frequency signal source using ad_mod includes the following steps: Parameter initialization phase: Configure AD sampling frequency, symbol bit width, main carrier frequency, remote control subcarrier parameters, remote control code rate, and ranging tone characteristic parameters; Frequency synthesis control stage: Based on the principle of direct digital frequency synthesis, the frequency control words corresponding to the main carrier, remote control subcarrier and ranging tone are calculated. The frequency control words are calculated by the formula ∆=2³²×fc / fs, where fc is the main carrier frequency and fs is the sampling rate. Multi-domain signal synthesis stage: Call the C language modulation program to modulate the BPSK modulated subcarrier and the configurable ranging tone component onto the phase domain of the main carrier to generate a composite PM signal; Signal post-processing stage: Amplitude normalization and dynamic range adjustment are performed on the synthesized signal; Timing alignment stage: Generate an enable signal sequence synchronized with the AD sampling clock; Signal injection stage: The digital intermediate frequency signal is transmitted to the input terminal of the DUT according to the AD interface protocol.
4. The method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language according to claim 3, characterized in that: The implementation process of the method includes: Verification environment initialization configuration: Automatically scan and extract RTL level code, identify the library resources required for simulation, and establish a simulation library mapping relationship in the library configuration file corresponding to the target device model and development environment version; Layered testing platform architecture construction: Automatically generate dut_if interface definition files and dut_wrap encapsulation files, build dedicated test cases in tb test control files, and complete system integration through tb_top top-level files; In-depth development of the excitation model: Based on the specification documents, a simulation model of the peripheral interface is constructed, and the intermediate frequency signal source is generated by ad_mod; Real-time waveform diagnostic analysis: Monitor the time-domain characteristics and integrity indicators of signals using a simulation tool such as a waveform viewer.
5. The method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language according to claim 4, characterized in that: The verification platform enables dynamic testing across multiple scenarios through a set of verification test cases, including primary carrier lock verification, remote control subcarrier lock verification, bit synchronization verification, code stream output verification, ranging tone energy detection and forwarding verification, loss-of-lock recapture verification, modulation error tolerance testing, remote control code rate adaptability testing, and Doppler frequency shift impact testing.
6. The method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language according to claim 5, characterized in that: The reacquisition verification includes: simulating primary carrier acquisition loss and tracking loss by setting Doppler frequency shift error and its rate of change error scenarios, or setting subcarrier frequency abnormality scenarios to verify the DUT's reacquisition capability after the communication link returns to normal.
7. The method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language according to claim 6, characterized in that: The library configuration file is cds.lib, and the flow control file is run.f. The flow control file is responsible for coordinating RTL code compilation, test stimulus compilation, and coverage collection configuration.
8. The method for building a collaborative verification platform for a USB measurement and control system based on System Verilog and C language according to claim 7, characterized in that: The remote control interface of the design under test conforms to the three-wire serial port standard, including remote control interface clock, data and gating signal, and the gating signal is driven by bit synchronization lock flag.