Global shutter pixel and image sensor

Abstract

The invention discloses a global shutter pixel and an image sensor, and relates to the technical field of image sensors, and the global shutter pixel comprises a photosensitive unit, a transmission unit, a reset unit, a storage unit, and a differential unit. The light sensing unit is used for sensing light to generate charges; the transmission unit is used for transmitting the charges to a floating diffusion node when the transmission unit is conducted; the reset unit is used for resetting a global shutter pixel when the reset unit is switched on; the storage unit is used for storing voltage at the floating diffusion node, and the voltage at the floating diffusion node comprises reset voltage and signal voltage; and the differential unit is used for outputting a difference value between the reset voltage and the signal voltage. The global shutter pixel can reduce the power consumption of the image sensor and improve the frame rate of the image sensor.

Description

Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to a global shutter pixel and an image sensor. Background Art

[0002] A global shutter exposure camera is usually used for high-speed and high-frame-rate imaging. The global shutter camera exposes the entire pixel array at the same time and ends the exposure at the same time, and stores the reset voltage and the signal voltage, and then transmits the reset voltage and the signal voltage row by row or column by column to the peripheral circuit. The analog-to-digital converter is used in the peripheral circuit to convert the analog signal into a digital signal output, and finally the actual signal value is calculated. At present, image sensors mostly use SSADC (single-slope analog-to-digital converter) quantization. However, the current mainstream solution adopts a column ADC quantization mode, that is, each column of pixels shares an ADC quantization. In order to further improve the frame rate, several more sets of ADCs will be made, and multiple rows will be quantized at the same time, but this solution has limited improvement in frame rate, and is accompanied by an exponential increase in power consumption, chip area and cost. Therefore, how to reduce the power consumption of image sensors and improve the frame rate of image sensors has become a technical problem that needs to be solved urgently by technicians in this field. Summary of the invention

[0003] The purpose of the present application is to provide a global shutter pixel and an image sensor, which can reduce the power consumption of the image sensor and improve the frame rate of the image sensor.

[0004] In order to solve the above technical problems, the present application provides a global shutter pixel, comprising:

[0005] Photosensitive unit, transmission unit, reset unit, storage unit, differential unit;

[0006] The photosensitive unit is used to generate charges by sensing light;

[0007] The transmission unit is used to transmit the charge to the floating diffusion node when the transmission unit is turned on;

[0008] The reset unit is used to reset the global shutter pixel when the reset unit is turned on;

[0009] The storage unit is used to store the voltage at the floating diffusion node, and the voltage at the floating diffusion node includes a reset voltage and a signal voltage;

[0010] The differential unit is used to output the difference between the reset voltage and the signal voltage.

[0011] In some embodiments, the storage unit includes:

[0012] A first storage unit and a second storage unit; the first storage unit and the second storage unit are used to store one of a reset voltage and a signal voltage, and the types of voltages stored in the first storage unit and the second storage unit are different.

[0013] In some embodiments, the first storage unit is connected to the input end of the second storage unit and serves as the input end of the storage unit, the output end of the first storage unit is connected to one input end of the differential unit, and the output end of the second storage unit is connected to the other input end of the differential unit.

[0014] In some embodiments, the input end of the first storage unit serves as the input end of the storage unit, the output end of the first storage unit is connected to the input end of the second storage unit and one input end of the differential unit, and the output end of the second storage unit is connected to the other input end of the differential unit.

[0015] In some embodiments, the differential unit is controlled by a first control signal. When the first control signal is a first level signal, the differential unit outputs the difference between the reset voltage and the signal voltage; the transmission unit is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit is turned on; the reset unit is controlled by a third control signal. When the third control signal is a first level signal, the reset unit is turned on to connect the power supply connecting the floating diffusion node to the reset unit; the first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor of the first storage unit is connected to the input end of the first storage unit.

[0016] In some embodiments, in the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal and the fourth control signal are first level signals; in the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal and the fourth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal and the third control signal are second level signals, and the fourth control signal is a first level signal; in the signal voltage storage stage, the first control signal, the third control signal and the fourth control signal are second level signals, and the second control signal is a first level signal; in the output stage, the first control signal is a first level signal, and the second control signal, the third control signal and the fourth control signal are second level signals.

[0017] In some embodiments, it also includes:

[0018] The amplifying unit is used to amplify the voltage at the floating diffusion node and output the amplified voltage to the input end of the storage unit.

[0019] In some embodiments, the differential unit is controlled by a first control signal. When the first control signal is a first level signal, the differential unit outputs the difference between the reset voltage and the signal voltage. The transmission unit is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a third control signal. When the third control signal is a first level signal, the reset unit is turned on to connect the power supply connecting the floating diffusion node to the reset unit. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor of the first storage unit is connected to the floating diffusion node. The second storage unit is controlled by a fifth control signal. When the fifth control signal is a first level signal, the second capacitor of the second storage unit is connected to the input end of the second storage unit. The amplification unit is controlled by a sixth control signal. When the sixth control signal is a first level signal, the amplification unit amplifies the voltage at the floating diffusion node and outputs it to the input end of the storage unit.

[0020] In some embodiments, in the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal and the third control signal are second level signals, and the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the signal voltage storage stage, the first control signal, the third control signal and the fourth control signal are second level signals, and the second control signal, the fifth control signal and the sixth control signal are first level signals; in the output stage, the first control signal is a first level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are second level signals.

[0021] In some embodiments, in the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal and the third control signal are second level signals, and the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the signal voltage storage stage, the first control signal, the third control signal and the fifth control signal are second level signals, and the second control signal, the fourth control signal and the sixth control signal are first level signals; in the output stage, the first control signal is a first level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are second level signals.

[0022] In some embodiments, the differential unit comprises:

[0023] a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;

[0024] The first end of the first transistor serves as an input end of the differential unit, the second end of the first transistor is connected to the third end of the second transistor and the third end of the third transistor, the third end of the first transistor is connected to the third end of the fourth transistor, the first end of the second transistor serves as another input end of the differential unit, the second end of the second transistor is connected to the third end of the fifth transistor and serves as an output end of the differential unit, the first end of the third transistor is connected to the first control signal, the second end of the third transistor is grounded, the first end of the fourth transistor is connected to the third end of the fourth transistor and the first end of the fifth transistor, the second end of the fourth transistor is connected to a power supply, and the second end of the fifth transistor is connected to a power supply.

[0025] In some embodiments, the photosensitive unit includes:

[0026] A photosensitive diode; an anode of the photosensitive diode is grounded, and a cathode of the photosensitive diode is connected to the transmission unit.

[0027] In some embodiments, the transmission unit includes:

[0028] A sixth transistor; a first end of the sixth transistor is connected to the second control signal, a second end of the sixth transistor is connected to the photosensitive unit, and a third end of the sixth transistor is connected to the floating diffusion node.

[0029] In some embodiments, the resetting unit comprises:

[0030] a seventh transistor; a first terminal of the seventh transistor is connected to the third control signal, a second terminal of the seventh transistor is connected to the floating diffusion node, and a third terminal of the seventh transistor is connected to a power supply.

[0031] In some embodiments, the first storage unit includes:

[0032] an eighth transistor and a first capacitor; a first end of the eighth transistor is connected to the fourth control signal, a second end of the eighth transistor serves as an input end of the first storage unit, a third end of the eighth transistor is connected to the first end of the first capacitor and serves as an output end of the first storage unit, and the other end of the first capacitor is grounded.

[0033] In some embodiments, the second storage unit includes:

[0034] A second capacitor; a first end of the second capacitor serves as an input end and an output end of the second storage unit, and a second end of the second capacitor is grounded.

[0035] In some embodiments, the second storage unit further includes:

[0036] a ninth transistor; a first end of the ninth transistor being connected to the fifth control signal, a second end of the ninth transistor being connected to the first end of the second capacitor and serving as the output end of the second storage unit, and a third end of the ninth transistor serving as the input end of the second storage unit.

[0037] In some embodiments, the amplification unit comprises:

[0038] a tenth transistor and an eleventh transistor;

[0039] The first end of the tenth transistor is connected to the floating diffusion node, the second end of the tenth transistor is connected to the third end of the eleventh transistor and serves as the output end of the amplification unit, the third end of the tenth transistor is connected to the power supply, the first end of the eleventh transistor is connected to the sixth control signal, and the second end of the eleventh transistor is grounded.

[0040] In order to solve the above technical problem, the present application also provides an image sensor, which includes the global shutter pixel as described above.

[0041] In some embodiments, a preset number of global shutter pixels in the image sensor share a differential unit.

[0042] In some embodiments, a preset number of global shutter pixels in the image sensor share a storage unit.

[0043] The global shutter pixel provided in the present application includes a photosensitive unit, a transmission unit, a reset unit, a storage unit, and a differential unit; the photosensitive unit is used to generate charges by sensing light; the transmission unit is used to transmit the charges to a floating diffusion node when the transmission unit is turned on; the reset unit is used to reset the global shutter pixel when the reset unit is turned on; the storage unit is used to store the voltage at the floating diffusion node, and the voltage at the floating diffusion node includes a reset voltage and a signal voltage; the differential unit is used to output the difference between the reset voltage and the signal voltage.

[0044] It can be seen that the global shutter pixel provided in the present application calculates the difference between the reset voltage and the signal voltage through the differential unit, and the global shutter pixel outputs the difference between the reset voltage and the signal voltage. In this way, the global shutter pixel only needs to output the signal to the analog-to-digital converter once, which reduces the number of signal outputs, thereby reducing the data processing amount of the analog-to-digital converter, reducing the power consumption of the image sensor, and improving the frame rate of the image sensor.

[0045] The image sensor provided in this application also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the prior art and the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A schematic diagram of the overall architecture of a CIS provided in an embodiment of the present application;

[0048] Figure 2 A schematic diagram of a single-slope analog-to-digital converter provided in an embodiment of the present application;

[0049] Figure 3 A schematic diagram of a first type of global shutter pixel provided in an embodiment of the present application;

[0050] Figure 4 A schematic diagram of a second global shutter pixel provided in an embodiment of the present application;

[0051] Figure 5The first timing diagram provided in the embodiment of the present application;

[0052] Figure 6 A schematic diagram of a third type of global shutter pixel provided in an embodiment of the present application;

[0053] Figure 7 A schematic diagram of a fourth type of global shutter pixel provided in an embodiment of the present application;

[0054] Figure 8 A schematic diagram of a fifth type of global shutter pixel provided in an embodiment of the present application;

[0055] Fig. 9 A second timing diagram provided in an embodiment of the present application;

[0056] Fig.10 A third timing diagram provided in an embodiment of the present application;

[0057] Fig.11 A schematic diagram of a first specific global shutter pixel provided in an embodiment of the present application;

[0058] Fig.12 A cross-sectional view of a first global shutter pixel provided in an embodiment of the present application;

[0059] Fig.13 A schematic diagram of a copper-to-copper bonding process provided in an embodiment of the present application;

[0060] Fig.14 A schematic diagram of a second specific global shutter pixel provided in an embodiment of the present application;

[0061] Fig.15 A cross-sectional view of a second global shutter pixel provided in an embodiment of the present application;

[0062] Fig.16 A schematic diagram of a third specific global shutter pixel provided in an embodiment of the present application;

[0063] Fig.17 A cross-sectional view of a second global shutter pixel provided in an embodiment of the present application;

[0064] Fig.18 A schematic diagram of a first pixel-sharing differential unit provided in an embodiment of the present application;

[0065] Fig.19 A schematic diagram of a second pixel-sharing differential unit provided in an embodiment of the present application;

[0066] Fig. 20 A schematic diagram of a third pixel-sharing differential unit provided in an embodiment of the present application;

[0067] Fig.21 A schematic diagram of a first type of pixel-shared storage unit and a differential unit provided in an embodiment of the present application;

[0068] Fig. 22 A schematic diagram of a second type of pixel-shared storage unit and a differential unit provided in an embodiment of the present application;

[0069] Fig.23 A schematic diagram of a first pixel-sharing reset unit, an amplifying unit, a storage unit, and a differential unit provided in an embodiment of the present application;

[0070] Fig.24 A schematic diagram of a pixel sharing reset unit, a storage unit and a differential unit provided in an embodiment of the present application;

[0071] Fig.25 A schematic diagram of a second pixel sharing reset unit, an amplifying unit, a storage unit and a differential unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] The core of this application is to provide a global shutter pixel and image sensor, which can reduce the power consumption of the image sensor and improve the frame rate of the image sensor.

[0073] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0074] like Figure 1 As shown, the complete circuit consists of the following parts:

[0075] Pixel array unit: It is a pixel unit of r rows × c columns, and its core functions are: photosensitizing and converting light signals into photogenerated electrons, then converting photogenerated electrons into electrical signals, and finally outputting reset voltage and signal voltage to the Vin terminal of the analog-to-digital converter connected in parallel to each column of pixels.

[0076] Analog-to-digital converter: Currently, the main SS-ADC (single slope ADC) is used, as shown in the attached Figure 2As shown, the voltage is connected to the Vin terminal of COMP (operational amplifier), and then the COMP is compared with the Vramp voltage. When Vin and Vramp are equal, COMP reverses and the counter stops counting. CDS (correlated double sampling) first samples the Vrst voltage (i.e. the reset voltage of the pixel), and then samples the Vrst+Vsig voltage (i.e. the signal voltage of the pixel). The rst count is obtained by up sampling once, and the sig+rst count is obtained by down sampling once. The difference between the two sampling counter counts is the actual output value count of the pixel.

[0077] Readout logic: The main components include adders or subtractors, multipliers, negation logic, and storage units.

[0078] Parallel-to-serial circuit: This part is currently mainly implemented using SA (sense amplifier), but can also be implemented through other circuits.

[0079] The current mainstream solution uses a column ADC quantization mode, that is, each column of pixels shares one ADC quantization. In order to increase the quantization speed, several more sets of ADCs are currently made, and multiple rows are quantized simultaneously, thereby achieving an increase in frame rate, but this will lead to increased power consumption, increased chip area and increased overall cost. In order to solve the above technical defects, this application provides a global shutter pixel.

[0080] Please refer to Figure 3 , Figure 3 A schematic diagram of a global shutter pixel provided in an embodiment of the present application, referring to Figure 3 As shown, the global shutter pixel includes:

[0081] Photosensitive unit 10, transmission unit 20, reset unit 30, storage unit 40, differential unit 50;

[0082] The photosensitive unit 10 is used for generating charges by sensing light;

[0083] The transmission unit 20 is used to transmit the charge to the floating diffusion node when the transmission unit 20 is turned on;

[0084] The reset unit 30 is used to reset the global shutter pixel when the reset unit 30 is turned on;

[0085] The storage unit 40 is used to store the voltage at the floating diffusion node, where the voltage at the floating diffusion node includes a reset voltage and a signal voltage;

[0086] The differential unit 50 is used to output the difference between the reset voltage and the signal voltage.

[0087] The photosensitive unit 10 is connected to the transmission unit 20, and the transmission unit 20, the reset unit 30 and the storage unit 40 are all connected to the floating diffusion node ( Figure 3 FD shown in FIG), the storage unit 40 is also connected to the differential unit 50. The reset voltage and signal voltage stored in the storage unit 40 are input to the differential unit 50, and the differential unit 50 outputs the difference between the reset voltage and the signal voltage. In this way, the reset voltage and the signal voltage in the global shutter pixel are calculated by the differential unit 50, and only one signal, that is, the difference between the reset voltage and the signal voltage, needs to be output to the analog-to-digital converter.

[0088] In some embodiments, the storage unit 40 includes:

[0089] A first storage unit 40 and a second storage unit 40; the first storage unit 40 and the second storage unit 40 are used to store one of a reset voltage and a signal voltage, and the types of voltages stored in the first storage unit 40 and the second storage unit 40 are different.

[0090] The first storage unit 40 is used to store the reset voltage, and the second storage unit 40 is used to store the signal voltage. Alternatively, the first storage unit 40 is used to store the signal voltage, and the second storage unit 40 is used to store the reset voltage.

[0091] In some embodiments, the first storage unit 40 is connected to the input end of the second storage unit 40 and serves as the input end of the storage unit 40, the output end of the first storage unit 40 is connected to one input end of the differential unit 50, and the output end of the second storage unit 40 is connected to the other input end of the differential unit 50.

[0092] In this embodiment, the first storage unit 40 and the second storage unit 40 are connected in a similar parallel manner. The input end of the first storage unit 40 is connected to the input end of the second storage unit 40, the output end of the first storage unit 40 is connected to one input end of the differential unit 50, and the output end of the second storage unit 40 is connected to the other input end of the differential unit 50. For example, Figure 4 As shown, the input end of the first storage unit 40 and the input end of the second storage unit 40 are both connected to the floating diffusion node, the output end of the first storage unit 40 is connected to one input end of the differential unit 50, and the output end of the second storage unit 40 is connected to the other input end of the differential unit 50.

[0093] In some embodiments, the input end of the first storage unit 40 serves as the input end of the storage unit 40 , the output end of the first storage unit 40 is connected to the input end of the second storage unit 40 and one input end of the differential unit 50 , and the output end of the second storage unit 40 is connected to the other input end of the differential unit 50 .

[0094] In this embodiment, the first storage unit 40 and the second storage unit 40 are connected in series. The input end of the first storage unit 40 serves as the input end of the storage unit 40, the output end of the first storage unit 40 is connected to the input end of the second storage unit 40 and one input end of the differential unit 50, and the output end of the second storage unit 40 is connected to the other input end of the differential unit 50.

[0095] In some embodiments, the differential unit 50 is controlled by a first control signal. When the first control signal is a first level signal, the differential unit 50 outputs the difference between the reset voltage and the signal voltage. The transmission unit 20 is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit 20 is turned on. The reset unit 30 is controlled by a third control signal. When the third control signal is a first level signal, the reset unit 30 is turned on to connect the power supply connecting the floating diffusion node to the reset unit 30. The first storage unit 40 is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor C1 of the first storage unit 40 is connected to the input end of the first storage unit 40.

[0096] The first control signal may be at a high level. When the first control signal is at a high level, the differential unit 50 outputs the difference between the reset voltage and the signal voltage; when the second control signal is at a high level, the transmission unit 20 is turned on; when the third control signal is at a high level, the reset unit 30 is turned on, and the power supply connecting the floating diffusion node and the reset unit 30 is turned on; when the fourth control signal is at a high level, the first capacitor C1 of the first storage unit 40 is connected to the input terminal of the first storage unit 40.

[0097] In some embodiments, in the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal and the fourth control signal are first level signals; in the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal and the fourth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal and the third control signal are second level signals, and the fourth control signal is a first level signal; in the signal voltage storage stage, the first control signal, the third control signal and the fourth control signal are second level signals, and the second control signal is a first level signal; in the output stage, the first control signal is a first level signal, and the second control signal, the third control signal and the fourth control signal are second level signals.

[0098] refer to Figure 5As shown, when the first control signal is at a high level and the second control signal is at a low level, Figure 4 The global shutter pixel shown works as follows:

[0099] Figure 5 In the figure, SEL represents the first control signal, TX represents the second control signal, RX represents the third control signal, and S1 represents the fourth control signal.

[0100] At time t0, the reset phase is entered. In the reset phase, the first control signal is at a low level (e.g., -1V to 0V), and the second control signal, the third control signal, and the fourth control signal are all at a high level (e.g., 2.5V to 3.5V). At this time, the states of the photosensitive unit 10, the floating diffusion node, the first storage unit 40, and the second storage unit 40 are reset, and the original charges of the photosensitive unit 10, the floating diffusion node, the first storage unit 40, and the second storage unit 40 are all cleared to ensure that all global shutter pixels constituting the entire image sensor are in a consistent original state, so that in the next exposure, the charges induced by the global shutter pixels at different positions are completely generated by light.

[0101] The reset state is maintained until time t1, and the exposure phase is entered at time t1. In the exposure phase, the second control signal is at a low level (e.g., -1V to 0V), and the photosensitive unit 10 begins to accumulate photogenerated electrons. At this time, the third control signal and the fourth control signal are maintained at a high level to remove the photogenerated electrons at the floating diffusion node, the first storage unit 40, and the second storage unit 40, thereby reducing the signal noise. At the same time, the light shielding structure at the floating diffusion node, the first storage unit 40, and the second storage unit 40 can also be omitted. Among them, under strong light, the charge storage in the photosensitive unit 10 is full, such as Figure 2 The dotted line shown in the figure can increase the negative voltage of the transmission unit 20 (for example, from -0.5V to 0.5V) to overflow some electrons to the floating diffusion node, thereby enhancing the signal crosstalk capability of the global exposure pixel and improving the image quality.

[0102] The exposure continues until the end of time t2, and then enters the reset voltage storage stage. In the reset voltage storage stage, the third control signal is at a low level, and the reset voltage of the floating diffusion node is stored in the first storage unit 40 and the second storage unit 40. Since the first storage unit 40 and the second storage unit 40 are directly connected to the floating diffusion node, the charge is transferred proportionally, which can increase the actual output swing. At time t3, the fourth control signal becomes a low level, and the reset voltage is latched into the first storage unit 40.

[0103] At time t3, the signal voltage storage stage is entered. In the signal voltage storage stage, the second control signal is at a high level, the transmission unit 20 is turned on, the photogenerated electrons in the photosensitive unit 10 flow into the floating diffusion node, the voltage of the floating diffusion node drops, and the signal voltage at the floating diffusion node is directly stored in the second storage unit 40.

[0104] At time t4, the output phase begins, and the signal calculation and reading are performed row by row (or column by column), including calculating the output signal Vout and transferring it to the SSADC count. In the output phase, the first control signal is at a high level, and the differential unit 50 starts to work. The output terminal Vout of the differential unit 50 outputs the value of the reset voltage minus the signal voltage.

[0105] Then, the SSADC outside the pixel array is turned on, and the Vout of the global shutter pixel is input to COMP through the Vin port, and compared with the gradually increasing Vramp voltage, the counter counts the grayscale value corresponding to the output signal, until Vin is equal to Vramp, COMP is reversed, the counter stops counting, and the count is the grayscale value of the actual pixel. Then, the grayscale value of the global shutter pixel in this row is transmitted to the storage unit 40 of the readout logic of the next level, and the global shutter pixel in this row enters the reset standby state at time t6, and the next row of global shutter pixels starts the operation from time t4 to time t6.

[0106] Finally, the data of all rows (or all columns) are collected in a parallel-to-serial circuit to perform image synthesis calculations and output an image with a high frame rate.

[0107] refer to Figure 6 As shown, in some embodiments, it also includes:

[0108] The amplifying unit 60 is used to amplify the voltage at the floating diffusion node and output the amplified voltage to the input end of the storage unit 40 .

[0109] The photosensitive unit 10 is connected to the transmission unit 20, the transmission unit 20 and the reset unit 30 are connected to the floating diffusion node, and the input end of the amplification unit 60 is used as the floating diffusion node. The input end of the storage unit 40 is connected to the output end of the amplification unit 60, and the storage unit 40 is also connected to the differential unit 50. Figure 7 As shown, the input end of the first storage unit 40 and the input end of the second storage unit 40 are both connected to the output end of the amplification unit 60, the output end of the first storage unit 40 is connected to one input end of the differential unit 50, and the output end of the second storage unit 40 is connected to the other input end of the differential unit 50. Or, as Figure 8As shown, the input end of the first storage unit 40 is connected to the output end of the amplifier unit 60, the output end of the first storage unit 40 is connected to one input end of the differential unit 50 and the input end of the second storage unit 40, and the output end of the second storage unit 40 is connected to the other input end of the differential unit 50. The amplifier unit 60 amplifies the voltage at the floating diffusion node and outputs it to the storage unit 40. The reset voltage and the signal voltage stored in the storage unit 40 are input to the differential unit 50, and the differential unit 50 outputs the difference between the reset voltage and the signal voltage.

[0110] In some embodiments, the differential unit 50 is controlled by a first control signal. When the first control signal is a first level signal, the differential unit 50 outputs the difference between the reset voltage and the signal voltage. The transmission unit 20 is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit 20 is turned on. The reset unit 30 is controlled by a third control signal. When the third control signal is a first level signal, the reset unit 30 is turned on to connect the power supply connecting the floating diffusion node to the reset unit 30. The first storage unit 40 is controlled by a fourth control signal. The second storage unit 40 is controlled by the fifth control signal. When the fifth control signal is a first level signal, the second capacitor C1 of the first storage unit 40 is connected to the floating diffusion node. The second storage unit 40 is controlled by the fifth control signal. When the fifth control signal is a first level signal, the second capacitor C2 of the second storage unit 40 is connected to the input end of the second storage unit 40. The amplifying unit 60 is controlled by the sixth control signal. When the sixth control signal is a first level signal, the amplifying unit 60 amplifies the voltage at the floating diffusion node and outputs it to the input end of the storage unit 40.

[0111] The first control signal can be a high level. When the first control signal is a high level, the differential unit 50 outputs the difference between the reset voltage and the signal voltage; when the second control signal is a high level, the transmission unit 20 is turned on; when the third control signal is a high level, the reset unit 30 is turned on, and the power supply connecting the floating diffusion node and the reset unit 30 is turned on; when the fourth control signal is a high level, the first capacitor C1 of the first storage unit 40 is connected to the floating diffusion node; when the fifth control signal is a high level, the second capacitor C2 of the second storage unit 40 is connected to the input end of the second storage unit 40; when the sixth control signal is a high level, the amplification unit 60 amplifies the voltage at the floating diffusion node and outputs it to the input end of the storage unit 40.

[0112] In some embodiments, in the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal and the third control signal are second level signals, and the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the signal voltage storage stage, the first control signal, the third control signal and the fourth control signal are second level signals, and the second control signal, the fifth control signal and the sixth control signal are first level signals; in the output stage, the first control signal is a first level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are second level signals.

[0113] refer to Fig. 9 As shown, when the first control signal is at a high level and the second control signal is at a low level, Figure 7 The global shutter pixel shown works as follows:

[0114] Fig. 9 In the figure, SEL represents the first control signal, TX represents the second control signal, RX represents the third control signal, S1 represents the fourth control signal, S2 represents the fifth control signal, and PC represents the sixth control signal.

[0115] At time t0, the reset phase is entered, the first control signal is at a low level (for example: -1V to 0V), the second control signal TX, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are at a high level (for example: 2.5V to 3.5V), and the photosensitive unit 10, the floating diffusion node, the first storage unit 40 and the second storage unit 40 are reset at this stage. The original charges of the photosensitive unit 10, the floating diffusion node, the first storage unit 40 and the second storage unit 40 are all cleared to ensure that all global shutter pixels constituting the entire image sensor are in a consistent original state, so that during the subsequent exposure, the charges induced by the pixels at different positions are completely generated by light.

[0116] The reset state is maintained until time t1, and the exposure phase is entered at time t1. In the exposure phase, the second control signal is at a low level (for example: -1V to 0V), the photosensitive unit 10 begins to accumulate photogenerated electrons, and the third control signal, the fourth control signal, the fifth control signal, and the sixth control signal are maintained at a high level, so as to remove the photogenerated electrons at the floating diffusion node, the first storage unit 40, and the second storage unit 40, reduce the noise of the signal, and also omit the light shielding structure of the floating diffusion node, the first storage unit 40, and the second storage unit 40. When the charge storage in the photosensitive unit 10 is full under strong light, the negative voltage of the transmission unit 20 can be increased (for example: -0.5V to 0.5V), and part of the electrons can overflow to the floating diffusion node, thereby enhancing the signal crosstalk capability of the pixel and improving the image quality.

[0117] The exposure phase lasts until the end of time t2, and then enters the reset signal storage phase. In the reset signal storage phase, the second control signal is at a low level, the fourth control signal and the fifth control signal are at a high level, the potential of the floating diffusion node is a reset voltage, and the reset voltage is converted to the first storage unit 40 and the second storage unit 40 through the amplification unit 60. Then at time t3, the fourth control signal becomes a low level, and the signal is latched into the first storage unit 40.

[0118] In the signal voltage storage stage, the second control signal is at a high level. In this stage, the photogenerated electrons in the photosensitive unit 10 flow into the floating diffusion node, and the voltage of the floating diffusion node decreases. Similarly, the amplification unit 60 converts the photogenerated signal into a signal voltage and stores it in the second storage unit 40. At time t4, the fifth control signal becomes a low level, and the signal voltage is latched into the second storage unit 40.

[0119] At time t4, the output phase begins, and the signal calculation and reading are performed row by row (or column by column), including calculating the output signal Vout and transferring it to the SSADC count. In the output phase, the first control signal is at a high level, and the differential unit 50 starts to work. The output terminal Vout of the differential unit 50 outputs the value of the reset voltage minus the signal voltage.

[0120] Then, the SSADC outside the pixel array is turned on, and the Vout of the global shutter pixel is input to COMP through the Vin port, and compared with the gradually increasing Vramp voltage, the counter counts the grayscale value corresponding to the output signal, until Vin is equal to Vramp, COMP is reversed, the counter stops counting, and the count is the grayscale value of the actual pixel. Then, the grayscale value of the global shutter pixel in this row is transmitted to the storage unit 40 of the readout logic of the next level, and the global shutter pixel in this row enters the reset standby state at time t6, and the next row of global shutter pixels starts the operation from time t4 to time t6.

[0121] Finally, the data of all rows (or all columns) are collected in a parallel-to-serial circuit to perform image synthesis calculations and output an image with a high frame rate.

[0122] In some embodiments, in the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal and the third control signal are second level signals, and the fourth control signal, the fifth control signal and the sixth control signal are first level signals; in the signal voltage storage stage, the first control signal, the third control signal and the fifth control signal are second level signals, and the second control signal, the fourth control signal and the sixth control signal are first level signals; in the output stage, the first control signal is a first level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are second level signals.

[0123] refer to Fig.10 As shown, when the first control signal is at a high level and the second control signal is at a low level, Figure 8 The global shutter pixel shown works as follows:

[0124] Fig.10 In the figure, SEL represents the first control signal, TX represents the second control signal, RX represents the third control signal, S1 represents the fourth control signal, S2 represents the fifth control signal, and PC represents the sixth control signal.

[0125] At time t0, the reset phase is entered, the first control signal is at a low level (for example: -1V to 0V), the second control signal TX, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are at a high level (for example: 2.5V to 3.5V), and the photosensitive unit 10, the floating diffusion node, the first storage unit 40 and the second storage unit 40 are reset at this stage. The original charges of the photosensitive unit 10, the floating diffusion node, the first storage unit 40 and the second storage unit 40 are all cleared to ensure that all global shutter pixels constituting the entire image sensor are in a consistent original state, so that during the subsequent exposure, the charges induced by the pixels at different positions are completely generated by light.

[0126] The reset state is maintained until time t1, and the exposure phase is entered at time t1. In the exposure phase, the second control signal is at a low level (for example: -1V to 0V), the photosensitive unit 10 begins to accumulate photogenerated electrons, and the third control signal, the fourth control signal, the fifth control signal, and the sixth control signal are maintained at a high level, so as to remove the photogenerated electrons at the floating diffusion node, the first storage unit 40, and the second storage unit 40, reduce the noise of the signal, and also omit the light shielding structure of the floating diffusion node, the first storage unit 40, and the second storage unit 40. When the charge storage in the photosensitive unit 10 is full under strong light, the negative voltage of the transmission unit 20 can be increased (for example: -0.5V to 0.5V), and part of the electrons can overflow to the floating diffusion node, thereby enhancing the signal crosstalk capability of the pixel and improving the image quality.

[0127] The exposure phase lasts until the end of time t2, and then enters the reset signal storage phase. In the reset signal storage phase, the second control signal is at a low level, the fourth control signal and the fifth control signal are at a high level, the potential of the floating diffusion node is a reset voltage, and the reset voltage is converted to the first storage unit 40 and the second storage unit 40 through the amplification unit 60. Then at time t3, the fifth control signal becomes a low level, and the signal is latched into the second storage unit 40.

[0128] In the signal voltage storage stage, the second control signal is at a high level. In this stage, the photogenerated electrons in the photosensitive unit 10 flow into the floating diffusion node, and the voltage of the floating diffusion node decreases. Similarly, the amplification unit 60 converts the photogenerated signal into a signal voltage and stores it in the first storage unit 40. At time t4, the fourth control signal becomes a low level, and the signal voltage is latched into the first storage unit 40.

[0129] At time t4, the output phase begins, and the signal calculation and reading are performed row by row (or column by column), including calculating the output signal Vout and transferring it to the SSADC count. In the output phase, the first control signal is at a high level, and the differential unit 50 starts to work. The output terminal Vout of the differential unit 50 outputs the value of the reset voltage minus the signal voltage.

[0130] Then, the SSADC outside the pixel array is turned on, and the Vout of the global shutter pixel is input to COMP through the Vin port, and compared with the gradually increasing Vramp voltage, the counter counts the grayscale value corresponding to the output signal, until Vin is equal to Vramp, COMP is reversed, the counter stops counting, and the count is the grayscale value of the actual pixel. Then, the grayscale value of the global shutter pixel in this row is transmitted to the storage unit 40 of the readout logic of the next level, and the global shutter pixel in this row enters the reset standby state at time t6, and the next row of global shutter pixels starts the operation from time t4 to time t6.

[0131] Finally, the data of all rows (or all columns) are collected in a parallel-to-serial circuit to perform image synthesis calculations and output an image with a high frame rate.

[0132] In some embodiments, the differential unit 50 includes:

[0133] A first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5;

[0134] The first end of the first transistor M1 serves as an input end of the differential unit 50, the second end of the first transistor M1 is connected to the third end of the second transistor M2 and the third end of the third transistor M3, the third end of the first transistor M1 is connected to the third end of the fourth transistor M4, the first end of the second transistor M2 serves as another input end of the differential unit 50, the second end of the second transistor M2 is connected to the third end of the fifth transistor M5 and serves as an output end of the differential unit 50, the first end of the third transistor M3 is connected to the first control signal, the second end of the third transistor M3 is grounded, the first end of the fourth transistor M4 is connected to the third end of the fourth transistor M4 and the first end of the fifth transistor M5, the second end of the fourth transistor M4 is connected to a power supply, and the second end of the fifth transistor M5 is connected to a power supply.

[0135] In some embodiments, the photosensitive unit 10 includes:

[0136] Photosensitive diode PD; the anode of the photosensitive diode PD is grounded, and the cathode of the photosensitive diode PD is connected to the transmission unit 20.

[0137] In some embodiments, the transmission unit 20 includes:

[0138] The sixth transistor M6; the first end of the sixth transistor M6 is connected to the second control signal, the second end of the sixth transistor M6 is connected to the photosensitive unit 10, and the third end of the sixth transistor M6 is connected to the floating diffusion node.

[0139] In some embodiments, the reset unit 30 includes:

[0140] A seventh transistor M7; a first terminal of the seventh transistor M7 is connected to the third control signal, a second terminal of the seventh transistor M7 is connected to the floating diffusion node, and a third terminal of the seventh transistor M7 is connected to a power supply.

[0141] In some embodiments, the first storage unit 40 includes:

[0142] an eighth transistor M8 and a first capacitor C1; a first end of the eighth transistor M8 is connected to the fourth control signal, a second end of the eighth transistor M8 serves as an input end of the first storage unit 40, a third end of the eighth transistor M8 is connected to the first end of the first capacitor C1 and serves as an output end of the first storage unit 40, and the other end of the first capacitor C1 is grounded.

[0143] In some embodiments, the second storage unit 40 includes:

[0144] Second capacitor C2: A first end of the second capacitor C2 serves as an input end and an output end of the second storage unit 40, and a second end of the second capacitor C2 is grounded.

[0145] like Fig.11 As shown, the first transistor M1 to the third transistor M3 and the sixth transistor M6 to the eighth transistor M8 may be NMOS transistors, and the fourth transistor M4 and the fifth transistor M5 may be PMOS transistors.

[0146] The global shutter pixel can adopt a stacking process to divide the global shutter pixel into a process structure of a photosensitive readout pixel layer (Pixel Layer) and a differential circuit logic layer (Logic Layer) to improve the fill factor (FF) of the photosensitive diode PD area. At the same time, the differential circuit logic layer can adopt the same or different process as the photosensitive readout pixel layer to reduce the difficulty of PMOS process development. Fig.11 The cross-section of the global shutter pixel is shown in Fig.12 As shown in FIG. 1 , the cross-sectional view is a general schematic diagram of the first capacitor C1, the second capacitor C2, the transistor of the differential unit 50, the eighth transistor M8 and the metal wiring part thereof. The interface between the pixel layer and the logic layer is called a hybrid bond interface, which usually uses a copper-to-copper bonding process at the pixel level (Cu-Cu Hybrid Bond). The process flow is shown in the attached figure. Fig.13As shown, a dielectric layer of uniform thickness is formed on the entire surface of the silicon using solid materials from chemical vapor deposition (PVD), followed by trenches and vias as part of the back end of line (BEOL). A copper seed is formed in the trench using a physical vapor deposition (PVD) method. After PVD, the trench is filled with copper using electrochemical deposition (ECD), excess copper is removed, and very low dielectric roughness is achieved through chemical mechanical polishing (CMP). During the CMP process, the copper is expected to be recessed to a certain extent, the plasma-activated wafers are bonded face-to-face, and the dielectrics are bonded instantaneously. After CMP, annealing is performed at a temperature of 150°C to 300°C. Since the coefficient of thermal expansion (CTE) of metal is higher than that of oxide, the metal will expand to fill the gap between them. As a result, after the above steps, due to the combination of dielectric and metal between the substrates, Cu-Cu hybrid bonding provides physical and electrical connections, thereby achieving normal pixel-level operation of the Pixel Layer and Logic Layer.

[0147] In some embodiments, the second storage unit 40 further includes:

[0148] a ninth transistor M9; a first end of the ninth transistor M9 is connected to the fifth control signal, a second end of the ninth transistor M9 is connected to the first end of the second capacitor C2 and serves as the output end of the second storage unit 40, and a third end of the ninth transistor M9 serves as the input end of the second storage unit 40.

[0149] like Fig.14 or Fig.16 As shown, the first transistor M1 to the third transistor M3 and the sixth transistor M6 to the ninth transistor M9 may be NMOS transistors, and the fourth transistor M4 and the fifth transistor M5 may be PMOS transistors.

[0150] When using the stack process, Fig.14 The cross-section diagram of the global shutter pixel shown can be referred to Fig.15 As shown, Fig.16 The cross-section diagram of the global shutter pixel shown can be referred to Fig.17 shown.

[0151] In some embodiments, the amplification unit 60 includes:

[0152] a tenth transistor M10 and an eleventh transistor M11;

[0153] The first end of the tenth transistor M10 is connected to the floating diffusion node, the second end of the tenth transistor M10 is connected to the third end of the eleventh transistor M11 and serves as the output end of the amplification unit 60, the third end of the tenth transistor M10 is connected to the power supply, the first end of the eleventh transistor M11 is connected to the sixth control signal, and the second end of the eleventh transistor M11 is grounded.

[0154] like Fig.14 or Fig.16 As shown, the first transistor M1 to the third transistor M3 and the sixth transistor M6 to the eleventh transistor M11 may be NMOS transistors, and the fourth transistor M4 and the fifth transistor M5 may be PMOS transistors.

[0155] To summarize, the global shutter pixel provided in the present application calculates the difference between the reset voltage and the signal voltage through the differential unit, and the global shutter pixel outputs the difference between the reset voltage and the signal voltage. In this way, the global shutter pixel only needs to output the signal to the analog-to-digital converter once, which reduces the number of signal outputs, thereby reducing the data processing amount of the analog-to-digital converter, reducing the power consumption of the image sensor, and improving the frame rate of the image sensor.

[0156] The present application also provides an image sensor, which includes the global shutter pixel as described in the above embodiment.

[0157] In some embodiments, a preset number of global shutter pixels in the image sensor share a differential unit. Fig.18 , Fig.19 , Fig. 20As shown. Two global shutter pixels share a differential unit. Among them, at the capacitors of the two global shutter pixels, selection transistors Share_S1_L, Share_S2_L and Share_S1_R, Share_S2_R are added respectively to increase the selection readout capability of the first transistor (DN1) and the second transistor (DN2). When reading the output value of the left global shutter pixel, Share_S1_L and Share_S2_L are turned on, Share_S1_R, and Share_S2_R are turned off, the voltage of capacitor C1_L is added to the first transistor, and the voltage of capacitor C2_L is added to the second transistor. At this time, the differential unit outputs the difference between the reset voltage and the signal voltage of the left global shutter pixel. When reading the output value of the right global shutter pixel, Share_S1_R and Share_S2_R are opened, Share_S1_L and Share_S2_L are closed, the voltage of capacitor C1_R is added to the first transistor, and the voltage of capacitor C2_R is added to the second transistor. At this time, the differential unit outputs the difference between the reset voltage and the signal voltage of the right global shutter pixel.

[0158] Global shutter pixels share differential units, which can reduce the number of devices, improve the fill factor of global shutter pixels, reduce costs, and improve the quantum efficiency of the camera.

[0159] In some embodiments, a preset number of global shutter pixels in the image sensor share a storage unit. Fig.21 , Fig. 22 As shown, two global shutter pixels share a storage unit. After exposure, the difference between the reset voltage and the signal voltage of the global shutter pixels in odd columns can be calculated first, and then the difference between the reset voltage and the signal voltage of the global shutter pixels in even columns can be calculated.

[0160] Global shutter pixels share storage units, which can reduce the number of devices, improve the fill factor of global shutter pixels, reduce costs, and improve the quantum efficiency of the camera.

[0161] Among them, the global shutter pixels can share both the differential unit and the storage unit, which can further reduce the number of devices, improve the fill factor of the global shutter pixels, reduce costs, and improve the quantum efficiency of the camera.

[0162] In some embodiments, a preset number of global shutter pixels in the image sensor share a reset unit, an amplification unit, a storage unit, and a differential unit. Fig.23 , Fig.25 In some embodiments, a preset number of global shutter pixels in the image sensor share a reset unit, a storage unit, and a differential unit. Fig.24The above embodiment can be applied to the combined reading of different photosensitive diodes, and different photosensitive diodes can also be designed under one photosensitive lens for automatic focusing and distance measurement.

[0163] The global shutter pixels share a differential unit, a shared storage unit, a reset unit and / or an amplification unit, which can further reduce the number of devices, improve the fill factor of the global shutter pixels, reduce costs, and improve the quantum efficiency of the camera.

[0164] Because the situation is complicated, it is impossible to list them one by one for explanation. Those skilled in the art should be able to realize that there may be multiple examples based on the basic principles of the embodiments provided in this application and combined with actual conditions, and they should all be within the scope of this application without paying enough creative work.

[0165] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0166] The global shutter pixel and image sensor provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0167] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A global shutter pixel, characterized in that: include: Photosensitive unit, transmission unit, reset unit, storage unit, differential unit; The photosensitive unit is used to generate charges by sensing light; The transmission unit is used to transmit the charge to the floating diffusion node when the transmission unit is turned on; The reset unit is used to reset the global shutter pixel when the reset unit is turned on; The storage unit is used to store the voltage at the floating diffusion node, and the voltage at the floating diffusion node includes a reset voltage and a signal voltage; The differential unit is used to output the difference between the reset voltage and the signal voltage.

2. The global shutter pixel according to claim 1, characterized in that: The storage unit comprises: A first storage unit and a second storage unit; the first storage unit and the second storage unit are used to store one of a reset voltage and a signal voltage, and the types of voltages stored in the first storage unit and the second storage unit are different.

3. The global shutter pixel according to claim 2, characterized in that: The first storage unit is connected to the input end of the second storage unit and serves as the input end of the storage unit, the output end of the first storage unit is connected to one input end of the differential unit, and the output end of the second storage unit is connected to the other input end of the differential unit.

4. The global shutter pixel according to claim 2, characterized in that: The input end of the first storage unit serves as the input end of the storage unit, the output end of the first storage unit is connected to the input end of the second storage unit and one input end of the differential unit, and the output end of the second storage unit is connected to the other input end of the differential unit.

5. The global shutter pixel according to claim 3, characterized in that: The differential unit is controlled by a first control signal. When the first control signal is a first level signal, the differential unit outputs the difference between the reset voltage and the signal voltage. The transmission unit is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a third control signal. When the third control signal is a first level signal, the reset unit is turned on to connect the power supply connecting the floating diffusion node to the reset unit. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor of the first storage unit is connected to the input end of the first storage unit.

6. The global shutter pixel according to claim 5, characterized in that: In the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal and the fourth control signal are first level signals; In the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal and the fourth control signal are first level signals; In the reset voltage storage stage, the first control signal, the second control signal, and the third control signal are second level signals, and the fourth control signal is a first level signal; In the signal voltage storage stage, the first control signal, the third control signal and the fourth control signal are second level signals, and the second control signal is a first level signal; In the output stage, the first control signal is a first level signal, and the second control signal, the third control signal and the fourth control signal are second level signals.

7. The global shutter pixel according to claim 1, characterized in that: Also includes: The amplifying unit is used to amplify the voltage at the floating diffusion node and output the amplified voltage to the input end of the storage unit.

8. The global shutter pixel according to claim 7, characterized in that: The differential unit is controlled by a first control signal. When the first control signal is a first level signal, the differential unit outputs the difference between the reset voltage and the signal voltage. The transmission unit is controlled by a second control signal. When the second control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a third control signal. When the third control signal is a first level signal, the reset unit is turned on to connect the power supply connecting the floating diffusion node to the reset unit. The first storage unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the first capacitor of the first storage unit is connected to the floating diffusion node. The second storage unit is controlled by a fifth control signal. When the fifth control signal is a first level signal, the second capacitor of the second storage unit is connected to the input end of the second storage unit. The amplification unit is controlled by a sixth control signal. When the sixth control signal is a first level signal, the amplification unit amplifies the voltage at the floating diffusion node and outputs it to the input end of the storage unit.

9. The global shutter pixel according to claim 8, characterized in that: In the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; In the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; In the reset voltage storage stage, the first control signal, the second control signal, and the third control signal are second level signals, and the fourth control signal, the fifth control signal, and the sixth control signal are first level signals; in the signal voltage storage stage, the first control signal, the third control signal, and the fourth control signal are second level signals, and the second control signal, the fifth control signal, and the sixth control signal are first level signals; In the output stage, the first control signal is a first level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are second level signals.

10. The global shutter pixel according to claim 8, characterized in that: In the reset stage, the first control signal is a second level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; In the exposure stage, the first control signal and the second control signal are second level signals, and the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are first level signals; In the reset voltage storage stage, the first control signal, the second control signal, and the third control signal are second level signals, and the fourth control signal, the fifth control signal, and the sixth control signal are first level signals; in the signal voltage storage stage, the first control signal, the third control signal, and the fifth control signal are second level signals, and the second control signal, the fourth control signal, and the sixth control signal are first level signals; In the output stage, the first control signal is a first level signal, and the second control signal, the third control signal, the fourth control signal, the fifth control signal and the sixth control signal are second level signals.

11. The global shutter pixel according to any one of claims 1 to 10, characterized in that: The differential unit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The first end of the first transistor serves as an input end of the differential unit, the second end of the first transistor is connected to the third end of the second transistor and the third end of the third transistor, the third end of the first transistor is connected to the third end of the fourth transistor, the first end of the second transistor serves as another input end of the differential unit, the second end of the second transistor is connected to the third end of the fifth transistor and serves as an output end of the differential unit, the first end of the third transistor is connected to the first control signal, the second end of the third transistor is grounded, the first end of the fourth transistor is connected to the third end of the fourth transistor and the first end of the fifth transistor, the second end of the fourth transistor is connected to a power supply, and the second end of the fifth transistor is connected to a power supply.

12. The global shutter pixel according to claim 1, characterized in that: The photosensitive unit comprises: A photosensitive diode; an anode of the photosensitive diode is grounded, and a cathode of the photosensitive diode is connected to the transmission unit.

13. The global shutter pixel according to claim 1, characterized in that: The transmission unit comprises: A sixth transistor; a first end of the sixth transistor is connected to the second control signal, a second end of the sixth transistor is connected to the photosensitive unit, and a third end of the sixth transistor is connected to the floating diffusion node.

14. The global shutter pixel according to claim 1, characterized in that: The reset unit comprises: a seventh transistor; a first terminal of the seventh transistor is connected to the third control signal, a second terminal of the seventh transistor is connected to the floating diffusion node, and a third terminal of the seventh transistor is connected to a power supply.

15. The global shutter pixel according to claim 2, characterized in that: The first storage unit comprises: an eighth transistor and a first capacitor; a first end of the eighth transistor is connected to the fourth control signal, a second end of the eighth transistor serves as an input end of the first storage unit, a third end of the eighth transistor is connected to the first end of the first capacitor and serves as an output end of the first storage unit, and the other end of the first capacitor is grounded.

16. The global shutter pixel according to claim 2, characterized in that: The second storage unit comprises: A second capacitor; a first end of the second capacitor serves as an input end and an output end of the second storage unit, and a second end of the second capacitor is grounded.

17. The global shutter pixel according to claim 2, characterized in that: The second storage unit also includes: a ninth transistor; a first end of the ninth transistor being connected to the fifth control signal, a second end of the ninth transistor being connected to the first end of the second capacitor and serving as the output end of the second storage unit, and a third end of the ninth transistor serving as the input end of the second storage unit.

18. The global shutter pixel according to claim 7, characterized in that: The amplification unit comprises: a tenth transistor and an eleventh transistor; The first end of the tenth transistor is connected to the floating diffusion node, the second end of the tenth transistor is connected to the third end of the eleventh transistor and serves as the output end of the amplification unit, the third end of the tenth transistor is connected to the power supply, the first end of the eleventh transistor is connected to the sixth control signal, and the second end of the eleventh transistor is grounded.

19. An image sensor, characterized in that: The image sensor comprises a global shutter pixel as claimed in any one of claims 1 to 18.

20. The image sensor according to claim 19, characterized in that: A preset number of global shutter pixels in the image sensor share a differential unit.

21. The image sensor according to claim 19, characterized in that: A preset number of global shutter pixels in the image sensor share a storage unit.

Images