Memory device and manufacturing method of the memory device

Abstract

A memory device includes a lower structure including a first pad exposed through a top surface of the lower structure, and a method of manufacturing the memory device. The memory device also includes an upper structure including a second pad exposed through a bottom surface of the upper structure. The first pad and the second pad are bonded to each other, and an interface where the first pad and the second pad are bonded to each other forms a curved surface.

Description

Technical Field

[0001] The present disclosure generally relates to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device manufactured by a wafer bonding manufacturing method and a method of manufacturing the memory device. Background Art

[0002] The memory device may include a memory cell array in which data is stored and a peripheral circuit configured to perform a program operation, a read operation, or an erase operation of the memory cell array.

[0003] The memory cell array may include a plurality of memory blocks, and the plurality of memory blocks may include a plurality of memory cells stacked in a vertical direction from a substrate.

[0004] As the number of memory cells included in the memory cell array increases to increase the data storage capacity of the memory device, the size of the memory device may increase. In order to reduce the size of the memory device, the peripheral circuit and the memory cell array may be formed on different substrates. Then, the peripheral circuit and the memory cell array formed on different substrates may be bonded to each other.

[0005] A pad may be used that allows a lower structure including a peripheral circuit and an upper structure including a memory cell array to be bonded to each other, and allows the lower structure and the upper structure to be electrically connected to each other. For example, a lower pad exposed to the top surface of the lower structure and an upper pad exposed to the bottom surface of the upper structure may be bonded to each other. When a contact failure occurs at the bonding surface between the lower pad and the upper pad, or when the area of ​​the bonding surface is reduced, the resistance between the lower pad and the upper pad may increase. Summary of the invention

[0006] According to one embodiment of the present disclosure, a memory device includes: a lower structure, the lower structure including a first pad exposed through a top surface of the lower structure; and an upper structure, the upper structure including a second pad exposed through a bottom surface of the upper structure, wherein the first pad and the second pad are joined to each other, and wherein an interface where the first pad and the second pad are joined to each other forms a curved surface.

[0007] According to another embodiment of the present disclosure, a method for manufacturing a memory device includes the following steps: forming a first peripheral layer on a first substrate; forming a first opening in the first peripheral layer; forming a first conductive layer for a first pad on the first opening and the first peripheral layer; performing a first planarization process on the first conductive layer using a first paste targeting the first conductive layer until the first peripheral layer is exposed; forming a second conductive pattern for a second pad on a second substrate; forming a second peripheral layer on the second pad and the second substrate; performing a second planarization process on the second peripheral layer using a second paste targeting the second peripheral layer until the second conductive pattern is exposed; and flipping the second substrate so that the second conductive pattern is located on the bottom surface of the second substrate and allowing the second conductive pattern to bond to the first conductive layer.

[0008] According to one embodiment of the present disclosure, a memory device includes a first structure, the first structure includes a peripheral circuit on a substrate, wherein at least one exposed first pad is embedded in the peripheral circuit relative to the substrate. The memory device also includes a second structure, the second structure includes a memory cell array, wherein at least one exposed second pad is embedded in the memory cell array. The exposed surfaces of at least one first pad and at least one second pad have opposite curvatures that match together, so that the first structure and the second structure are connected by bonding at least one first pad to at least one second pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure feasible for those skilled in the art.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0011] Figure 1A and Figure 1B is a view illustrating a method of manufacturing a memory device according to the present disclosure.

[0012] Figure 2 is a diagram illustrating a memory device.

[0013] Figure 3 is a view illustrating a memory device in which a lower structure and an upper structure are bonded to each other according to one embodiment of the present disclosure.

[0014] 4A to 4Dare views illustrating a method of manufacturing a memory device according to a first embodiment of the present disclosure.

[0015] FIG. 5A to FIG. 5G is a view illustrating a method of manufacturing a lower structure of a memory device according to a first embodiment of the present disclosure.

[0016] 6A to 6H is a view illustrating a method of manufacturing an upper structure of a memory device according to a first embodiment of the present disclosure.

[0017] Figure 7 : is a view illustrating a joining structure of a manufactured lower structure and a manufactured upper structure according to the first embodiment of the present disclosure.

[0018] Figure 8 is a view illustrating another embodiment of the lower structure and the upper structure.

[0019] Fig. 9 is a view illustrating a memory device according to a second embodiment of the present disclosure.

[0020] Fig.10 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0021] Fig.11 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0022] The specific structural and functional descriptions disclosed herein are merely exemplified for the purpose of describing the embodiments conceived according to the present disclosure. Additional embodiments conceived according to the present disclosure can be implemented in various forms. Therefore, the present disclosure should not be interpreted as being limited to the embodiments set forth herein.

[0023] Hereinafter, it will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element and do not imply the number or order of the elements.

[0024] Some embodiments provide a memory device and a method of manufacturing the memory device, which can improve a bonding process of the memory device.

[0025] Figure 1A and Figure 1B is a view illustrating a method of manufacturing a memory device according to the present disclosure.

[0026] Reference Figure 1A, the lower structure D_ST and the upper structure U_ST of the memory device may include a first pad P1 and a second pad P2 formed on different substrates in different ways. The substrate may be a silicon substrate. The first pad P1 may be included in the lower structure D_ST and surrounded by the first material layer M1. The first pad P1 may be formed of a material different from that of the first material layer M1. The second pad P2 may be included in the upper structure U_ST and surrounded by the second material layer M2. The second pad P2 may be formed of a material different from that of the second material layer M2.

[0027] When the first pad P1 is formed in the lower structure D_ST, a first planarization process may be performed so that the top surface of the first pad P1 is formed into a concave shape. The first planarization process may be a chemical mechanical polishing process. A first slurry using the first pad P1 as a target TG may be utilized in the first planarization process. When the first slurry using the first pad P1 as a target TG is coated on the top surface of the lower structure D_ST and then polished, a portion of the first pad P1 may be further polished even if the first material layer M1 is exposed.

[0028] Therefore, through the first planarization process, the top surface of the first pad P1 may have a more concave shape than the top surface of the first material layer M1.

[0029] When the second pad P2 is formed in the upper structure U_ST, a second planarization process different from the first planarization process may be performed so that the top surface of the second pad P2 is formed into a convex shape. The second planarization process may be a chemical mechanical polishing process. In the second planarization process, a second slurry using the second material layer M2 instead of the second pad P2 as the target TG may be utilized. When the second slurry using the second material layer M2 as the target TG is coated on the upper structure U_ST and then polished, a portion of the second material layer M2 may be further polished even if the second pad P2 is exposed. Therefore, through the second planarization process, the top surface of the second pad P2 may have a more convex shape than the top surface of the second material layer M2.

[0030] Reference Figure 1B, when the upper structure U_ST is flipped over and the flipped upper structure U_ST is set on the top of the lower structure D_ST, the first pad P1 and the second pad P2 can be bonded to each other. The first pad P1 and the second pad P2 can be formed of the same material, and the first material layer M1 and the second material layer M2 can be formed of the same material. Because the surface of the first pad P1 has a concave curved surface, and the surface of the second pad P2 has a convex curved surface, when the lower structure D_ST and the upper structure U_ST are bonded to each other, the area of ​​the bonding surface of the first pad P1 and the second pad P2 can be increased. Therefore, the bonding force between the first pad P1 and the second pad P2 can be increased. In addition, because the concave curved surface and the convex curved surface are bonded to each other, the misalignment of the lower structure D_ST and the upper structure U_ST can be reduced.

[0031] When the above manufacturing method is applied to wafer bonding technology, the bonding force between the lower structure and the upper structure manufactured on different substrates can be increased.

[0032] Figure 2 is a diagram illustrating a memory device.

[0033] Reference Figure 2 , the memory device 100 may include a memory cell array 110 and a peripheral circuit 170 .

[0034] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to j-th memory blocks BLK1 to BLKj, and a bit line BL may be commonly connected to the first to j-th memory blocks BLK1 to BLKj.

[0035] The first to j-th memory blocks BLK1 to BLKj may be formed in a two-dimensional structure or a three-dimensional structure. A memory block having a two-dimensional structure may include memory cells arranged parallel to a substrate. A memory block having a three-dimensional structure may include memory cells stacked in a vertical direction above a substrate. In this embodiment, a memory block formed in a three-dimensional structure is disclosed.

[0036] The memory cell can store one bit or two or more bits of data according to the programming method. For example, the method of storing one bit of data in one memory cell is called a single-level cell method, and the method of storing two bits of data in one memory cell is called a multi-level cell method. The method of storing three bits of data in one memory cell is called a three-level cell method, and the method of storing four bits of data in one memory cell is called a four-level cell method. In addition, five or more bits of data can be stored in one memory cell.

[0037] The peripheral circuit 170 may be configured to perform a program operation for storing data, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control circuit 180.

[0038] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 is configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, and an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0039] The programming voltage is a voltage applied to a selected word line among word lines WL in a programming operation, and can be used to increase the threshold voltage of a memory cell connected to the selected word line. The turn-on voltage can be applied to a drain select line DSL or a source select line SSL, and is used to turn on a drain select transistor or a source select transistor. The cut-off voltage can be applied to a drain select line DSL or a source select line SSL, and is used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage can be set to 0V. Precharge voltages are voltages higher than 0V, and they can be applied to bit lines in a read operation. Verification voltages can be used in a verification operation to determine whether the threshold voltage of a selected memory cell has been increased or decreased to a target level. The verification voltages can be set to various levels according to the target level, and they can be applied to the selected word line.

[0040] A read voltage may be applied to a selected word line in a read operation of a selected memory cell. For example, the read voltage may be set to various levels according to a programming method of the selected memory cell. A pass voltage is a voltage applied to an unselected word line among word lines WL in a programming operation or a read operation, and they may be used to turn on memory cells connected to the unselected word lines.

[0041] The erase voltage may be used in an erase operation for erasing memory cells included in a selected memory block, and is applied to the source line SL.

[0042] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the j-th memory block BLKj through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0043] The page buffer group 140 may include page buffers (not shown) connected to the first to j-th memory blocks BLK1 to BLKj, respectively. Each of the page buffers (not shown) may be connected to the first to j-th memory blocks BLK1 to BLKj through a bit line BL. In a read operation, the page buffer (not shown) may sense a current or voltage of a bit line that varies according to a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and temporarily store the sensed data.

[0044] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL, and it may transmit an enable signal through the column line. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0045] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller to the control circuit 180 through the input / output line I / O, and may transmit data received from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller through the input / output line I / O.

[0046] The control circuit 180 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control a device included in the peripheral circuit 170 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control a device included in the peripheral circuit 170 to perform a read operation of a selected memory block and output read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control a device included in the peripheral circuit 170 to perform an erase operation of a selected memory block.

[0047] Figure 3 is a view illustrating a memory device in which a lower structure and an upper structure are bonded to each other according to one embodiment of the present disclosure.

[0048] Reference Figure 3 , the memory device may include a stacked lower structure D_ST and an upper structure U_ST. The lower structure D_ST may include a first substrate 1SUB, a peripheral circuit 170, and a first pad P1. The upper structure U_ST may include a memory cell array 110 and a second pad P2. The first pad P1 may contact a contact portion of the peripheral circuit 170, and they may be formed of a conductive material. The second pad P2 may contact a contact portion of the memory cell array 110, and they may be formed of a conductive material.

[0049] The first pad P1 and the second pad P2 may be bonded to each other, and each of the interfaces ITF at which the first pad P1 and the second pad P2 are bonded to each other may form a curved surface. For example, the interface ITF of each of the first pads P1 bonded to the second pad P2 may be concave, and the interface ITF of each of the second pads P2 bonded to the first pad P1 may be convex. Alternatively, each of the first pads P1 bonded to the second pad P2 may be convex, and the interface ITF of each of the second pads P2 bonded to the first pad P1 may be concave. Compared to the case where the interface ITF forms a flat surface, when each of the interfaces ITF at which the first pad P1 and the second pad P2 may be bonded to each other forms a curved surface, the bonding area of ​​the first pad P1 and the second pad P2 may be increased. Therefore, the bonding strength between the first pad P1 and the second pad P2 is stronger. Therefore, the bonding force or strength between the lower structure D_ST and the upper structure U_ST may be increased, and the misalignment of the lower structure D_ST and the upper structure U_ST may be reduced.

[0050] In the present embodiment, different planarization processes may be performed on the lower structure D_ST and the upper structure U_ST so that the surface of each first pad P1 and the surface of each second pad P2 have different curved surfaces. Figure 4A and Figure 4B To describe different planarization processes.

[0051] 4A to 4D are views illustrating a method of manufacturing a memory device according to a first embodiment of the present disclosure.

[0052] Reference Figure 4A , the lower structure D_ST may include a first substrate 1SUB and a peripheral circuit 170 stacked on the first substrate 1SUB. The peripheral circuit 170 may include a plurality of transistors, wires, and contacts. The peripheral layer covering the first pad may be exposed to the first surface 1SF, which is the uppermost surface of the peripheral circuit 170. For example, the peripheral layer may be filled between the first pads. The peripheral layer covering the top of the first pad may be exposed through the first surface 1SF until the first planarization process 1CMP is performed. The first pad and the peripheral layer may be formed of different materials.

[0053] The first planarization process 1CMP is a chemical mechanical polishing process and can be performed using a first slurry 1SLR for chemical polishing and a polishing pad PD for mechanical polishing. For example, the first slurry 1SLR can be uniformly coated on the lower structure D_ST, and a constant pressure can be applied to the lower structure D_ST using a rotating polishing pad PD.

[0054] The first planarization process 1CMP may be performed until the first pad located on the bottom of the peripheral layer is exposed. For the surface of each of the first pads to be concave, the first slurry 1SLR used in the first planarization process 1CMP may be made of a composition using the first pad as a target. The first slurry 1SLR using the first pad as a target may be a polishing solution having a polishing speed of the first pad faster than the polishing speed of the peripheral layer. Therefore, when the first pad is exposed while the peripheral layer is polished, polishing may be temporarily performed on each of the first pads until the first planarization process 1CMP ends, and the top surface of each of the first pads may be temporarily polished faster than the peripheral layer by the first slurry 1SLR. Because polishing may be performed faster when the area exposed to the first slurry 1SLR becomes wider, the central portion of each of the first pads is further polished than the edge of each of the first pads, and therefore, the top surface of each of the first pads may become concave.

[0055] Reference Figure 4B, the upper structure U_ST may include a second substrate 2SUB and a memory cell array 110 stacked on the second substrate 2SUB. The memory cell array 110 may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of cell plugs and contacts contacting the plurality of cell plugs. Each of the plurality of cell plugs may include a plurality of memory cells and a selection transistor.

[0056] The peripheral layer covering the second pads may be exposed to the second surface 2SF which is the uppermost surface of the memory cell array 110. For example, the peripheral layer may be filled between the second pads. The peripheral layer covering the top of the second pads may be exposed through the second surface 2SF until before the second planarization process 2CMP is performed. The second pads and the peripheral layer may be formed of different materials.

[0057] The second planarization process 2CMP is a chemical mechanical polishing process and can be performed using a second slurry 2SLR for chemical polishing and a polishing pad PD for mechanical polishing. For example, the second slurry 2SLR can be uniformly coated on the upper structure U_ST, and a constant pressure can be applied to the upper structure U_ST using a rotating polishing pad PD.

[0058] The second planarization process 2CMP may be performed until the second pad located on the bottom of the peripheral layer is exposed. For the surface of each of the second pads to be formed into a convex shape when the second pad is exposed as the peripheral layer is polished, the second slurry 2SLR used in the second planarization process 2CMP may be made of a component using the peripheral layer as a target. The second slurry 2SLR using the peripheral layer as a target may be a polishing solution having a polishing speed of the peripheral layer faster than the polishing speed of the second pad. Therefore, when the second pad is exposed while the peripheral layer is polished, polishing may be further performed on the peripheral layer compared to the second pad until the second planarization process 2CMP ends. Therefore, compared to the central portion of each of the second pads, the edge portion of each of the second pads is polished together with the peripheral layer, and therefore, the top surface of the second pad may become convex.

[0059] Reference Figure 4C , a wafer bonding process can be performed. For example, referring to Figure 4B The described upper structure U_ST can be flipped, and the flipped upper structure U_ST can be stacked on the reference Figure 4A Thus, the first surface 1SF of the lower structure D_ST and the second surface 2SF of the upper structure U_ST may be bonded to each other.

[0060] Reference Figure 4D, because the first surface 1SF of the lower structure D_ST and the second surface 2SF of the upper structure U_ST are bonded to each other, each of the first pads exposed through the first surface 1SF and having a concave curved surface and each of the second pads exposed through the second surface 2SF and having a convex curved surface can be bonded to each other. Because the interface at which the first pad and the second pad are bonded to each other is a curved surface, misalignment of the first pad and the second pad can be prevented. For example, the convex protrusion of the second pad P2 is aligned into the concave recess of the first pad P1. The bonding force or strength can increase as the area of ​​the bonding interface increases. Subsequently, the second substrate 2SUB included in the upper structure U_ST can be removed.

[0061] A detailed structure and a manufacturing method of a portion where a pad is formed in each of the lower structure D_ST and the upper structure U_ST are described below.

[0062] FIG. 5A to FIG. 5G is a view illustrating a method of manufacturing a lower structure of a memory device according to a first embodiment of the present disclosure.

[0063] Reference Figure 5A , the first capping layer 51, the first insulating layer 52, the first barrier layer 53 and the first mask pattern 54 may be sequentially stacked on the lower substructure DSS. The lower substructure DSS may be a partial structure included in the lower structure. For example, the lower substructure DSS may include at least one first contact portion CT1 and at least one first contact insulating layer IS1. In addition, although Figure 5A Although not shown in the figure, the lower substructure DSS may further include a substrate and transistors constituting peripheral circuits.

[0064] The first capping layer 51 may be formed of a nitride layer. For example, the nitride layer may be a silicon nitride layer (SiN). The first insulating layer 52 may be formed of an oxide layer. For example, the oxide layer may be a silicon oxide layer (SiO2). The first barrier layer 53 may be formed of a carbonitride layer. For example, the carbonitride layer may be a silicon carbonitride layer (SiCN). The first mask pattern 54 may include a first opening OP1 exposing a portion of the first barrier layer 53. The first opening OP1 may have a circular, elliptical, rectangular or square layout, and may be formed in the form of a hole or a groove according to the length or aspect ratio in the Y direction or the X direction.

[0065] Reference Figure 5B , can be achieved by passing through the first opening ( Figure 5AThe second opening OP2 is formed by etching a portion of the first barrier layer 53, the first insulating layer 52, and the first covering layer 51 exposed through the first opening OP1. The etching process for forming the second opening OP2 may be performed as an anisotropic dry etching process. In Figure 5B , it is illustrated that the first capping layer 51 is exposed through the bottom surface of the second opening OP2. However, over etching may be performed so that the first contact portion CT1 is exposed.

[0066] Reference Figure 5C , after forming the second opening OP2, the first mask pattern 54 may be removed, and a second mask pattern 55 may be formed on the first barrier layer 53. The second mask pattern 55 may include a third opening OP3 having a width wider than the width of the second opening OP2. The third opening OP3 may have a circular, elliptical, rectangular, or square layout, and may be formed in the form of a hole or a groove according to the length or aspect ratio in the Y direction or the X direction. For example, when the second opening OP2 has a first width W1, the third opening OP3 may have a second width W2 wider than the first width W1. Therefore, the second opening OP2 and a portion of the first barrier layer 53 may be exposed through the third opening OP3. Because the second opening OP2 is exposed through the third opening OP3, the first cover layer 51 exposed through the bottom surface of the second opening OP2 may also be exposed through the third opening OP3.

[0067] Reference Figure 5D , can be removed by etching process through the second opening ( Figure 5C The fourth opening OP4 is formed by exposing a portion of the first barrier layer 53 through the second opening OP2 shown in FIG. The fourth opening OP4 may have a circular, elliptical, rectangular or square layout, and may be formed in the form of a hole or a groove according to a length or aspect ratio in the Y direction or the X direction. An anisotropic dry etching process may be performed as an etching process. In the etching process for forming the fourth opening OP4, a portion of the first covering layer 51 exposed through the second opening OP2 may also be etched, so that a portion of the first contact portion CT1 is exposed.

[0068] Reference Figure 5E After forming the fourth opening OP4, the second mask pattern ( Figure 5D55 shown in ). Subsequently, a first barrier layer 56 may be formed along the surface of the entire structure from which the second mask pattern 55 is removed. The first barrier layer 56 is a layer for increasing the bonding force between the conductive layer for the first pad to be formed in a subsequent process and the layer exposed through the second opening OP2 and the fourth opening OP4 and preventing diffusion, and the material of the first barrier layer 56 may be determined according to the conductive layer for the first pad.

[0069] Reference Fig. 5F , a first conductive layer 57 may be formed on top of the first barrier layer 56. The first conductive layer 57 may be formed such that the second opening OP2 and the fourth opening OP4 are completely filled therewith. The first conductive layer 57 may be formed of copper (Cu).

[0070] Reference Figure 5G , the first planarization process 1CMP may be performed until the first barrier layer 53 is exposed. The first planarization process 1CMP may be similar to the reference Figure 4A The first planarization process 1CMP described above is performed identically. When the first barrier layer 53 is exposed in the first planarization process 1CMP, the first conductive layer ( Fig. 5F 57) and the first barrier layer ( Fig. 5F A portion of the first conductive pattern 57p and the first barrier pattern 56p shown in FIG. 5 is removed, and thus, the first conductive pattern 57p and the first barrier pattern 56p may remain in the second opening OP2 and the fourth opening OP4. The first conductive pattern 57p and the first barrier pattern 56p may become the first pad P1.

[0071] Since the first slurry used in the first planarization process 1CMP is made of a composition using the first conductive pattern 57p as a target, the first conductive pattern 57p may be over-polished even when the first barrier layer 53 is exposed. Therefore, the top surface of the first conductive pattern 57p may have a concave curved surface CC in a direction toward the lower substructure DSS. Therefore, the lower structure D_ST including the first pad P1 may be formed.

[0072] 6A to 6H is a view illustrating a method of manufacturing an upper structure of a memory device according to a first embodiment of the present disclosure.

[0073] Reference Fig. 6A , a second cover layer 61, a second insulating layer 62, and a third mask pattern 63 may be sequentially stacked on the upper substructure USS. The upper substructure USS may be a partial structure included in the upper structure. For example, the upper substructure USS may include at least one second contact portion CT2 and at least one second contact insulating layer IS2. In addition, although not in Fig. 6AAlthough not shown in FIG. 1 , the upper substructure USS may further include cell plugs and gate lines constituting a memory block.

[0074] The second capping layer 61 may be formed of a nitride layer. For example, the nitride layer may be a silicon nitride layer (SiN). The second insulating layer 62 may be formed of an oxide layer. For example, the oxide layer may be a silicon oxide layer (SiO2). The third mask pattern 63 may include a fifth opening OP5 exposing a portion of the second insulating layer 62. The fifth opening OP5 may have a circular, elliptical, rectangular or square layout and may be formed in the form of a hole or a groove according to the length or aspect ratio in the Y direction or the X direction.

[0075] Reference Figure 6B , can be achieved by passing through the fifth opening ( Fig. 6A The second insulating layer 62 and the second cover layer 61 exposed by the third mask pattern (OP5) are sequentially etched to form a sixth opening OP6 exposing the second contact portion CT2. The sixth opening OP6 may have a circular, elliptical, rectangular, or square layout, and may be formed in the form of a hole or a groove according to a length or aspect ratio in the Y direction or the X direction. When the sixth opening OP6 is formed, the third mask pattern (OP5) may be removed. Fig. 6A 63 shown in FIG. 63). When the third mask pattern ( Fig. 6A 63) shown in FIG, a second barrier layer 64 may be formed along the surface of the entire structure including the sixth opening OP6. The second barrier layer 64 is a layer for increasing the bonding force between the conductive layer for the second pad to be formed in a subsequent process and the layer exposed through the sixth opening OP6 and preventing diffusion, and the material of the second barrier layer 64 may be determined according to the conductive layer for the second pad.

[0076] Reference Figure 6C , a second conductive layer 65 may be formed on the second barrier layer 64. The second conductive layer 65 may be formed such that the sixth opening OP6 is completely filled therewith. The second conductive layer 65 may be formed of copper Cu.

[0077] Reference Fig.6D , a sacrificial pattern 66 including a seventh opening OP7 may be formed on the second conductive layer 65. The seventh opening OP7 may have a circular, elliptical, rectangular, or square layout, and may be formed in the form of a hole or a groove according to a length or aspect ratio in the Y direction or the X direction. The sacrificial pattern 66 may be formed of a material having an etching selectivity different from that of the second conductive layer 65. The seventh opening OP7 may be formed in a region where the sixth opening OP6 is located, and may have a width wider than that of the sixth opening OP6.

[0078] Reference Fig. 6E, a third conductive pattern 67 p may be formed in the seventh opening OP7. The third conductive pattern 67 p may be formed of the same material as the second conductive layer 65.

[0079] Reference Fig. 6F , the sacrificial pattern can be removed ( Fig. 6E 66), and a method for removing the second conductive layer ( Fig. 6E 65) and the second barrier layer ( Fig. 6E The second conductive layer ( 64 ) remaining in the lower region of the third conductive pattern 67 p after the etching process Fig. 6E The third conductive pattern 65) shown in FIG. 65 may become the second conductive pattern 65p, and the second barrier layer ( 65 ) remaining in the lower region of the third conductive pattern 67p after the etching process. Fig. 6E 64) shown in FIG. 64 may become a second barrier pattern 64p.

[0080] Since the third conductive pattern 67p is formed of the same material as the second conductive layer 65, after removing the sacrificial pattern 66, the second conductive layer ( Fig. 6E 65) in the etching process shown in FIG. 65, a portion of the third conductive pattern 67p is removed. For example, when removing the second conductive layer ( Fig. 6E 65), the corner CN of the third conductive pattern 67p may be etched further than the central flat surface of the third conductive pattern 67p. Therefore, the shape of the upper corner of the third conductive pattern 67p may be changed from a right angle structure to a curved surface structure.

[0081] Reference Figure 6G , the second barrier pattern 64p, the second conductive pattern 65p, and the third conductive pattern 67p may constitute a second pad P2. Subsequently, a second barrier layer 68 may be formed on the entire structure including the second pad P2. The second barrier layer 68 may be formed of a carbonitride layer. For example, the carbonitride layer may be a silicon carbonitride layer (SiCN).

[0082] Reference Figure 6H , the second planarization process 2CMP may be performed until the third conductive pattern 67p of the second pad P2 is exposed. The second planarization process 2CMP may be performed in the same manner as in the reference Figure 4BThe second planarization process 2CMP described above is performed in the same manner. The second planarization process 2CMP may be performed until the third conductive pattern 67p is exposed. Because the second slurry used in the second planarization process 2CMP is made of a composition using the second barrier layer 68 as a target, the second barrier layer 68 may be over-polished even when the third conductive pattern 67p is exposed. Therefore, the top surface of the third conductive pattern 67p may have a convex curved surface VC in a direction opposite to the upper substructure USS. Therefore, an upper structure U_ST including a second pad P2 may be formed.

[0083] Figure 7 : is a view illustrating a joining structure of a manufactured lower structure and a manufactured upper structure according to the first embodiment of the present disclosure.

[0084] Reference Figure 7 , refer to Figure 6H The described upper structure U_ST can be turned over, and the turned over upper structure U_ST can be joined to the reference Figure 5G The top of the lower structure D_ST described. Therefore, the first pad P1 of the lower structure D_ST and the second pad P2 of the upper structure U_ST can be bonded to each other, and the first barrier layer 53 of the lower structure D_ST and the second barrier layer 68 of the upper structure U_ST can be bonded to each other. Because the first pad P1 has a concave curved surface and the second pad P2 has a convex surface, misalignment can be prevented when the lower structure D_ST and the upper structure U_ST are bonded to each other. For example, the convex upper second pad P2 is guided by the curvature of the lower first pad P1 to fit into the recess formed by the concave lower first pad P1 at the correct lateral position. After the lower structure D_ST and the upper structure U_ST are bonded to each other, a heat treatment process can be further performed to increase the bonding force. When the heat treatment process is performed, the bonding force between the first barrier layer 53 and the second barrier layer 68 can be increased, and the bonding force between the first pad P1 and the second pad P2 can also be increased.

[0085] Because the interface ITF at which the first pad P1 and the second pad P2 are bonded to each other is a curved surface, the bonding area of ​​the first pad P1 and the second pad P2 can become larger than when the interface ITF is a flat surface. Therefore, the bonding force between the first pad P1 and the second pad P2 can be increased. The first covering layer 51, the first insulating layer 52, and the first barrier layer 53 included in the lower structure D_ST may constitute a first peripheral layer 1PeL surrounding the first pad P1, but the embodiments of the present disclosure are not limited to the first peripheral layer 1PeL. For example, the first peripheral layer 1PeL may be formed as a single layer having an insulating component. The second covering layer 61, the second insulating layer 62, and the second barrier layer 68 included in the upper structure U_ST may constitute a second peripheral layer 2PeL surrounding the second pad P2, but the embodiments of the present disclosure are not limited to the second peripheral layer 2PeL and the upper substructure USS.

[0086] Figure 8 is a view illustrating another embodiment of the lower structure and the upper structure.

[0087] Reference Figure 8 , the lower structure D_ST may include a first substrate 1SUB, a transistor TR, a contact portion CT, a connection line CNL, an interlayer insulating layer ITS, and a first pad P1. The first substrate 1SUB may be a silicon substrate, and the transistor TR, the contact portion CT, and the connection line CNL may be disposed on the first substrate 1SUB. The first pad P1 may be in contact with the top of some of the contact portions CT. The interlayer insulating layer ITS may be formed between the transistor TR, the connection line CNL, and the first pad P1. The top surface of each of the first pads P1 may have a concave curved surface.

[0088] The upper structure U_ST may include a second pad P2, a contact portion CT, a bit line BL, a cell plug CP, a gate line GL, an insulating layer IS, and a source line SL. For example, the insulating layer IS, the gate line GL, and the source line SL may be stacked on the interlayer insulating layer ITS of the lower structure D_ST. The cell plug CP may penetrate a portion of the source line SL, the insulating layer IS, and the gate line GL, and be electrically connected to the bit line BL through the contact portion CT. The second pad P2 may be bonded to the top of the first pad P1, and the second pad P2 and the bit line BL may be electrically connected to each other through the contact portion CT. The bit line BL and the second pad P2 may be connected to each other through the contact portion CT, and may be connected to each other in different regions according to the layout.

[0089] The cell plug CP may include a drain selection transistor, a memory cell, and a source selection transistor. The gate line GL may include a drain selection line connected to the drain selection transistor, a word line connected to the memory cell, and a source selection line connected to the source selection transistor. The top of the cell plug CP may contact the source line SL.

[0090] exist Figure 8 In the structure shown, the interface where the first pad P1 and the second pad P2 are bonded to each other may also form a curved surface.

[0091] Fig. 9 is a view illustrating a memory device according to a second embodiment of the present disclosure.

[0092] Reference Fig. 9 In the second embodiment of the present disclosure, the first pad P1 may have a convex curved surface, and the second pad P2 may have a concave surface. For example, the planarization process in the process of forming the first pad P1 included in the lower structure D_ST may be used as a reference. Figure 4B The second planarization process 2CMP described above is performed. The planarization process in the process of forming the second pad P2 included in the upper structure U_ST can be used as a reference. Figure 4A The first planarization process 1CMP described above is performed. Therefore, the surface of the first pad P1 can form a convex curved surface in the direction toward the upper structure U_ST, and the surface of the second pad P2 can form a concave curved surface in the direction opposite to the lower structure D_ST. Therefore, the interface where the first pad P1 and the second pad P2 are bonded to each other can form a curved surface. Therefore, the bonding force between the first pad P1 and the second pad P2 can be increased, and misalignment can be prevented.

[0093] Fig.10 is a diagram illustrating a memory card system 3000 to which the memory device of the present disclosure is applied.

[0094] Reference Fig.10 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0095] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a programming operation, a read operation, or an erase operation of the memory device 3200, or control a background operation. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0096] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller 3100 can communicate with an external device (e.g., a host) through at least one of various communication protocols such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics device (IDE), firewire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication protocols mentioned above.

[0097] The memory device 3200 may include a memory cell and is configured to Figure 2 The memory device 100 shown in FIG.

[0098] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC, and eMMC), an SD card (SD, mini SD, micro SD, and SDHC), or a universal flash storage (UFS).

[0099] Fig.11 is a diagram illustrating a solid state drive (SSD) system 4000 to which the memory device of the present disclosure is applied.

[0100] Reference Fig.11 , the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001 and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0101] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0102] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be configured to Figure 2 The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0103] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive power PWR input from the host 4100 and charge the power PWR. When the power supply from the host 4100 is not stable, the auxiliary power supply 4230 may provide power to the SSD 4200. The auxiliary power supply 4230 may be located in the SSD 4200, or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and provide auxiliary power to the SSD 4200.

[0104] The buffer memory 4240 may operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0105] According to the present disclosure, when a lower structure and an upper structure manufactured on different substrates are bonded to each other, a bonding force between the lower structure and the upper structure may be increased, and misalignment between the lower structure and the upper structure may be prevented.

[0106] Although the present disclosure has been shown and described with reference to certain embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0107] In the above-mentioned embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed according to the described order and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0108] In addition, the embodiments of the present disclosure are described in the drawings and the specification. Although specific terms are used here, these terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and there may be many changes in the spirit and scope of the present disclosure. It is obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0109] CROSS-REFERENCE TO RELATED APPLICATIONS

[0110] This application claims the priority of Korean Patent Application No. 10-2023-0097344 filed on July 26, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a lower structure comprising a first pad exposed through a top surface of the lower structure; as well as an upper structure including a second pad exposed through a bottom surface of the upper structure, wherein the first pad and the second pad are bonded to each other, and The interface where the first pad and the second pad are bonded to each other forms a curved surface.

2. The memory device according to claim 1, wherein: The top surface of the first pad has a concave curved surface, and Wherein, the bottom surface of the second pad has a convex curved surface.

3. The memory device according to claim 1, wherein: The top surface of the first pad has a convex curved surface, and Wherein, the bottom surface of the second pad has a concave curved surface.

4. The memory device according to claim 1, wherein: The lower structure comprises: substrate; and A peripheral circuit is located on the substrate, wherein the peripheral circuit is in contact with the first pad.

5. The memory device according to claim 4, wherein: The peripheral circuit includes a transistor, a contact portion and a connecting line, Some of the contact portions are in contact with the first pad and some of the connection lines, and Some of the contact portions are in contact with the transistor.

6. The memory device according to claim 1, wherein: The upper structure includes a memory block contacting the second pad.

7. The memory device according to claim 6, wherein: The storage block comprises: a bit line, the bit line being located above the second pad; a gate line, the gate line being located above the bit line, the gate lines being stacked to be spaced apart from each other; a source line, the source line being located above the gate line; and a cell plug, the cell plug being located between the source line and the bit line while penetrating the gate line, and The bit line contacts the second pad through a contact portion.

8. The memory device according to claim 1, wherein: The second pad includes the same material as the first pad.

9. The memory device according to claim 1, wherein: The first pad and the second pad include a conductive material.

10. The memory device of claim 1, further comprising: a first peripheral layer, the first peripheral layer being included in the lower structure, the first peripheral layer surrounding the first pad; as well as a second peripheral layer, the second peripheral layer being included in the upper structure, the second peripheral layer surrounding the second pad, Wherein, the first outer layer and the second outer layer are bonded to each other.

11. A method of manufacturing a memory device, the method comprising the steps of: forming a first peripheral layer on the first substrate; forming a first opening in the first peripheral layer; forming a first conductive layer for a first pad on the first opening and the first peripheral layer; performing a first planarization process on the first conductive layer using a first slurry targeting the first conductive layer until the first peripheral layer is exposed; forming a second conductive pattern for a second pad on a second substrate; forming a second peripheral layer on the second pad and the second substrate; performing a second planarization process on the second peripheral layer using a second slurry targeting the second peripheral layer until the second conductive pattern is exposed; as well as The second substrate is turned over so that the second conductive pattern is located on a bottom surface of the second substrate, and the second conductive pattern is allowed to be bonded to the first conductive layer.

12. The method according to claim 11, wherein: The first planarization process comprises: coating the first slurry on the first conductive layer; and A constant pressure is applied to the first conductive layer coated with the first slurry using a rotating polishing pad.

13. The method according to claim 11, wherein: The second planarization process includes: coating the second slurry on the second outer layer; and A constant pressure is applied to the second peripheral layer coated with the second slurry using a rotating polishing pad.

14. The method according to claim 11, wherein: The step of forming the second conductive pattern comprises: forming a sacrificial pattern including a second opening on the second substrate; forming the second conductive pattern in the second opening; and The sacrificial pattern is removed. 15 . The method according to claim 11 , further comprising forming a first barrier layer along a surface of an entire structure including the first opening before forming the first conductive layer for the first pad.

16. The method according to claim 15, wherein: In the first planarization process, the first barrier layer formed on the first peripheral layer is removed.

17. The method according to claim 11, wherein: The second conductive pattern and the first conductive layer are formed of the same material.

18. The method according to claim 11, wherein: The first conductive layer and the second conductive pattern are formed of a conductive material. 19 . The method of claim 11 , further comprising stacking a second barrier pattern and a third conductive pattern for the second pad on the second substrate before forming the second conductive pattern.

20. The method according to claim 19, wherein: The third conductive pattern is formed of the same material as the second conductive pattern.

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