Phase change memory and method for forming the same

Abstract

This disclosure provides a phase-change memory and a method for forming the same. The phase-change memory includes: a first conductive line, a second conductive line, and a memory cell located between the first conductive line and the second conductive line in a first direction; the memory cell extends along the first direction; the first conductive line extends along a second direction and is connected to a plurality of memory cells arranged along the second direction; the second conductive line extends along a third direction and is connected to a plurality of memory cells arranged along the third direction; the second direction intersects the third direction and is perpendicular to the first direction; a first isolation structure is located between two adjacent memory cells in the third direction and between the first conductive lines respectively connected to the two adjacent memory cells in the third direction; the thermal conductivity of the first isolation structure is in the range of 0.08 W / (m·K) to 0.12 W / (m·K).

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a phase-change memory and a method for forming the same. Background Technology

[0002] Phase-change memory (PCM), as an emerging non-volatile memory device, possesses significant advantages in many aspects, including read / write speed, read / write cycles, data retention time, cell area, and multi-value implementation. However, with the increasing integration density of PCM, there is a need to further improve the reliability of PCM data storage and retrieval. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a phase-change memory and a method for forming the same.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a phase-change memory, including:

[0006] A first conductive line, a second conductive line, and a storage cell located between the first conductive line and the second conductive line in a first direction; the storage cell extends along the first direction; the first conductive line extends along a second direction and connects to a plurality of storage cells arranged along the second direction; the second conductive line extends along a third direction and connects to a plurality of storage cells arranged along the third direction; the second direction intersects the third direction and is perpendicular to the first direction.

[0007] A first isolation structure is located between two adjacent memory cells in the third direction and between first conductive lines connected to the two adjacent memory cells in the third direction; the thermal conductivity of the first isolation structure is in the range of 0.08 W / (m·K) to 0.12 W / (m·K).

[0008] In one alternative implementation, the first isolation structure comprises polyimide.

[0009] In one optional implementation, the phase-change memory further includes:

[0010] A second isolation structure is located between two adjacent memory cells in the second direction and between the second conductive lines that are respectively connected to the two adjacent memory cells in the second direction; the thermal conductivity of the second isolation structure is greater than that of the first isolation structure.

[0011] In one alternative embodiment, the thermal conductivity of the second insulating structure ranges from 0.2 W / (m·K) to 0.28 W / (m·K).

[0012] In one alternative implementation, the second isolation structure extends along the third direction and is located between two adjacent first isolation structures in the second direction.

[0013] In one optional implementation, the storage unit includes:

[0014] A first electrode, a gating element, a second electrode, a phase change element, and a third electrode are stacked sequentially along the first direction; the first electrode is located between the gating element and the first conductive line; the third electrode is located between the phase change element and the second conductive line.

[0015] In one optional implementation, the phase-change memory further includes:

[0016] A third isolation structure and a fourth isolation structure; the third isolation structure covers the phase change element and the third electrode of the memory cell on the same side of the opposite sides of the third third upward direction; the fourth isolation structure covers the third isolation structure, the second electrode, the gating element, the first electrode, and the first conductive line connected to the memory cell on the same side of the opposite sides of the third third upward direction; the fourth isolation structure is located between the first isolation structure and the third isolation structure.

[0017] In one optional embodiment, the third isolation structure includes a first dielectric layer and a second dielectric layer; the second dielectric layer is located between the first dielectric layer and the fourth isolation structure; the first dielectric layer and the fourth isolation structure include silicon nitride; the second dielectric layer includes silicon oxide.

[0018] Secondly, embodiments of this disclosure provide a method for forming a phase-change memory, comprising:

[0019] A first conductive line extending along the second direction is formed;

[0020] A memory cell is formed on one of the opposite sides of the first conductive line along a first direction; the memory cell extends along the first direction; one of the first conductive lines is connected to a plurality of memory cells arranged along a second direction;

[0021] A first isolation structure is formed; the first isolation structure is located between two adjacent memory cells in the third direction and between the first conductive lines respectively connected to the two adjacent memory cells in the third direction; the thermal conductivity of the first isolation structure is in the range of 0.08 W / (m·K) to 0.12 W / (m·K); the second direction intersects the third direction and is perpendicular to the first direction.

[0022] A second conductive line extending along the third direction is formed on one side of the storage cell opposite to the first conductive line along the first direction; one of the second conductive lines is connected to a plurality of the storage cells arranged along the third direction.

[0023] In one optional embodiment, the storage cell includes a first electrode, a gating element, a second electrode, a phase change element, and a third electrode stacked sequentially along the first direction; the first electrode is located between the gating element and the first conductive line; forming the first isolation structure includes:

[0024] A first initial isolation structure is formed by spin coating between two adjacent memory cells in the third direction and filling the space between the first conductive lines connected to the two adjacent memory cells in the third direction with an insulating material; the top surface of the first initial isolation structure is located between the top and bottom surfaces of the third electrode in the first direction.

[0025] The first initial isolation structure is etched to form a second initial isolation structure, the top surface of the second initial isolation structure being located between the top and bottom surfaces of the phase change element in the first direction;

[0026] The isolation material is filled into the second initial isolation structure by the spin coating process to form the first isolation structure.

[0027] In the technical solution provided in this disclosure, the phase change memory includes a first isolation structure located between two adjacent memory cells in the third direction and between a first conductive line connecting the two adjacent memory cells in the third direction. The thermal conductivity of the first isolation structure ranges from 0.08 W / (m·K) to 0.12 W / (m·K), and is less than the thermal conductivity of the second isolation structure located between two adjacent memory cells in the second direction. As a result, the degree of heat transfer along the third direction can be reduced when a reset operation is performed on the selected memory cell, thereby mitigating thermal crosstalk to the non-selected memory cells adjacent to the selected memory cell in the third direction. Attached Figure Description

[0028] Figure 1A three-dimensional structural diagram of a portion of the phase-change memory provided in an embodiment of this disclosure;

[0029] Figure 2 A top view of a partial structure of a phase-change memory provided in a disclosed embodiment;

[0030] Figure 3 for Figure 2 Cross-sectional view along line AA';

[0031] Figure 4 for Figure 3 Enlarged schematic diagram of the middle section structure;

[0032] Figure 5 for Figure 2 Cross-sectional view along line BB';

[0033] Figure 6 A schematic flowchart illustrating the formation process of a phase-change memory provided in an embodiment of this disclosure;

[0034] Figures 7 to 12 This is a schematic diagram of the phase change memory formation process provided in an embodiment of the present disclosure. Detailed Implementation

[0035] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0038] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] Phase-change memory (PCM), as an emerging non-volatile memory device, possesses significant advantages in many aspects, including read / write speed, read / write cycles, data retention time, cell area, and multi-value implementation. However, with the increasing integration density of PCM, there is a need to further improve the reliability of PCM data storage and retrieval.

[0041] Figure 1 This is a three-dimensional structural diagram of a portion of the phase-change memory provided in the embodiments of this disclosure, such as... Figure 1 As shown, the phase-change memory includes a first conductive line 121, a second conductive line 122, and a memory cell 100 located between the first conductive line 121 and the second conductive line 122 in a first direction. The memory cell 100 extends along the first direction, the first conductive line 121 extends along a second direction and connects to a plurality of memory cells 100 arranged along the second direction, and the second conductive line 122 extends along a third direction and connects to a plurality of memory cells 100 arranged along the third direction. Here, the first direction is taken as the Z direction, the second direction as the X direction, and the third direction as the Y direction as an example.

[0042] In some embodiments, the storage unit 100 includes a first electrode 101, a gating element 102, a second electrode 103, a phase change element 104, and a third electrode 105 arranged sequentially along a first direction, wherein the first electrode 101 is located between the first conductive line 121 and the gating element 102, and the third electrode 105 is located between the phase change element 104 and the second conductive line 122.

[0043] In some specific examples, the first conductive line 121 can be a bit line (BL), and the third electrode 105 is connected to the second conductive line 122, which can be a word line (WL).

[0044] In some specific examples, the first conductive line 121 and the second conductive line 122 may include conductive materials. Here, the conductive material may be at least one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., tungsten, titanium, tantalum, aluminum, copper, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0045] In some specific examples, the first electrode 101, the second electrode 103, and the third electrode 105 may include conductive materials and may serve as conductive paths.

[0046] In some specific examples, the second electrode 103 may also include a thermally insulating material, thereby reducing thermal crosstalk between the gating element 102 and the phase change element 104. For example, the second electrode 103 may include amorphous carbon.

[0047] In some specific examples, the resistance of the gating element 102 can vary in response to a change in the selection voltage applied between the first electrode 101 and the second electrode 103. In some embodiments, the gating element 102 may comprise a material having an omnidirectional threshold switch (OTS) property. The material having the OTS property may include at least one element selected from oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as Zn. x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te zWhen the voltage applied between the first electrode 101 and the second electrode 103 is lower than its threshold voltage, the gating element 102 can be in a high-resistance state that prevents current from flowing through, and when the voltage applied between the first electrode 101 and the second electrode 103 is higher than its threshold voltage, the gating element 102 can be in a low-resistance state that allows current to flow through.

[0048] In some specific examples, the phase change element 104 may include a chalcogenide component, such as at least one of binary compounds such as GaSb, InSb, InSe, SbTe and GeTe, ternary compounds such as GeSbTe, GaSeTe, InSbTe, SnSbTe and InSbGe, and quaternary compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and TeGeSbS.

[0049] In some specific examples, the phase change element 104 can reversibly switch between a crystalline and amorphous state, and data storage can be achieved by utilizing the difference in resistivity between its crystalline and amorphous states. Specifically, the crystalline phase of the phase change element 104 can be changed by the Joule heat generated by the voltage applied between the second electrode 103 and the third electrode 105, causing it to crystallize or amorphize, thereby changing the resistance of the phase change element 104 and thus changing the data stored in the phase change storage unit 100. When the phase change element 104 is in the crystalline state, the storage unit 100 is in the set state, and the data stored in the storage unit 100 can be either "0" or "1". When the phase change element 104 is in the amorphous state, the storage unit 100 is in the reset state, and the data stored in the storage unit 100 can be either "0" or "1".

[0050] Since the amorphization of the phase change element 104 requires a higher temperature, when the memory cell 100 needs to be converted to a reset state, a larger voltage needs to be applied between the second electrode 103 and the third electrode 105 to generate a larger current and more heat. During this process, heat may be transferred to the non-selected memory cell adjacent to the selected memory cell, which may cause thermal crosstalk to the non-selected memory cell adjacent to the selected memory cell, causing the crystal phase of the phase change element in the non-selected memory cell to change. For example, if the non-selected memory cell is in a reset state, the part of the amorphous phase change element close to the selected memory cell may be converted to a crystalline state after being heated. This may cause misreading when performing a read operation on the non-selected memory cell, thereby reducing the reliability of the phase change memory storing data.

[0051] Therefore, it is necessary to reduce thermal crosstalk between adjacent memory cells to improve the reliability of phase-change memory. The present disclosure proposes the following implementation methods to address this.

[0052] Figure 2 This is a top view of a partial structure of a phase-change memory provided in a disclosed embodiment. Figure 3 for Figure 2 Cross-sectional view along line AA' Figure 4 for Figure 3 Enlarged schematic diagram of the middle part of the structure, in conjunction with reference Figures 1 to 4 The phase-change memory includes: a first conductive line 121, a second conductive line 122, and a memory cell 100 located between the first conductive line 121 and the second conductive line 122 in a first direction; the memory cell 100 extends along the first direction; the first conductive line 121 extends along a second direction and is connected to a plurality of memory cells 100 arranged along the second direction; the second conductive line 122 extends along a third direction and is connected to a plurality of memory cells 100 arranged along the third direction; a first isolation structure 201 is located between two adjacent memory cells 100 in the third direction and between the first conductive lines 121 respectively connected to the two adjacent memory cells 100 in the third direction; the thermal conductivity of the first isolation structure 201 ranges from 0.08 W / (m·K) to 0.12 W / (m·K).

[0053] In this embodiment, the second direction intersects with the third direction and is perpendicular to the first direction. Here, we take the first direction as the Z direction, the second direction as the X direction, and the third direction as the Y direction as an example.

[0054] In some specific examples, the first isolation structure 201 includes polyimide.

[0055] In one specific example, the thermal conductivity of polyimide is approximately 0.1 W / (m·K).

[0056] In some embodiments, Figure 5 for Figure 2 Cross-sectional view along line BB', in conjunction with reference Figure 2 and Figure 5 The phase-change memory further includes a second isolation structure 202, which is located between two adjacent memory cells 100 in the second direction and between second conductive lines 122 that are respectively connected to the two adjacent memory cells 100 in the second direction; the thermal conductivity of the second isolation structure 202 is greater than that of the first isolation structure 201.

[0057] In some embodiments, refer to Figure 2 The second isolation structure 202 extends along a third direction and is located between two adjacent first isolation structures 201 in the second direction.

[0058] In some specific examples, the thermal conductivity of the second isolation structure 202 ranges from 0.2 W / (m·K) to 0.28 W / (m·K).

[0059] In a specific example, the second isolation structure 202 includes SixOyCz, wherein the ratio of x, y, and z makes the thermal conductivity of the second isolation structure 202 approximately 0.25 W / (m·K).

[0060] In some embodiments, in conjunction with reference Figure 3 and Figure 4 The storage unit 100 includes: a first electrode 101, a gating element 102, a second electrode 103, a phase change element 104, and a third electrode 105 stacked sequentially along a first direction; the first electrode 101 is located between the gating element 102 and the first conductive line 121; the third electrode 105 is located between the phase change element 104 and the second conductive line 122. The specific material composition of the storage unit 100 can be referred to the aforementioned... Figure 1 For the sake of brevity, the description will not be repeated here.

[0061] In some specific examples, in conjunction with reference Figure 3 and Figure 4 The phase-change memory further includes a first adhesion layer 106 located between the first conductive line 121 and the first electrode 101, and a second adhesion layer 107 located between the second conductive line 122 and the third electrode 105. Both the first adhesion layer 106 and the second adhesion layer 107 may comprise metal nitrides, such as titanium nitride. The first adhesion layer 106 can improve the adhesion between the first conductive line 121 and the first electrode 101 and reduce the contact resistance, while the second adhesion layer 107 can improve the adhesion between the second conductive line 122 and the third electrode 105 and reduce the contact resistance.

[0062] In some embodiments, refer to Figure 4 The phase-change memory further includes a third isolation structure 203 and a fourth isolation structure 204. The third isolation structure 203 covers the same side of the phase-change element 104 and the third electrode 105 of the memory cell 100 on opposite sides in the third direction. The fourth isolation structure 204 covers the same side of the third isolation structure 203, the second electrode 103, the gating element 102, the first electrode 101, and the first conductive line 121 connected to the memory cell 100 on opposite sides in the third direction. The fourth isolation structure 204 is located between the first isolation structure 201 and the third isolation structure 203. Here, the memory cell 100 and the first conductive line 121 connected to the memory cell 100 are provided with the third isolation structure 203 and the fourth isolation structure 204 on opposite sides in the third direction. Both the third isolation structure 203 and the fourth isolation structure 204 include dielectric material and can serve as sidewall protection, preventing cross-contamination between different material layers.

[0063] In some specific examples, such as Figure 4As shown, the third isolation structure 203 includes a first dielectric layer 2031 and a second dielectric layer 2032, and the fourth isolation structure 204 is a single-layer structure. The first dielectric layer 2031 and the fourth isolation structure 204 may include silicon nitride, and the second dielectric layer 2032 may include silicon oxide.

[0064] In some specific examples, refer to Figure 5 The phase-change memory also includes a fifth isolation structure 205 and a sixth isolation structure 206. Both the fifth isolation structure 205 and the sixth isolation structure 206 include dielectric material and can serve as sidewall protection to prevent cross-contamination between different material layers. Specifically, the fifth isolation structure 205 covers the phase-change element 104, the third electrode 105, and the second conductive line 122 connected to the storage unit 100 on the same side of opposite sides in the second direction. The sixth isolation structure 206 covers the fifth isolation structure 205, the second electrode 103, the gating element 102, and the first electrode 101 on the same side of opposite sides in the second direction, and the sixth isolation structure 206 is located between the second isolation structure 202 and the fifth isolation structure 205. The fifth isolation structure 205 includes a third dielectric layer 2051 and a fourth dielectric layer 2052, and the sixth isolation structure 206 includes a fifth dielectric layer 2061 and a sixth dielectric layer 2062. The third dielectric layer 2051 and the fifth dielectric layer 2061 may include silicon nitride, and the fourth dielectric layer 2052 and the sixth dielectric layer 2062 may include silicon oxide.

[0065] Combined with reference Figure 4 and Figure 5 The second conductive line 122 and the storage cell 100 are both covered with four dielectric layers on their respective sidewalls in the second direction, and the dielectric layers have high thermal conductivity. However, the first conductive line 121 is only covered with one dielectric layer on its respective sidewalls in the third direction. Therefore, when a reset operation is performed on the selected storage cell, heat is easily transferred along the third direction to the non-selected storage cell that is adjacent to the selected storage cell in the third direction.

[0066] In related embodiments, the first isolation structure and the second isolation structure include materials with similar thermal conductivity. In this case, when a reset operation is performed on the selected memory cell, most of the heat will be transferred along the third direction, that is, the extension direction of the second conductive line, to the non-selected memory cell adjacent to the selected memory cell in the third direction, and cause more serious thermal crosstalk to the non-selected memory cell, causing a partial phase change of the phase change element in the non-selected memory cell, thereby reducing the reliability of its stored data.

[0067] In this embodiment of the disclosure, the phase change memory includes a first isolation structure 201 located between two adjacent memory cells 100 in the third direction and between a first conductive line 121 connected to the two adjacent memory cells 100 in the third direction. The thermal conductivity of the first isolation structure 201 ranges from 0.08 W / (m·K) to 0.12 W / (m·K), and is less than the thermal conductivity of the second isolation structure 202 located between two adjacent memory cells 100 in the second direction. As a result, the degree of heat transfer along the third direction can be reduced when a reset operation is performed on the selected memory cell, and thermal crosstalk to the non-selected memory cells adjacent to the selected memory cell in the third direction can be mitigated.

[0068] It should be noted that, in this embodiment, the thermal conductivity of the first isolation structure 201 is greater than a lower limit even if it is less than an upper limit. This is because an excessively low thermal conductivity of the first isolation structure 201 may cause excessive heat transfer along the second direction, resulting in thermal crosstalk to non-selected memory cells adjacent to the selected memory cell in the second direction. By limiting the thermal conductivity of the first isolation structure 201 within a suitable range and appropriately reducing its thermal conductivity, heat transfer in both the second and third directions can be balanced, thereby reducing thermal crosstalk between memory cells in the phase-change memory and improving the reliability of the phase-change memory.

[0069] The above embodiment takes a phase change memory including a layer of memory cells arranged in an array along a second direction and a third direction as an example. In other embodiments, the phase change memory may include multiple memory layers stacked along a first direction, and each memory layer includes a first conductive line, a second conductive line, and a memory cell located between the first conductive line and the second conductive line in the first direction, as well as a first isolation structure located between two adjacent memory cells and between the first conductive lines respectively connected to the two adjacent memory cells, and the thermal conductivity of the first isolation structure is in the range of 0.08 W / (m·K) to 0.12 W / (m·K).

[0070] Based on a concept similar to the phase-change memory described above, this disclosure also provides a method for forming a phase-change memory. Figure 6 A schematic flowchart illustrating the formation process of the phase-change memory provided in this embodiment of the disclosure is shown below. Figure 6 As shown, the method for forming a phase-change memory includes the following steps:

[0071] Step S10: Form a first conductive line extending along the second direction;

[0072] Step S20: A memory cell is formed on one side of the first conductive line along the first direction; the memory cell extends along the first direction; one of the first conductive lines is connected to a plurality of memory cells arranged along the second direction;

[0073] Step S30: Form a first isolation structure; the first isolation structure is located between two adjacent memory cells in the third direction and between the first conductive lines respectively connected to the two adjacent memory cells in the third direction; the thermal conductivity of the first isolation structure is in the range of 0.08 W / (m·K) to 0.12 W / (m·K); the second direction intersects the third direction and is perpendicular to the first direction;

[0074] Step S40: A second conductive line extending along the third direction is formed on the side of the storage cell opposite each other along the first direction that is away from the first conductive line; one of the second conductive lines is connected to a plurality of storage cells arranged along the third direction.

[0075] Figures 7 to 12 This is a schematic diagram of the formation process of the phase-change memory provided in the embodiments of this disclosure. The following will be combined with... Figures 6 to 12 The method for forming a phase-change memory provided in the embodiments of this disclosure will be described.

[0076] In some embodiments, refer to Figure 7 The specific process of performing step S10 may include: forming a first conductive line 121 extending along a second direction on the substrate 300, wherein the substrate 300 may include a contact structure and a pad connected to the contact structure, and the contact structure may include a bit line contact structure connected to the first conductive line 121. Here, the structure of the substrate 300 is only an example, and this disclosure does not impose specific limitations on it.

[0077] In some embodiments, the specific process of performing step S20 may include: forming a storage cell 100 on the side of the first conductive line 121 opposite to each other along the first direction away from the substrate 300, the storage cell 100 extending along the first direction and including a first electrode 101, a gating element 102, a second electrode 103, a phase change element 104 and a third electrode 105 stacked sequentially along the first direction, and a first conductive line 121 connected to a plurality of storage cells 100 arranged along the second direction.

[0078] In some specific examples, the process of forming the first conductive line 121 may include: forming a conductive layer on the substrate 300 by a deposition process, and etching the conductive layer to divide the conductive layer into a plurality of first conductive lines 121 extending along a second direction and arranged along a third direction. The process of forming the memory cell 100 may include: forming a stacked structure by a deposition process, the stacked structure including a plurality of material layers stacked along a first direction, and etching the stacked structure along the second and third directions respectively to divide the stacked structure into a plurality of memory cells 100 arranged in an array along the second and third directions, and a sacrificial layer 123 located on the memory cell 100. Figure 7 As shown, during the etching process described above, a trench extending into the substrate 300 along the first direction can be formed.

[0079] In the embodiments disclosed herein, the deposition processes include, but are not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0080] In the embodiments disclosed herein, the etching process can be a dry etching process, including but not limited to plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE).

[0081] In some embodiments, in conjunction with reference Figure 4 and Figure 7 The method of forming a phase-change memory further includes: forming a third isolation structure 203, the third isolation structure 203 covering the same side of the phase-change element 104 and the third electrode 105 of the memory cell 100 on the opposite sides of the third direction; and a fourth isolation structure 204 covering the same side of the third isolation structure 203, the second electrode 103, the gating element 102, the first electrode 101, and the first conductive line 121 connected to the memory cell 100 on the opposite sides of the third direction.

[0082] In some embodiments, in conjunction with reference 7 and Figure 8The specific process of executing step S30 may include: filling the space between two adjacent storage cells 100 in the third direction and between the first conductive lines 121 connected to the two adjacent storage cells 100 in the third direction with an insulating material to form a first initial isolation structure 210; the top surface of the first initial isolation structure 210 is located between the top and bottom surfaces of the third electrode 105 in the first direction.

[0083] In some embodiments, in conjunction with reference Figure 8 and Figure 9 The specific process of performing step S30 may include: etching the first initial isolation structure 210 to form a second initial isolation structure 211, wherein the top surface of the second initial isolation structure 211 is located between the top and bottom surfaces of the phase change element 104 in the first direction.

[0084] In some embodiments, in conjunction with reference Figures 9 to 11 The specific process of performing step S30 may include: filling the second initial isolation structure 211 with isolation material through a spin coating process to form the first isolation structure 201. Specifically, as... Figure 10 As shown, in order to fully fill the gap between two adjacent storage cells 100 in the third-order upward direction with isolation material, a third initial isolation structure 212 can be formed after filling the second initial isolation structure 211 with isolation material. The top surface of the third initial isolation structure 212 can be higher than the top surface of the sacrificial layer 123. Figure 11 As shown, excess isolation material can be removed by chemical mechanical polishing and / or etching processes, and the remaining isolation material constitutes the first isolation structure 201.

[0085] In some specific examples, the thermal conductivity of the first isolation structure 201 formed by the above method ranges from 0.08 W / (m·K) to 0.12 W / (m·K).

[0086] In one specific example, the first isolation structure 201 comprises polyimide with a thermal conductivity of approximately 0.1 W / (m·K).

[0087] In this embodiment of the disclosure, refer to Figure 8 and Figure 9When filling the space between two adjacent memory cells 100 with an isolation material through spin coating, the small spacing between the adjacent memory cells 100 may cause voids due to the high viscosity of the filling material. In this case, by first forming a first initial isolation structure 210 and then etching the first initial isolation structure 210, the voids in the first initial isolation structure 210 can be opened. Then, the isolation material can be filled on the second initial isolation structure 211, thereby reducing the voids in the final first isolation structure 201 and improving the reliability of the first isolation structure 201.

[0088] In some embodiments, in conjunction with reference Figure 11 and Figure 12 The specific process of executing step S40 may include: forming a second conductive line 122 extending along a third direction on one side of the storage cell 100 away from the first conductive line 121 on opposite sides along the first direction; and connecting a second conductive line 122 to a plurality of storage cells 100 arranged along the third direction.

[0089] In some embodiments, the method of forming a phase change memory may further include: forming a second isolation structure 202, the second isolation structure 202 being located between two adjacent memory cells 100 in a second direction and between second conductive lines 122 respectively connected to the two adjacent memory cells 100 in the second direction; the thermal conductivity of the second isolation structure 202 is greater than the thermal conductivity of the first isolation structure 201.

[0090] In some specific examples, the second isolation structure 202 can be formed by spin coating, and the thermal conductivity of the second isolation structure ranges from 0.2 W / (m·K) to 0.28 W / (m·K).

[0091] In a specific example, the second isolation structure 202 includes SixOyCz, wherein the ratio of x, y, and z makes the thermal conductivity of the second isolation structure 202 approximately 0.25 W / (m·K).

[0092] In this embodiment of the disclosure, the phase change memory formed by the above-described forming method includes a first isolation structure located between two adjacent memory cells in the third direction and between a first conductive line connecting the two adjacent memory cells in the third direction. The thermal conductivity of the first isolation structure ranges from 0.08 W / (m·K) to 0.12 W / (m·K), and is less than the thermal conductivity of the second isolation structure located between two adjacent memory cells in the second direction. As a result, the degree of heat transfer along the third direction can be reduced when a reset operation is performed on the selected memory cell, thereby mitigating thermal crosstalk to the non-selected memory cells adjacent to the selected memory cell in the third direction.

[0093] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0094] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0095] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A phase-change memory, characterized in that, include: A first conductive line, a second conductive line, and a storage unit located between the first conductive line and the second conductive line in a first direction; The storage unit extends along the first direction; The first conductive line extends along a second direction and is connected to a plurality of the memory cells arranged along the second direction; The second conductive line extends along a third direction and connects to a plurality of memory cells arranged along the third direction; the second direction intersects the third direction and is perpendicular to the first direction. A first isolation structure is located between two adjacent memory cells in the third direction and between first conductive lines connected to the two adjacent memory cells in the third direction; the thermal conductivity of the first isolation structure is in the range of 0.08 W / (m·K) to 0.12 W / (m·K). A second isolation structure is located between two adjacent memory cells in the second direction and between the second conductive lines respectively connected to the two adjacent memory cells in the second direction; The thermal conductivity of the second isolation structure is greater than that of the first isolation structure.

2. The phase-change memory according to claim 1, characterized in that, The first isolation structure comprises polyimide.

3. The phase-change memory according to claim 1, characterized in that, The thermal conductivity of the second isolation structure ranges from 0.2 W / (m·K) to 0.28 W / (m·K).

4. The phase-change memory according to claim 1, characterized in that, The second isolation structure extends along the third direction and is located between two adjacent first isolation structures in the second direction.

5. The phase-change memory according to claim 1, characterized in that, The storage unit includes: A first electrode, a gating element, a second electrode, a phase change element, and a third electrode are stacked sequentially along the first direction; the first electrode is located between the gating element and the first conductive line; the third electrode is located between the phase change element and the second conductive line.

6. The phase-change memory according to claim 5, characterized in that, The phase-change memory further includes: A third isolation structure and a fourth isolation structure; the third isolation structure covers the phase change element and the third electrode of the memory cell on the same side of the opposite sides of the third third upward direction; the fourth isolation structure covers the third isolation structure, the second electrode, the gating element, the first electrode, and the first conductive line connected to the memory cell on the same side of the opposite sides of the third third upward direction; the fourth isolation structure is located between the first isolation structure and the third isolation structure.

7. The phase-change memory according to claim 6, characterized in that, The third isolation structure includes a first dielectric layer and a second dielectric layer; the second dielectric layer is located between the first dielectric layer and the fourth isolation structure; the first dielectric layer and the fourth isolation structure include silicon nitride; the second dielectric layer includes silicon oxide.

8. A method for forming a phase-change memory, characterized in that, include: A first conductive line extending along the second direction is formed; A memory cell is formed on one of the two opposite sides of the first conductive line along the first direction; The storage cell extends along the first direction; a first conductive line is connected to a plurality of the storage cells arranged along the second direction; A first isolation structure is formed; the first isolation structure is located between two adjacent memory cells in the third direction and between the first conductive lines respectively connected to the two adjacent memory cells in the third direction; the thermal conductivity of the first isolation structure is in the range of 0.08 W / (m·K) to 0.12 W / (m·K); the second direction intersects the third direction and is perpendicular to the first direction. A second conductive line extending along the third direction is formed on one side of the storage cell opposite to each other along the first direction, away from the first conductive line; one of the second conductive lines is connected to a plurality of the storage cells arranged along the third direction. Forming a second isolation structure; The second isolation structure is located between two adjacent memory cells in the second direction and between the second conductive lines that are respectively connected to the two adjacent memory cells in the second direction; The thermal conductivity of the second isolation structure is greater than that of the first isolation structure.

9. The method for forming a phase-change memory according to claim 8, characterized in that, The storage unit includes a first electrode, a gating element, a second electrode, a phase change element, and a third electrode arranged in sequence along the first direction; The first electrode is located between the gating element and the first conductive line; The formation of the first isolation structure includes: A first initial isolation structure is formed by spin coating between two adjacent memory cells in the third direction and filling the space between the first conductive lines connected to the two adjacent memory cells in the third direction with an insulating material; the top surface of the first initial isolation structure is located between the top and bottom surfaces of the third electrode in the first direction. The first initial isolation structure is etched to form a second initial isolation structure, the top surface of the second initial isolation structure being located between the top and bottom surfaces of the phase change element in the first direction; The isolation material is filled into the second initial isolation structure by the spin coating process to form the first isolation structure.

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