Backside illuminated photodiode structure and method of fabrication, x-ray detector

Abstract

The application discloses a back-illuminated photodiode structure and a preparation method and an X-ray detector, and belongs to the field of semiconductor photoelectric sensors in nuclear technology application. The back-illuminated photodiode structure comprises an epitaxial layer, an electrode area located on a non-photosensitive side of the epitaxial layer, a first dielectric layer located on the non-photosensitive side of the epitaxial layer, electrodes and leads located on a side of the first dielectric layer away from the epitaxial layer and penetrating through the first dielectric layer to be connected with the electrode area, a bonding layer located on a side of the electrodes and leads away from the first dielectric layer and covering the electrodes and leads, a carrier sheet bonded with a side of the bonding layer away from the electrodes and leads, and a through-silicon via structure penetrating through the carrier sheet and the bonding layer and connected with the electrodes and leads. The application can reduce the risk of fragments, is suitable for large-size CMOS process lines, improves production efficiency, reduces cost, and realizes splicing on the side.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of photoelectric sensors of nuclear technology, and particularly relates to a back-illuminated photodiode structure and a preparation method and an X-ray detector. BACKGROUND

[0002] The back-illuminated photodiode for X-ray detection is generally produced by using a 6-inch special production line. After forming an electrode pad of the back-illuminated photodiode, the back surface of the 6-inch wafer needs to be thinned, and then subsequent processes are continued. However, with the increase of the wafer size (for example, 8 inches or 12 inches), the mechanical strength of the thinned wafer is getting worse, the risk of chipping is greatly increased, and the wafer cannot be subjected to subsequent processes after being thinned. SUMMARY

[0003] The application aims to at least solve one of the technical problems in the prior art. To this end, the application provides a back-illuminated photodiode structure and a preparation method and an X-ray detector, which can reduce the risk of chipping, are suitable for a large-size wafer process line, and realize splicing on the side.

[0004] In a first aspect, the application provides a back-illuminated photodiode structure, comprising:

[0005] an epitaxial layer, comprising an electrode region located on a non-photosensitive side of the epitaxial layer;

[0006] a first dielectric layer located on the non-photosensitive side of the epitaxial layer;

[0007] an electrode and a lead wire located on a side of the first dielectric layer away from the epitaxial layer, and penetrating the first dielectric layer to be connected with the electrode region;

[0008] a bonding layer located on a side of the electrode lead wire away from the first dielectric layer, and covering the electrode and the lead wire;

[0009] a carrier bonded to a side of the bonding layer away from the electrode lead wire;

[0010] a through-silicon via structure penetrating the carrier and the bonding layer, and connected with the electrode and the lead wire.

[0011] According to the back-illuminated photodiode structure of the application, the bonding layer is formed on the non-photosensitive side of the pixel sheet, and the carrier is permanently bonded through the bonding layer, the mechanical strength of the epitaxial layer is increased, the risk of chipping is reduced, and the back-illuminated photodiode can be produced on a large-size wafer (for example, 12-inch commercial) process line, that is, it is suitable for a large-size wafer process line. Compared with a 6-inch wafer process special line, the production efficiency is improved, the cost is reduced, and the electrode of the back-illuminated photodiode is led out from the side of the carrier through the through-silicon via structure, so that the side of the back-illuminated photodiode structure can be spliced, and it is suitable for a large-area pixel array.

[0012] According to an embodiment of the present application, the back-illuminated photodiode structure further comprises:

[0013] a deep trench isolation structure extending into the epitaxial layer from a light sensing side of the epitaxial layer, and the deep trench isolation structure is located at a lateral side of the electrode region, the light sensing side being opposite to the non-light sensing side.

[0014] According to an embodiment of the present application, the back-illuminated photodiode structure further comprises:

[0015] an anti-reflection coating located at the light sensing side of the epitaxial layer.

[0016] According to an embodiment of the present application, the back-illuminated photodiode structure further comprises:

[0017] a second dielectric layer located at a side of the carrier away from the bonding layer, and the through-silicon via structure further penetrates the second dielectric layer;

[0018] a pad located at a side of the second dielectric layer away from the carrier and connected with the through-silicon via structure.

[0019] According to an embodiment of the present application, the first dielectric layer has a thickness greater than a target thickness. According to an embodiment of the present application, the electrode region comprises a highly doped region opposite to a doping type of the epitaxial layer, and the electrode and the lead wire comprise a lead wire connected with the highly doped region.

[0020] The epitaxial layer further comprises a floating doped region located at a non-light sensing side of the epitaxial layer, the floating doped region being different from the doping type of the epitaxial layer, the floating doped region being located at a bottom of the lead wire and being laterally spaced apart from the electrode region.

[0021] According to an embodiment of the present application, a lateral surface of the back-illuminated photodiode structure is a splicing surface.

[0022] In a second aspect, the present application provides an X-ray detector comprising the back-illuminated photodiode structure according to the first aspect.

[0023] According to an embodiment of the present application, the X-ray detector comprises a plurality of the back-illuminated photodiode structures spliced together.

[0024] In a third aspect, the present application provides a preparation method of a back-illuminated photodiode structure, comprising:

[0025] The method comprises the following steps: providing a substrate, a first dielectric layer and an electrode and a lead, wherein the substrate comprises an epitaxial layer, the epitaxial layer comprises an electrode area located on a non-photosensitive side of the epitaxial layer, the first dielectric layer is located on the non-photosensitive side of the epitaxial layer, and the electrode and the lead are located on a side of the first dielectric layer away from the epitaxial layer and are connected with the electrode area through the first dielectric layer;

[0026] forming a bonding layer on a side of the electrode and the lead away from the first dielectric layer, and the bonding layer covers the electrode and the lead;

[0027] bonding a wafer to a side of the bonding layer away from the electrode and the lead;

[0028] performing a thinning process on a side of the substrate away from the first dielectric layer;

[0029] forming a through-silicon via structure penetrating through the wafer and the bonding layer, and the through-silicon via structure is connected with the electrode and the lead.

[0030] According to one embodiment of the present application, the substrate is a wafer with a size greater than 6 inches.

[0031] According to one embodiment of the present application, the substrate further comprises a substrate located on a photosensitive side of the epitaxial layer, and the photosensitive side is arranged opposite to the non-photosensitive side;

[0032] The thinning process on the side of the substrate away from the first dielectric layer comprises:

[0033] removing the substrate and performing a thinning process on a side of the epitaxial layer away from the first dielectric layer.

[0034] According to one embodiment of the present application, after the thinning process on the side of the substrate away from the first dielectric layer, the method further comprises:

[0035] forming a deep trench isolation structure on a peripheral side of the electrode area, and the deep trench isolation structure extends from the photosensitive side of the substrate to the epitaxial layer;

[0036] forming an antireflection film on the photosensitive side of the substrate.

[0037] According to one embodiment of the present application, before the forming of the through-silicon via structure penetrating through the wafer and the bonding layer, the method further comprises:

[0038] performing a thinning process on a side of the wafer away from the bonding layer;

[0039] forming a second dielectric layer on a side of the wafer away from the bonding layer, and the through-silicon via structure further penetrates through the second dielectric layer;

[0040] After the forming of the through-silicon via structure penetrating the carrier and the bonding layer, the method further comprises:

[0041] A pad is formed on the side of the second medium layer away from the carrier, and the pad is connected with the through-silicon via structure.

[0042] The one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0043] By forming a bonding layer on the non-photosensitive side of the epitaxial layer and permanently bonding the carrier through the bonding layer, the mechanical strength of the epitaxial layer is increased, the risk of fragmentation is reduced, the back-illuminated photodiode can be produced on a large-size wafer process line, that is, it is suitable for a large-size wafer process line, compared with a 6-inch wafer process line, the production efficiency is improved, the cost is reduced, and the electrode of the back-illuminated photodiode is led out from the carrier side through the through-silicon via structure, so that the side of the back-illuminated photodiode structure can be spliced, and it is suitable for a large-area pixel array.

[0044] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0045] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings, wherein:

[0046] Figure 1 is one of the structure schematic diagrams of the back-illuminated photodiode structure provided by the embodiments of the present application;

[0047] Figure 2 is the second structure schematic diagram of the back-illuminated photodiode structure provided by the embodiments of the present application;

[0048] Figure 3 is the flowchart of the preparation method of the back-illuminated photodiode structure provided by the embodiments of the present application;

[0049] Figure 4 is one of the structure schematic diagrams of the preparation method of the back-illuminated photodiode structure provided by the embodiments of the present application;

[0050] Figure 5 is the second structure schematic diagram of the preparation method of the back-illuminated photodiode structure provided by the embodiments of the present application;

[0051] Figure 6 is the third structure schematic diagram of the preparation method of the back-illuminated photodiode structure provided by the embodiments of the present application;

[0052] Figure 7Fig. 4 is a structural schematic diagram of a preparation method of a back-illuminated photodiode structure according to an embodiment of the present application;

[0053] Figure 8 Fig. 5 is a structural schematic diagram of a preparation method of a back-illuminated photodiode structure according to an embodiment of the present application;

[0054] Figure 9 Fig. 6 is a structural schematic diagram of a preparation method of a back-illuminated photodiode structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] Embodiments of the present application are described in detail below with reference to the accompanying drawings, in which the same or similar components have the same or similar designations and functions throughout. The embodiments described below are examples in which the present application is applied to explain the present application, and should not be interpreted as limiting the present application.

[0056] A back-illuminated photodiode structure and a preparation method thereof, and an X-ray detector are described below with reference to the accompanying drawings according to an embodiment of the present application.

[0057] Figure 1 Fig. 1 is a structural schematic diagram of a back-illuminated photodiode structure according to an embodiment of the present application. The back-illuminated photodiode structure is a back-illuminated photodiode structure based on a CMOS process, and the back-illuminated photodiode can be applied to an X-ray detector, which is a back-illumination detector.

[0058] In the case where the back-illuminated photodiode in the present embodiment is applied to an X-ray detector, the back-illuminated photodiode is used to convert a visible light signal (converted from an X-ray signal by a scintillator) into an electrical signal, which is output to a data processing and control circuit after being processed by an ADC (analog-to-digital converter).

[0059] The working principle of the back-illuminated photodiode is as follows: when light (a visible light signal) of a certain wavelength is incident into an epitaxial layer (such as silicon), and the photon energy is greater than the band gap Eg of silicon (for silicon, the wavelength is less than 1100 nm), the electrons on the valence band will absorb the photon energy to jump to the conduction band to form an electron-hole pair. When the electron-hole pair is generated in the PN junction depletion region, the electron and the hole will be separated under the action of the built-in electric field, and if the PN junction external circuit forms a loop, a photoelectric current will be formed. When the electron-hole pair is generated outside the PN junction depletion region, if the minority carrier lifetime in the corresponding region is long enough, the minority carriers in the electron-hole pair can diffuse into the depletion region and then be collected to form a photoelectric current.

[0060] As shown in Fig. 1, the back-illuminated photodiode structure includes a substrate 1, a first epitaxial layer 2, a second epitaxial layer 3, a third epitaxial layer 4, a fourth epitaxial layer 5, a fifth epitaxial layer 6, a sixth epitaxial layer 7, a seventh epitaxial layer 8, a first electrode 9, a second electrode 10, and a third electrode 11. Figure 1As shown, the back-illuminated photodiode structure provided by the embodiments of the present application includes an epitaxial layer 1, a first dielectric layer 21, an electrode and lead 3, a bonding layer 4, a carrier sheet 5, and a through-silicon structure 6.

[0061] The epitaxial layer 1 includes an electrode region 11, which is located on the non-photosensitive side of the epitaxial layer 1. It should be noted that the back of the epitaxial layer 1 is the photosensitive side, which refers to the side on which light is incident to the epitaxial layer 1. The non-photosensitive side of the epitaxial layer 1 is arranged opposite to the photosensitive side, that is, the front of the epitaxial layer 1 is the non-photosensitive side, and the electrode region 11 is located on the front of the epitaxial layer 1. The photosensitive side of the back-illuminated photodiode has no metal interconnection lines and other structures, which does not affect the light incidence, and the photosensitive side has no high-doped “dead zone”, so the quantum efficiency of the back-illuminated photodiode is higher than that of the front-illuminated photodiode, and the quantum efficiency of the back-illuminated photodiode can theoretically reach 100%.

[0062] The resistance of the epitaxial layer 1 is a target resistance, which can be set according to actual needs. The epitaxial layer 1 can be a semiconductor layer including silicon, or a semiconductor layer including other elements. The epitaxial layer 1 can be a first-doped-type epitaxial layer, and the first-doped-type can be N-type. For example, a small amount of pentavalent elements such as phosphorus and arsenic can be doped in the epitaxial layer 1 to form an N-type epitaxial layer. In some embodiments, the epitaxial layer 1 is an N-type low-doped epitaxial layer.

[0063] In some embodiments, the electrode region 11 can include a high-doped region (i.e., a first high-doped region 111) different from the doped type of the epitaxial layer 1, that is, the first high-doped region 111 has a second doped type different from the first doped type. For example, trivalent elements such as boron can be doped in the first high-doped region 111 to form a P-type high-doped region. In some embodiments, the epitaxial layer 1 is an N-type low-doped epitaxial layer, and the first high-doped region 111 is a P-type high-doped region. The first high-doped region 111 is one electrode of the back-illuminated photodiode, such as a cathode or an anode. The first high-doped region 111 can be connected to a readout circuit (including a power supply) through a conductive structure such as an electrode and a lead.

[0064] The electrode region 11 can also include a second high-doped region 112 having the same doped type as the epitaxial layer 1, that is, the second high-doped region 112 has the first doped type. The doping concentration of the second high-doped region 112 is greater than the doping concentration of the epitaxial layer 1. In some embodiments, the epitaxial layer 1 is an N-type low-doped epitaxial layer, the first high-doped region 111 is a P-type high-doped region, and the second high-doped region 112 is an N-type high-doped region. The second high-doped region 112 is one electrode of the back-illuminated photodiode, such as a cathode or an anode. The second high-doped region 112 can be grounded through a conductive structure such as an electrode and a lead.

[0065] The second high-doped region 112 and the first high-doped region 111 are located on the non-photosensitive side of the epitaxial layer 1, and the second high-doped region 112 is laterally spaced apart from the first high-doped region 111. Lateral refers to a direction parallel to the front surface of the epitaxial layer 1. The second high-doped region 112 and the first high-doped region 111 are different electrodes of the back-illuminated photodiode. For example, the first high-doped region 111 is a cathode, and the second high-doped region 112 is an anode; or the first high-doped region 111 is an anode, and the second high-doped region 112 is a cathode.

[0066] The first dielectric layer 21 is located on the non-photosensitive side of the epitaxial layer 1, i.e., the first dielectric layer 21 is located on the side of the epitaxial layer 1 close to the electrode region 11 and covers the electrode region 11. The first dielectric layer 21 can include silicon oxide and the like.

[0067] The electrode and lead 3 is located on the side of the first dielectric layer 21 away from the epitaxial layer 1, and the electrode and lead 3 longitudinally penetrates the first dielectric layer 21 and is connected to the electrode region 11. Longitudinal refers to a direction perpendicular to the front surface of the epitaxial layer 1. The electrode and lead 3 can include one or more combinations of copper, aluminum, tungsten, platinum, nickel, and titanium and the like.

[0068] In some embodiments, the electrode and lead 3 can include a lead (i.e., the first lead 31) connected to the high-doped region (i.e., the first high-doped region 111). The first lead 31 is located on the side of the first dielectric layer 21 away from the epitaxial layer 1, and the first lead 31 longitudinally penetrates the first dielectric layer 21 and is connected to the first high-doped region 111. The first lead 31 can extend laterally to increase the connection window, facilitating the connection of the through-silicon via structure.

[0069] The electrode and lead 3 can also include a second lead 32 connected to the second high-doped region 112, and the second lead 32 is spaced apart from the first lead 31. The second lead 32 is located on the side of the first dielectric layer 21 away from the epitaxial layer 1, and the second lead 32 longitudinally penetrates the first dielectric layer 21 and is connected to the second high-doped region 112. The second lead 32 can extend laterally to increase the connection window, facilitating the connection of the through-silicon via structure.

[0070] The bonding layer 4 is located on the side of the electrode and lead 3 away from the first dielectric layer 21, and covers the electrode and lead 3. The bonding layer 4 also covers the first dielectric layer 21. The bonding layer 4 can include silicon oxide and the like.

[0071] The carrier wafer 5 is bonded to the side of the bonding layer 4 away from the electrodes and the leads 3, and the bonding is permanent bonding. The bonding of the carrier wafer 5 can increase the mechanical strength of the epitaxial layer 1 and reduce the risk of chipping, so that the back-illuminated photodiode structure can be produced on a large-size (such as 8-inch or 12-inch, etc.) wafer process line. Compared with a 6-inch wafer process line, a large-size wafer process line has the advantages of high production efficiency, low production cost, and good process stability. The embodiment is suitable for a large-size wafer process line, can improve the production efficiency of the back-illuminated photodiode structure, reduce the cost, and improve the product stability.

[0072] The thickness of the carrier wafer 5 cannot be too thin to avoid insufficient strengthening of the mechanical strength of the epitaxial layer 1, and the thickness of the carrier wafer 5 cannot be too thick to avoid that the through-silicon via structure 6 cannot completely penetrate the carrier wafer 5. The thickness of the carrier wafer 5 can meet the through-silicon via (TSV) process, for example, the thickness of the carrier wafer 5 is about 200 μm. The carrier wafer 5 can include a wafer or glass, etc.

[0073] The through-silicon via structure 6 longitudinally penetrates the carrier wafer 5 and the bonding layer 4, and the through-silicon via structure 6 is connected with the electrodes and the leads 3. The electrode region 11 is connected with the through-silicon via structure 6 through the electrodes and the leads 3, that is, the electrode region 11 is led out to the side of the carrier wafer 5 away from the epitaxial layer 1 through the electrodes and the leads 3 and the through-silicon via structure 6.

[0074] In some embodiments, the through-silicon via structure 6 can include a first through-silicon via sub-structure 61 and a second through-silicon via sub-structure 62 which are transversely spaced. The first through-silicon via sub-structure 61 longitudinally penetrates the carrier wafer 5 and the bonding layer 4, and is connected with the first lead 31, so as to lead the first high-doped region 111 out to the side of the carrier wafer 5 away from the epitaxial layer 1 through the first through-silicon via sub-structure 61 and the first lead 31. The second through-silicon via sub-structure 62 longitudinally penetrates the carrier wafer 5 and the bonding layer 4, and is connected with the second lead 32, so as to lead the second high-doped region 112 out to the side of the carrier wafer 5 away from the epitaxial layer 1 through the second through-silicon via sub-structure 62 and the second lead 32.

[0075] In some embodiments, the first through-silicon via sub-structure 61 and the second through-silicon via sub-structure 62 each include a conductive layer 63 and a spacing layer 64. The conductive layer 63 longitudinally penetrates the carrier wafer 5 and the bonding layer 4, and is connected with the electrodes and the leads 3, that is, the conductive layer 63 in the first through-silicon via sub-structure 61 longitudinally penetrates the carrier wafer 5 and the bonding layer 4, and is connected with the first lead 31, and the conductive layer 63 in the second through-silicon via sub-structure 62 longitudinally penetrates the carrier wafer 5 and the bonding layer 4, and is connected with the second lead 32. The spacing layer 64 is arranged around the conductive layer 63 to isolate the conductive layer 63 from other film layers. The conductive layer 63 can include one or more combinations of copper, aluminum, tungsten, platinum, nickel, and titanium, and the spacing layer 64 can include one or more combinations of silicon nitride and silicon oxide, etc.

[0076] The electrode region 11 is led out from the side of the wafer 5 (non-photosensitive side) through the electrode and lead wire 3 and the through-silicon via structure 6, so that the peripheral side of the back-illuminated photodiode structure is a splicing surface, that is, the peripheral side of the back-illuminated photodiode structure can be spliced with the peripheral side of other back-illuminated photodiode structures. In the case where the cross section of the back-illuminated photodiode structure is rectangular, the four sides of the back-illuminated photodiode structure are all splicing surfaces. A plurality of back-illuminated photodiode structures can form a pixel array of any size through splicing, which is suitable for security inspection, industrial detection, medical imaging and other scenes.

[0077] In some embodiments, the back-illuminated photodiode structure further comprises a deep trench isolation structure (DTI) 7. The deep trench isolation structure 7 extends longitudinally from the photosensitive side of the epitaxial layer 1 into the epitaxial layer 1. The deep trench isolation structure 7 has a high aspect ratio, and the extension length of the deep trench isolation structure 7 can be adjusted according to the thickness of the epitaxial layer 1, such as the extension length of the deep trench isolation structure 7 can be half of the thickness of the epitaxial layer 1, which is not specifically limited here. The deep trench isolation structure 7 is located on the peripheral side of the electrode region 11, such as the deep trench isolation structure 7 can be arranged along the boundary of the pixel unit.

[0078] The related art improves the problem of inter-pixel crosstalk by increasing the spacing of adjacent pixel photosensitive regions, but the increase in spacing reduces the photosensitive area of the pixel, thereby causing the external quantum efficiency to decrease. However, the present embodiment isolates adjacent pixel units by arranging the deep trench isolation structure 7, so as to greatly reduce the inter-pixel crosstalk without affecting the photosensitive area.

[0079] In some embodiments, the back-illuminated photodiode structure further comprises an anti-reflection film 8, which is located on the photosensitive side of the epitaxial layer 1, that is, the anti-reflection film 8 is located on the side of the epitaxial layer 1 away from the electrode and lead wire 3. The anti-reflection film 8 can include one or more combinations of silicon oxide and silicon nitride.

[0080] The present embodiment arranges the anti-reflection film 8 on the photosensitive side of the epitaxial layer 1, which can reduce light reflection and increase transmitted light intensity, thereby improving the external quantum efficiency.

[0081] In some embodiments, the back-illuminated photodiode structure further comprises a second dielectric layer 22 and a pad 9. The second dielectric layer 22 is located on the side of the wafer 5 away from the bonding layer 4, and the through-silicon via structure 6 also penetrates the second dielectric layer 22, that is, the through-silicon via structure 6 longitudinally penetrates the second dielectric layer 22, the wafer 5 and the bonding layer 4, and is connected with the electrode and lead wire 3. The second dielectric layer 22 can include one or more combinations of silicon nitride and silicon oxide.

[0082] The pad 9 is located on the side of the second dielectric layer 22 away from the wafer 5 and is connected with the through-silicon via structure 6. The pad 9 is connected with the conductive layer 63 in the through-silicon via structure 6. The pad 9 can include one or more combinations of copper, aluminum, tungsten, platinum, nickel and titanium.

[0083] In some embodiments, the pad 9 can include a first soldering point 91 and a second soldering point 92 arranged laterally apart. The first soldering point 91 is located on the side of the second dielectric layer 22 facing away from the wafer 5 and is connected with the conductive layer 62 in the first through-silica via substructure 61, so that the first highly-doped region 111 is led out through the first lead 31, the first through-silica via substructure 61 and the first soldering point 91. The first soldering point 91 can be connected with a power supply or a signal line, so that the first highly-doped region 111 is connected with the power supply or the signal line through the first lead 31, the first through-silica via substructure 61 and the first soldering point 91. The second soldering point 92 is located on the side of the second dielectric layer 22 facing away from the wafer 5 and is connected with the conductive layer 62 in the first through-silica via substructure 61, so that the second highly-doped region 112 is led out through the second lead 32, the second through-silica via substructure 62 and the second soldering point 92. The second soldering point 92 can be connected with a power supply or a signal line, so that the second highly-doped region 112 is connected with the power supply or the signal line through the second lead 32, the second through-silica via substructure 62 and the second soldering point 92.

[0084] In some embodiments, the thickness of the first dielectric layer 21 is greater than a target thickness. For example, the target thickness is greater than 100 nm. A parasitic capacitance is formed between the first lead 31 and the epitaxial layer 1, and the parasitic capacitance can be reduced by increasing the thickness of the first dielectric layer 21 between the first lead 31 and the epitaxial layer 1.

[0085] In some embodiments, as shown in FIG. 1B, the epitaxial layer 1 further includes a floating-doped region 12 located on the non-photosensitive side of the epitaxial layer 1. The floating-doped region 12 is located at the bottom of the lead (i.e., the first lead 31), i.e., the orthographic projection of the first lead 31 on the epitaxial layer 1 covers the floating-doped region 12. The floating-doped region 12 is arranged laterally apart from the electrode region 11, i.e., the floating-doped region 12 is arranged laterally apart from the first highly-doped region 111 and the second highly-doped region 112, respectively. Figure 2

[0086] The depth and width of the floating-doped region 12 are not specifically limited. The floating-doped region 12 has a doping type opposite to that of the epitaxial layer 1, i.e., the floating-doped region 12 has a second doping type. The doping concentration of the floating-doped region 12 is not specifically limited, i.e., the floating-doped region 12 can be a low-doped region or a high-doped region.

[0087] In some embodiments, the epitaxial layer 1 is an N-type low-doped epitaxial layer, the first highly-doped region 111 and the floating-doped region 12 are both P-type high-doped regions, and the second highly-doped region 112 is an N-type high-doped region. The first highly-doped region 111 and the floating-doped region 12 can be formed simultaneously without additional photomasks, thereby avoiding increasing the process complexity and the production cost.

[0088] ​The first lead wire 31 and the epitaxial layer 1 form a parasitic capacitance. The floating doping region 12 is added at the bottom of the first lead wire 31, so that a junction capacitance is formed between the floating doping region 12 and the epitaxial layer 1, and the junction capacitance is connected in series with the parasitic capacitance, thereby reducing the parasitic capacitance.

[0089] In summary, according to the back-illuminated photodiode structure provided in the embodiments of the present application, the bonding layer 4 is formed on the non-photosensitive side of the epitaxial layer 1, and the epitaxial layer 1 is permanently bonded to the carrier 5 through the bonding layer 4, thereby increasing the mechanical strength of the epitaxial layer 1, reducing the risk of fragmentation, and enabling the back-illuminated photodiode to be produced on a large-size (for example, 12-inch commercial) wafer process line, that is, to be applicable to a large-size wafer process line, thereby improving production efficiency and reducing costs. In addition, the electrode of the back-illuminated photodiode is led out from the side of the carrier 5 through the through-silicon via structure 6, so that the lateral side of the back-illuminated photodiode structure can be spliced, and the back-illuminated photodiode structure is applicable to a large-area pixel array.

[0090] Correspondingly, the embodiments of the present application also provide an X-ray detector.

[0091] The X-ray detector provided in the embodiments of the present application includes the back-illuminated photodiode structure, which is the back-illuminated photodiode in the above embodiments, and will not be described in detail here.

[0092] The X-ray detector can be applied to the fields of security inspection, industrial detection, medical imaging, etc. The X-ray signal is converted into a visible light signal by using a scintillator, and then the visible light signal is converted into an electric signal by the back-illuminated photodiode. After being processed by an ADC, the electric signal is output to a signal processing and control circuit.

[0093] In some embodiments, the X-ray detector can include a plurality of back-illuminated photodiode structures spliced together. The back-illuminated photodiode structure is a splicable structure, that is, the lateral side of the back-illuminated photodiode structure is a splicable surface. In the case where the cross section of the back-illuminated photodiode structure is rectangular, the four lateral sides of the back-illuminated photodiode structure are splicable surfaces. The plurality of back-illuminated photodiode structures can form a large-area pixel array by splicing, and are applicable to X-ray CT scenarios, etc.

[0094] Correspondingly, the embodiments of the present application also provide a preparation method of the back-illuminated photodiode structure, which can be used to prepare the back-illuminated photodiode structure in the above embodiments.

[0095] As shown in Figure 3 The preparation method of the back-illuminated photodiode structure provided in the embodiments of the present application includes steps 110 to 150.

[0096] Step 110, providing a substrate, a first dielectric layer and an electrode and a lead, the substrate comprising an epitaxial layer, the epitaxial layer comprising an electrode region located at a non-photosensitive side of the epitaxial layer, the first dielectric layer located at the non-photosensitive side of the epitaxial layer, the electrode and the lead located at a side of the first dielectric layer away from the epitaxial layer and connected with the electrode region through the first dielectric layer.

[0097] In combination Figure 4 As shown in FIG. 1, a substrate 10 is provided, which can comprise an epitaxial layer 1. In some embodiments, the substrate 10 can further comprise a substrate 13, i.e. the epitaxial layer 1 is formed on the substrate 13 through a thin film deposition process. The doping type of the epitaxial layer 1 and the substrate 13 can be the same or different. For example, the epitaxial layer 1 can be an N-type low-doped epitaxial layer, and the substrate 13 can be a P-type high-doped substrate.

[0098] In some embodiments, the substrate 10 is a wafer with a size greater than 6 inches, for example, the substrate 10 can be an 8-inch wafer or a 12-inch wafer, i.e. the back-illuminated photodiode in the embodiment can be produced on an 8-inch wafer process line or a 12-inch wafer process line.

[0099] The related art uses a 6-inch wafer special production line to produce a back-illuminated photodiode, i.e. a 6-inch wafer is used as a substrate to produce a back-illuminated photodiode. Compared with the 6-inch wafer special production line, the large-size (greater than 6 inches) wafer process line has the advantages of high production efficiency, low production cost, and good process stability. The embodiment adopts the large-size wafer process line to produce the back-illuminated photodiode, which can improve the production efficiency of the back-illuminated photodiode structure, reduce the cost, and improve the process stability.

[0100] Then, the non-photosensitive side of the epitaxial layer 1 is doped through an ion implantation process, and a high-temperature annealing is used to activate, thereby forming an electrode region 3 at the non-photosensitive side of the epitaxial layer 1. The electrode region 11 can comprise a first high-doped region 111 having a doping type different from that of the epitaxial layer 1 and a second high-doped region 112 having a doping type same as that of the epitaxial layer 1. For example, the first high-doped region 111 is a P-type high-doped region, and the second high-doped region 112 is an N-type high-doped region. The second high-doped region 112 and the first high-doped region 111 are both located at the non-photosensitive side of the epitaxial layer 1, and the second high-doped region 112 and the first high-doped region 111 are laterally spaced apart. One of the second high-doped region 112 and the first high-doped region 111 is an anode, and the other is a cathode.

[0101] It should be noted that the doping types of the first high-doped region 111 and the second high-doped region 112 are different, and two masks are required to form the first high-doped region 111 and the second high-doped region 112. The order of forming the first high-doped region 111 and the second high-doped region 112 is not specifically limited.

[0102] Then, a first dielectric layer 21 is formed on the non-photosensitive side of the epitaxial layer 1 by a thin film deposition process (such as chemical vapor deposition CVD). Two through holes are formed in the first dielectric layer 21 by an etching process, and the two through holes respectively correspond to the positions of the first high-doped region 111 and the second high-doped region 112.

[0103] Then, a metal layer is formed on the side of the first dielectric layer 21 away from the epitaxial layer 1 by a thin film deposition process, and the metal layer fills the two through holes and respectively contacts the first high-doped region 111 and the second high-doped region 112 to form a low-resistance contact. The metal layer is etched by an etching process to form an electrode and a lead 3. The electrode and the lead 3 include a first lead 31 connected to the first high-doped region 111 and a second lead 32 connected to the second high-doped region 112, and the first lead 31 and the second lead 32 are laterally spaced apart.

[0104] Step 120, a bonding layer is formed on the side of the electrode and the lead away from the first dielectric layer, and the bonding layer covers the electrode and the lead.

[0105] In combination Figure 5 As shown, a bonding layer 4 is formed on the side of the electrode and the lead 3 away from the first dielectric layer 21 by a thin film deposition process (such as CVD), and the bonding layer 4 covers the electrode and the lead 3 and also covers the first dielectric layer 21. A CMP (Chemical Mechanical Polishing) process is used to polish the side of the bonding layer 4 away from the electrode and the lead 3, so as to facilitate subsequent bonding with a carrier 5.

[0106] Step 130, the carrier is bonded with the side of the bonding layer away from the electrode and the lead.

[0107] In combination Figure 6 As shown, the carrier 5 is permanently bonded with the side of the bonding layer 4 away from the electrode and the lead 3, so as to increase the mechanical strength of the wafer and make the embodiment suitable for large-size wafer process lines.

[0108] Step 140, a thinning process is performed on the side of the substrate away from the first dielectric layer.

[0109] In the case where the substrate 10 includes the epitaxial layer 1, the thinning process performed on the side of the substrate away from the first dielectric layer in step 140 includes: a thinning process is performed on the side of the epitaxial layer 1 away from the first dielectric layer 21. During the thinning process, the resistance value of the epitaxial layer 1 is monitored, and when the resistance value of the epitaxial layer 1 reaches a target resistance value, the thinning process of the epitaxial layer 1 is stopped, that is, the resistance value of the epitaxial layer 1 after the thinning process is the target resistance value. The target resistance value can be set according to actual needs, which is not limited here.

[0110] In the case where the substrate 10 includes the epitaxial layer 1 and the substrate 13, the thinning process on the side of the substrate away from the first dielectric layer in step 140 includes: removing the substrate, and thinning the side of the epitaxial layer away from the first dielectric layer.

[0111] In combination Figure 7 As shown, the side of the substrate 10 away from the first dielectric layer 21 is thinned, such as removing the substrate 13, and the side of the epitaxial layer 1 away from the first dielectric layer 21 is thinned. During the thinning process, the resistance of the substrate 10 is monitored, and when the resistance of the substrate 10 reaches a target resistance, the thinning of the substrate 10 is stopped, that is, the resistance of the thinned substrate 10 is the target resistance.

[0112] The related art directly thins the side of the substrate away from the electrode and the lead after forming the electrode and the lead, and the mechanical strength after thinning is weak, the risk of fragmentation is increased, and most current large-size machines cannot pass in the thinned wafer, resulting in that the wafer cannot continue the subsequent process after being thinned. The embodiment forms a bonding layer 4 on the electrode and the lead 3, and is permanently bonded with a carrier 5, increases the mechanical strength of the wafer, reduces the risk of fragmentation, and is suitable for large-size wafer process lines.

[0113] In some embodiments, after the thinning process on the side of the substrate away from the first dielectric layer in step 140, the method further includes: forming a deep trench isolation structure on the periphery of the electrode area, and the deep trench isolation structure extends from the light-sensitive side of the substrate into the epitaxial layer; and forming an anti-reflection film on the light-sensitive side of the substrate.

[0114] In combination Figure 8 As shown, an etching process is used to form a high-aspect-ratio deep trench on the light-sensitive side of the epitaxial layer 1, the deep trench extends from the light-sensitive side of the epitaxial layer 1 into the epitaxial layer 1, and the deep trench is arranged around the periphery of the electrode area 11. Through surface passivation process and oxide filling process, a deep trench structure 7 is formed in the deep trench. The deep trench isolation structure 7 can isolate adjacent pixel units to greatly reduce the crosstalk between pixels without affecting the area of the light-sensitive area.

[0115] Then, an anti-reflection film 8 is formed on the light-sensitive side of the epitaxial layer 1 to reduce light reflection and increase transmitted light intensity, thereby improving quantum efficiency.

[0116] It should be noted that the above process is completed based on a CMOS production line, and subsequent processes are generally completed by a packaging factory. The structure completed by the CMOS production line is a wafer structure, and the wafer structure includes a plurality of back-illuminated photodiode chips. The wafer structure can be cut to obtain a single back-illuminated photodiode chip.

[0117] Step 150, a through-silicon via structure is formed through the carrier and the bonding layer, and the through-silicon via structure is connected with the electrode and the lead.

[0118] In some embodiments, before the forming of the through-silicon via structure in step 150, the method further comprises: thinning the side of the carrier wafer away from the bonding layer; and forming a second dielectric layer on the side of the carrier wafer away from the bonding layer, the through-silicon via structure also penetrating the second dielectric layer.

[0119] In combination Figure 9 As shown in FIG. 5, the side of the carrier wafer 5 away from the bonding layer 4 is thinned to a suitable thickness. The thickness of the thinned carrier wafer 5 should not be too thin, otherwise the mechanical strength of the wafer will be insufficient for subsequent processes. The thickness of the thinned carrier wafer 5 should not be too thick, otherwise the subsequent through-silicon via process will not be able to completely penetrate the carrier wafer 5.

[0120] Then, in combination Figure 1 As shown in FIG. 6, a second dielectric layer 22 is formed on the side of the carrier wafer 5 away from the bonding layer 4 using a thin film deposition process. A plurality of through-silicon vias (including first through-silicon vias and second through-silicon vias) are formed by an etching process, the through-silicon vias penetrating the second dielectric layer 22, the carrier wafer 5, and the bonding layer 4 to expose the electrodes and the leads 3, the first through-silicon vias and the second through-silicon vias corresponding to the exposed first leads 31 and the second leads 32, respectively. A spacer layer 64 is formed on the sidewalls of the first through-silicon vias and the second through-silicon vias using a thin film deposition process, and then a conductive layer 63 is filled in the first through-silicon vias and the second through-silicon vias to form a through-silicon via structure 6. The through-silicon via structure 6 can include a first through-silicon via substructure 61 located in the first through-silicon via and a second through-silicon via substructure 62 located in the second through-silicon via.

[0121] After the forming of the through-silicon via structure in step 150, the method further comprises:

[0122] A pad is formed on the side of the second dielectric layer away from the carrier wafer, and the pad is connected to the through-silicon via structure.

[0123] In combination Figure 1 As shown in FIG. 7, a pad 9 is formed on the side of the second dielectric layer 22 away from the carrier wafer 5 using a thin film deposition process. The pad 9 can include a first pad point 91 and a second pad point 92 arranged transversely. The first pad point 91 and the second pad point 92 are connected to the first leads 31 and the second leads 32 through the first through-silicon via substructure 61 and the second through-silicon via substructure 62, respectively, so as to lead out the anode and the cathode of the back-illuminated photodiode to the side (non-photosensitive side) of the carrier wafer 5, so that the circumferential side of the back-illuminated photodiode structure is a splicing surface.

[0124] It should be noted that the order of processing the light-sensitive surface and processing the side of the wafer is not limited. In some embodiments, the wafer side is processed first, including wafer thinning, through-silicon via and subsequent processes, and then the light-sensitive surface is processed, including substrate thinning, deep trench isolation and antireflection coating growth, and in this case all processes are completed by the foundry.

[0125] In some embodiments, the thickness of the first dielectric layer 21 is greater than the target thickness to reduce the parasitic capacitance between the first lead 31 and the epitaxial layer 1.

[0126] In some embodiments, the epitaxial layer 1 further includes a floating doped region 12 located on the non-light-sensitive side of the epitaxial layer 1. The floating doped region 12 is opposite in doping type to the epitaxial layer 1, and the floating doped region 12 is located at the bottom of the first lead 31 and is laterally spaced apart from the electrode region 11.

[0127] In combination Figure 2 As shown, before the first dielectric layer 21 is formed, the non-light-sensitive side of the epitaxial layer 1 is doped by an ion implantation process to form the floating doped region 12. The order in which the floating doped region 12, the first highly doped region 111 and the second highly doped region 112 are formed is not specifically limited. In some embodiments, the floating doped region 12 and the first highly doped region 111 can be formed simultaneously, so that the floating doped region 12 and the first highly doped region 111 have the same doping type and doping concentration, avoiding the need for additional masks and reducing production costs.

[0128] A parasitic capacitance is formed between the first lead 31 and the epitaxial layer 1. The floating doped region 12 is added at the bottom of the first lead 31 to form a junction capacitance between the floating doped region 12 and the epitaxial layer 1, and the junction capacitance is connected in series with the parasitic capacitance, thereby reducing the parasitic capacitance.

[0129] In summary, the preparation method of the back-illuminated photodiode structure provided by the embodiments of the present application increases the mechanical strength of the epitaxial layer 1 by forming a bonding layer 4 on the non-light-sensitive side of the epitaxial layer 1 and permanently bonding the wafer 5 through the bonding layer 4, reduces the risk of chipping, and enables the back-illuminated photodiode to be produced on a large-size wafer process line, i.e. suitable for a large-size wafer process line, improving production efficiency and reducing costs. The electrode of the back-illuminated photodiode is drawn out from the side of the wafer 5 through the through-silicon via structure 6, so that the back-illuminated photodiode structure can be spliced on the side, and is suitable for a large-area pixel array.

[0130] The terms "first", "second", and the like in the description and in the claims of this application are used for distinguishing between similar objects and not necessarily for describing a specific sequential or chronological order. It is to be understood that the use of these terms herein is merely for distinguishing between the similar objects and the use of these terms in the description and the claims of this application is not to be construed as implying a specific order or chronology between the similar objects. It is to be understood that the data used herein can be interchanged, where appropriate, without departing from the scope of the application, and that the embodiments of this application can be carried out in other than the order discussed herein without departing from the scope of the application and that "first", "second", etc. differentiated objects are generally of one type and are not limited to specific numbers of objects.

[0131] In the description of the application, "a plurality" means two or more.

[0132] In the description of the application, the use of the terms "one embodiment", "some embodiments", "an illustrative embodiment", "an example", "a specific example", or "some examples" to describe certain features, structures, materials, or characteristics in connection with an embodiment or example are not used to limit or restrict the scope of the embodiments or examples to those features, structures, materials, or characteristics described. Rather, these terms are used herein to simply convey that the particular features, structures, materials, or characteristics being described are included in at least one embodiment or example of the present application. The use of these terms in the description of the application is not to be interpreted to limit or restrict the scope of the application to only those particular features, structures, materials, or characteristics described in connection with the illustrative term.

[0133] While the embodiments of the application have been shown and described herein, it is understood that modifications, substitutions, changes, and alterations can be made by those skilled in the art without departing from the spirit and scope of the application, which is defined by the claims and their equivalents.

Claims

1. A method for fabricating a back-illuminated photodiode structure, characterized in that, The method comprises: providing a substrate, a first dielectric layer and an electrode and a lead, the substrate comprising an epitaxial layer, the epitaxial layer comprising an electrode region on a non-photosensitive side of the epitaxial layer, the first dielectric layer being on the non-photosensitive side of the epitaxial layer, the electrode and the lead being on a side of the first dielectric layer facing away from the epitaxial layer and connected to the electrode region through the first dielectric layer; the electrode region comprising a first highly doped region and a second highly doped region arranged laterally apart, the first highly doped region being opposite to a doping type of the epitaxial layer, the second highly doped region being the same as the doping type of the epitaxial layer; forming a bonding layer on a side of the electrode and the lead facing away from the first dielectric layer, and the bonding layer covering the electrode and the lead; bonding a carrier wafer to a side of the bonding layer facing away from the electrode and the lead; thinning a side of the substrate facing away from the first dielectric layer; forming a through-silicon via structure through the carrier wafer and the bonding layer, and the through-silicon via structure being connected to the electrode and the lead.

2. The method of claim 1, wherein The substrate is a wafer with a size greater than 6 inches.

3. The method of claim 1, wherein the method further comprises: The substrate further comprises a substrate on a photosensitive side of the epitaxial layer, the photosensitive side being arranged opposite to the non-photosensitive side; The thinning of the side of the substrate facing away from the first dielectric layer comprises: removing the substrate and thinning a side of the epitaxial layer facing away from the first dielectric layer.

4. The method of claim 1, wherein After the thinning of the side of the substrate facing away from the first dielectric layer, the method further comprises: forming a deep trench isolation structure on a peripheral side of the electrode region, and the deep trench isolation structure extending from the photosensitive side of the substrate into the epitaxial layer; forming an anti-reflection film on the photosensitive side of the substrate.

5. The method of claim 1, wherein Before the forming of the through-silicon via structure through the carrier wafer and the bonding layer, the method further comprises: thinning a side of the carrier wafer facing away from the bonding layer; forming a second dielectric layer on a side of the carrier wafer facing away from the bonding layer, and the through-silicon via structure further penetrating through the second dielectric layer; After the forming of the through-silicon via structure through the carrier wafer and the bonding layer, the method further comprises: forming a pad on a side of the second dielectric layer facing away from the carrier wafer, and the pad being connected to the through-silicon via structure.

6. A backside illuminated photodiode structure, characterized by A back-illuminated photodiode structure is formed by a method as claimed in any one of claims 1-5, the back-illuminated photodiode structure comprising: an epitaxial layer comprising an electrode region on a non-photosensitive side of the epitaxial layer; a first dielectric layer on the non-photosensitive side of the epitaxial layer; an electrode and a lead on a side of the first dielectric layer facing away from the epitaxial layer and connected to the electrode region through the first dielectric layer; a bonding layer on a side of the electrode and the lead facing away from the first dielectric layer, and the bonding layer covering the electrode and the lead; a carrier wafer bonded to a side of the bonding layer facing away from the electrode and the lead; a through-silicon via structure through the carrier wafer and the bonding layer and connected to the electrode and the lead.

7. The backside illuminated photodiode structure of claim 6, wherein, The back-illuminated photodiode structure further comprises: A deep trench isolation structure extends into the epitaxial layer from a light receiving side of the epitaxial layer, and the deep trench isolation structure is located at a peripheral side of the electrode region, the light receiving side being arranged opposite to the non-light receiving side.

8. The backside illuminated photodiode structure of claim 6, wherein, The back-illuminated photodiode structure further comprises: An anti-reflection film is located at the light receiving side of the epitaxial layer.

9. The backside illuminated photodiode structure of claim 6, wherein, The back-illuminated photodiode structure further comprises: A second dielectric layer is located at a side of the carrier away from the bonding layer, and the through-silicon via structure further penetrates the second dielectric layer; A pad is located at a side of the second dielectric layer away from the carrier and is connected with the through-silicon via structure.

10. The backside illuminated photodiode structure of claim 6, wherein, The thickness of the first dielectric layer is greater than a target thickness.

11. The backside illuminated photodiode structure of claim 6, wherein, The electrode and the lead wire include a lead wire connected with the first high-doped region; The epitaxial layer further comprises a floating doped region located at a non-light receiving side of the epitaxial layer, the floating doped region being opposite to a doped type of the epitaxial layer, the floating doped region being located at a bottom of the lead wire and being arranged laterally spaced apart from the electrode region.

12. The backside illuminated photodiode structure according to any of claims 6-11, wherein, A peripheral side surface of the back-illuminated photodiode structure is a splicable surface.

13. An X-ray detector, characterized by The back-illuminated photodiode structure comprises the back-illuminated photodiode structure according to any one of claims 6-12.

14. The X-ray detector of claim 13, characterized in that The X-ray detector comprises a plurality of the back-illuminated photodiode structures spliced together.

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