A back contact cell and photovoltaic module

Abstract

The application discloses a back contact cell and a photovoltaic module, and relates to the technical field of photovoltaics, which is used for field passivation of a first region and an overlapping region by a doping layer, and the doping layer can form a favorable electric field consistent with an induced direction of a first doped silicon layer, and improve the collection efficiency of the first doped silicon layer on carriers. The back contact cell comprises a semiconductor substrate, a tunnel passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer and a doping layer. The tunnel passivation layer and the first doped silicon layer are sequentially and layerwisely arranged on the first region and the overlapping region. The intrinsic silicon layer and the second doped silicon layer are sequentially and layerwisely arranged on a second region, and further extend to cover the tunnel passivation layer and the first doped silicon layer located in the overlapping region. The doping layer is arranged in the first region and the overlapping region of the semiconductor substrate. The doping concentration of a first doped element in the doping layer, which is of the same conductive type as the first doped silicon layer, is greater than the doping concentration of the first doped element in the second region of the semiconductor substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaic technology, and in particular to a back contact cell and a photovoltaic module. BACKGROUND

[0002] A solar cell is a device capable of converting light energy of the sun into electric energy. Specifically, when the solar cell is in a working state, sunlight is shone on a semiconductor p-n junction of the solar cell to form new hole-electron pairs, under the action of a built-in electric field of the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region, and after connecting a circuit, an electric current can be generated. The solar cell in which the positive electrode and the negative electrode are both on the back surface of the cell is a back contact cell. Compared with a double-sided contact solar cell, the back contact cell has no metal electrode on the front surface, so that the light utilization rate of the light-facing side of the back contact cell is higher, and therefore the back contact cell has higher short-circuit current and photoelectric conversion efficiency, and is one of the technical directions for realizing high-efficiency crystalline silicon cells.

[0003] However, the passivation effect of the back surface side of the existing back contact cell is poor, which is not conducive to improving the conversion efficiency of the back contact cell. SUMMARY

[0004] The present application aims to provide a back contact cell and a photovoltaic module, so as to field passivate the first region and the overlapping region of the semiconductor substrate by the doping layer, and the doping layer can form a favorable electric field consistent with the induction direction of the first doped silicon layer, improve the collection efficiency of the first doped silicon layer for carriers, reduce the recombination rate of carriers, and be conducive to improving the conversion efficiency of the back contact cell.

[0005] To achieve the above object, in a first aspect, the present application provides a back contact cell, comprising a semiconductor substrate, a tunneling passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer and a doped layer. The semiconductor substrate comprises opposite first and second faces. The first face comprises first and second regions and an overlap region between the first and second regions. The tunneling passivation layer and the first doped silicon layer are sequentially stacked on the first and overlap regions along the thickness direction of the semiconductor substrate. The intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region along the thickness direction of the semiconductor substrate. The intrinsic silicon layer and the second doped silicon layer are also extended from the second region to cover the tunneling passivation layer and the first doped silicon layer in the overlap region. The second doped silicon layer has an opposite conductivity type to the first doped silicon layer. The doped layer is disposed in the first and overlap regions of the semiconductor substrate. The doping concentration of a first doped element in the doped layer, which has the same conductivity type as the first doped silicon layer, is greater than the doping concentration of the first doped element in the second region of the semiconductor substrate. The doping concentration of a second doped element in each part of the second region of the semiconductor substrate, which has the same conductivity type as the second doped silicon layer, is the same along the direction from the first face to the second face.

[0006] With the above technical solution, the back contact cell provided by the present application has the selective contact structure composed of the tunneling passivation layer and the first doped silicon layer on the first face of the semiconductor substrate, and also has the selective contact structure composed of the intrinsic silicon layer and the second doped silicon layer. Specifically, the selective contact structure can not only selectively collect carriers, but also passivate the first face of the semiconductor substrate, reduce the carrier recombination rate on the first face side of the semiconductor substrate, and improve the conversion efficiency of the back contact cell. Moreover, the intrinsic silicon layer and the second doped silicon layer are sequentially stacked and also extended from the second region to cover the tunneling passivation layer and the first doped silicon layer in the overlap region. At this time, there is no groove between the first doped silicon layer and the second doped silicon layer along the distribution direction of the first and second regions, which can increase the setting area of the first doped silicon layer and the second doped silicon layer on the first face and improve the carrier collection efficiency.

[0007] Furthermore, a doped layer is disposed in the first region and the overlapping region of the semiconductor substrate. This doped layer contains a first dopant element with the same conductivity type as the first doped silicon layer, and the doping concentration of the first dopant element in the doped layer is greater than that in the second region of the semiconductor substrate. At this point, the doping concentration of the first dopant element in the doped layer is higher, and since the conductivity type of the first dopant element is the same as that of the first doped silicon layer, the doped layer can perform field passivation on the first region and the overlapping region of the semiconductor substrate, improving the passivation effect. Moreover, because the conductivity type of the first dopant element in the doped layer is the same as that of the first doped silicon layer, the doped layer can form a favorable electric field consistent with the induced direction of the first doped silicon layer. The presence of this favorable electric field can repel minority carriers and attract majority carriers on the surface of the first region and the overlapping region of the semiconductor substrate, improving the carrier collection efficiency of the first doped silicon layer, further reducing the carrier recombination rate, and thus improving the conversion efficiency of the back contact battery.

[0008] Furthermore, along the direction from the first surface to the second surface, the doping concentration of the second doping element with the same conductivity type as the second doped silicon layer is the same in each part of the second region of the semiconductor substrate. In other words, there is no inward doping region with the same conductivity type as the second doped silicon layer in the second region of the semiconductor substrate. This can prevent the doped layer and the inward doping region with the opposite conductivity type from making electrical contact, which would lead to a high risk of leakage and ensure that the back contact battery has a high conversion efficiency.

[0009] As one possible implementation, the second region includes a groove. Along the direction from the second surface to the first surface, the surface height of the portion of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate is less than the surface height of the doped layer away from the tunneling passivation layer.

[0010] In the above technical solution, the second region includes a groove. The presence of this groove not only indicates that after patterning the tunneling passivation layer and the first doped silicon layer formed in one layer, the portions of both located in the second region have been completely removed, improving the yield of the back contact cell, but also, because the surface height of the portion of the second doped silicon layer at the bottom of the groove away from the semiconductor substrate is less than the surface height of the doped layer away from the tunneling passivation layer, there are no structurally aligned portions of the doped layer and the second doped silicon layer along the thickness direction of the semiconductor substrate. In other words, the presence of the groove also allows the doped layer and the first doped silicon layer to be staggered from the second doped silicon layer, which has an opposite conductivity type, along the thickness direction of the semiconductor substrate, reducing the risk of leakage between the doped layer and the second doped silicon layer, and further improving the conversion efficiency of the back contact cell. In addition, it is understandable that the portion of the second doped silicon layer located at the bottom of the trench is mainly used to collect and export charge carriers. Therefore, the surface height of the portion of the second doped silicon layer located at the bottom of the trench away from the semiconductor substrate is set to be less than the surface height of the doped layer away from the tunneling passivation layer. This also helps to prevent the first doping element in the doped layer, which has the opposite conductivity type to the second doped silicon layer, from diffusing into the second doped silicon layer, thus ensuring that the second doped silicon layer has a high charge carrier collection capability for the portion at the bottom of the trench.

[0011] As one possible implementation, the depth of the groove is greater than or equal to 300 nm and less than or equal to 15 μm.

[0012] When the above technical solution is adopted, the depth of the groove is within the aforementioned range. This helps to prevent a small gap between the doped layer and the second doped silicon layer at the bottom of the groove along the thickness direction of the semiconductor substrate, which would otherwise result in a higher risk of leakage. Furthermore, it also prevents a large groove depth from causing a small light absorption depth in the corresponding portion of the semiconductor substrate, ensuring high photoelectric conversion efficiency of the semiconductor substrate and thus ensuring high performance of the back contact battery.

[0013] As one possible implementation, along the direction from the second surface to the first surface, the difference between the surface height of the second doped silicon layer located at the bottom of the trench on the side facing away from the semiconductor substrate and the surface height of the doped layer on the side facing away from the tunneling passivation layer is greater than or equal to 180 nm and less than or equal to 14.7 μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the trench depth being greater than or equal to 300 nm and less than or equal to 15 μm described above, and will not be repeated here.

[0014] As one possible implementation, the width of the doped layer is greater than or equal to the width of the first doped silicon layer along the width direction of the overlapping region. In this case, the doped layer has a larger formation range, which is beneficial to improving the field passivation effect of the doped layer and further reducing the carrier recombination rate on one side of the first surface of the semiconductor substrate.

[0015] As one possible implementation, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer is greater than 0 and less than or equal to 50 μm. In this case, the width of the doped layer is approximately the same as the width of the first doped silicon layer, ensuring that the first region and the overlapping region of the semiconductor substrate have a high carrier recombination rate under the passivation effect of the doped layer. Furthermore, it is understood that the overlapping region is adjacent to the second region, and the second doped silicon layer located in the second region is mainly used to collect and extract carriers, while the conductivity type of the first dopant element in the doped layer is opposite to that of the second doped silicon layer. Based on this, when the difference between the width of the doped layer and the width of the first doped silicon layer is within the above range, it can prevent a large width of the doped layer from causing a small distance between the edge of the doped layer and the edge of the second doped silicon layer, reducing the risk of leakage between the doped silicon and the second doped silicon layer.

[0016] As one possible implementation, the second region includes a groove. Along the width direction of the overlapping region, the sides of the groove have continuously distributed first and second sub-regions, with the second sub-region being close to the first region. The surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of ​​the portion of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface. The surface of the second sub-region is planar. Furthermore, the doped layer extends to the second sub-region of the semiconductor substrate; or, the doped layer extends to the second sub-region of the semiconductor substrate and to a portion of the first sub-region close to the second sub-region.

[0017] With the above technical solution, when the depth of the groove is fixed, the surface of the first sub-region on the side of the groove is inclined relative to the surface of the first region, and the cross-sectional area of ​​the part of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface. This is beneficial to increase the lateral spacing between the doped layer and the second doped silicon layer located on the bottom of the groove, so that the edge of the doped layer only extends from the overlapping area to the second sub-region of the semiconductor substrate and the part of the first sub-region near the second sub-region, and does not extend to the bottom surface of the groove, further reducing the risk of leakage between the two.

[0018] As one possible implementation, the doping concentration of the first dopant element in the doped layer gradually increases along the direction from the second surface to the first surface. In this case, a high-low junction can be formed between different regions of the doped layer along the direction from the second surface to the first surface. The built-in electric field of the high-low junction is consistent with the induced direction of the first doped silicon layer, which can further improve the carrier collection efficiency of the first doped silicon layer, further reduce the carrier recombination rate, and help improve the conversion efficiency of the back contact cell.

[0019] As one possible implementation, the doping concentration of the first doped element within the first doped silicon layer is greater than that within the doped layer. In this case, the first doped silicon layer ensures a higher field passivation effect, improving its carrier collection capability. Furthermore, a high-low junction can be formed between the first doped silicon layer and the doped layer, with the built-in electric field direction of this high-low junction aligned with the induced direction of the first doped silicon layer, further enhancing its carrier collection capability.

[0020] As one possible implementation, the aforementioned back contact battery further includes a transparent conductive layer. The transparent conductive layer covers the side of the first doped silicon layer and the second doped silicon layer facing away from the semiconductor substrate. Insulating trenches are provided within the transparent conductive layer to disconnect portions of the transparent conductive layer corresponding to the first and second regions from each other. The portion of the transparent conductive layer with the same carrier conductivity type as the second doped silicon layer does not overlap with the doped layer along the thickness direction of the semiconductor substrate. In this case, the transparent conductive layer has good conductivity, which can improve carrier collection efficiency. Furthermore, the absence of overlap between the portion of the transparent conductive layer with the same carrier conductivity type as the second doped silicon layer and the doped layer along the thickness direction of the semiconductor substrate prevents the portion of the transparent conductive layer with the same carrier conductivity type as the second doped silicon layer from overlapping with a doped silicon layer doped with a first dopant element with a conductivity type opposite to that of the second doped silicon layer, thus preventing an increase in leakage risk and ensuring high electrical reliability of the back contact battery.

[0021] As one possible implementation, the doping depth of the doped layer along the thickness direction of the semiconductor substrate is greater than or equal to 1 nm and less than or equal to 300 nm.

[0022] When the above technical solution is adopted, the doping depth of the doped layer is within the aforementioned range, which helps to prevent poor field passivation capability due to a shallow doping depth. Furthermore, it also prevents a high Auger recombination rate in the semiconductor substrate due to a large doping depth, thus avoiding negative impacts on passivation and ensuring a low carrier recombination rate in the first region and overlapping region of the doped layer on the semiconductor substrate. If, during the actual manufacturing process, the first dopant element in the doped layer diffuses from the first doped silicon layer into the doped layer, then the doping depth within the aforementioned range also prevents a low doping concentration of the first dopant element in the first doped silicon layer due to a large doping depth, ensuring a high carrier collection efficiency in the first doped silicon layer.

[0023] As one possible implementation, the doping concentration of the first dopant element in the aforementioned doped layer is less than or equal to 9 × 10⁻⁶. 20 / cm 3 And greater than or equal to 8 × 10 9 / cm 3 In this case, a poor passivation effect due to a low doping concentration of the first dopant element within the doped layer can be prevented. Additionally, a high doping concentration of the first dopant element within the doped layer can prevent band dips that would result in low carrier collection efficiency in the first doped silicon layer, ensuring high conversion efficiency for the back contact cell. If, during actual manufacturing, the first dopant element diffuses from the first doped silicon layer into the doped layer, and the doping concentration of the first dopant element within the doped layer is within the aforementioned range, a low doping concentration of the first dopant element within the first doped silicon layer can also be prevented due to a high doping concentration, ensuring high carrier collection efficiency for the first doped silicon layer.

[0024] As one possible implementation, the thickness of the first doped silicon layer is greater than or equal to 20 nm and less than or equal to 300 nm.

[0025] With the above technical solution, the thickness of the first doped silicon layer within the aforementioned range can prevent a low field passivation effect due to a small thickness, ensuring that the first doped silicon layer has a high carrier collection efficiency. Furthermore, if, during the actual manufacturing process, the first dopant element diffuses from the first doped silicon layer into the doped layer, the thickness of the first doped silicon layer within the aforementioned range can also prevent a low doping concentration of the first dopant element diffused from the first doped silicon layer into the doped layer due to a small thickness, ensuring that the doped layer has a high field passivation effect. Additionally, it can prevent a large amount of consumable material from being used for the first doped silicon layer due to a large thickness, and also prevent the problem of excessively high doping concentration of the first dopant element within the doped layer, ensuring that the back contact cell has a high conversion efficiency.

[0026] As one possible implementation, the doping concentration of the first doped element in the first doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 The application principle of the beneficial effect in this case is similar to that of the beneficial effect described above when the thickness of the first doped silicon layer is greater than or equal to 20 nm and less than or equal to 300 nm, and will not be repeated here.

[0027] As one possible implementation, the thickness of the intrinsic silicon layer is greater than or equal to 5 nm and less than or equal to 20 nm.

[0028] With the above technical solution, in the second region of the semiconductor substrate, the intrinsic silicon layer is located between the semiconductor substrate and the second doped silicon layer, and it can act as a diffusion barrier for the dopants in the second doped silicon layer. Based on this, the thickness of the intrinsic silicon layer, within the aforementioned range, can prevent a weak diffusion barrier effect on the dopants in the second doped silicon layer due to a small intrinsic silicon layer thickness, ensuring that no inwardly diffused doped layer with the same conductivity type as the second doped silicon layer is formed in the second region. Furthermore, it can also prevent a large transport resistance due to a large intrinsic silicon layer thickness, ensuring that the second doped silicon layer has a high carrier collection efficiency.

[0029] As one possible implementation, the doping concentration of the second doped element in the second doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3In this case, while ensuring that the second doped silicon layer has a high field passivation effect, it prevents the second doping element in the second doped silicon layer from easily diffusing into the second region of the semiconductor substrate to form an inner doped layer. It also ensures that the doped layer will not make electrical contact with the inner doped region with the opposite conductivity type, which would lead to a high risk of leakage, thereby ensuring that the back contact cell has a high conversion efficiency.

[0030] As one possible implementation, the thickness of the second doped silicon layer is greater than or equal to 10 nm and less than or equal to 100 nm. The beneficial effect in this case can be understood by referring to the previously mentioned principle that the doping concentration of the second dopant element within the second doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 The application principles behind its beneficial effects will not be elaborated here.

[0031] As one possible implementation, the sum of the thicknesses of the second doped silicon layer and the intrinsic silicon layer is greater than or equal to 15 nm and less than or equal to 120 nm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect described above when the thickness of the intrinsic silicon layer is greater than or equal to 5 nm and less than or equal to 20 nm, and the thickness of the second doped silicon layer is greater than or equal to 10 nm and less than or equal to 100 nm, which will not be repeated here.

[0032] As one possible implementation, the conductivity types of the first doped silicon layer and the doped layer are the same as those of the semiconductor substrate. The second region of the semiconductor substrate does not contain a second doping element. In this case, a high-low junction can be formed between each adjacent pair of the semiconductor substrate, the doped layer, and the first doped silicon layer. Under the built-in electric field of the high-low junction, the carrier collection efficiency of the first doped silicon layer can be further improved, thereby further enhancing the conversion efficiency of the back contact cell. Furthermore, the presence of a second doping element with a conductivity type opposite to that of the doped layer within the second region of the semiconductor substrate ensures that the doped layer will not make electrical contact with the inwardly expanding doped region with a conductivity type opposite to its own, thus preventing a high risk of leakage and ensuring a high conversion efficiency for the back contact cell.

[0033] As one possible implementation, the conductivity type of the doped layer and the first doped silicon layer is N-type, and the conductivity type of the second doped silicon layer is P-type.

[0034] As one possible implementation, the second region includes a groove with a textured bottom surface, and the thickness of the second doped silicon layer on the bottom of the groove is less than the thickness of the second doped silicon layer in the overlapping region.

[0035] With the above technical solution, the thickness of the second doped silicon layer at the bottom of the groove is small. This can ensure good field passivation while preventing the diffusion of more second doped elements into the second region of the semiconductor substrate due to the larger thickness of the second doped silicon layer at the bottom of the groove. This ensures that the doped layer will not make electrical contact with the inner expansion doped region with the opposite conductivity type, thus preventing a high risk of leakage. In this way, the back contact battery has a high conversion efficiency.

[0036] In a second aspect, the present invention provides a photovoltaic module comprising a back contact battery provided in the first aspect and various implementations thereof.

[0037] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0039] Figure 1 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 1 ;

[0040] Figure 2 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 2 ;

[0041] Figure 3 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 3 ;

[0042] Figure 4 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 4 ;

[0043] Figure 5 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 5 ;

[0044] Figure 6 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 6 ;

[0045] Figure 7 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 7 ;

[0046] Figure 8A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 8 ;

[0047] Figure 9 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 9 ;

[0048] Figure 10 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 10 ;

[0049] Figure 11 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 10 one;

[0050] Figure 12 A schematic diagram of the structure of a back contact battery provided in an embodiment of the present invention. Figure 10 two.

[0051] Reference numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is an overlapping region, 15 is a tunneling passivation layer, 16 is a first doped silicon layer, 17 is an intrinsic silicon layer, 18 is a second doped silicon layer, 19 is a doped layer, 20 is a trench, 21 is a first sub-region, 22 is a second sub-region, 23 is a transparent conductive layer, 24 is an insulating trench, 25 is a surface passivation layer, and 26 is an anti-reflection layer. Detailed Implementation

[0052] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0053] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0054] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0056] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0057] In a first aspect, embodiments of the present invention provide a back-contact battery. For example... Figure 1As shown, the back contact battery provided in this embodiment of the invention includes: a semiconductor substrate 11, a tunneling passivation layer 15, a first doped silicon layer 16, an intrinsic silicon layer 17, a second doped silicon layer 18, and a doped layer 19. The semiconductor substrate 11 includes a first surface and a second surface opposite to each other. The first surface includes an alternately spaced first region 12 and a second region 13, and an overlapping region 14 located between the first region 12 and the second region 13. Along the thickness direction of the semiconductor substrate 11, the tunneling passivation layer 15 and the first doped silicon layer 16 are sequentially stacked on the first region 12 and the overlapping region 14. Along the thickness direction of the semiconductor substrate 11, the intrinsic silicon layer 17 and the second doped silicon layer 18 are sequentially stacked on the second region 13. Furthermore, the stacked intrinsic silicon layer 17 and the second doped silicon layer 18 extend from the second region 13 to cover the tunneling passivation layer 15 and the first doped silicon layer 16 located on the overlapping region 14. It is understood that the overlapping region 14 refers to the region where the tunneling passivation layer 15 and the first doped silicon layer 16, the intrinsic silicon layer 17, and the second doped silicon layer 18 are simultaneously disposed. The conductivity type of the second doped silicon layer 18 is opposite to that of the first doped silicon layer 16. The doped layer 19 is disposed within the first region 12 and the overlapping region 14 of the semiconductor substrate 11. The doping concentration of the first dopant element with the same conductivity type as the first doped silicon layer 16 in the doped layer 19 is greater than the doping concentration of the first dopant element in the second region 13 of the semiconductor substrate 11. Along the direction from the first surface to the second surface, the doping concentration of the second dopant element with the same conductivity type as the second doped silicon layer 18 is the same in each part of the second region 13 of the semiconductor substrate 11.

[0058] When the above technical solution is adopted, such as Figure 1As shown, in the back-contact battery provided in this embodiment of the invention, the first surface of the semiconductor substrate 11 is not only provided with a selective contact structure composed of a tunneling passivation layer 15 and a first doped silicon layer 16, but also with a selective contact structure composed of an intrinsic silicon layer 17 and a second doped silicon layer 18. Specifically, the above-mentioned selective contact structure can not only achieve selective collection of charge carriers, but also passivate the first surface of the semiconductor substrate 11, reducing the carrier recombination rate on one side of the first surface of the semiconductor substrate 11, which is beneficial to improving the conversion efficiency of the back-contact battery. Furthermore, the stacked intrinsic silicon layer 17 and second doped silicon layer 18 extend from the second region 13 to cover the tunneling passivation layer 15 and the first doped silicon layer 16 located on the overlapping region 14. At this time, there is no groove isolation between the first doped silicon layer 16 and the second doped silicon layer 18 along the distribution direction of the first region 12 and the second region 13, which can increase the area of ​​the first doped silicon layer 16 and the second doped silicon layer 18 on the first surface and improve the carrier collection efficiency. In addition, a doped layer 19 is provided in the first region 12 and the overlapping region 14 of the semiconductor substrate 11. The doped layer 19 is doped with a first doping element of the same conductivity type as the first doped silicon layer 16, and the doping concentration of the first doping element in the doped layer 19 is greater than the doping concentration of the first doping element in the second region 13 of the semiconductor substrate 11. At this time, the doping concentration of the first doping element in the doped layer 19 is high, and the conductivity type of the first doping element is the same as that of the first doped silicon layer 16. Therefore, the first region 12 and the overlapping region 14 of the semiconductor substrate 11 can be field passivated by the doped layer 19, thereby improving the passivation effect. Furthermore, the conductivity type of the first doped element in the doped layer 19 is the same as that of the first doped silicon layer 16. Therefore, the doped layer 19 can form a favorable electric field consistent with the induced direction of the first doped silicon layer 16. The presence of this favorable electric field can repel minority carriers and attract majority carriers on the surface of the first region 12 and the overlapping region 14 of the semiconductor substrate 11, thereby improving the carrier collection efficiency of the first doped silicon layer 16 and further reducing the carrier recombination rate, which is beneficial to improving the conversion efficiency of the back contact battery. Moreover, along the direction from the first surface to the second surface, the doping concentration of the second doped element with the same conductivity type as the second doped silicon layer 18 is the same in each part of the second region 13 of the semiconductor substrate 11. That is to say, there is no inward doping region with the same conductivity type as the second doped silicon layer 18 in the second region 13 of the semiconductor substrate 11. This can prevent the doped layer 19 from making electrical contact with the inward doping region with the opposite conductivity type to the doped layer 19 (i.e., the inward doping region with the same conductivity type as the second doped silicon layer 18), which would lead to a high risk of leakage, thus ensuring that the back contact battery has a high conversion efficiency.

[0059] In the actual application process, the embodiments of the present invention do not specifically limit the material and conductivity type of the semiconductor substrate. Exemplarily, the above semiconductor substrate may be a silicon substrate; or, the above semiconductor substrate may also be a substrate of any semiconductor material such as a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate. Additionally, the above semiconductor substrate may be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0060] Secondly, the above semiconductor substrate includes opposite first and second surfaces. The first surface of the semiconductor substrate corresponds to the backlight surface of the back-contact battery, and the second surface of the semiconductor substrate corresponds to the light-facing surface of the back-contact battery. Among them, the distribution of the above first region, second region, and overlapping region on the first surface can be determined according to the distribution of the first doped silicon layer and the second doped silicon layer formed on the first surface. Specifically, since the first doped silicon layer included in the back-contact battery is disposed on the first region and the overlapping region, the distribution ranges of the first region and the overlapping region on the first surface can be determined according to the distribution requirements of the first doped silicon layer in the actual application scenario. Since a partial region of the second doped silicon layer included in the back-contact battery is disposed on the second region of the first surface, the distribution range of the second region on the first surface can be determined according to the distribution requirements of the second doped silicon layer on the semiconductor substrate in the actual application scenario. It can be understood that for the first surface, except for the first region and the overlapping region, other regions are the second region.

[0061] It can be understood that the first region corresponds to the first emitter region, and the second region corresponds to the second emitter region. One of the first region and the second region corresponds to the P region, the other corresponds to the N region, and the overlapping region corresponds to the PN overlapping region.

[0062] As for the specific morphologies of the first region and the second region, they can be set according to actual needs. For example: the first region and the second region can be alternately spaced in a strip shape, or can be alternately spaced in a finger shape (i.e., similar to a Feng character shape).

[0063] In terms of the surface morphology, as Figure 1 shown, the first and second surfaces of the semiconductor substrate 11 can be flat. Or, as Figure 2 shown, the second surface of the semiconductor substrate 11 can also be a matte surface to improve the light trapping effect of the second surface and improve the light utilization rate of the semiconductor substrate 11. Of course, in the first surface, it can also be that the surface of a partial region (such as the second region) is a matte surface, and the surface of a partial region (such as the first region) is flat.

[0064] Secondly, as Figure 1 and Figure 2 shown, the surfaces of the first region 12 and the second region 13 of the first surface can be flush; or, as Figure 3As shown, the second region 13 may also include a groove 20. In this case, along the direction from the second surface to the first surface, the surface height of the second region 13 corresponding to the groove 20 is lower than the surface height of the first region 12. In this situation, the presence of the groove 20 not only indicates that after patterning the tunneling passivation layer 15 and the first doped silicon layer 16 formed in the entire layer, the portions of both located in the second region 13 have been completely removed, improving the yield of the back contact battery, but also that the presence of the groove 20 can at least partially offset the first doped silicon layer 16 and the second doped silicon layer 18, which have opposite conductivity types, along the thickness direction of the semiconductor substrate 11, reducing the leakage risk between the first doped silicon layer 16 and the second doped silicon layer 18, and further improving the conversion efficiency of the back contact battery.

[0065] As for the depth of the groove, it can be set according to actual needs; no specific limit is set here. Additionally, if... Figure 3 As shown, the surface of the groove 20 can be a plane; or as... Figure 4 As shown, the bottom surface of the groove 20 can also be a textured surface to increase the contact area between the second doped silicon layer 18 formed on the second region 13 and the corresponding conductive material (transparent conductive layer 23 or metal electrode, etc.), which helps to reduce transmission loss.

[0066] Specifically, such as Figure 3 As shown, the side surface of the groove 20 can be perpendicular to the bottom surface of the groove 20. Or, as... Figure 4 and Figure 5 As shown, at least a portion of the side surface of the groove 20 can also be inclined relative to the bottom surface of the groove, and the cross-sectional area of ​​the bottom of the groove 20 is smaller than the cross-sectional area of ​​the opening; in this case, the entire side surface of the groove 20 can be inclined relative to the bottom surface of the groove; or, along the width direction of the overlapping region 14, the side surface of the groove 20 has a continuously distributed first sub-region 21 and a second sub-region 22, and the second sub-region 22 is close to the first region 12. The surface of the first sub-region 21 is inclined relative to the surface of the first region 12, and the cross-sectional area of ​​the portion of the groove 20 corresponding to the first sub-region 21 gradually increases along the direction from the second surface to the first surface. The surface of the second sub-region 22 is a plane, which can be parallel to the second surface or inclined relative to the second surface. Furthermore, in this case, with the depth of the groove 20 fixed, the surface of the first sub-region 21 on the side of the groove 20 is inclined relative to the surface of the first region 12, and the cross-sectional area of ​​the portion of the groove 20 corresponding to the first sub-region 21 gradually increases along the direction from the second surface to the first surface. This is beneficial to increase the lateral spacing between the doped layer 19 and the second doped silicon layer 18 located at the bottom of the groove, thereby reducing the risk of leakage between them. In addition, since the second doped silicon layer 18 is formed relatively gently on the inclined surface corresponding to the first sub-region 21, it is beneficial to improve the film formation quality of the second doped silicon layer 18.

[0067] In addition, such asFigure 4 As shown, along the direction from the first surface to the second surface, the doping concentration of the second doped element with the same conductivity type as the second doped silicon layer 18 is the same in each part of the second region 13 of the semiconductor substrate 11. Specifically, the doping concentration of the second doped element in each part of the second region 13 of the semiconductor substrate 11 can all be 0, that is, there is no second doped element in each part of the second region 13 of the semiconductor substrate 11; or, the second doped element can also be doped in each part of the second region 13 of the semiconductor substrate 11, but the distribution concentration of the second doped element at each position in the semiconductor substrate 11 corresponding to the second region 13 is the same. The doping concentration of the doped element in the second region 13 can be determined according to the actual application scenario, and is not specifically limited here. It should be noted that, in the actual manufacturing process, if the dopant element in the second doped silicon layer 18 diffuses through the intrinsic silicon layer 17 into the second region 13 of the semiconductor substrate 11, according to the diffusion principle, the doping concentration of the dopant element diffused from the second doped silicon layer 18 into the second region 13 of the semiconductor substrate 11 will gradually decrease along the direction from the first surface to the second surface. However, in the embodiment of the present invention, along the direction from the first surface to the second surface, the doping concentration of the second dopant element with the same conductivity type as the second doped silicon layer 18 is the same in each part of the second region 13 of the semiconductor substrate 11. Therefore, even if there is a second dopant element in the second region 13 of the semiconductor substrate 11, the second dopant element is not formed by the diffusion of the second doped silicon layer 18, but is the second dopant element doped by the semiconductor substrate 11 itself.

[0068] Regarding the aforementioned tunneling passivation layer and the first doped silicon layer, from a material perspective, the tunneling passivation layer can be made of any passivation material with a tunneling effect, such as silicon oxide, aluminum oxide, titanium oxide, and zinc oxide. Secondly, the aforementioned first doped silicon layer can be a doped crystalline silicon layer, and the material of this doped crystalline silicon layer can include polycrystalline silicon and / or monocrystalline silicon.

[0069] In terms of conductivity type, the first doped silicon layer can be N-type, and the second doped silicon layer can be P-type; alternatively, the first doped silicon layer can also be P-type, and the second doped silicon layer can be N-type. Optionally, when the material of the first doped silicon layer includes polycrystalline silicon, the conductivity type of the first doped silicon layer is N-type. In this case, compared to P-type doped amorphous, microcrystalline, and nanocrystalline materials (i.e., the second doped silicon layer is P-type), when the material of the first doped silicon layer is P-type polycrystalline silicon, the contact resistance between the P-type doped polycrystalline silicon material and the conductive material is higher, and the field passivation effect is poorer. Therefore, setting the conductivity type of the first doped silicon layer to N-type and the conductivity type of the second doped silicon layer to P-type can further improve the field passivation effect of the first doped silicon layer, while reducing the contact resistance between the first doped silicon layer and the conductive material, which is beneficial for improving the electrical performance of the back contact battery.

[0070] The thickness of the tunneling passivation layer and the first doped silicon layer can be set according to actual needs, and no specific limit is made here.

[0071] For example, the thickness of the tunneling passivation layer can be greater than or equal to 0.5 nm and less than or equal to 2.5 nm. For instance, the thickness of the tunneling passivation layer can be 0.5 nm, 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 2 nm, 2.2 nm, or 2.5 nm, etc. In this case, it can prevent the tunneling resistance from being too high due to a larger thickness of the tunneling passivation layer, thus affecting the carrier collection efficiency of the first doped silicon layer. Furthermore, it is understood that within a certain thickness range, the thickness of the tunneling passivation layer is proportional to its diffusion blocking effect. Therefore, if, in the actual manufacturing process, at least a portion of the first doped element in the doped layer is formed by the first doped element in the first doped silicon layer diffusing through the tunneling passivation layer to the first region and overlapping region of the semiconductor substrate, then the thickness of the tunneling passivation layer within the aforementioned range can also prevent the doping concentration of the first doped element in the doped layer from being too low or too high due to excessive thickness, thus affecting the field passivation effect of the doped layer and avoiding high carrier recombination rates in the first region and overlapping region.

[0072] For example, the thickness of the first doped silicon layer can be greater than or equal to 20 nm and less than or equal to 300 nm. For instance, the thickness of the first doped silicon layer can be 20 nm, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 260 nm, 280 nm, or 300 nm. In this case, the thickness of the first doped silicon layer within the above range can prevent a low field passivation effect due to a small thickness, ensuring that the first doped silicon layer has a high carrier collection efficiency. Furthermore, if, during the actual manufacturing process, the first dopant element in the doped layer diffuses from the first doped silicon layer into the doped layer, then the thickness of the first doped silicon layer within the above range can also prevent a low doping concentration of the first dopant element diffused from the first doped silicon layer into the doped layer due to a small thickness. Therefore, setting the thickness of the first doped silicon layer within the above range can ensure that the doped layer has a high field passivation effect. In addition, it can prevent the large amount of consumables used for the first doped silicon layer due to its large thickness, and the problem of excessively high doping concentration of the first doped element in the doped layer, thus ensuring that the back contact battery has a high conversion efficiency.

[0073] It should be noted that the first dopant element can be of one type, such as phosphorus; or, the first dopant element can be of multiple types with the same conductivity, such as phosphorus and arsenic. The type of the first dopant element within the first doped silicon layer can be the same as or different from the type of the first dopant element within the doped layer. For example, if both the first doped silicon layer and the doped layer have an N-type conductivity, both the first doped silicon layer and the first dopant element within the doped layer can be phosphorus. Another example: if both the first doped silicon layer and the doped layer have a P-type conductivity, both the first doped silicon layer and the first dopant element within the doped layer can be boron. Yet another example: if both the first doped silicon layer and the doped layer have an N-type conductivity, the first dopant element within the first doped silicon layer can be phosphorus, while the first dopant element within the doped layer can be arsenic. It is understood that if, during the actual manufacturing process, the first dopant element in the doped layer diffuses from the first doped silicon layer into the doped layer, then the type of the first dopant element within the first doped silicon layer is the same as the type of the first dopant element within the doped layer. In the above case, the doping concentration of the first doped element in the first doped silicon layer will affect its field passivation performance. Secondly, in the actual manufacturing process, if at least part of the first doped element in the doped layer diffuses from the first doped silicon layer into the doped layer, the doping concentration of the first doped element in the first doped silicon layer will also affect the doping concentration of the first doped element in the doped layer. Therefore, it can be determined according to the field passivation effect of the first doped silicon layer and the doping concentration requirements of the first doped element in the doped layer in the actual application scenario. No specific limitation is made here.

[0074] For example, the doping concentration of the first doped element in the first doped silicon layer can be greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 For example, the doping concentration of the first doped element in the first doped silicon layer can be 1×10⁻⁶. 18 / cm 3 1×10 19 / cm 3 2×10 19 / cm 3 4×10 19 / cm 3 6×10 19 / cm 3 8×10 19 / cm 3 1×10 20 / cm 3 2×10 20 / cm 3 4×10 20 / cm 3 6×10 20 / cm 3 8×10 20 / cm 3 9×10 20 / cm 3 Or 1×10 21 / cm 3 The application principle of the beneficial effect in this case is similar to that of the beneficial effect described above when the thickness of the first doped silicon layer is greater than or equal to 20 nm and less than or equal to 300 nm, and will not be repeated here.

[0075] Regarding the intrinsic silicon layer and the second doped silicon layer mentioned above, in terms of materials, the materials of the intrinsic silicon layer and / or the second doped silicon layer may include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0076] In terms of formation location, such as Figure 4 As shown, the intrinsic silicon layer 17 and the second doped silicon layer 18, which are stacked together, extend to cover the portion above the overlapping region 14, and can be directly located on the tunneling passivation layer 15 and the first doped silicon layer 16, and are in contact with the first doped silicon layer 16. Alternatively, as... Figure 6As shown, the back contact battery may further include an insulating layer 27, which is located between the intrinsic silicon layer 17 and the first doped silicon layer 16 in the overlapping region 14. In this case, the insulating layer 27 isolates the second doped silicon layer 18 from the first doped silicon layer 16 in the overlapping region 14, reducing forward leakage loss and further improving the conversion efficiency of the back contact battery. The material and thickness of the insulating layer can be determined according to the actual application scenario and are not specifically limited here. For example, the insulating layer may include a silicon oxide layer and / or an aluminum oxide layer, etc.

[0077] Furthermore, as mentioned earlier, there is no internal doping layer corresponding to the second doped silicon layer in the second region of the semiconductor substrate. On the second region of the semiconductor substrate, the intrinsic silicon layer is located between the semiconductor substrate and the second doped silicon layer. It acts as a diffusion barrier for the dopants within the second doped silicon layer. Therefore, the thickness of the intrinsic silicon layer not only affects its own transmission resistance but also the doping concentration of the second doping element within the semiconductor substrate (the second doping element can be a single type, such as boron; or multiple types of the same conductivity type, such as boron and aluminum). In addition, the thickness of the second doped silicon layer and the doping concentration of the second doping element within it not only affect the field passivation effect of the second doped silicon layer but may also affect whether the second doping element within the second doped silicon layer diffuses into the second region of the semiconductor substrate. Therefore, the thickness of the intrinsic silicon layer can be determined based on the requirements for transmission resistance and diffusion barrier effect in the actual application scenario. Furthermore, the thickness and doping concentration of the second doped silicon layer can be determined based on the requirements for field passivation effect and the diffusion requirements of the second doping element within the second doped silicon layer in the actual application scenario; no specific limitations are made here.

[0078] For example, the thickness of the intrinsic silicon layer can be greater than or equal to 5 nm and less than or equal to 20 nm. For instance, the thickness of the intrinsic silicon layer can be 5 nm, 7 nm, 9 nm, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm, or 20 nm. In this case, the thickness of the intrinsic silicon layer within the above range can prevent a weak diffusion barrier effect on the dopant elements in the second doped silicon layer due to a small intrinsic silicon layer thickness. This ensures that no inward doped layer with the same conductivity type as the second doped silicon layer is formed in the second region. Furthermore, it can prevent a large intrinsic silicon layer thickness from resulting in a large transport resistance, thus ensuring that the second doped silicon layer has a high carrier collection efficiency.

[0079] For example, the doping concentration of the second doped element in the second doped silicon layer can be greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3For example, the doping concentration of the second doped element in the second doped silicon layer can be 1×10⁻⁶. 18 / cm 3 1×10 19 / cm 3 2×10 19 / cm 3 4×10 19 / cm 3 6×10 19 / cm 3 8×10 19 / cm 3 1×10 20 / cm 3 2×10 20 / cm 3 4×10 20 / cm 3 6×10 20 / cm 3 8×10 20 / cm 3 9×10 20 / cm 3 Or 1×10 21 / cm 3 In this case, while ensuring that the second doped silicon layer has a high field passivation effect, it is necessary to prevent the high doping concentration of the second doped element in the second doped silicon layer from causing an excessive difference in doping concentration between the second doped silicon layer and the second region of the semiconductor substrate, which could easily diffuse into the second region of the semiconductor substrate and form an inner doped layer. This ensures that the doped layer will not make electrical contact with the inner doped layer, which has an opposite conductivity type, thus preventing a high risk of leakage current, and thereby ensuring that the back contact cell has a high conversion efficiency.

[0080] For example, the thickness of the second doped silicon layer can be greater than or equal to 10 nm and less than or equal to 100 nm. For instance, the thickness of the second doped silicon layer can be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm, etc. The application principle of the beneficial effect in this case can be referred to the previously mentioned method where the doping concentration of the second doping element in the second doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 The application principle of its beneficial effects will not be elaborated here. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer.

[0081] For example, the sum of the thicknesses of the second doped silicon layer and the intrinsic silicon layer can be greater than or equal to 15 nm and less than or equal to 120 nm. For instance, the sum of the thicknesses of the second doped silicon layer and the intrinsic silicon layer can be 15 nm, 20 nm, 30 nm, 50 nm, 70 nm, 90 nm, 100 nm, or 120 nm, etc. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects described above for intrinsic silicon layer thicknesses greater than or equal to 5 nm and less than or equal to 20 nm, and for second doped silicon layer thicknesses greater than or equal to 10 nm and less than or equal to 100 nm, which will not be repeated here.

[0082] In addition, such as Figure 6 As shown, when the second region 13 includes a groove 20, the depth of the groove 20 affects the alignment between the portion of the second doped silicon layer 18 at the bottom of the groove 20 and the doped layer 19 located in the first region 12 and the overlapping region 14. Furthermore, since the conductivity type of the first doped element in the doped layer 19 is opposite to that of the second doped silicon layer 18, the alignment between the portion of the second doped silicon layer 18 at the bottom of the groove 20 and the doped layer 19 located in the first region 12 and the overlapping region 14 affects the leakage risk between them. Based on this, the depth of the groove 20 and the position between the surface height of the portion of the second doped silicon layer 18 at the bottom of the groove 20 away from the semiconductor substrate 11 and the surface height of the doped layer 19 away from the tunneling passivation layer 15 can be determined according to the actual manufacturing process and the requirements for leakage risk between the doped layer 19 and the second doped silicon layer 18 in actual application scenarios. No specific limitations are made here.

[0083] For example, such as Figure 7As shown, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the trench 20 away from the semiconductor substrate 11 can be less than the surface height of the doped layer 19 away from the tunneling passivation layer 15. In this case, the doped layer 19 and the second doped silicon layer 18 located at the bottom of the trench 20 do not have any structurally aligned portions along the thickness direction of the semiconductor substrate 11. In other words, the presence of the trench 20 can also offset the doped layer 19 and the first doped silicon layer 16 from the second doped silicon layer 18, which has the opposite conductivity type, along the thickness direction of the semiconductor substrate 11, reducing the leakage risk between the doped layer 19 and the second doped silicon layer 18, and further improving the conversion efficiency of the back contact cell. Additionally, it is understood that the portion of the second doped silicon layer 18 located at the bottom of the trench 20 is mainly used to collect and discharge charge carriers. Therefore, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the trench 20 away from the semiconductor substrate 11 is set to be less than the surface height of the doped layer 19 away from the tunneling passivation layer 15. This also helps to prevent the first doping element in the doped layer 19, which has the opposite conductivity type to the second doped silicon layer 18, from diffusing into the second doped silicon layer 18. This ensures that the portion of the second doped silicon layer 18 corresponding to the bottom of the trench has a high charge carrier collection capability and prevents leakage between the second doped silicon layer 18 and the doped layer 19 located at the bottom of the trench, which would affect the power generation efficiency of the back contact battery.

[0084] Or, such as Figure 6 As shown, the surface height of the portion of the second doped silicon layer 18 located at the bottom of the trench 20 away from the semiconductor substrate 11 can be lower than the surface height of the doped layer 19 near the tunneling passivation layer 15, but higher than the surface height of the doped layer 19 away from the tunneling passivation layer 15. In this case, while preventing all portions of the doped layer 19 along the thickness direction from being aligned with the portion of the second doped silicon layer 18 located at the bottom of the trench, the depth of the trench 20 can be reduced, so that the portion of the semiconductor substrate 11 corresponding to the trench 20 has a higher light absorption depth. This improves the photoelectric conversion efficiency of the semiconductor substrate 11 and also helps to shorten the transmission path of charge carriers bypassing the sidewalls of the deeper trench 20 and being collected by the portion of the second doped silicon layer 18 located at the bottom of the trench, thus reducing transmission loss.

[0085] For example, the depth of the aforementioned groove can be greater than or equal to 300 nm and less than or equal to 15 μm. For instance, the groove depth can be 300 nm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm, 9 μm, 10 μm, 12 μm, or 15 μm, etc. In this case, the groove depth within the above range helps to prevent a small spacing between the doped layer and the second doped silicon layer located at the bottom of the groove along the thickness direction of the semiconductor substrate, which could lead to a higher risk of leakage. Additionally, it can prevent a large groove depth from causing a small light absorption depth in the semiconductor substrate corresponding to the groove, ensuring high photoelectric conversion efficiency of the semiconductor substrate, and thus ensuring high operating performance of the back contact battery. Furthermore, when the first dopant element in the doped layer is formed by diffusion from the first doped silicon layer to the semiconductor substrate, the groove depth within the above range also ensures that after removing the first doped silicon layer on the second region, the groove arrangement can completely remove the doped layer formed in the second region by the first doped silicon layer, preventing the electric field of the residual doped layer in the second region from affecting the carrier collection energy of the second doped silicon layer. It should be noted that when the bottom surface of the groove is textured, the depth of the groove is the distance between the surface of the first region and the bottom of the textured structure (the side closer to the semiconductor substrate).

[0086] For example, along the direction from the second surface to the first surface, the difference between the surface height of the second doped silicon layer at the bottom of the trench on the side facing away from the semiconductor substrate and the surface height of the doped layer on the side facing away from the tunneling passivation layer can be greater than or equal to 180 nm and less than or equal to 14.7 μm. For instance, the difference between the surface height of the second doped silicon layer at the bottom of the trench on the side facing away from the semiconductor substrate and the surface height of the doped layer on the side facing away from the tunneling passivation layer can be 180 nm, 200 nm, 500 nm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, or 14.7 μm, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the trench depth being greater than or equal to 300 nm and less than or equal to 15 μm described above, and will not be repeated here.

[0087] In addition, in practical applications, such as Figure 7As shown, when the bottom surface of the aforementioned groove 20 is textured, the thickness of the second doped silicon layer 18 located on the bottom of the groove 20 can be less than the thickness of the second doped silicon layer 18 located on the overlapping region 14. In this case, the smaller thickness of the second doped silicon layer 18 located on the bottom of the groove 20 ensures good field passivation while preventing the diffusion of a large number of second doped elements into the second region 13 of the semiconductor substrate 11 due to the larger thickness of the second doped silicon layer 18 located on the bottom of the groove. This ensures that the doped layer 19 will not make electrical contact with the inner doped layer 19, which has an opposite conductivity type, thus preventing a high risk of leakage and ensuring that the back contact cell has a high conversion efficiency. In addition, the smaller thickness of the second doped silicon layer 18 located on the bottom of the groove can also increase the distance between itself and the doped layer 19 along the thickness direction of the semiconductor substrate 11, preventing the diffusion of the first doped element in the doped layer 19 into the second doped silicon layer 18, ensuring that the second doped silicon layer 18 has a high field passivation effect and carrier collection efficiency. Specifically, the difference between the thickness of the second doped silicon layer 18 located at the bottom of the groove 20 and the thickness of the second doped silicon layer 18 located in the overlapping region 14 can be set according to the size of the textured structure and actual needs, and is not specifically limited here.

[0088] Of course, the thickness of the second doped silicon layer located at the bottom of the groove can also be equal to the thickness of the second doped silicon layer located in the overlapping region.

[0089] Regarding the doped layer described above, in terms of its formation range, as mentioned earlier, the doped layer is disposed in the first region and the overlapping region of the semiconductor substrate. Specifically, in the width direction of the overlapping region, the doped layer can be disposed only in a local area of ​​the first region and the overlapping region of the semiconductor substrate; or, the doped layer can be disposed throughout the entire first region and the overlapping region; in other words, along the width direction of the overlapping region, the width of the doped layer can be greater than or equal to the width of the first doped silicon layer. In this case, the doped layer has a larger formation range, which is beneficial to improving the field passivation effect of the doped layer and further reducing the carrier recombination rate on one side of the first surface of the semiconductor substrate.

[0090] As for the difference in width between the doped layer and the first doped silicon layer, it can be determined based on the passivation treatment range of the doped layer and the requirements for leakage risk in the actual application scenario, and no specific limit is made here.

[0091] For example, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer can be greater than 0 and less than or equal to 50 μm. For instance, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer can be 5 nm, 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 300 nm, 400 nm, 500 nm, 1 μm, 1.5 μm, 2 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, etc. In this case, the width of the doped layer is approximately the same as the width of the first doped silicon layer, ensuring that the first region and the overlapping region of the semiconductor substrate have a high carrier recombination rate under the passivation effect of the doped layer. Furthermore, it is understood that the overlapping region is adjacent to the second region, and the second doped silicon layer located in the second region is mainly used to collect and extract carriers, while the conductivity type of the first doped element in the doped layer is opposite to the conductivity type of the second doped silicon layer. Based on this, when the difference between the width of the doped layer and the width of the first doped silicon layer is within the above range, it can prevent the width of the doped layer from being too large, which would result in a small distance between the edge of the doped layer and the edge of the second doped silicon layer, thereby reducing the risk of leakage between the doped silicon and the second doped silicon layer.

[0092] Furthermore, as mentioned above, in the case where the second region includes a groove, and the sides of the groove have continuously distributed first and second sub-regions, such as Figure 8 and Figure 9 As shown, the doped layer 19 can also extend to the second sub-region 22 of the semiconductor substrate 11; or, the doped layer 19 can also extend to the second sub-region 22 of the semiconductor substrate 11 and a portion of the first sub-region 21 near the second sub-region 22. In this case, with the depth of the groove 20 fixed, the surface of the first sub-region 21 on the side of the groove 20 is inclined relative to the surface of the first region 12, and the cross-sectional area of ​​the portion of the groove 20 corresponding to the first sub-region 21 gradually increases along the direction from the second surface to the first surface. This is beneficial for increasing the lateral spacing between the doped layer 19 and the second doped silicon layer 18 located on the bottom of the groove, so that the edge of the doped layer 19 only extends from the overlapping region 14 to the second sub-region 22 of the semiconductor substrate 11 and a portion of the first sub-region 21 near the second sub-region 22, and does not extend to the bottom surface of the groove 20, further reducing the risk of leakage between them. At the same time, it can also increase the formation range of the doped layer 19 in the semiconductor substrate 11, increase the passivation treatment range, and further reduce the carrier recombination rate on the first surface side.

[0093] Furthermore, along the thickness direction of the semiconductor substrate, the doping depth of the doped layer can be determined based on the manufacturing process of the doped layer and the requirements for the passivation effect of the doped layer; no specific limitation is made here.

[0094] For example, along the thickness direction of the semiconductor substrate, the doping depth of the doped layer can be greater than or equal to 1 nm and less than or equal to 300 nm. For instance, the doping depth of the doped layer can be 1 nm, 5 nm, 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 260 nm, or 300 nm, etc. In this case, the doping depth of the doped layer within the above range helps to prevent poor field passivation capability due to a small doping depth. Additionally, it can prevent a high Auger recombination rate in the semiconductor substrate due to a large doping depth, thus affecting the passivation effect and ensuring a low carrier recombination rate in the first region and overlapping region of the semiconductor substrate where the doped layer is formed. If, in the actual manufacturing process, the first dopant element in the doped layer diffuses from the first doped silicon layer into the doped layer, then the doping depth of the doped layer within the above range can also prevent a low doping concentration of the first dopant element in the first doped silicon layer due to a large doping depth, ensuring a high carrier collection efficiency in the first doped silicon layer.

[0095] As for the doping concentration of the first doped element in the doped layer, it can be set according to actual needs, as long as the doping concentration of the first doped element in the doped layer is greater than the doping concentration of the first doped element in the second region of the semiconductor substrate.

[0096] For example, the doping concentration of the first dopant element in the aforementioned doped layer can be less than or equal to 9 × 10⁻⁶. 20 / cm 3 And greater than or equal to 8 × 10 9 / cm 3 For example, the doping concentration of the first dopant element within the doped layer can be 8 × 10⁻⁶. 9 / cm 3 1×10 10 / cm 3 1×10 12 / cm 3 1×10 16 / cm 3 1×10 16 / cm 3 2×10 16 / cm 3 4×10 16 / cm 3 6×10 16 / cm 3 8×10 16 / cm 3 1×10 17 / cm 3 1×10 18 / cm3 1×10 19 / cm 3 1×10 20 / cm 3 Or 9×10 20 / cm 3 In this case, it can prevent poor passivation due to a low doping concentration of the first dopant element in the doped layer. Additionally, it can prevent band dips caused by a high doping concentration of the first dopant element in the doped layer, thus preventing low carrier collection efficiency in the first doped silicon layer and ensuring high conversion efficiency of the back contact cell. If, during actual manufacturing, the first dopant element diffuses from the first doped silicon layer into the doped layer, and the doping concentration of the first dopant element in the doped layer is within the aforementioned range, it can also prevent a low doping concentration of the first dopant element in the first doped silicon layer due to a high doping concentration, ensuring high carrier collection efficiency of the first doped silicon layer.

[0097] Specifically, along the direction from the second surface to the first surface, the doping concentration of the first doped element in each region of the doped layer can be the same. Alternatively, along the direction from the second surface to the first surface, the doping concentration of the first doped element in the doped layer can gradually increase. In this case, a high-low junction can be formed between different regions of the doped layer along the direction from the second surface to the first surface. The built-in electric field of this high-low junction is consistent with the induction direction of the first doped silicon layer, which can further improve the carrier collection efficiency of the first doped silicon layer and further reduce the carrier recombination rate, thus improving the conversion efficiency of the back contact battery. It should be noted that during the detection of the doping concentration and doping depth of the doped layer, when the detection device detects that the doping concentration of the first doped element in the semiconductor substrate is 0 (or close to 0); or when it detects that the doping concentration of the first doped element in the semiconductor substrate tends to be uniform, the region where the doping concentration of the first doped element in the semiconductor substrate is 0, or the region where the doping concentration tends to be uniform, can be considered as the undoped layer of the semiconductor substrate. The region where the doping concentration of the first doped element in the semiconductor substrate is greater than 0, or the region where the doping concentration of the first doped element gradually decreases along the direction from the first surface to the second surface, is the doped layer.

[0098] Furthermore, the doping concentration of the first doped element within the first doped silicon layer can be greater than that within the doped layer. In this case, a higher field passivation effect is ensured in the first doped silicon layer, improving its carrier collection capability. Moreover, a high-low junction can be formed between the first doped silicon layer and the doped layer, with the built-in electric field direction of this high-low junction aligned with the induced direction of the first doped silicon layer, further enhancing its carrier collection capability.

[0099] Alternatively, the doping concentration of the first doped element in the first doped silicon layer can be at least equal to the doping concentration of the first doped element on the side of the doped layer near the tunnel passivation layer.

[0100] As for the conductivity type of the doped layer, you can refer to the conductivity type of the first doped silicon layer, which will not be repeated here.

[0101] Optionally, the conductivity type of the first doped silicon layer and the doped layer can both be the same as the conductivity type of the semiconductor substrate. Furthermore, the second region of the semiconductor substrate does not contain a second doping element. In this case, a high-low junction can be formed between each adjacent pair of the semiconductor substrate, the doped layer, and the first doped silicon layer. Under the built-in electric field of the high-low junction, the carrier collection efficiency of the first doped silicon layer can be further improved, further enhancing the conversion efficiency of the back contact cell. Since the second region of the semiconductor substrate does not contain a second doping element with a conductivity type opposite to that of the doped layer, it ensures that the doped layer will not make electrical contact with the inwardly expanding doped layer with a conductivity type opposite to its own, thus preventing a high risk of leakage. It also reduces the recombination rate of electrons and holes within the semiconductor substrate, thereby ensuring a high conversion efficiency for the back contact cell.

[0102] It should be noted that in the actual manufacturing process, the doped layer can be formed separately in the first region and overlapping region of the semiconductor substrate through diffusion or ion implantation before the formation of the tunneling passivation layer and the first doped silicon layer. In this case, the formation depth of the doped layer in the semiconductor substrate and the doping concentration of the first doped element within it can be controlled by controlling the concentration, time, and temperature of the diffusion or ion implantation. Alternatively, the doped layer can be formed simultaneously with the formation of the tunneling passivation layer and the first doped silicon layer by the diffusion of the first doped element within the first doped silicon layer into the semiconductor substrate. In this case, the formation range of the doped layer in the semiconductor substrate and the doping concentration of the first doped element within it can be controlled by controlling the thickness of the tunneling passivation layer, the thickness and doping concentration of the first doped silicon layer, as well as the time and temperature during doping of the first doped silicon layer.

[0103] In addition, along the direction from the first surface to the second surface, the doping concentration of the second doping element with the same conductivity type as the second doped silicon layer is the same in each part of the second region of the semiconductor substrate. This can be controlled by controlling the thickness of the intrinsic silicon layer, the thickness and doping concentration of the second doped silicon layer, and the time and temperature during doping of the second doped silicon layer, so as to avoid or prevent the second doping element in the second doped silicon layer from spreading into the second region of the semiconductor substrate.

[0104] In one example, such as Figure 10 and Figure 11As shown, the aforementioned back-contact battery may further include a transparent conductive layer 23. This transparent conductive layer 23 covers the side of the first doped silicon layer 16 and the second doped silicon layer 18 facing away from the semiconductor substrate 11 to improve carrier collection efficiency. Furthermore, the transparent conductive layer 23 has a through-hole insulating trench 24 to disconnect the portion of the transparent conductive layer 23 corresponding to the first doped silicon layer 16 from the portion corresponding to the second doped silicon layer 18, preventing short circuits. Specifically, along the width direction of the overlapping region 14, both sides of the insulating trench 24 may be located above the overlapping region 14; or, one side of the insulating trench 24 may be located above the overlapping region 14, and the other side may be located above the first region 12; or, one side of the insulating trench may be located above the overlapping region, and the other side may be located above the second region; or, one side of the insulating trench may be located above the first region, and the other side may be located above the second region.

[0105] Specifically, the embodiments of the present invention do not impose specific limitations on the material and thickness of the transparent conductive layer, as long as it can be applied to the back contact battery provided in the embodiments of the present invention. For example, the material of the transparent conductive layer may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The thickness of the transparent conductive layer may be greater than or equal to 10 nm and less than or equal to 200 nm. The surface of the portion of the transparent conductive layer covering the groove that faces away from the semiconductor substrate may be flush with the side of the doped layer facing away from the tunneling passivation layer, or it may be higher or lower than the side of the doped layer facing away from the tunneling passivation layer.

[0106] Regarding the width of the insulating groove, such as Figure 10 As shown, when both sides of the insulating trench 24 are located above the overlapping region 14, the etching amount required to create the insulating trench 24 within the transparent conductive layer 23 is smaller, which is beneficial for improving etching capacity. Furthermore, in this case, if the second doped silicon layer 18 on the overlapping region 14 can be electrically contacted with the first doped silicon layer 16 through the intrinsic silicon layer 17, then the second doped silicon layer 18 on the overlapping region 14 is covered with a transparent conductive layer 23 extending from the second region 13, which can form a reverse leakage structure and reduce the risk of hot spots on the back contact battery. And if... Figure 11As shown, when one edge of the insulating groove 24 can be located above the overlapping region 14, and the other edge can be located above the first region 12, although the etching amount of the insulating groove 24 is relatively large, the insulating groove 24 can completely isolate the portions of the transparent conductive layer 23 corresponding to the second region 13 and the first region 12, greatly reducing the risk of leakage and improving the conversion efficiency of the back contact battery. From the above, it can be seen that different widths of the insulating groove 24 have different effects. The width of the insulating groove 24 can be set according to different application scenarios, improving the applicability of the back contact battery provided in this embodiment of the invention in different application scenarios.

[0107] In addition, such as Figure 11 and Figure 12 As shown, when the back contact battery also includes a transparent conductive layer 23, the portion of the transparent conductive layer 23 with the same carrier conductivity type as the second doped silicon layer 18 does not overlap with the doped layer 19 along the thickness direction of the semiconductor substrate 11. In this case, the transparent conductive layer 23 has good conductivity, which can improve the carrier collection efficiency. In addition, the absence of overlap between the portion of the transparent conductive layer 23 with the second doped silicon layer 18 and the doped layer 19 along the thickness direction of the semiconductor substrate 11 prevents the portion of the transparent conductive layer 23 with the same carrier conductivity type as the second doped silicon layer 18 from overlapping with the doped layer 19, which is doped with a first dopant element with the opposite conductivity type to that of the second doped silicon layer 18, thus preventing an increase in leakage risk and ensuring high electrical reliability of the back contact battery.

[0108] In some cases, such as Figure 12 As shown, the back-contact battery provided in this embodiment of the invention may further include a surface passivation layer 25 and an anti-reflection layer 26 sequentially stacked on the second surface along the thickness direction of the semiconductor substrate 11, in order to reduce the carrier recombination rate on the second surface side and facilitate more light to enter the semiconductor substrate 11 from the second surface side, thereby further improving the conversion efficiency of the back-contact battery provided in this embodiment of the invention. The materials and thicknesses of the surface passivation layer 25 and the anti-reflection layer 26 are not specifically limited in this embodiment of the invention.

[0109] For example, the surface passivation layer may include at least one of a silicon oxide layer, an aluminum oxide layer, and an intrinsic silicon layer.

[0110] For example, the antireflection layer may include a silicon nitride layer and / or a silicon oxynitride layer.

[0111] Secondly, embodiments of the present invention provide a photovoltaic module, which includes a back contact battery provided in the first aspect and various implementations thereof.

[0112] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0113] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0114] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A back-contact battery, characterized in that, include: A semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other; the first surface including a first region and a second region that are alternately distributed, and an overlapping region located between the first region and the second region; Along the thickness direction of the semiconductor substrate, a tunneling passivation layer and a first doped silicon layer are sequentially stacked on the first region and the overlapping region; An intrinsic silicon layer and a second doped silicon layer are sequentially stacked on the second region along the thickness direction of the semiconductor substrate; the stacked intrinsic silicon layer and second doped silicon layer also extend from the second region to cover the tunneling passivation layer and the first doped silicon layer located in the overlapping region; the conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer; the second doped silicon layer includes a second doping element; A doped layer is disposed in the first region and the overlapping region of the semiconductor substrate; the doping concentration of the first doping element in the doped layer having the same conductivity type as the first doped silicon layer is greater than the doping concentration of the first doping element in the second region of the semiconductor substrate; the doping concentration of the first doping element in the first doped silicon layer is greater than the doping concentration of the first doping element in the doped layer. The first doped silicon layer and the doped layer have the same conductivity type as the semiconductor substrate, and the second region of the semiconductor substrate does not have the second doping element; or, the semiconductor substrate has the same conductivity type as the second doped silicon layer, and along the direction from the first surface to the second surface, the doping concentration of the second doping element with the same conductivity type as the second doped silicon layer is the same in each part of the second region of the semiconductor substrate.

2. The back contact battery according to claim 1, characterized in that, The second region includes a groove; along the direction from the second surface to the first surface, the surface height of the portion of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate is less than the surface height of the doped layer away from the tunneling passivation layer.

3. The back contact battery according to claim 2, characterized in that, Along the direction from the second surface to the first surface, the difference between the surface height of the portion of the second doped silicon layer located at the bottom of the groove away from the semiconductor substrate and the surface height of the doped layer away from the tunneling passivation layer is greater than or equal to 180 nm and less than or equal to 14.7 μm.

4. The back contact battery according to claim 2, characterized in that, The depth of the groove is greater than or equal to 300 nm and less than or equal to 15 μm.

5. The back contact battery according to claim 1, characterized in that, Along the width direction of the overlapping region, the width of the doped layer is greater than or equal to the width of the first doped silicon layer; And / or, along the width direction of the overlapping region, the difference between the width of the doped layer and the width of the first doped silicon layer is greater than 0 and less than or equal to 50 μm.

6. The back contact battery according to claim 1, characterized in that, The second region includes a groove; along the width direction of the overlapping region, the side of the groove has a continuously distributed first sub-region and a second sub-region, and the second sub-region is close to the first region; the surface of the first sub-region is inclined relative to the surface of the first region, and the cross-sectional area of ​​the portion of the groove corresponding to the first sub-region gradually increases along the direction from the second surface to the first surface; the surface of the second sub-region is planar. The doped layer further extends to the second sub-region of the semiconductor substrate; or, the doped layer further extends to the second sub-region of the semiconductor substrate and a portion of the first sub-region adjacent to the second sub-region.

7. The back contact battery according to claim 1, characterized in that, Along the direction from the second surface to the first surface, the doping concentration of the first dopant element in the doped layer gradually increases.

8. The back contact battery according to claim 1, characterized in that, The back contact battery further includes a transparent conductive layer; the transparent conductive layer covers the side of the first doped silicon layer and the second doped silicon layer away from the semiconductor substrate; The transparent conductive layer has an insulating groove to disconnect the portions of the transparent conductive layer corresponding to the first region and the second region from each other; The portion of the transparent conductive layer that carries the same type of charge carriers as the second doped silicon layer does not overlap with the doped layer along the thickness direction of the semiconductor substrate.

9. The back contact battery according to claim 1, characterized in that, Along the thickness direction of the semiconductor substrate, the doping depth of the doped layer is greater than or equal to 1 nm and less than or equal to 300 nm.

10. The back contact battery according to claim 1, characterized in that, The doping concentration of the first dopant element within the doped layer is less than or equal to 9 × 10⁻⁶. 20 / cm 3 And greater than or equal to 8 × 10 9 / cm 3 .

11. The back contact battery according to claim 1, characterized in that, The thickness of the first doped silicon layer is greater than or equal to 20 nm and less than or equal to 300 nm; And / or, the doping concentration of the first doped element in the first doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 .

12. The back contact battery according to claim 1, characterized in that, The sum of the thicknesses of the second doped silicon layer and the intrinsic silicon layer is greater than or equal to 15 nm and less than or equal to 120 nm; And / or, the doping concentration of the second doped element in the second doped silicon layer is greater than or equal to 1 × 10⁻⁶. 18 / cm 3 And less than or equal to 1×10 21 / cm 3 .

13. The back contact battery according to claim 1, characterized in that, The conductivity type of the doped layer and the first doped silicon layer is N-type, and the conductivity type of the second doped silicon layer is P-type.

14. The back contact battery according to claim 1, characterized in that, The second region includes a groove; the bottom surface of the groove is textured, and the thickness of the second doped silicon layer on the bottom of the groove is less than the thickness of the second doped silicon layer in the overlapping region.

15. A photovoltaic module, characterized in that, Including the back contact battery as described in any one of claims 1 to 14.

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