Electronic device

Abstract

An electronic device is disclosed. An electronic device includes a display panel including a base substrate including an active area and a peripheral area, pixels located on the active area, pads arranged in the peripheral area and in a first direction, a signal line connecting the pixels to the pads, and a cursor mark arranged in the first direction, the cursor mark is located on the peripheral area and spaced apart from the pad and the signal line, the circuit board includes a base film and a lead, and a conductive adhesive member extends in a first direction to connect the pad to the lead. Each of the plurality of cursor marks includes a plurality of patterns spaced apart from each other, and a portion of the conductive adhesive member overlaps at least one of the plurality of patterns. In a plan view, in a second direction intersecting the first direction, a width from a lowermost pattern to an uppermost pattern among the plurality of patterns is 100 [mu] m or more and 450 [mu] m or less.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 201910535090.7 filed on June 20, 2019 and invention name “Display panel, electronic device including the same, and method for manufacturing electronic device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0071858, filed on Jun. 22, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0004] Herein, embodiments of the present disclosure relate to a display panel, an electronic device including the display panel, and a method of manufacturing the electronic device, and, for example, to a display panel capable of improving process reliability, an electronic device including the display panel, and a method of manufacturing the electronic device. Background Art

[0005] An electronic device may include two or more electronic components. For example, an electronic device such as a portable phone, a notebook computer, or a television may include a display panel configured to display an image and a circuit board.

[0006] The two electronic components can be electrically connected to each other through the connection of the pads. The two electronic components can be physically and electrically connected to each other through the conductive adhesive member. After aligning the conductive adhesive member with the pads, the two electronic components can be connected to each other through a heat pressing tool.

[0007] Process errors such as misalignment may occur at the two electronic components due to vibration of the two electronic components and / or manufacturing equipment, and thus connection reliability of the electronic components may be deteriorated. Summary of the invention

[0008] The present disclosure may provide a display panel capable of improving reliability in a manufacturing process, an electronic device including the display panel, and a method of manufacturing the electronic device.

[0009] In an embodiment of the present disclosure, an electronic device includes a display panel, a circuit board, and a conductive adhesive member, the display panel includes a base substrate, a plurality of pixels, a plurality of pads, a plurality of signal lines, and a vernier mark, the base substrate includes an active area and a peripheral area adjacent to the active area, a plurality of pixels are located on the active area, a plurality of pads are located in the peripheral area and arranged in a first direction, a plurality of signal lines connect the pixels to the pads, and the vernier mark is located in the peripheral area and is spaced apart from the pads and the signal lines, the circuit board is located on the display panel and includes a base film and leads located on the base film and overlapping with the pads in a plan view, and the conductive adhesive member extends in the first direction and is located between the display panel and the circuit board to connect the pads to the leads. When viewed in a second direction intersecting the first direction, the conductive adhesive member overlaps the vernier mark.

[0010] In an embodiment, when viewed in a plan view, a bottom end of the vernier mark may be aligned with a top end of the pad in the first direction.

[0011] In an embodiment, a top end of the conductive adhesive member may be aligned with a bottom end of the vernier mark in the first direction when viewed in a plan view.

[0012] In an embodiment, the conductive adhesive member may overlap a portion of the vernier mark when viewed in a plan view.

[0013] In an embodiment, the circuit board may overlap a portion of the vernier mark when viewed in plan view.

[0014] In an embodiment, the vernier mark may include a conductive material or a semiconductor material.

[0015] In an embodiment, the pixel may include a thin film transistor and a light emitting element, the thin film transistor including a control electrode, a semiconductor pattern, an input electrode and an output electrode, and the light emitting element is connected to the thin film transistor and includes a first electrode, a second electrode and an emission layer located between the first electrode and the second electrode. The vernier mark may be located on the same layer as at least one selected from the control electrode, the semiconductor pattern, the input electrode, the output electrode and the first electrode.

[0016] In an embodiment, the vernier mark may include a first pattern and a second pattern located on the first pattern, an insulating layer interposed between the first pattern and the second pattern to intersect the first pattern, and the second pattern may penetrate the insulating layer to be connected to the first pattern.

[0017] In embodiments, the vernier marks may be located on a single layer to have a single overall shape.

[0018] In an embodiment, the vernier mark may include a plurality of line patterns arranged in the second direction and extending in the first direction. At least one or some of the line patterns may be exposed from the conductive adhesive member.

[0019] In an embodiment, the vernier mark may further include a vertical pattern extending in the second direction and intersecting the line pattern.

[0020] In an embodiment, the vernier mark may further include a horizontal pattern extending in the first direction and located between the line patterns, and a length of the horizontal pattern may be smaller than a length of each of the line patterns.

[0021] In an embodiment, the vernier mark may have an Arabic numeral shape when viewed in a plan view.

[0022] In an embodiment, the vernier mark may be spaced apart from the signal line when viewed in a plan view.

[0023] In an embodiment, the display panel may further include a panel alignment mark that is spaced apart from the pad and overlaps the conductive adhesive member in a plan view, and the circuit board may further include a board alignment mark that corresponds to the panel alignment mark and overlaps the conductive adhesive member in a plan view. When viewed in the second direction, the left end of the vernier mark may be aligned with the right end of the panel alignment mark.

[0024] In an embodiment, a distance from a top end of the pad to a top end of the conductive adhesive member in the second direction may be less than 100 μm when viewed in a plan view.

[0025] In an embodiment of the present disclosure, a display panel includes a base substrate, a plurality of pixels, a plurality of signal lines, a plurality of pads, and a vernier mark, the base substrate including an active area and a peripheral area adjacent to the active area, a plurality of pixels are located on the active area of ​​the base substrate, a plurality of signal lines are connected to the pixels, a plurality of pads are located in the peripheral area, a plurality of pads are arranged in a first direction and connected to the signal lines, and a vernier mark is located in the peripheral area, the vernier mark is spaced apart from the pad and includes at least one selected from a conductor material and a semiconductor material. When viewed in a plan view, the bottom end of the vernier mark may be aligned with the top end of the pad in the first direction.

[0026] In an embodiment, each of the pixels may include a thin film transistor and a light emitting element, the thin film transistor including a semiconductor pattern, an input electrode and an output electrode respectively connected to one side and the other side of the semiconductor pattern, and a control electrode overlapping the semiconductor pattern, and the light emitting element is connected to the thin film transistor and includes a first electrode, a second electrode located on the first electrode, and an emission layer located between the first electrode and the second electrode. The vernier mark may include the same material as at least one selected from the semiconductor pattern, the input electrode, the output electrode, the control electrode, and the first electrode.

[0027] In an embodiment, the vernier mark may be located on the same layer as at least one selected from the group consisting of the semiconductor pattern, the input electrode, the output electrode, the control electrode, and the first electrode.

[0028] In an embodiment, the vernier mark may include a plurality of line patterns extending in a first direction and arranged in a second direction intersecting the first direction.

[0029] In an embodiment, the vernier mark may further include a vertical pattern extending in the second direction, intersecting the line pattern, and connected to the line pattern.

[0030] In an embodiment, the line pattern and the vertical pattern may be located on the same layer.

[0031] In an embodiment, the line pattern and the vertical pattern may be located on different layers with an insulating layer interposed therebetween, and the vertical pattern may penetrate the insulating layer to be connected to the line pattern.

[0032] In an implementation, a distance between line patterns adjacent to each other may be about 50 μm.

[0033] In an embodiment, the vernier mark may be spaced apart from the pad and the signal line when viewed in a plan view.

[0034] In an embodiment, each of the pads may extend in a direction inclined with respect to the first direction when viewed in a plan view.

[0035] In an embodiment of the present disclosure, a method of manufacturing an electronic device may include: aligning a conductive adhesive member extending in one direction on a pad of a display panel; performing a first bonding process to press the conductive adhesive member; aligning a circuit board on the conductive adhesive member; and performing a second bonding process to press the circuit board and the pad. The alignment of the conductive adhesive member may include: aligning a position of the conductive adhesive member based on a vernier mark of the display panel spaced apart from the pad.

[0036] In an embodiment, the alignment of the position of the conductive adhesive member may include checking the overlap degree of the vernier mark and the conductive adhesive member. The checking of the overlap degree of the vernier mark and the conductive adhesive member may be performed using naked eyes or a magnifying glass.

[0037] In an embodiment, the method may further include: correcting the position of the conductive adhesive member. Correcting the position of the conductive adhesive member may include: checking the overlap between the vernier mark and the conductive adhesive member; and moving the relative position of the conductive adhesive member relative to the display panel when the overlap exceeds a set or predetermined range.

[0038] In an embodiment, the movement of the relative position of the conductive adhesive member may include moving the conductive adhesive member in a direction intersecting the one direction.

[0039] In an embodiment, correction of the position of the conductive adhesive member may be performed before alignment of the circuit board.

[0040] In an embodiment of the present disclosure, an electronic device includes a display panel, a circuit board and a conductive adhesive member, the display panel includes a base substrate, a plurality of pixels, a plurality of pads, a plurality of signal lines and a plurality of vernier marks, the base substrate includes an active area and a peripheral area adjacent to the active area, a plurality of pixels are located on the active area, a plurality of pads are located on the peripheral area and are arranged in a first direction, a plurality of signal lines connect the plurality of pixels to the plurality of pads, a plurality of vernier marks are located on the peripheral area and are spaced apart from the plurality of pads and the plurality of signal lines, the circuit board is located on the display panel and may include a base film and a plurality of leads, the plurality of leads are located on the base film and overlap with corresponding pads in a plan view, the conductive adhesive member extends in a first direction and is located between the display panel and the circuit board to connect the plurality of pads to the plurality of leads, and wherein each of the plurality of vernier marks includes a plurality of patterns spaced apart from each other, a portion of the conductive adhesive member overlaps with at least one of the plurality of patterns, wherein in a plan view, in a second direction intersecting the first direction, a width from a lowermost pattern to an uppermost pattern among the plurality of patterns is 100 μm or greater and 450 μm or less.

[0041] In an implementation, an upper end of the conductive adhesive member may be aligned with any one of the plurality of patterns overlapping the conductive adhesive member in the first direction.

[0042] In an implementation, each of the plurality of patterns may have a line shape extending in the first direction and may be spaced apart from each other in the second direction.

[0043] In an implementation, each of the plurality of patterns may have a width of 1 μm or more and 3 μm or less in the second direction.

[0044] In an implementation, in the first direction, a separation distance between adjacent ones of the plurality of patterns may be 10 μm or more and 50 μm or less.

[0045] In an embodiment, each of the multiple cursor marks may also include a horizontal pattern and a vertical pattern, the horizontal pattern may extend in a first direction, have a smaller width than the multiple patterns in the first direction, and be arranged between adjacent multiple patterns, and the vertical pattern may extend in a second direction and be arranged between an adjacent pattern and the horizontal pattern.

[0046] In an embodiment, each of the plurality of pixels may include a thin film transistor and a light emitting element, the thin film transistor may include a control electrode, a semiconductor pattern, an input electrode, and an output electrode, the light emitting element may be connected to the thin film transistor and may include a first electrode, a second electrode, and an emission layer located between the first electrode and the second electrode, and wherein the plurality of patterns may be set on the same layer as any one of the control electrode, the semiconductor pattern, the input electrode, the output electrode, and the first electrode.

[0047] In an implementation, the plurality of patterns may have the same material as any one of the control electrode, the semiconductor pattern, the input electrode, the output electrode, and the first electrode.

[0048] In an embodiment, any one of the plurality of patterns may overlap the conductive adhesive member, and an area of ​​a portion of the plurality of patterns overlapping the conductive adhesive member may be smaller than an area of ​​a portion of the plurality of patterns spaced apart from the conductive adhesive member.

[0049] In an embodiment, the number of patterns overlapping with the conductive adhesive member among the plurality of patterns may be less than the number of patterns not overlapping with the conductive adhesive member among the plurality of patterns.

[0050] In an embodiment, the display panel may further include a panel alignment mark, which may be spaced apart from the plurality of pads and may overlap with the conductive adhesive member in a plan view, wherein the circuit board may further include a board alignment mark, which may overlap with the conductive adhesive member in a plan view and correspond to the panel alignment mark, wherein when viewed in the second direction, one end of each of the plurality of patterns adjacent to the plurality of pads may be aligned with one end of the panel alignment mark.

[0051] In an implementation, in the second direction, a distance from a top end of the pad to a top end of the conductive adhesive member may be less than 100 μm.

[0052] In an embodiment, at least a portion of the plurality of pads may be tilted in a first oblique direction relative to the first direction and the second direction in a plan view, and the remaining pads of the plurality of pads may be tilted in a second oblique direction intersecting the first oblique direction in a plan view.

[0053] In an embodiment, the circuit board may overlap a portion of each of the plurality of patterns and may expose another portion of each of the plurality of patterns.

[0054] In an embodiment, each of the plurality of patterns may extend in a first direction and be spaced apart from each other in a second direction, each of the plurality of cursor marks may further include a plurality of vertical patterns, the plurality of vertical patterns may extend in the second direction and may be spaced apart from each other in the first direction, and the plurality of patterns and the plurality of vertical patterns may have a grid shape when viewed in a plan view. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings are included to provide a further understanding of the subject matter of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the embodiments of the present disclosure. In the drawings:

[0056] Figure 1A is an exploded perspective view showing an electronic device according to an embodiment of the present disclosure;

[0057] Figure 1B It is shown Figure 1A A combined perspective view of an electronic device;

[0058] Figure 1C It is shown Figure 1B a perspective view of a portion of an electronic device;

[0059] Figure 1D yes Figure 1A Circuit diagrams of components of electronic equipment;

[0060] Figure 2A It is shown Figure 1B An exploded plan view of the electronic equipment;

[0061] Figure 2B It is shown Figure 2A A combined plan view of the electronic equipment;

[0062] Figure 2C It is along Figure 2B A cross-sectional view taken along line II';

[0063] Figure 3 It is shown Figure 2B an enlarged plan view of a portion of an electronic device;

[0064] Figure 4 is a cross-sectional view schematically showing a portion of an electronic device according to an embodiment of the present disclosure;

[0065] FIG. 5A to FIG. 5C is a cross-sectional view schematically illustrating a portion of an electronic device according to some embodiments of the present disclosure;

[0066] FIG. 6A to FIG. 6D is a plan view showing a portion of an electronic device according to some embodiments of the present disclosure;

[0067] FIG. 7A to FIG. 7B is a cross-sectional view showing a portion of an electronic device according to some embodiments of the present disclosure;

[0068] Fig. 8A is an exploded plan view showing an electronic device according to an embodiment of the present disclosure;

[0069] Figure 8B is a combined plan view showing an electronic device according to an embodiment of the present disclosure;

[0070] Fig.9A is an exploded perspective view showing an electronic device according to an embodiment of the present disclosure;

[0071] FIG. 9B to FIG. 9C It is shown Fig.9A A cross-sectional view of an embodiment of a portion of an electronic device;

[0072] FIG. 10A to FIG. 10E is a perspective view showing a method of manufacturing an electronic device according to an embodiment of the present disclosure;

[0073] FIG. 11A to FIG. 11D is a plan view showing some processes of a method of manufacturing an electronic device according to an embodiment of the present disclosure;

[0074] FIG. 12A to FIG. 12C is a plan view showing some processes of a method of manufacturing an electronic device according to an embodiment of the present disclosure;

[0075] Fig.13A is a perspective view showing an electronic device according to an embodiment of the present disclosure;

[0076] Fig. 13B It is shown Fig.13A an exploded perspective view of a portion of an electronic device;

[0077] Fig.14A It is shown Fig.13A a plan view of a portion of the electronic device; and

[0078] Fig. 14B is a plan view showing a portion of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] Hereinafter, the subject matter of the present disclosure will be described more comprehensively with reference to the accompanying drawings showing various embodiments. However, the subject matter of the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. The same reference numerals always represent the same elements.

[0080] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or there can be intervening elements. In contrast, the term "directly on" means that there are no intervening elements between the element and the other element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0081] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms, and include "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when the terms "comprise" and / or "comprising" or "include" and / or "including" are used in this specification, the presence of the stated features, regions, wholes, steps, operations, elements and / or parts is indicated, but the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or clusters thereof is not excluded.

[0082] Spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that in addition to the orientation shown in the figure, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as being "below" or "beneath" other elements or features will subsequently be oriented to be above the other elements or features. Therefore, the exemplary term "below" can include both the orientations of above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0083] It should be understood that although the words first, second, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these words. These words are only used to distinguish an element, component, region, layer or part from another region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0084] As used herein, the terms "about" and "approximately" include values ​​and means that are within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements and errors associated with measurement of the particular quantity (e.g., limitations of the measurement system).

[0085] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views of exemplary illustrations that may be idealized. In the figures, the thickness of layers and regions may be exaggerated for clarity. Accordingly, changes in the shapes of the illustrations caused by, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the embodiments described herein should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape caused by, for example, manufacturing. For example, an etched region shown as a rectangle may have rounded or curved features. Therefore, the regions shown in the figures may be schematic in nature, and their shapes are not necessarily intended to limit the actual shapes of the regions, and are not intended to limit the scope of the embodiments described herein.

[0086] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0087] Figure 1A is an exploded perspective view showing an electronic device according to an embodiment of the present disclosure. Figure 1B It is shown Figure 1A Combination perspective view of electronic devices. Figure 1C It is shown Figure 1B A perspective view of a portion of an electronic device. Figure 1D yes Figure 1A In the following, reference will be made to the circuit diagram of the components of the electronic device. Figures 1A to 1D The embodiments of the present disclosure are described.

[0088] The electronic device DD may include a display panel DP, a circuit board DC, a conductive adhesive member AF, and an optical member OPL. The display panel DP may include a base substrate BS, and an image may be displayed through a front surface FS of the base substrate BS. The front surface FS may be parallel to the first direction D1 and the second direction D2 (e.g., substantially parallel), and may be perpendicular to the third direction D3 (e.g., substantially perpendicular). The front surface FS may include an active area AA in which an image is displayed and a peripheral area PA adjacent to the active area AA. In the present embodiment, the peripheral area PA may have a frame shape surrounding the edge of the active area AA. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the peripheral area PA may be adjacent to a portion of the edge of the active area AA.

[0089] The display panel DP may include a plurality of pixels PX arranged in the active area AA. In the present embodiment, each of the pixels PX may receive an electrical signal to display or emit light forming an image. Figure 1A , the pixels PX are shown to correspond to the light emitting areas of the display light, respectively. Therefore, the pixels PX are spaced apart from each other. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, when viewed in a plan view, some components of the pixels PX may overlap each other.

[0090] Figure 1D A circuit diagram including pixels PX and signal lines connected to the pixels PX is schematically shown. One pixel PX may be connected to one gate line GL, one data line DL, and one power line PL. The signal line SL may include at least one selected from the gate line GL, the data line DL, and the power line PL.

[0091] The gate line GL may extend in the first direction D1. The gate line GL may transmit a gate signal to the pixel PX. The gate line GL may be provided in plurality, and the plurality of gate lines GL may be spaced apart from each other and may be arranged in the second direction D2. The plurality of gate lines GL may sequentially provide gate signals to the pixels PX arranged in the second direction D2.

[0092] The data line DL may be insulated from the gate line GL and may intersect the gate line GL. In the present embodiment, the data line DL may extend in the second direction D2. The data line DL may transmit a data signal to the pixel PX. The data line DL may be provided in plurality, and the plurality of data lines DL may be spaced apart from each other and may be arranged in the first direction D1.

[0093] The power line PL may be insulated from the gate line GL and the data line DL. In the present embodiment, the power line PL may extend in the second direction D2. The power line PL may transmit a first power signal to the pixel PX. A plurality of power lines PL may be provided, and the plurality of power lines PL may be spaced apart from each other and may be arranged in the first direction D1.

[0094] The pixel PX may include a first transistor TR1, a second transistor TR2, a capacitor CP, and a light emitting element OLD. The first transistor TR1 may be turned on by a gate signal provided through the gate line GL, and may provide a data signal provided through the data line DL to the capacitor CP.

[0095] The capacitor CP may store a voltage corresponding to a potential difference between the data signal and a first power signal supplied from the power line PL. The second transistor TR2 may be turned on by the voltage stored in the capacitor CP and may supply the first power signal supplied from the power line PL to the light emitting element OLD.

[0096] In the present embodiment, the light emitting element OLD may be connected to the power supply terminal VSS and may receive a second power supply signal from the power supply terminal VSS. The potential of the second power supply signal may be different from the potential of the first power supply signal. The light emitting element OLD may generate and emit light corresponding to the potential difference between the first power supply signal provided from the second transistor TR2 and the second power supply signal provided from the power supply terminal VSS.

[0097] The circuit board DC may be disposed at one side of the display panel DP and may be electrically connected to the display panel DP. The circuit board DC may generate an electrical signal and may provide the generated electrical signal to the display panel DP, and / or the circuit board DC may receive the electrical signal generated from the display panel DP and may process the received electrical signal.

[0098] The electrical signal generated from the circuit board DC may be provided to the pixel PX through the signal line SL of the display panel DP. The signal line SL may include at least one selected from the power line PL, the gate line GL, and the data line DL.

[0099] The circuit board DC may include a flexible film CB and a driving circuit DV. The flexible film CB may be directly bonded to the display panel DP through a conductive adhesive member AF. The flexible film CB may have flexibility. Therefore, the flexible film CB may be assembled with the display panel DP in a state where a portion of the flexible film CB is bent toward the rear surface of the display panel DP.

[0100] The driving circuit DV may be mounted on the flexible film CB. The driving circuit DV may be electrically connected to the flexible film CB through a circuit line included in the flexible film CB. The flexible film CB may electrically connect the driving circuit DV to the display panel DP, and the driving circuit DV may generate an electrical signal provided to the display panel DP and / or may process an electrical signal provided from the display panel DP.

[0101] The driving circuit DV may include a gate driving circuit for generating a gate signal or a data driving circuit for generating a data signal. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the driving circuit DV may include various suitable control circuits for generating and processing various control signals used to drive the display panel DP.

[0102] The conductive adhesive member AF may be arranged between the circuit board DC and the display panel DP to couple the circuit board DC and the display panel DP to each other. The conductive adhesive member AF may have both conductivity and adhesiveness. Therefore, the conductive adhesive member AF may physically and electrically couple the circuit board DC and the display panel DP to each other. The conductive adhesive member AF may include an anisotropic conductive adhesive film (ACF).

[0103] The conductive adhesive member AF may extend in a direction intersecting the signal line SL. In the present embodiment, the conductive adhesive member AF may have a shape extending in the first direction D1 and having a length in the first direction D1. In an embodiment, a portion of the conductive adhesive member AF may protrude outside the flexible film CB. In other words, on the display panel DP, the length of the conductive adhesive member AF in the first direction D1 may be equal to or greater than the width of the flexible film CB in the first direction D1. Therefore, one end of the conductive adhesive member AF may be aligned with a corner or edge of the flexible film CB, or a portion of the conductive adhesive member AF may be exposed from the flexible film CB.

[0104] The optical member OPL may be arranged on the display panel DP. The optical member OPL may cover the active area AA. The optical member OPL may be optically transparent. Therefore, the image IM displayed in the active area AA may be transmitted through the optical member OPL. The image IM displayed by the display panel DP may be transmitted through the optical member OPL so as to be displayed on the top surface of the optical member OPL, and therefore, the user may easily observe the image IM.

[0105] The optical member OPL may also cover at least a portion of the peripheral area PA. The optical member OPL may reduce the reflectivity of external light. The optical member OPL may reduce the incidence of external light on the front surface of the display panel DP and / or may reduce the transmittance of reflected light when external light is incident through the optical member OPL and then reflected from a component of the display panel DP toward the optical member OPL. For example, the optical member OPL may include at least one selected from a polarizing film and a phase delay film. However, embodiments of the present disclosure are not limited thereto. In certain embodiments, the optical member OPL may include a color filter. In an embodiment, the optical member OPL may be bonded to the front surface of the display panel DP by an adhesive member, or may be directly formed on the front surface of the display panel DP.

[0106] On the other hand, the display panel DP according to the present embodiment may include a vernier mark VM. The vernier mark VM may be arranged in the peripheral area PA. The vernier mark VM may be used as a reference for checking or verifying whether the conductive adhesive member AF is aligned with the pad PD in a plan view and the degree of alignment of the conductive adhesive member AF with the pad PD. The conductive adhesive member AF may be arranged adjacent to the vernier mark VM, or may be arranged to overlap with a portion of the vernier mark VM. The display panel DP may be connected to the circuit board DC through an electrical connection between the pad PD connected to the signal line SL and the circuit board DC. The pad PD may exist in an area covered by the circuit board DC. The alignment between the conductive adhesive member AF and the pad PD may mean that the overlapping area between the conductive adhesive member AF and the pad PD in a plan view is large.

[0107] The connection between the circuit board DC and the signal line SL may be achieved by alignment between the conductive adhesive member AF and the pad PD and alignment between the circuit board DC and the conductive adhesive member AF.

[0108] According to an embodiment of the present disclosure, the alignment degree between the conductive adhesive member AF and the pad PD can be checked or verified by the degree of adjacency / overlap between the conductive adhesive member AF and the vernier mark VM. Therefore, the alignment degree between the conductive adhesive member AF and the pad PD can be easily checked or verified without additional fine measurement equipment such as a visual camera or a scope.

[0109] Figure 2A It is shown Figure 1B An exploded plan view of the electronic equipment, and Figure 2B It is shown Figure 2A Combined plan view of electronic equipment. Figure 2C It is along Figure 2B A cross-sectional view taken along line II'. Figure 3 It is shown Figure 2B An enlarged plan view of a portion of an electronic device. Figure 3 The area where the vernier mark VM exists is shown in FIG. 1 , the base film BF of the circuit board DC is omitted, and the conductive adhesive member AF is indicated by hatching. FIG. 2A to FIG. 2C and Figure 3 The embodiments of the present disclosure are described. In addition, for the purpose of simplicity and convenience of description, the same Figures 1A to 1D The same components as those described above will be denoted by the same reference numerals, and description thereof will be omitted.

[0110] like Figure 2AAs shown in , the display panel DP may include a base substrate BS, pixels PX, signal lines SL, pads PD, alignment pads PD-A, first alignment marks AM1-P, second alignment marks AM2-P, and vernier marks VM. The base substrate BS may be a substrate including an active area AA and a peripheral area PA, and may be a base layer in which pixels PX, signal lines SL, pads PD, alignment pads PD-A, first alignment marks AM1-P, second alignment marks AM2-P, and vernier marks VM are arranged. The base substrate BS may have insulation.

[0111] In the present embodiment, for the purpose of simplicity and convenience of description and illustration, some of the pixels PX, some of the signal lines SL, and some of the pads PD are shown. FIG. 2A to FIG. 2B In the embodiment, the signal lines SL may connect the pads PD to the pixels PX, respectively. Therefore, the electrical signals received from the pads PD may be transmitted to the pixels PX, respectively, through the signal lines SL. In the present embodiment, the pads PD may extend in a direction inclined with respect to the first direction D1 and the second direction D2.

[0112] The alignment pad PD-A may be spaced apart from the pad PD in the first direction D1. The alignment pad PD-A may have a shape corresponding to the shape of at least one of the pads PD. The alignment pad PD-A may be a floating pattern. Therefore, even if the alignment pad PD-A is connected to the circuit board DC or the electrical signal is transmitted to the alignment pad PD-A, the electrical signal may not be provided to the pixel PX. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the alignment pad PD-A may be an inspection pad for inspecting the electrical characteristics of the display panel DP. In this case, the alignment pad PD-A may be electrically connected to at least one of the pixels PX, but may not be connected to the circuit board DC. In an embodiment, the alignment pad PD-A may be omitted from the display panel DP.

[0113] The first alignment mark AM1-P and the second alignment mark AM2-P may be used as a reference for alignment between the display panel DP and the circuit board DC. The first alignment mark AM1-P and the second alignment mark AM2-P may be electrically insulated from the pixel PX. In the present embodiment, the first alignment mark AM1-P is adjacent to the alignment pad PD-A, and the second alignment mark AM2-P is spaced apart from the alignment pad PD-A. In addition, the first alignment mark AM1-P and the second alignment mark AM2-P have shapes different from each other. However, the embodiments of the present disclosure are not limited thereto. In certain embodiments, the first alignment mark AM1-P and the second alignment mark AM2-P may be disposed at various suitable positions in the display panel DP and may have various suitable shapes.

[0114] When viewed in a plan view, the vernier mark VM may be arranged in the peripheral area PA, and may be spaced apart from the pad PD, the signal line SL, the alignment pad PD-A, the first alignment mark AM1-P, and the second alignment mark AM2-P. In the present embodiment, the vernier mark VM may be set in plurality, and when viewed in the second direction D2, the plurality of vernier marks VM may be spaced apart from each other in the first direction D1, with the pad PD interposed therebetween. The vernier mark VM may be used as a reference for alignment between the conductive adhesive member AF and the pad PD. For example, in the display panel DP according to an embodiment of the present disclosure, when viewed in a plan view, the adhesive area ADA on which the conductive adhesive member AF is arranged may be defined so that the top end of the adhesive area ADA meets the bottom end of the vernier mark VM. This will be described in more detail below.

[0115] The flexible film CB may include a base film BF, a plurality of interconnection lines SL-F, a plurality of leads LD, an alignment lead LD-A, a third alignment mark AM1-F, and a fourth alignment mark AM2-F. The base film BF may have flexibility and may have insulation. Therefore, the flexible film CB may be bent in a state where it is coupled to the display panel DP.

[0116] The lead LD, the alignment lead LD-A, the third alignment mark AM1-F, and the fourth alignment mark AM2-F may be arranged on one surface of the base film BF. The lead LD may be connected to the display panel DP. The lead LD may be spaced apart from each other in the first direction D1 and may provide electrical signals independent of each other. In the present embodiment, the lead LD may extend in a direction inclined relative to the first direction D1 and the second direction D2. The lead LD may have a shape substantially corresponding to the shape of the pad PD.

[0117] The base film BF of the circuit board DC and / or the base substrate BS of the display panel DP may be thermally deformed due to the heat generated in the process of connecting the circuit board DC and the display panel DP to each other. Therefore, in this process, the spacing of the pads PD and / or the spacing of the leads LD may change differently from the designed values. However, according to an embodiment of the present disclosure, the leads LD and the pads PD may be designed to have a shape extending in an inclined direction. Therefore, even if the spacing of the leads LD and / or the spacing of the pads PD changes, the alignment between the pads PD and the leads LD can be easily corrected by moving the position of the circuit board DC in the second direction D2.

[0118] When viewed in a plan view, the alignment lead LD-A may be spaced apart from the lead LD. The alignment lead LD-A may be spaced apart from the lead LD in the first direction D1. The alignment lead LD-A may have a shape corresponding to the shape of at least one of the leads LD. The alignment lead LD-A may be a floating pattern. Therefore, even if the alignment lead LD-A is connected to the display panel DP or an electrical signal is transmitted to the alignment lead LD-A, the electrical signal may not be provided to the pixel PX. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the alignment lead LD-A may be an inspection lead for inspecting the electrical characteristics of the circuit board DC. In an embodiment, the alignment lead LD-A may be omitted from the circuit board DC.

[0119] The third alignment mark AM1-F and the fourth alignment mark AM2-F may be used as a reference for alignment between the display panel DP and the circuit board DC. The third alignment mark AM1-F and the fourth alignment mark AM2-F may be electrically insulated from the lead LD. In the present embodiment, the third alignment mark AM1-F may correspond to the first alignment mark AM1-P of the display panel DP, and the fourth alignment mark AM2-F may correspond to the second alignment mark AM2-P of the display panel DP. The third alignment mark AM1-F and the fourth alignment mark AM2-F may be aligned with the first alignment mark AM1-P and the second alignment mark AM2-P of the display panel DP, respectively, and therefore, the circuit board DC may be easily aligned with the display panel DP.

[0120] In this embodiment, the third alignment mark AM1-F and the fourth alignment mark AM2-F have different shapes from each other. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the third alignment mark AM1-F and the fourth alignment mark AM2-F may be disposed at various suitable positions in the circuit board DC and may have various suitable shapes.

[0121] The interconnection lines SL-F may be arranged on one surface of the base film BF. One end of each of the interconnection lines SL-F may be connected to each of the lead lines LD. The other end of each of the interconnection lines SL-F may be connected to the drive circuit DV (see Figure 1A ). Therefore, the electric signal processed in the driving circuit DV can be output to the lead LD through the interconnection line SL-F.

[0122] The conductive adhesive member AF and the flexible film CB may be arranged along Figure 2A, and then the circuit board DC may be disposed on the conductive adhesive member AF by aligning the first alignment mark AM1-P and the second alignment mark AM2-P of the display panel DP with the third alignment mark AM1-F and the fourth alignment mark AM2-F of the circuit board DC. Thereafter, the display panel DP and the circuit board DC may be coupled to each other via the conductive adhesive member AF. Figure 2B and Figure 3 , the circuit board DC and the display panel DP may be aligned with each other by forming the first alignment mark AM1-P and the third alignment mark AM1-F into a first alignment pattern AM1 and forming the second alignment mark AM2-P and the fourth alignment mark AM2-F into a second alignment pattern AM2, and then, the circuit board DC may be connected to the display panel DP.

[0123] When viewed in a plan view, the pad PD may overlap the lead LD. In the present embodiment, the pad PD is indicated by hatching to easily distinguish the pad PD from the lead LD. Each of the pads PD may be connected to a corresponding one of the leads LD. The pad PD and the lead LD connected in parallel to each other are shown as a connection pattern PLD.

[0124] According to an embodiment of the present disclosure, the lead LD and the pad PD may be designed so that the length of the lead LD in the second direction D2 is greater than the length of the pad PD in the second direction D2. Therefore, even if the circuit board DC moves relative to the display panel DP in the second direction D2 within the process tolerance, the circuit board DC and the display panel DP may be stably connected to each other. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the length of the lead LD may be substantially equal to or less than the length of the pad PD.

[0125] Reference Figure 2C , the lead LD may be connected to the pad PD through the conductive adhesive member AF. In the present embodiment, for the purpose of simplicity and convenience of description, the pad PD arranged on one surface of the base substrate BS and the lead LD arranged on one surface of the base film BF are shown. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, at least one insulating layer may be arranged between the base substrate BS and the pad PD, and / or at least one insulating layer may be arranged between the base film BF and the lead LD.

[0126] In the present embodiment, the conductive adhesive member AF may have a length in the first direction D1 and a width in the second direction D2. The length of the conductive adhesive member AF can cover the pad PD, the alignment pad PD-A, the first alignment pattern AM1, and the second alignment pattern AM2. In addition, the width of the conductive adhesive member AF can at least cover the pad PD. Therefore, the conductive adhesive member AF can at least completely cover the pad PD. As a result, the reliability of the electrical connection between the circuit board DC and the display panel DP can be improved.

[0127] The conductive adhesive member AF may include an adhesive layer AD and a plurality of conductive particles CD. The conductive particles CD may be dispersed in the adhesive layer AD. The leads LD may be respectively disposed on the pads PD. The leads LD may be physically connected to the pads PD through the adhesive layer AD. In addition, the lead LD may be electrically connected to the pads PD through the conductive particles CD arranged between the lead LD and the pads PD. In the present embodiment, when viewed in a cross-sectional view, the leads LD may completely overlap with the pads PD, respectively. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, there may be areas where the leads partially do not overlap with the corresponding pads due to errors occurring in the design and / or vibrations occurring in the first direction D1 during the connection or bonding process.

[0128] Will refer to Figure 2B and Figure 3 The vernier mark VM and the conductive adhesive member AF are described in more detail. According to an embodiment of the present disclosure, the position of the conductive adhesive member AF can be determined based on the vernier mark VM. The vernier mark VM may be defined in an area having a rectangular shape having a lateral length LDD measured in a first direction D1 and a longitudinal length WD measured in a second direction D2. When viewed in a plan view, the vernier mark VM may be spaced apart from the pad PD, the alignment pad PD-A, the alignment marks AM1-P and AM2-P, and the signal line SL. In other words, in the present embodiment, when viewed in a plan view, the vernier mark VM may not overlap with the pad PD, the alignment pad PD-A, the alignment marks AM1-P and AM2-P, and the signal line SL. Therefore, the vernier mark VM may not be electrically interfered with by the pad PD, the alignment pad PD-A, the alignment marks AM1-P and AM2-P, and the signal line SL adjacent to the vernier mark VM.

[0129] The shape of the vernier mark VM may be variously modified or changed in an area spaced apart from adjacent components. In the present embodiment, the vernier mark VM may include a plurality of line patterns LP. Each of the line patterns LP may have a line shape extending parallel (e.g., substantially parallel) to the first direction D1. The line patterns LP may be spaced apart from each other in the second direction D2 and may be arranged in the second direction D2. For example, the line patterns LP may be spaced apart from each other at uniform (e.g., substantially uniform) intervals in the second direction D2.

[0130] When viewed in a plan view, the line pattern LP may include a lowermost line LP-L closest to the pad PD and an uppermost line LP-U farthest from the pad PD. The lowermost line LP-L may extend along a first imaginary line VL1. The lowermost line LP-L in the plan view may overlap with the first imaginary line VL1. The lowermost line LP-L may be one of the line pattern LP that is closest to the conductive adhesive member AF. The first imaginary line VL1 may extend parallel (e.g., substantially parallel) to the first direction D1. The first imaginary line VL1 may meet the top of the pad PD in a plan view. In other words, in the present embodiment, the lowermost line LP-L of the line pattern LP may be substantially aligned with the top of the pad PD along a single common imaginary line (e.g., the first imaginary line VL1).

[0131] Therefore, when the conductive adhesive member AF is positioned to contact the bottom end of the vernier mark VM, it can be evaluated that the conductive adhesive member AF is arranged at a position that stably overlaps with at least the pad PD. As the position of the conductive adhesive member AF moves upward from the bottom end of the vernier mark VM along the second direction D2 in a plan view, the separation distance between the top end of the conductive adhesive member AF and the top end of the pad PD may increase. If the separation distance increases beyond a set or predetermined range, the overlapping area between the conductive adhesive member AF and the pad PD may decrease, resulting in misalignment of the conductive adhesive member AF. Therefore, the connection failure between the conductive adhesive member AF and the pad PD may be easily caused. However, according to an embodiment of the present disclosure, since the display panel DP also includes a vernier mark VM aligned along the second imaginary line VL2, it can be easily determined or checked whether the conductive adhesive member AF is misaligned with the pad PD.

[0132] The end EGP of the line pattern LP may be aligned along the second imaginary line VL2. The end EGP of the line pattern LP may be the end closest to the pad PD. The second imaginary line VL2 may extend parallel to (e.g., substantially parallel to) the second direction D2. The second imaginary line VL2 may meet one end of the first alignment mark AM1-P. In other words, in the present embodiment, the end EGP of the line pattern LP may be substantially aligned with the end of the first alignment mark AM1-P along a common imaginary line (e.g., the second imaginary line VL2).

[0133] The lateral length LDD of the vernier mark VM may be defined as the length of each of the line patterns LP, and the longitudinal length WD of the vernier mark VM may correspond to the distance between the uppermost line LP-U and the lowermost line LP-L of the line pattern LP. In more detail, the longitudinal length WD of the vernier mark VM may correspond to the length between a point of the second imaginary line VL2 overlapping the uppermost line LP-U and a point of the second imaginary line VL2 overlapping the lowermost line LP-L.

[0134] In the present embodiment, when viewed in the second direction D2, the lateral length LDD may be a length that allows the conductive adhesive member AF to overlap with the vernier mark VM. For example, the lateral length LDD of the vernier mark VM may be about 1200 μm. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the lateral length LDD of the vernier mark VM may be differently designed according to the position of the vernier mark VM and / or the length of the conductive adhesive member AF in the first direction D1.

[0135] According to an embodiment of the present disclosure, the separation distance from the top end of the pad PD to the top end (e.g., top side) of the conductive adhesive member AF (e.g., the degree of misalignment of the conductive adhesive member AF relative to the pad PD) can be measured within the range of the longitudinal length WD of the vernier mark VM. Therefore, as the longitudinal length WD of the vernier mark VM increases, the range of the degree of misalignment of the conductive adhesive member AF that can be determined or checked can be increased. The longitudinal length WD of the vernier mark VM may be equal to or greater than the allowable misalignment range.

[0136] For example, when the misalignment degree of the conductive adhesive member AF (e.g., the separation distance between the top end of the conductive adhesive member AF and the top end of the pad PD) is about 100 μm or less in a good product according to an embodiment of the present disclosure, the longitudinal length WD of the vernier mark VM can be designed to be about 100 μm or more. In this case, by checking whether the top end of the conductive adhesive member AF exceeds the top end of the vernier mark VM (e.g., the uppermost line LP-U), it can be easily determined or checked whether the alignment degree of the conductive adhesive member AF is good, and therefore, the process time can be reduced.

[0137] On the other hand, as the longitudinal length WD of the vernier mark VM increases, the possibility of interference between the vernier mark VM and the signal line SL or the first alignment mark AM1-P adjacent thereto may increase. Conversely, as the lateral length LDD of the vernier mark VM decreases, the number of line patterns LP may decrease, or the distance between the line patterns LP may decrease. As the number of line patterns LP decreases, it may be difficult to check or determine subtle differences in the degree of alignment. As the distance between the line patterns LP decreases, readability determined or checked by the naked eye may be difficult. As used herein, the term "naked eye" refers to the human eye (or human vision) without the aid of a magnifying device or equipment other than typical prescription glasses.

[0138] According to an embodiment of the present disclosure, the vernier mark VM may be designed to have a size sufficient to ensure a sufficient number of line patterns LP without causing interference with adjacent components and / or to maintain a distance between the line patterns LP that can easily determine or check alignment. For example, the longitudinal length WD of the vernier mark VM according to an embodiment of the present disclosure may be about 450 μm.

[0139] However, the embodiments of the present disclosure are not limited thereto. The vernier mark VM may be designed differently as long as it does not interfere with the adjacent signal line and has a position and size capable of determining or checking the degree of misalignment of the conductive adhesive member AF. For example, the top end of the pad PD may not overlap with the lowermost line LP-L in the first direction D1. In this case, the conductive adhesive member AF may be arranged to overlap with a portion of the vernier mark VM when viewed in a plan view.

[0140] In an embodiment, the width of each of the line patterns LP and the distance between the line patterns LP may be designed differently. Therefore, the pitch of the line patterns LP may be designed differently. As described above, as the pitch of the line patterns LP increases, the vernier mark VM may be easily observed by the naked eye in the process. Therefore, the degree of alignment of the conductive adhesive member AF may be checked or determined in real time by naked eye inspection (e.g., visual inspection), and therefore, the process may be simplified and the process time may be reduced.

[0141] In an embodiment, as the pitch of the line pattern LP decreases, the number of line patterns LP of the vernier mark VM in the same area can be increased. Therefore, it is possible to evaluate the degree of fine alignment and whether the conductive adhesive member AF is aligned. As a result, process reliability can be improved. In an embodiment, even if it is somewhat difficult to check or determine the degree of alignment with the naked eye, the line pattern LP can be designed to have a pitch that can be observed through a microscope (such as a small magnifying glass). As used herein, the term "loupe" or "small magnifying glass" refers to a magnifying device or equipment, including a magnifying glass and glasses, but is not limited thereto.

[0142] In the vernier mark VM according to an embodiment of the present disclosure, each of the line patterns LP may have a width of about 3 μm, and the pitch of the line patterns LP may be about 50 μm. The pitch can be checked or determined with the naked eye. In addition, the design pitches of the line patterns LP of the vernier mark VM may be equal to each other. Therefore, by checking the number of line patterns LP overlapping with the conductive adhesive member AF, the degree of alignment of the conductive adhesive member AF can be easily quantitatively checked. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the vernier mark VM may include line patterns LP having finer pitches, or may include line patterns LP arranged at different pitches.

[0143] According to an embodiment of the present disclosure, the degree of alignment of the conductive adhesive member AF may be determined according to the number of line patterns of the line pattern LP of the vernier mark VM that overlap the conductive adhesive member AF. According to an embodiment of the present disclosure, under the condition that the vernier mark VM checks or determines the degree of alignment of the conductive adhesive member AF and whether the conductive adhesive member AF is aligned, the position and / or size of the vernier mark VM may be designed differently.

[0144] The vernier mark VM according to an embodiment of the present disclosure may include a conductive material or a semiconductor material. For example, the vernier mark VM may include a metal, a metal oxide, or a semiconductor material. In more detail, the vernier mark VM may include a material having a reflectivity or a refractive index different from that of the insulating layer or the base substrate BS. Therefore, the vernier mark VM can be easily distinguished from the adjacent area by a magnifying glass or the naked eye.

[0145] In the present embodiment, the circuit board DC may partially overlap with the vernier mark VM. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the circuit board DC may be arranged at a position that does not overlap with the vernier mark VM in a plan view, or may have a size that does not overlap with the vernier mark VM in a plan view.

[0146] When viewed in a plan view, at least a portion of the conductive adhesive member AF may protrude from the circuit board DC in the first direction D1 or in a direction opposite to the first direction D1. This may be because the length of the conductive adhesive member AF in the first direction D1 is greater than the width of the circuit board DC in the first direction D1. When viewed in the second direction D2, the conductive adhesive member AF may have a length that can overlap with the vernier mark VM. According to an embodiment of the present disclosure, the alignment degree of the conductive adhesive member AF can be easily checked by the vernier mark VM that is not covered by the circuit board DC.

[0147] In an embodiment, the conductive adhesive member AF may be completely covered by the circuit board DC in a plan view. In this case, when viewed in the second direction D2, the vernier mark VM may be shifted from the position shown in the first direction D1 or the opposite direction so as to be closer to the signal line SL, and therefore, the vernier mark VM may be defined at a position overlapping one or some of the pads PD. An electronic device DD according to an embodiment of the present disclosure may include a conductive adhesive member AF, wherein the shape and size of the conductive adhesive member AF are modified differently under the condition of checking or determining the degree of alignment of the conductive adhesive member AF using the vernier mark VM.

[0148] Figure 4 is a cross-sectional view schematically showing a portion of an electronic device according to an embodiment of the present disclosure. FIG. 5A to FIG. 5C Schematically illustrates a cross-sectional view of a portion of an electronic device according to some embodiments of the present disclosure. For the purpose of simplicity and convenience of description and illustration, Figure 4 shows a portion of a pixel PX and along Figure 3 The area intercepted by line II-II'. FIG. 5A to FIG. 5C Shown with Figure 4 In the following, reference will be made to Figures 4 to 5C The embodiments of the present disclosure are described. In addition, for the purpose of simplicity and convenience of description, the same Figures 1A to 3 The same components as those described above will be denoted by the same reference numerals, and description thereof will be omitted.

[0149] like Figure 4 As shown in , the display panel DP may include a base substrate BS, a pixel layer PXL, and an encapsulation layer TFE. As described above, the base substrate BS may be a base layer on which the pixels PX and the vernier mark VM are arranged. The base substrate BS may have insulating properties. For example, the base substrate BS may include a resin substrate or a glass substrate.

[0150] The pixel layer PXL may be disposed on the base substrate BS. The pixel layer PXL may include a pixel PX and a plurality of insulating layers BL, 10, 20, 30, and 40. The insulating layers BL, 10, 20, 30, and 40 may include a base layer BL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, and a fourth insulating layer 40. In this embodiment, Figure 1D The second transistor TR2 (hereinafter referred to as a thin film transistor) and the light emitting element OLD of some of the components of the pixel PX are shown as examples.

[0151] The thin film transistor TR2 may be arranged on the base substrate BS. The thin film transistor TR2 may include a semiconductor pattern SP, an input electrode IE, an output electrode OE, and a control electrode CE. In the present embodiment, a base layer BL may be arranged between the semiconductor pattern SP and the base substrate BS. The base layer BL may include a single insulating layer or a plurality of insulating layers. For example, the base layer BL may include at least one selected from a buffer layer and a barrier layer. Therefore, the thin film transistor TR2 may be stably formed on the base substrate BS, and oxygen or moisture provided through the base substrate BS may be prevented or reduced from penetrating into the pixel PX through the base layer BL.

[0152] The control electrode CE may be spaced apart from the semiconductor pattern SP with the first insulating layer 10 interposed therebetween. The input electrode IE and the output electrode OE may be spaced apart from the control electrode CE with the second insulating layer 20 interposed therebetween. The input electrode IE and the output electrode OE may penetrate the first insulating layer 10 and the second insulating layer 20, respectively, to be connected to one side and the other side of the semiconductor pattern SP.

[0153] According to other embodiments, in the thin film transistor TR2, the control electrode CE may be arranged under the semiconductor pattern SP, and / or the input electrode IE and the output electrode OE may be arranged under the semiconductor pattern SP or may be arranged on the same layer as the semiconductor pattern SP to be directly connected to the semiconductor pattern SP. The thin film transistor TR2 according to the present disclosure may have any of various suitable structures and may not be limited to a specific embodiment.

[0154] The light emitting element OLD may be disposed on the third insulating layer 30. The light emitting element OLD may include a first electrode E1, an emission layer EL, and a second electrode E2 sequentially stacked in the third direction D3.

[0155] The first electrode E1 may penetrate the third insulating layer 30 to be connected to the thin film transistor TR2. In some embodiments, a connection electrode may be additionally disposed between the first electrode E1 and the thin film transistor TR2. In this case, the first electrode E1 may be electrically connected to the thin film transistor TR2 through the connection electrode.

[0156] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may have an opening defined therein. The opening may expose at least a portion of the first electrode E1. The fourth insulating layer 40 may be a pixel defining layer.

[0157] The emission layer EL may be arranged on the first electrode E1. The emission layer EL may include a light-emitting material. For example, the emission layer EL may include at least one selected from materials emitting red light, green light, and blue light. In an embodiment, the emission layer EL may include a fluorescent material or a phosphorescent material. In some embodiments, the emission layer EL may include an organic light-emitting material or an inorganic light-emitting material, such as quantum dots. The emission layer EL may emit light in response to a potential difference between the first electrode E1 and the second electrode E2.

[0158] The second electrode E2 may be disposed on the emission layer EL. The second electrode E2 may be opposite to the first electrode E1. The second electrode E2 may be connected to Figure 1D The light emitting element OLD may receive a second power signal through the second electrode E2.

[0159] The second electrode E2 may include a transparent conductive material or a semi-transparent conductive material. Therefore, the light generated from the emission layer EL may be easily emitted through the second electrode E2 in the third direction D3. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the first electrode E1 may include a transparent conductive material or a semi-transparent conductive material, and the light emitting element OLD may be driven in a rear surface light emitting type (or kind). In yet another embodiment, the light emitting element OLD may be driven in a two-surface light emitting type (or kind) such that light is emitted through the front surface and the rear surface.

[0160] In some embodiments, the light emitting element OLD may further include at least one organic layer or at least one inorganic layer disposed between the emission layer EL and the first electrode E1 and / or between the emission layer EL and the second electrode E2. The organic layer or the inorganic layer may control the movement of charges flowing from the first electrode E1 and the second electrode E2 into the emission layer EL to improve the light efficiency and service life of the light emitting element OLD.

[0161] The encapsulation layer TFE may be disposed on the light emitting element OLD to encapsulate the light emitting element OLD. In some embodiments, a cover layer covering the second electrode E2 may be disposed between the second electrode E2 and the encapsulation layer TFE.

[0162] The encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 sequentially stacked in the third direction D3. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the encapsulation layer TFE may further include a plurality of inorganic layers and / or a plurality of organic layers.

[0163] The first inorganic layer IOL1 may cover the second electrode E2. The penetration of external moisture and / or oxygen into the light emitting element OLD may be prevented or reduced by the first inorganic layer IOL1. For example, the first inorganic layer IOL1 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The first inorganic layer IOL1 may be formed by a deposition process.

[0164] The organic layer OL may be arranged on the first inorganic layer 10L1 and may be in contact with the first inorganic layer 10L1. The organic layer OL may be planarized on the first inorganic layer 10L1. The organic layer OL may cover the curved portion of the top surface of the first inorganic layer 10L1 and / or particles present on the first inorganic layer 10L1, and thus, may block the influence of the curved portion and / or particles on the components formed on the organic layer OL. In addition, the organic layer OL may relax or release stress between layers in contact with the organic layer OL. The organic layer OL may include an organic material and may be formed by a solution process such as a spin coating process, a slit coating process, and / or an inkjet process.

[0165] The second inorganic layer IOL2 may be arranged on the organic layer OL to cover the organic layer OL. The second inorganic layer IOL2 may be stably formed on a relatively flat top surface of the organic layer OL compared to the top surface of the first inorganic layer IOL1. The second inorganic layer IOL2 may block moisture flowing out of the organic layer OL so that moisture can be prevented or reduced from escaping to the outside. For example, the second inorganic layer IOL2 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The second inorganic layer IOL2 may be formed by a deposition process.

[0166] In some embodiments, the encapsulation layer TFE may include a glass substrate. In this case, the encapsulation layer TFE may be connected to the base substrate BS via a fusion seal. In certain embodiments, the encapsulation layer TFE may have at least one of various other suitable shapes for encapsulating the light emitting element OLD.

[0167] In some embodiments, an input sensing unit including a plurality of sensor patterns may be disposed on the encapsulation layer TFE. In this case, an optical member OPL and an adhesive layer ADL may be disposed on the input sensing unit.

[0168] The optical member OPL may be arranged on the display panel DP. In some embodiments, the electronic device DD according to an embodiment of the present disclosure may further include an adhesive layer ADL. The adhesive layer ADL may be arranged between the display panel DP and the optical member OPL to physically connect the optical member OPL to the display panel DP. For example, the adhesive layer ADL may include an optically clear adhesive (OCA), an optically clear resin (OCR), or a pressure-sensitive adhesive (PSA).

[0169] In the present embodiment, the peripheral area PA may be exposed from the optical member OPL and the adhesive layer ADL. The optical member OPL and the adhesive layer ADL may not cover the vernier mark VM.

[0170] In the present embodiment, the area where the vernier mark VM is arranged may be covered by the insulating layers BL, 10, 20, 30 and 40 and may be exposed from the encapsulation layer TFE. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, at least a portion of the encapsulation layer TFE may extend to overlap with the vernier mark VM. Optionally, at least one selected from the second insulating layer 20, the third insulating layer 30 and the fourth insulating layer 40 on the vernier mark VM may be omitted so as not to overlap with the vernier mark VM. In some embodiments, the stacking structure in the peripheral area PA may be modified differently.

[0171] As the number of layers covering the vernier mark VM decreases, it may be relatively easy to check the vernier mark VM with the naked eye. As the number of layers covering the vernier mark VM increases, damage to the vernier mark VM during the process may be prevented or reduced and / or static electricity generated by adjacent components may be prevented or reduced. Therefore, the reliability of the process may be improved. In some embodiments, the vernier mark VM may be arranged at various suitable positions within the range that can be checked or identified from the outside to align the conductive adhesive member AF and ensure its stability during the process.

[0172] In this embodiment, the line pattern LP of the vernier mark VM may be arranged on the same layer. For example, the uppermost line LP-U and the lowermost line LP-L of the line pattern LP may be arranged on the same layer. Therefore, the vernier mark VM may be formed by a single patterning process.

[0173] In the present embodiment, the vernier mark VM may be arranged on the same layer as the control electrode CE. Therefore, the vernier mark VM may be arranged between the first insulating layer 10 and the second insulating layer 20. The vernier mark VM may be formed of the same material as the control electrode CE. For example, the vernier mark VM may be formed of a conductive material. Therefore, the vernier mark VM may be formed simultaneously (e.g., synchronously) with the control electrode CE in the process of forming the control electrode CE by using a single mask. As a result, the vernier mark VM may be formed without an additional process, and therefore, the manufacturing process may be simplified and the process cost may be reduced.

[0174] In another embodiment, Figure 5A As shown in FIG. 1 , the vernier mark VM- 1 may be disposed on the same layer as the input electrode IE and the output electrode OE. Therefore, the vernier mark VM- 1 may be disposed between the second insulating layer 20 and the third insulating layer 30 .

[0175] In this case, the vernier mark VM-1 may be formed of the same material as the input electrode IE and the output electrode OE. Therefore, the vernier mark VM-1 may be formed simultaneously (e.g., synchronously) with the input electrode IE and the output electrode OE by using a single mask in the process of forming the input electrode IE and the output electrode OE. As a result, the vernier mark VM-1 may be formed without an additional process, and therefore, the manufacturing process may be simplified and the process cost may be reduced.

[0176] In another embodiment, Figure 5B As shown in , the vernier mark VM-2 may be arranged on the same layer as the first electrode E1. Therefore, the vernier mark VM-2 may be arranged between the third insulating layer 30 and the fourth insulating layer 40. In this case, the vernier mark VM-2 may be formed of the same material as the first electrode E1. Therefore, the vernier mark VM-2 may be formed simultaneously (e.g., synchronously) with the first electrode E1 in the process of forming the first electrode E1 by using a single mask. As a result, the vernier mark VM-2 may be formed without an additional process, and therefore, the manufacturing process may be simplified and the process cost may be reduced.

[0177] In another embodiment, Figure 5C As shown in , the vernier mark VM-3 may be arranged on the same layer as the semiconductor pattern SP. Therefore, the vernier mark VM-3 may be arranged between the base layer BL and the first insulating layer 10. In this case, the vernier mark VM-3 may be formed of the same material as the semiconductor pattern SP. Therefore, the vernier mark VM-3 may be formed simultaneously (e.g., synchronously) with the semiconductor pattern SP by using a single mask in the process of forming the semiconductor pattern SP. As a result, the vernier mark VM-3 may be formed without an additional process, and therefore, the manufacturing process may be simplified and the process cost may be reduced.

[0178] FIG. 6A to FIG. 6D is a plan view showing a portion of an electronic device according to some embodiments of the present disclosure. For the purpose of simplicity and convenience of description, FIG. 6A to FIG. 6D Shown with Figure 3 In addition to the cursor marks VM1, VM2, VM3, and VM4, FIG. 6A to FIG. 6D Other components of the electronic devices DD1, DD2, DD3 and DD4 can be used with Figure 3 The corresponding components of the electronic device DD are substantially the same.

[0179] FIG. 6A to FIG. 6D Each of the cursor markers VM1, VM2, VM3, and VM4 in the Figure 3 The cursor mark VM has the same lateral length LDD and longitudinal length WD. However, in the plan view FIG. 6A to FIG. 6DThe cursor marks VM1, VM2, VM3 and VM4 in the embodiment may have different shapes. Hereinafter, for the purpose of simplicity and convenience of description, the same components as those in the above-mentioned embodiment will be indicated by the same reference numerals, and description thereof will be omitted.

[0180] like Fig. 6A As shown in FIG. 1 , when viewed in a plan view, the vernier mark VM1 may include a plurality of line patterns LP1, a plurality of horizontal patterns LP-S, and a vertical pattern LP-V. When viewed in a plan view, the line pattern LP1 may include an uppermost line LP1-U and a lowermost line LP1-L. The uppermost line LP1-U and the lowermost line LP1-L may correspond to Figure 3 The uppermost line LP-U and the lowermost line LP-L are described above, and therefore, a repeated description thereof will not be repeated here.

[0181] Each of the horizontal patterns LP-S may have a line shape extending in the first direction D1. The length of each of the horizontal patterns LP-S in the first direction D1 may be smaller than the length of each of the line patterns LP1 in the first direction D1. In other words, the length of each of the horizontal patterns LP-S in the first direction D1 may be shorter than the lateral length LDD of the vernier mark VM1.

[0182] The horizontal patterns LP-S may be spaced apart from each other in the second direction D2 and may be arranged in the second direction D2. The horizontal pattern LP-S may be arranged between the line patterns LP1. The horizontal pattern LP-S and the line pattern LP1 may be alternately arranged in the second direction D2. Since the line pattern LP1 and the horizontal pattern LP-S having a length different from that of the line pattern LP1 are alternately arranged, the horizontal pattern LP-S may be easily distinguished from the line pattern LP1. When the conductive adhesive member AF overlaps with the vernier mark VM1, the misalignment and the degree of misalignment of the conductive adhesive member AF may be easily checked by one (or both) of the horizontal pattern LP-S and the line pattern LP1 overlapping with the conductive adhesive member AF.

[0183] In some embodiments, the vernier mark VM1 may further include a vertical pattern LP-V. The vertical pattern LP-V may extend in the second direction D2. The vertical pattern LP-V may intersect the line pattern LP1 and the horizontal pattern LP-S, and may be connected to the line pattern LP1 and the horizontal pattern LP-S. The vertical pattern LP-V may be arranged at the center of the line pattern LP1. Therefore, the vertical pattern LP-V may be arranged at the center of the lateral length LDD of the vernier mark VM1.

[0184] Since the vernier mark VM1 also includes the vertical pattern LP-V, the alignment degree of the conductive adhesive member AF in the first direction D1 can be easily checked. As a result, the misalignment degree of the conductive adhesive member AF in various directions (e.g., the first direction D1 and the second direction D2) can be easily checked, and thus, the conductive adhesive member AF can be accurately aligned.

[0185] like Figure 6B As shown in , the vernier mark VM2 may include a plurality of line patterns LP2-H and a plurality of vertical patterns LP2-V. The line patterns LP2-H may be spaced apart from each other in the second direction D2 and may be arranged in the second direction D2. Each of the line patterns LP2-H may extend in the first direction D1. The vertical patterns LP2-V may be spaced apart from each other in the first direction D1 and may be arranged in the first direction D1. Each of the vertical patterns LP2-V may extend in the second direction D2.

[0186] When viewed in a plan view, the line pattern LP2-H may intersect the vertical pattern LP2-V. The line pattern LP2-H may be connected to the vertical pattern LP2-V. The vernier mark VM2 may have a substantially grid shape.

[0187] Since the vernier mark VM2 has a grid shape including a line pattern LP2-H parallel to (e.g., substantially parallel to) the first direction D1 and a vertical pattern LP2-V parallel to (e.g., substantially parallel to) the second direction D2, the alignment degree of the conductive adhesive member AF can be easily checked in the first direction D1 and the second direction D2. Therefore, the position of the conductive adhesive member AF can be easily corrected in the first direction D1 and the second direction D2. As a result, the misalignment and misalignment degree of the conductive adhesive member AF can be accurately determined and corrected, and can be easily checked with the naked eye through the vernier mark VM2. Therefore, the reliability in the process can be improved and the process time can be reduced.

[0188] like Figure 6C As shown in FIG. 1 , the vernier mark VM3 may include a plurality of pattern groups PTG spaced apart from each other in the first direction D1. In the present embodiment, the vernier mark VM3 includes three pattern groups PTG. Each of the pattern groups PTG may include a plurality of line patterns LP3 -H and a plurality of vertical patterns LP3 -V.

[0189] The line patterns LP3 -H may extend in the first direction D1 and may be arranged in the second direction D2 . Each of the vertical patterns LP3 -V may extend in the second direction D2 .

[0190] Each of the vertical patterns LP3-V may be arranged between two line patterns LP3-H adjacent to each other to connect the two line patterns LP3-H. In addition, the vertical patterns LP3-V may be arranged discontinuously in the second direction D2. In other words, the vertical patterns LP3-V may be arranged in a zigzag form in the second direction D2. Therefore, each of the pattern groups PTG may have a curved line shape extending in the second direction D2 while reciprocating in the first direction D1 and in a direction opposite to the first direction D1.

[0191] like Fig.6D As shown in , the vernier mark VM4 may include a plurality of pattern groups PTG-1 spaced apart from each other in the first direction D1. In the present embodiment, the vernier mark VM4 includes seven pattern groups PTG-1. Each of the pattern groups PTG-1 may include a plurality of patterns LP41, LP42, LP43, LP44, and LP45. Each of the patterns LP41, LP42, LP43, LP44, and LP45 may have an Arabic numeral shape.

[0192] For example, the patterns LP41, LP42, LP43, LP44, and LP45 may include a first pattern LP41 having a shape of a number "10", a second pattern LP42 having a shape of a number "20", a third pattern LP43 having a shape of a number "30", a fourth pattern LP44 having a shape of a number "40", and a fifth pattern LP45 having a shape of a number "50". The first pattern LP41, the second pattern LP42, the third pattern LP43, the fourth pattern LP44, and the fifth pattern LP45 may be sequentially arranged in the second direction D2. According to the present embodiment, since the patterns LP41, LP42, LP43, LP44, and LP45 in the shape of numbers are used as the vernier mark VM4, the misalignment and the degree of misalignment of the conductive adhesive member AF can be easily checked with the naked eye. Therefore, the manufacturing process can be simplified and the process cost can be reduced.

[0193] FIG. 7A to FIG. 7B is a cross-sectional view showing a portion of an electronic device according to some embodiments of the present disclosure. For the purpose of simplicity and convenience of description and illustration, FIG. 7A to FIG. 7B shows a portion of the active area AA and along Fig. 6A The area intercepted by line III-III'. FIG. 7A to FIG. 7B Detailed description of the invention is given below. FIG. 7A to FIG. 7B The embodiments of the present disclosure are described. In addition, for the purpose of simplicity and convenience of description, the same FIG. 1A to FIG. 6D The same components as those described above will be denoted by the same reference numerals, and description thereof will be omitted.

[0194] like Fig. 7AAs shown in FIG. 1 , the vernier mark VM1 may be formed of a single layer. In the present embodiment, the vernier mark VM1 may be arranged between the first insulating layer 10 and the second insulating layer 20. Therefore, the line pattern LP1 (see FIG. 1 ) of the vernier mark VM1 is Fig. 6A ), horizontal pattern LP-S (see Fig. 6A ) and vertical pattern LP-V (see Fig. 6A ) can have a single overall shape arranged on the same layer.

[0195] Alternatively, if Figure 7B As shown in , the vernier mark VM1-A may include stacked patterns arranged on different layers from each other. In the present embodiment, the vernier mark VM1-A may include a vertical pattern LP-V arranged between the first insulating layer 10 and the second insulating layer 20, and a line pattern LP1 and a horizontal pattern LP-S arranged between the second insulating layer 20 and the third insulating layer 30. The line pattern LP1 and the horizontal pattern LP-S may be arranged on the same layer.

[0196] The vertical pattern LP-V may be arranged on a layer different from the layer on which the line pattern LP1 and the horizontal pattern LP-S are arranged, and the second insulating layer 20 may be arranged between the vertical pattern LP-V and the line pattern LP1 and the horizontal pattern LP-S. In this case, the line pattern LP1 and the horizontal pattern LP-S may penetrate the second insulating layer 20 to be connected to the vertical pattern LP-V. Therefore, the occurrence of static electricity from the parasitic capacitance between the patterns LP1, LP-S, and LP-V may be prevented or reduced. As a result, the electrical reliability of the electronic device may be improved.

[0197] According to an embodiment of the present disclosure, the vernier mark VM1 or VM1 -A may have at least one of various suitable structures including a single-layer structure and a stacked structure.

[0198] Fig. 8A is an exploded plan view showing an electronic device according to an embodiment of the present disclosure, and Figure 8B 1 is a combined plan view showing an electronic device according to an embodiment of the present disclosure. For the purpose of simplicity and convenience of description, FIG. 8A to FIG. 8B Shown with FIG. 2A to FIG. 2B In the following, reference will be made to FIG. 8A to FIG. 8B The embodiments of the present disclosure are described. In addition, for the purpose of simplicity and convenience of description, the same Figures 1A to 7B The same components as those described above will be denoted by the same reference numerals, and description thereof will be omitted.

[0199] like FIG. 8A to FIG. 8BAs shown in, the display panel DP-1 may include a first pad group PG1 and a second pad group PG2 separated from each other in the second direction D2. The first pad group PG1 may include a plurality of first pads PD1 arranged in the first direction D1, a first alignment pad PD1-A spaced apart from the first pad PD1, and a first alignment mark AM11-P. The second pad group PG2 may include a plurality of second pads PD2 arranged in the first direction D1, a second alignment pad PD2-A spaced apart from the second pad PD2, and a second alignment mark AM21-P. The first alignment pad PD1-A, the first alignment mark AM11-P, the second alignment pad PD2-A, and the second alignment mark AM21-P may be used as a reference for alignment of the circuit board DC-1 (e.g., the base film BF), the display panel DP-1, and the conductive adhesive member AF-1. The first alignment pad PD1-A, the second alignment pad PD2-A, the first alignment mark AM11-P, and the second alignment mark AM21-P may substantially correspond to Figure 2A The alignment pad PD-A, the first alignment mark AM1-P, and the second alignment mark AM2-P are described herein, and therefore, a repeated description thereof will not be repeated here.

[0200] Each of the first pad PD1 and the second pad PD2 may be connected to a corresponding one of the signal lines SL-1. The first pad PD1 and the second pad PD2 may receive electrical signals independently of each other. For example, the first pad PD1 may be connected to some of the pixels PX, and the second pad PD2 may be connected to other pixels of the pixels PX. In another embodiment, when the display panel DP-1 includes an input sensing unit, the first pad PD1 may be connected to the pixel PX to provide an electrical signal related to image information to the pixel PX, and the second pad PD2 may be connected to the input sensing unit to provide an electrical signal related to input sensing to the input sensing unit.

[0201] The circuit board DC-1 may include a first lead group LG1 and a second lead group LG2 separated from each other in a second direction D2. The first lead group LG1 may include a plurality of first leads LD1 arranged in the first direction D1, a first alignment lead LD1-A, and a third alignment mark AM11-F. The second lead group LG2 may include a plurality of second leads LD2 arranged in the first direction D1, a second alignment lead LD2-A, and a fourth alignment mark AM21-F. The first pad PD1 and the plurality of first leads LD1 form a first connection pattern PLD1, and the second pad PD2 and the plurality of second leads LD2 form a second connection pattern PLD2. The first alignment lead LD1-A, the second alignment lead LD2-A, the third alignment mark AM11-F, and the fourth alignment mark AM21-F may substantially correspond to Figure 2AThe alignment lead LD-A, the third alignment mark AM1-F, and the fourth alignment mark AM2-F are described herein, and therefore, a repeated description thereof will not be repeated here.

[0202] The first lead LD1 and the second lead LD2 may be connected to corresponding interconnection lines SL-F1 arranged on the base film BF to connect the drive circuit DV (see Figure 1A ) is provided to the display panel DP-1. The first lead LD1 and the second lead LD2 may be connected to the first pad PD1 and the second pad PD2 corresponding thereto. The first lead LD1 and the second lead LD2 may provide electrical signals independent of each other. The first lead LD1 may provide a signal related to an image or a signal related to input sensing to the first pad PD1. Similarly, the second lead LD2 may provide a signal related to an image or a signal related to input sensing to the second pad PD2. The circuit board DC-1 may provide various suitable signals.

[0203] The adhesive area ADA may be defined adjacent to the vernier mark VM. When viewed in a plan view, the vernier mark VM may include a bottom side (or bottom end) aligned with the top end of the first pad PD1. The conductive adhesive member AF-1 may have a size that covers at least the first pad PD1 and the second pad PD2. According to an embodiment of the present disclosure, even if the first pad PD1 and the second pad PD2 are covered by the base film BF of the circuit board DC-1 and the conductive adhesive member AF-1, the alignment of the conductive adhesive member AF-1 can be easily checked by the vernier mark VM. In addition, according to an embodiment of the present disclosure, even if the number of pads increases and the area of ​​the conductive adhesive member AF-1 increases, the alignment of the conductive adhesive member AF-1 can be checked in real time in the manufacturing process by the vernier mark VM. Therefore, the position of the conductive adhesive member AF-1 can be easily corrected in real time. As a result, the process time can be reduced and the process cost can be reduced.

[0204] Fig.9A is an exploded perspective view showing an electronic device according to an embodiment of the present disclosure. FIG. 9B to FIG. 9C It is shown Fig.9A A cross-sectional view of an embodiment of a portion of an electronic device. FIG. 9B to FIG. 9C 1 shows a portion of the active area AA in which the pixels PX are arranged, and a portion of the peripheral area PA on which the vernier mark VM is arranged. 9A to 9C The embodiments of the present disclosure are described. In addition, for the purpose of simplicity and convenience of description, the same Figures 1A to 8B The same components as those described above will be denoted by the same reference numerals, and description thereof will be omitted.

[0205] The electronic device DD-T may include an electronic board EP, a circuit board DC-T, a conductive adhesive member AF, and an optical member OPL. The electronic board EP may include a display panel DP and an input sensing unit TS. The display panel DP may include a base substrate BS, a pixel layer PXL, and an encapsulation layer TFE. The base substrate BS, the pixel layer PXL, and the encapsulation layer TFE of the active area AA may correspond to Figure 4 Hereinafter, repeated description will be omitted.

[0206] The input sensing unit TS can sense external input. The input sensing unit TS can be formed directly on the encapsulation layer TFE to sense the external input applied to the electronic device DD-T. The external input may include at least one of various suitable types (or types) of input. For example, the external input according to an embodiment of the present disclosure may include at least one of various suitable external inputs, such as a part of the user's body (e.g., a finger), light, heat, and pressure. However, the embodiments of the present disclosure are not limited thereto. According to an embodiment of the present disclosure, one of various other suitable types of display panels may be applied to the electronic device DD-T.

[0207] The input sensing unit TS may include a sensor SS and a cover layer TL. The sensor SS may be disposed on the active area AA. The sensor SS may include a plurality of first sensing electrodes SP1 and a plurality of second sensing electrodes SP2 that receive electrical signals independently of each other.

[0208] Each of the first sensing electrodes SP1 may extend in the first direction D1. The first sensing electrodes SP1 may be spaced apart from each other in the second direction D2 and may be arranged in the second direction D2. Each of the second sensing electrodes SP2 may extend in the second direction D2. The second sensing electrodes SP2 may be spaced apart from each other in the first direction D1 and may be arranged in the first direction D1. Fig.9A In the drawings, for the purpose of simplicity and convenience in description and illustration, the second sensing electrode SP2 is indicated by hatching to be distinguished from the first sensing electrode SP1.

[0209] The sensor SS may sense sensing information about the external input by using a capacitance change between the first sensing electrode SP1 and the second sensing electrode SP2, a capacitance change of each of the first sensing electrode SP1 and the second sensing electrode SP2 due to the external input, or a resistance change of each of the first sensing electrode SP1 and the second sensing electrode SP2. The sensor SS may sense the external input by various suitable methods, and the embodiments of the present disclosure are not limited to specific embodiments.

[0210] Each of the first sensing electrode SP1 and the second sensing electrode SP2 may include a conductive material. For example, each of the first sensing electrode SP1 and the second sensing electrode SP2 may include a transparent conductive material. In an embodiment, each of the first sensing electrode SP1 and the second sensing electrode SP2 may include a plurality of grid lines defining openings. Each of the openings may overlap with the emission layer EL of each of the pixels PX. Therefore, even if the sensor SS is arranged on the active area AA to overlap with the pixel PX of the display panel DP, the visibility of the image displayed by the display panel DP may be prevented or reduced due to the sensor SS. FIG. 9B to FIG. 9C , for the purpose of simplicity and convenience of description, a sensor SS including grid lines is shown as an example.

[0211] The cover layer TL may be disposed on the encapsulation layer TFE to cover the sensor SS. The cover layer TL may have insulation properties. The cover layer TL may be an organic layer, or may have a stack structure of an organic layer and an inorganic layer. The cover layer TL may protect the sensor SS.

[0212] The signal line SL-T may be connected to the display panel DP and the input sensing unit TS to provide an electrical signal to the display panel DP and the input sensing unit TS. The signal line SL-T may include a gate line GL (see Figure 1D ), data line DL (see Figure 1D ), power line PL (see Figure 1D ) and a plurality of sensing lines connected to the first sensing electrode SP1 and the second sensing electrode SP2. In the present embodiment, some of the sensing lines connected to the sensor SS and some of the signal lines connected to the display panel DP are shown as examples of the signal lines SL-T.

[0213] The circuit board DC-T may be connected to the electronic board EP. The circuit board DC-T may include Figure 1A The flexible film CB and the driving circuit DV of the electronic device DD-T and the driving circuit DV. The display panel DP and the input sensing unit TS may be driven by the circuit board DC-T. For example, the circuit board DC-T may be electrically connected to the display panel DP to send / receive electrical signals related to the image, and the circuit board DC-T may also be electrically connected to the input sensing unit TS to send / receive electrical signals related to input sensing. In an embodiment, the display panel DP and the input sensing unit TS may both be controlled by a single circuit board DC-T. However, the embodiments of the present disclosure are not limited thereto. In another embodiment, the electronic device DD-T may include a circuit board for driving the display panel DP and an additional circuit board for driving the input sensing unit TS.

[0214] In this embodiment, the vernier mark VM-T may be arranged on the same layer as the sensor SS. In this embodiment, when viewed in a plan view, the vernier mark VM-T may have the same Figure 3 Therefore, the vernier mark VM-T may include a plurality of line patterns LP extending in the first direction D1 and arranged in the second direction D2. The uppermost line LP-U of the line pattern LP in a plan view may be closest to the active area AA, and the lowermost line LP-L of the line pattern LP in a plan view may be farthest from the active area AA.

[0215] For example, Fig. 9B As shown in , the vernier mark VM-T may be arranged in the same layer as the sensor SS. In this case, the encapsulation layer TFE and the cover layer TL may extend onto the peripheral area PA. The vernier mark VM-T may be arranged directly on the encapsulation layer TFE and may be covered by the cover layer TL. In another embodiment, the cover layer TL arranged on the vernier mark VM-T may be omitted from the peripheral area PA.

[0216] like Fig. 9C As shown in FIG. 1 , the vernier mark VM-T1 may be arranged on the same layer as the sensor SS. The vernier mark VM-T1 may be arranged between the second inorganic layer IOL2 and the cover layer TL. Fig. 9C The layer arranged between the vernier mark VM-T1 and the base substrate BS can be connected with the Fig. 9B In the embodiment, the layers arranged between the vernier mark VM-T and the base substrate BS are different. For example, the organic layer OL and the fourth insulating layer 40 may be omitted between the vernier mark VM-T1 and the base substrate BS. Therefore, the second inorganic layer IOL2 in which the vernier mark VM-T1 is arranged may contact the first inorganic layer IOL1 in the peripheral area PA. In the present embodiment, the vernier mark VM-T1 may be disposed at a lower level (height) than the sensor SS relative to the base substrate BS.

[0217] According to an embodiment of the present disclosure, in an electronic device DD-T including an input sensing unit TS and a display panel DP, a vernier mark VM-T or VM-T1 may be arranged on the same layer as the sensor SS. Therefore, in addition to the insulating layer (e.g., the cover layer TL), the vernier mark VM-T or VM-T1 may be arranged at a position at the uppermost portion of the base substrate BS located in the peripheral area PA in the thickness direction. As a result, the vernier mark VM-T or VM-T1 may be easily observed with the naked eye. The conductive adhesive member AF may be easily aligned by the naked eye through the vernier mark VM-T or VM-T1, and therefore, the reliability of the electrical connection between the circuit board DC-T and the electronic board EP may be improved, and the connection process may be simplified.

[0218] In some embodiments, the vernier mark VM-T or VM-T1 may include the same material as the sensor SS. Therefore, the vernier mark VM-T or VM-T1 and the sensor SS may be patterned simultaneously by using a single mask. As a result, the vernier mark VM-T or VM-T1 may be easily formed without an additional process.

[0219] FIG. 10A to FIG. 10E is a perspective view showing a method of manufacturing an electronic device according to an embodiment of the present disclosure. For the purpose of simplicity and convenience of description, FIG. 10A to FIG. 10E Shows the manufacturing Figure 1C In the following, reference will be made to FIG. 10A to FIG. 10E The embodiments of the present disclosure are described.

[0220] Reference Fig. 10A , the conductive adhesive member AF may be aligned with the display module DM. The display module DM may include a display panel DP and an optical member OPL. The optical member OPL may expose the pad PD of the display module DM. The vernier mark VM may exist in the area exposed from the optical member OPL.

[0221] The conductive adhesive member AF may be aligned with the adhesive area ADA to cover the pad PD. The adhesive area ADA may be defined adjacent to the vernier mark VM.

[0222] Afterwards, if FIG. 10B to FIG. 10C As shown in , a first bonding process may be performed to bond the conductive adhesive member AF to the display panel DP. In the first bonding process, the conductive adhesive member AF may be bonded to the bonding area ADA, and then may be pressed by the pressing device PS1. At this time, the degree of alignment of the conductive adhesive member AF may be easily checked by the degree of overlap with the vernier mark VM. According to an embodiment of the present disclosure, even if the pad PD is covered by the conductive adhesive member AF, and therefore, it is difficult to accurately determine whether the conductive adhesive member AF is aligned with the pad PD, the degree of alignment of the conductive adhesive member AF may be easily checked by the degree of overlap between the vernier mark VM and the conductive adhesive member AF.

[0223] Next, if FIG. 10D to FIG. 10EAs shown in , a second bonding process of bonding the circuit board DC to the display panel DP may be performed to manufacture the electronic device DD. In the second bonding process, the circuit board DC may be arranged on the conductive adhesive member AF, and then may be pressed by the pressing device PS2. After the circuit board DC is aligned on the conductive adhesive member AF, the circuit board DC may be pressed by the pressing device PS2 to enhance the bonding strength between the circuit board DC and the conductive adhesive member AF and the bonding strength between the display panel DP and the conductive adhesive member AF. At this time, because the alignment degree of the conductive adhesive member AF is checked in real time, the alignment accuracy of the circuit board DC may also be improved based on the checked alignment degree of the conductive adhesive member AF. Therefore, the reliability of the electronic device may be improved in the process of connecting the circuit board DC, and the process time and process cost may be reduced.

[0224] FIG. 11A to FIG. 11D 1 is a plan view showing some processes of a method for manufacturing an electronic device according to an embodiment of the present disclosure. For the purpose of simplicity and convenience of description, FIG. 11A to FIG. 11D Shown with Fig. 9C In the following, we will refer to FIG. 11A to FIG. 11D The embodiments of the present disclosure are described.

[0225] like Fig.11A As shown in , in the method of manufacturing an electronic device according to an embodiment of the present disclosure, the conductive adhesive member AF-B may be set to overlap with a portion of the vernier mark VM. At this time, the width W1 of the conductive adhesive member AF-B in the second direction D2 may be greater than the width W2 of the pad PD in the second direction D2. Therefore, when the conductive adhesive member AF-B overlaps with a portion of the vernier mark VM, it can be recognized that the conductive adhesive member AF-B is aligned to stably cover the pad PD of the display panel DP-B. As a result, the degree of alignment of the conductive adhesive member AF-B can be easily checked by the degree of overlap of the vernier mark VM with the conductive adhesive member AF-B.

[0226] like FIG. 11B to FIG. 11D As shown in , the method of manufacturing an electronic device according to an embodiment of the present disclosure may further include correcting the position of the conductive adhesive member AF. Fig. 11B As shown in , when the conductive adhesive member AF is aligned at a position that completely covers the pad PD of the display panel DP, the conductive adhesive member AF may meet the vernier mark VM. In other words, in the present embodiment, when the bottom end of the vernier mark VM meets the conductive adhesive member AF, the conductive adhesive member AF may have a maximum overlapping area with the pad PD.

[0227] Alternatively, even if something like Fig. 11B In the process of performing initial alignment, the degree of misalignment may also increase due to vibration or repeated misalignment, and therefore, Fig. 11CAs shown in , the conductive adhesive member AF may be bonded to the display panel DP-C in a state where the overlapping area between the conductive adhesive member AF and the pad PD is extremely reduced. At this time, most of the line pattern of the vernier mark VM may overlap with the conductive adhesive member AF. When the line patterns are arranged at an equal distance, the degree of misalignment of the conductive adhesive member AF can be easily checked by the number of line patterns overlapping with the conductive adhesive member AF.

[0228] Afterwards, if Fig.11D As shown in Fig. 11C By moving the conductive adhesive member AF in the arrow direction of , the conductive adhesive member AF can be aligned with the pad PD of the display panel DP-C1. According to an embodiment of the present disclosure, the misalignment and misalignment degree of the conductive adhesive member AF can be easily checked by the vernier mark VM, and thus, the position of the conductive adhesive member AF can be easily corrected. As a result, the manufacturing process can be simplified.

[0229] FIG. 12A to FIG. 12C 1 is a plan view showing some processes of a method for manufacturing an electronic device according to an embodiment of the present disclosure. For the purpose of simplicity and convenience of description, FIG. 12A to FIG. 12C Shown with Fig. 10C In the following, we will refer to FIG. 12A to FIG. 12C The embodiments of the present disclosure are described.

[0230] like Fig. 12A As shown in , the conductive adhesive member AF1 may be arranged to meet the vernier mark VM. The top of the conductive adhesive member AF1 may be parallel (eg, substantially parallel) to the bottommost line LP1 of the vernier mark VM. In this embodiment, Fig. 12A The conductive adhesive member AF1 shown in FIG. 1 may be in an aligned state. Therefore, the alignment of the circuit board DC (see FIG. 1 ) may be performed without an additional correction process. Fig. 10D ) is bonded to the conductive bonding member AF1 in a second bonding process.

[0231] like Fig. 12B As shown in , the conductive adhesive member AF2 may overlap a portion of the vernier mark VM. In the present embodiment, the conductive adhesive member AF2 may overlap the first line pattern LLP1 and the second line pattern LLP2 of the lower portion of the vernier mark VM, and the top end of the conductive adhesive member AF2 may be aligned parallel (e.g., substantially parallel) to the third line pattern LLP3. Fig. 12B , the conductive adhesive member AF2 does not overlap with the fourth line pattern LLP4, the fifth line pattern LLP5, the sixth line pattern LLP6, the seventh line pattern LLP7, the eighth line pattern LLP8, the ninth line pattern LLP9, the tenth line pattern LLP10 or the eleventh line pattern LLP11. Fig. 12AWhen the conductive adhesive member AF1 is in an aligned state, the conductive adhesive member AF2 may be in a misaligned state.

[0232] The degree of misalignment of the conductive adhesive member AF2 may be determined by the number of overlapping line patterns and the distance between the line patterns. The degree of misalignment of the conductive adhesive member AF2 may be a first distance Y1 in the second direction D2. When the first distance Y1 is within the designed allowable misalignment range, the process of bonding the circuit board DC may be performed without a process of correcting the position of the conductive adhesive member AF2. Conversely, when the first distance Y1 exceeds the designed allowable misalignment range, a process of correcting the position of the conductive adhesive member AF2 may be performed by moving the conductive adhesive member AF2 in the second direction D2. At this time, the degree of correction may correspond to the first distance Y1 in the second direction D2.

[0233] In some embodiments, Fig. 12C As shown in , when viewed in a plan view, the conductive adhesive member AF3 may overlap with the vernier mark VM in an inclined state relative to the vernier mark VM. At this time, the conductive adhesive member AF3 may overlap with the three line patterns LLP1, LLP2 and LLP3 of the vernier mark VM, and the top of the conductive adhesive member AF3 may not be parallel to the fourth line pattern LLP4. According to an embodiment of the present disclosure, the conductive adhesive member AF3 may be moved a second distance Y2 in the second direction D2, and may be rotated so that the top of the conductive adhesive member AF3 is aligned with the vernier mark VM, and thus, the position of the conductive adhesive member AF3 may be corrected. According to an embodiment of the present disclosure, the degree of misalignment of the conductive adhesive member AF3 can be easily checked by the vernier mark VM, and thus, the correction of the position of the conductive adhesive member AF3 can be performed in real time. As a result, the manufacturing process can be simplified, and the process cost can be reduced.

[0234] Fig.13A is a perspective view showing an electronic device according to an embodiment of the present disclosure. Fig. 13B It is shown Fig.13A An exploded perspective view of a portion of an electronic device. Fig.14A It is shown Fig.13A A plan view of a portion of an electronic device. Fig. 14B 1 is a plan view showing a portion of an electronic device DD-21 according to an embodiment of the present disclosure. For the purpose of simplicity and convenience of description, Fig. 14B Shown with Fig.14A In the following, reference will be made to FIG. 13A to FIG. 14B The embodiments of the present disclosure are described.

[0235] like Fig.13AAs shown in FIG. 1 , the electronic device DD-2 may include a display panel DP, an optical member OPL, and a driving circuit DC-2. The display panel DP and the optical member OPL may correspond to Figure 1A The display panel DP and the optical member OPL shown in FIG. 1 are schematically illustrated in FIG. 1 , and therefore, a repeated description thereof will not be repeated here.

[0236] The driving circuit DC-2 may be mounted on the display panel DP. In more detail, the driving circuit DC-2 may be arranged on a base substrate BS (see FIG. 1 ) of the display panel DP on which the signal lines SL are arranged. Figure 4 ) Fig. 13B , the driving circuit DC- 2 may be arranged to be aligned with the connection area COA of the display panel DP, and thus, the driving circuit DC- 2 may be connected to the pad PD of the display panel DP.

[0237] The driving circuit DC-2 may include an integrated circuit, wherein the integrated circuit includes a plurality of interconnecting lines and at least one driving device connected to the interconnecting lines. The driving circuit DC-2 may be provided in a chip form and may be connected to the display panel DP via an additional coupling member. The coupling member may include an optically transparent adhesive layer, an anisotropic conductive film, a pressure-sensitive adhesive layer, or a solder ball.

[0238] According to an embodiment of the present disclosure, the driving circuit DC-2 may be aligned with the connection area COA by using a vernier mark VM. When viewed in the second direction D2, the driving circuit DC-2 may be arranged to overlap with the vernier mark VM. FIG. 14A to FIG. 14B In the figure, for the purpose of simplicity and convenience of description, the pad PD is shown as being observed through the driving circuit DC-2.

[0239] For example, Fig.14A As shown in , when the width of the driving circuit DC-2 in the second direction D2 is substantially equal to the width of the pad PD in the second direction D2, the driving circuit DC-2 can be aligned on the pad PD in a manner such that the top end of the driving circuit DC-2 meets and is parallel (e.g., substantially parallel) to the bottom end of the vernier mark VM in a plan view. In some embodiments, as Fig. 14B As shown in , when the width W1 of the driving circuit DC-2A in the second direction D2 is greater than the width W2 of the pad PD in the second direction D2, the driving circuit DC-2A can be aligned on the pad PD in such a way that the driving circuit DC-2A overlaps with at least a portion of the cursor mark VM when viewed in a plan view.

[0240] According to an embodiment of the present disclosure, when the driving circuit DC-2 is directly mounted on the display panel DP, the vernier mark VM may be used in the process of aligning the driving circuit DC-2. According to an embodiment of the present disclosure, the driving circuit DC-2 may be aligned with the display panel DP by the naked eye through the vernier mark VM. Therefore, the manufacturing process may be simplified and the process cost may be reduced.

[0241] According to the embodiments of the present disclosure, the alignment between the conductive adhesive member and the pad of the display panel can be checked with the naked eye, and thus, the process can be simplified and the process time can be reduced. In addition, according to the embodiments of the present disclosure, the misalignment of the conductive adhesive member can also be easily checked with the naked eye, and thus, the position of the conductive adhesive member can be corrected in real time (for example, can be corrected synchronously with the positioning of the conductive adhesive member). As a result, the reliability of the electrical connection between the circuit board and the display panel can be improved.

[0242] Although the subject matter of the present disclosure has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure. Therefore, it should be understood that the embodiments described herein are not restrictive but illustrative. Therefore, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

Claims

1. An electronic device, comprising: A display panel, the display panel comprising: a base substrate, the base substrate comprising an active region and a peripheral region adjacent to the active region; a plurality of pixels, the plurality of pixels being located on the active area; a plurality of pads, the plurality of pads being located on the peripheral area and arranged in a first direction; a plurality of signal lines connecting the plurality of pixels to the plurality of pads; and a plurality of vernier marks located on the peripheral area and spaced apart from the plurality of pads and the plurality of signal lines; A circuit board, the circuit board is located on the display panel and includes: basement membrane; and a plurality of leads located on the base film and overlapping the corresponding pads in a plan view; and a conductive adhesive member extending in the first direction and located between the display panel and the circuit board to connect the plurality of pads to the plurality of leads, and wherein each of the plurality of vernier marks includes a plurality of patterns spaced apart from each other, a portion of the conductive adhesive member overlaps with at least one of the plurality of patterns, Here, in the plan view, in a second direction intersecting the first direction, a width from a lowermost pattern to an uppermost pattern among the plurality of patterns is 100 μm or more and 450 μm or less.

2. The electronic device according to claim 1, wherein: An upper end of the conductive adhesive member is aligned with any one of the plurality of patterns overlapping the conductive adhesive member in the first direction.

3. The electronic device according to claim 1, wherein: Each of the plurality of patterns has a line shape extending in the first direction and is spaced apart from each other in the second direction.

4. The electronic device according to claim 3, wherein: In the second direction, each of the plurality of patterns has a width of 1 μm or more and 3 μm or less.

5. The electronic device according to claim 3, wherein: In the first direction, a separation distance between adjacent ones of the plurality of patterns is 10 μm or more and 50 μm or less.

6. The electronic device according to claim 1, wherein: Each of the plurality of cursor marks further comprises: a horizontal pattern extending in the first direction, having a smaller width than the plurality of patterns in the first direction, and disposed between adjacent ones of the plurality of patterns, and A vertical pattern extending in the second direction and arranged between an adjacent one of the patterns and the horizontal pattern.

7. The electronic device according to claim 1, wherein: Each of the plurality of pixels comprises: A thin film transistor, the thin film transistor comprising a control electrode, a semiconductor pattern, an input electrode and an output electrode; and a light emitting element connected to the thin film transistor and including a first electrode, a second electrode, and an emission layer located between the first electrode and the second electrode, and The plurality of patterns are arranged on the same layer as any one of the control electrode, the semiconductor pattern, the input electrode, the output electrode and the first electrode.

8. The electronic device according to claim 7, wherein: The plurality of patterns have the same material as any one of the control electrode, the semiconductor pattern, the input electrode, the output electrode, and the first electrode.

9. The electronic device according to claim 1, wherein: Any one of the plurality of patterns overlaps with the conductive adhesive member, and An area of ​​a portion of the plurality of patterns overlapping the conductive adhesive member is smaller than an area of ​​a portion of the plurality of patterns spaced apart from the conductive adhesive member.

10. The electronic device according to claim 1, wherein: The number of patterns among the plurality of patterns overlapping with the conductive adhesive member is less than the number of patterns among the plurality of patterns not overlapping with the conductive adhesive member.

11. The electronic device according to claim 1, wherein: The display panel further includes: a panel alignment mark spaced apart from the plurality of pads and overlapping the conductive adhesive member in the plan view, Wherein, the circuit board also includes: a board alignment mark overlapping the conductive adhesive member in the plan view and corresponding to the panel alignment mark, and Wherein, when viewed in the second direction, one end of each of the plurality of patterns adjacent to the plurality of pads is aligned with one end of the panel alignment mark.

12. The electronic device according to claim 1, wherein: In the second direction, a distance from a top end of the pad to a top end of the conductive adhesive member is less than 100 μm.

13. The electronic device according to claim 1, wherein: At least a portion of the plurality of pads are inclined in a first oblique direction relative to the first direction and the second direction in the plan view, and the remaining pads of the plurality of pads are inclined in a second oblique direction intersecting the first oblique direction in the plan view.

14. The electronic device according to claim 1, wherein: The circuit board overlaps a portion of each of the plurality of patterns and exposes another portion of each of the plurality of patterns.

15. The electronic device according to claim 1, wherein: Each of the plurality of patterns extends in the first direction and is spaced apart from each other in the second direction, Each of the plurality of vernier marks further includes a plurality of vertical patterns extending in the second direction and spaced apart from each other in the first direction, When viewed in the plan view, the plurality of patterns and the plurality of vertical patterns have a grid shape.

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