Display substrate and display device

Abstract

The invention discloses a display substrate and a display device, and the display substrate comprises a substrate which comprises a display area and a peripheral area, and the peripheral area comprises a first signal access area and a second signal access area which are located at one side of the display area; the plurality of first contact pads and the second contact pads are located in the first signal access area and are configured to be bound with the driving chip, and the plurality of first contact pads are connected with the data line; the plurality of third contact pads are located in the second signal access area and are configured to be bound with the circuit board; the plurality of connecting lines are used for connecting the plurality of second contact pads and the plurality of third contact pads, and at least one connecting line in the plurality of connecting lines comprises at least two conductive layers which are in direct contact; and the protective layer is positioned on one side, far away from the substrate, of the plurality of connecting lines, covers the surfaces and the side surfaces, far away from the substrate, of the plurality of connecting lines, and is used for preventing the plurality of connecting lines from being eroded by an etching solution for preparing an anode layer of the display substrate. According to the display substrate, the display effect is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diode display devices have the advantages of high contrast, wide viewing angle, and low power consumption, and are increasingly used in products such as smartphones. However, in actual applications, there are problems with dark spots.

[0003] How to solve the dark spot problem of organic light emitting diode display devices and improve the display effect of the display devices has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] In order to solve at least one of the above problems, a first embodiment of the present invention provides a display substrate, comprising:

[0005] A substrate, comprising a display area and a peripheral area at least partially surrounding the display area, wherein the peripheral area comprises a signal access area located at one side of the display area, and the signal access area comprises a first signal access area and a second signal access area located at a side of the first signal access area away from the display area;

[0006] A plurality of sub-pixels are located on one side of the substrate and in the display area;

[0007] a plurality of data lines, located in the display area and extending to the signal access area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels;

[0008] a plurality of first contact pads, located in the first signal access area and connected to the plurality of data lines;

[0009] a plurality of second contact pads, located in the first signal access area and located on a side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound to a driving chip;

[0010] a plurality of third contact pads, located in the second signal access area and configured to be bound to the circuit board;

[0011] a plurality of connection lines, located between the plurality of second contact pads and the plurality of third contact pads and connecting the plurality of second contact pads and the plurality of third contact pads, at least one connection line among the plurality of connection lines comprises at least two conductive layers, and the at least two conductive layers are in direct contact;

[0012] The protective layer is located on the side of the multiple connecting lines away from the substrate, and the protective layer covers the surface and side of the multiple connecting lines away from the substrate to prevent the multiple connecting lines from being corroded by the etching solution for preparing the anode layer of the display substrate.

[0013] For example, in the display substrate provided in some embodiments of the present application, the at least two conductive layers include a first conductive layer and a second conductive layer sequentially stacked on the substrate, and at least one of the at least two conductive layers contains aluminum and / or titanium;

[0014] The second conductive layer covers a surface and a side surface of the first conductive layer away from the substrate, and the protective layer covers a surface and a side surface of the second conductive layer away from the substrate.

[0015] For example, in the display substrate provided in some embodiments of the present application, the surface and side of the first conductive layer away from the substrate are in direct contact with the second conductive layer, and the protective layer is in direct contact with the surface and side of the second conductive layer away from the substrate.

[0016] For example, in the display substrate provided in some embodiments of the present application, in a direction perpendicular to the substrate, the sum of the thicknesses of the at least two conductive layers is greater than or equal to 9000 angstroms and less than or equal to 22000 angstroms.

[0017] For example, in the display substrate provided in some embodiments of the present application, the display substrate includes a circuit structure layer and a light-emitting structure layer stacked on the substrate, the circuit structure layer includes a first gate insulation layer, a first gate metal layer, a second gate insulation layer, a second gate metal layer, an interlayer insulation layer, a first source-drain metal layer, a passivation layer, a first flat layer, a second source-drain metal layer, a second flat layer, a third source-drain metal layer, a third flat layer and an isolation layer stacked in sequence on the substrate; the light-emitting structure layer includes an anode layer.

[0018] For example, in the display substrate provided in some embodiments of the present application, the first conductive layer and the second source-drain metal layer are located on the same layer, the second conductive layer and the third source-drain metal layer are located on the same layer, and the protective layer and the anode layer or the isolation layer are located on the same layer.

[0019] For example, in the display substrate provided in some embodiments of the present application, one of the at least two conductive layers is provided at the same layer as one of the first gate metal layer, the second gate metal layer and the first source-drain metal layer;

[0020] Another conductive layer of the at least two conductive layers is disposed on the same layer as one of the second source-drain metal layer and the third source-drain metal layer;

[0021] The protective layer is arranged on the same layer as the anode layer and is made of the same material.

[0022] For example, in the display substrate provided in some embodiments of the present application, the at least two conductive layers include a third conductive layer, a fourth conductive layer and a fifth conductive layer, the third conductive layer and the first gate metal layer are located on the same layer, the fourth conductive layer and the second gate metal layer are located on the same layer, and the fifth conductive layer and the first source-drain metal layer are located on the same layer;

[0023] The protective layer is arranged on the same layer as the passivation layer, the isolation layer and one of the anode layers and is made of the same material.

[0024] For example, in the display substrate provided in some embodiments of the present application, the materials of the first gate metal layer and the second gate metal layer are both metal molybdenum, and the material of the first source-drain metal layer is a titanium / aluminum / titanium three-layer stack.

[0025] A second embodiment of the present invention provides a display device, comprising the display substrate as described in the first embodiment, a driving chip, and a flexible circuit board.

[0026] The beneficial effects of the present invention are as follows:

[0027] In view of the existing problems, the present invention develops a display substrate and a display device. Considering the risk of connection lines arranged in the signal access area being exposed to the anodic etching solution, a protective layer in direct contact with the connection lines is arranged on the side of the connection lines away from the substrate to avoid the anodic etching solution from corroding the connection lines. In particular, the protective layer covers the surface and side of the connection lines away from the substrate, thereby avoiding poor display caused by metal particles precipitated during the corrosion process entering the display area. This can remedy the problems existing in the prior art, effectively improve the display effect of the display substrate, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1A is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0030] Figure 1B is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0031] Figure 2 for Figure 1AThe schematic cross-sectional view of the display region of the display substrate taken along line aa' is shown;

[0032] Figure 3 A schematic top view of a signal access area of ​​a display substrate according to an embodiment of the present disclosure;

[0033] Figure 4 It is a structural schematic diagram of a signal access area of ​​a display substrate according to an embodiment of the present disclosure;

[0034] Figure 5 for Figure 4 The schematic cross-sectional view of the signal access area of ​​the display substrate taken along the FF line is shown;

[0035] Figure 6 It is a structural schematic diagram of a signal access area of ​​a display substrate according to an embodiment of the present disclosure;

[0036] Figure 7 It is a structural schematic diagram of a signal access area of ​​a display substrate according to an embodiment of the present disclosure;

[0037] Figure 8 The present invention is a schematic structural diagram of a signal access area of ​​a display substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to more clearly illustrate the present invention, the present invention is further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present invention.

[0039] It should be noted that the terms “on…”, “formed on…” and “disposed on…” described herein may indicate that a layer is directly formed or disposed on another layer, or may indicate that a layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers. In this article, unless otherwise specified, the terms “disposed on the same layer” and “located on the same layer” used mean that two layers, parts, components, elements or parts can be formed by the same composition process, and that the two layers, parts, components, elements or parts are generally formed of the same material. In this article, unless otherwise specified, the expression “composition process” generally includes steps such as coating, exposure, development, etching and stripping of photoresist. The expression “one-time composition process” means a process of forming patterned layers, parts, components, etc. using a mask.

[0040] Figure 1A A schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1B Another schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1A and Figure 1B All of the diagrams are plan views of the display substrate before the bending process is performed.

[0041] In some examples, such as Figure 1A and Figure 1B As shown, the display substrate may include: a display area AA, and a peripheral area BB surrounding the periphery of the display area AA. For example, the peripheral area BB may include: a first frame area B1 located on one side of the display area AA, and frame areas located on other sides of the display area AA (for example, may include a second frame area B2, a third frame area B3, and a fourth frame area B4). The first frame area B1 may be, for example, a lower frame of the display panel, the second frame area B2 may be, for example, an upper frame of the display panel, the third frame area B3 may be, for example, a left frame of the display panel, and the fourth frame area B4 may be, for example, a right frame of the display panel.

[0042] In some examples, such as Figure 1A and Figure 1B As shown, the display area AA may include at least: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions, and a sub-pixel PX may be provided in each sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signal may include a scan signal and a light emitting control signal, or may include a scan signal, or may include a scan signal, a reset control signal, and a light emitting control signal.

[0043] In some examples, such as Figure 1A and Figure 1B As shown, the first direction X may be the extension direction (e.g., row direction) of the gate lines GL in the display area AA, and the second direction Y may be the extension direction (e.g., column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0044] Figure 2 for Figure 1A The schematic cross-sectional view shown is taken along line aa' in the display area of ​​the display substrate. Figure 2The structure of a sub-pixel in the display area is used as an example for illustration. In this example, the same type of multiple transistors in the pixel circuit of each sub-pixel of the display substrate is used for illustration. For example, multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or all use oxide thin-film transistors. In other examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. In addition, this example takes the display panel integrating a mutual capacitance touch structure to form a flexible multi-layer covered surface (Flexible Multi-Layer On Cell, FMLOC for short) structure as an example for illustration.

[0045] In some examples, such as Figure 2 As shown, in the direction perpendicular to the display panel, the display area of ​​the display panel may include: a substrate 100, and a circuit structure layer 20, a light emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50 and a color filter layer 60 sequentially arranged on the substrate 100. Among them, the display structure layer may include at least a circuit structure layer 20 and a light emitting structure layer 30. The circuit structure layer 20 may include at least: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 30 may include at least: a light emitting element of a plurality of sub-pixels.

[0046] In some examples, Figure 2In the figure, a thin film transistor 21 and a capacitor 22 included in each sub-pixel are used as an example for illustration. In some examples, the circuit structure layer 20 in the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the circuit structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be provided between the semiconductor layer and the first gate metal layer, a second gate insulating layer 202 may be provided between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 203 may be provided between the second gate metal layer and the first source-drain metal layer, a passivation layer 204 and a first flat layer 205 may be provided between the first source-drain metal layer and the second source-drain metal layer, a second flat layer 206 may be provided between the second source-drain metal layer and the third source-drain metal layer, a third flat layer 207 may be provided on the side of the third source-drain metal layer away from the substrate 100, and an isolation layer 208 between the third flat layer 207 and the first electrode 301 of the light emitting structure layer 30. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, the passivation layer 204 and the isolation layer 208 may be inorganic insulating layers, and the first flat layer 205, the second flat layer 206 and the third flat layer 207 may be organic insulating layers. However, this embodiment is not limited to this. In some other examples, the passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the first planarization layer may be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0047] In some examples, such as Figure 2As shown, the semiconductor layer in the display area may include at least: an active layer 210 of a thin film transistor 21. The active layer 210 of the thin film transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a gate electrode 213 of the thin film transistor 21, and a first electrode plate 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 100 may cover the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 100. The second gate metal layer may include at least: a second electrode plate 222 of the capacitor 22. The orthographic projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 100 may at least partially overlap, for example, the two may overlap. The first source-drain metal layer may include at least: a source electrode 211 and a drain electrode 212 of the thin film transistor 21. The interlayer insulating layer 203 may be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202 and the first gate insulating layer 201 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 203, the second gate insulating layer 202 and the first gate insulating layer 201 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least: a first transfer electrode 231. The first transfer electrode 231 can be electrically connected to the drain 212 of the thin film transistor 21 of the pixel circuit through the third pixel via hole opened in the passivation layer 204 and the first flat layer 205. The third source-drain metal layer can include at least: a second transfer electrode 232. The second transfer electrode 232 can be electrically connected to the first transfer electrode 231 located in the second source-drain metal layer through the fourth pixel via hole opened in the second flat layer 206. The first transfer electrode 231 can be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through the fifth pixel via hole opened in the third flat layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element can be realized through the first transfer electrode 231 and the second transfer electrode 232.

[0048] In some examples, the gate line of the display area may be located at the first gate metal layer or the second gate metal layer, the data line of the display area may be located at the second source-drain metal layer or the third source-drain metal layer, and the high-potential power line of the display area may be located at least one of the second source-drain metal layer and the third source-drain metal layer. This embodiment is not limited to this. The circuit structure layer of this example includes three source-drain metal layers, which can avoid arranging more wiring in a single source-drain metal layer, thereby facilitating the realization of a narrow frame structure.

[0049] In some examples, such as Figure 2 As shown, the light emitting structure layer 30 may include: a pixel definition layer 304 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 301, an organic light emitting layer 302 and a second electrode 303. The first electrode 301 of the light emitting element may be an anode, and the first electrode 301 may be disposed on the third flat layer 207 and electrically connected to the second transfer electrode 232 through a fifth pixel via hole provided in the third flat layer 207, or the first electrode 301 may be disposed on the isolation layer 208 and electrically connected to the second transfer electrode 232 through a via hole provided in the isolation layer 208. The pixel definition layer 304 is disposed on the first electrode 301 and the isolation layer 208, and the pixel definition layer 304 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light emitting layer 302 may be disposed in one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light emitting layer 302 and connected to the organic light emitting layer 302. The organic light emitting layer 302 can emit light of corresponding colors under the driving of the first electrode 301 and the second electrode 303 .

[0050] In some examples, such as Figure 2As shown, in the direction perpendicular to the substrate, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked. Among them, the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 may be arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or it may be a polymer resin, etc. to flatten the surface of the display panel, and can relieve the stress of the first encapsulation layer 401 and the third encapsulation layer 403, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0051] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0052] In some examples, such as Figure 2As shown, in a direction perpendicular to the substrate, the touch structure layer 50 of the display area may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512 arranged in sequence. Among them, the touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, for example, SiNx layers. For example, the first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure connected to each other. The second touch conductive layer 512 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias provided in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes and a plurality of second connecting portions, and the second touch electrodes and the second connecting portions may be an integrated structure connected to each other; the second touch conductive layer may include a plurality of first connecting portions, and the first connecting portions may be connected to adjacent first touch electrodes through vias provided in the touch interlayer insulating layer. In some examples, the first touch electrode may be a drive (Tx) electrode, and the second touch electrode may be a sense (Rx) electrode. Alternatively, the first touch electrode may be a sense (Rx) electrode, and the second touch electrode may be a drive (Tx) electrode. This embodiment is not limited to this.

[0053] In some examples, such as Figure 2 As shown, in a direction perpendicular to the substrate, the color filter layer (Color filter On Encapsulation, COE) 60 may include: an insulating layer 601, a color filter layer and an OC film (overcoat) 602 arranged in sequence, wherein the color filter layer includes a black matrix 610 and a color filter unit 611 arranged between the black matrix 610, and the color filter unit 611 may be, for example, a red filter unit, a green filter unit or a blue filter unit.

[0054] It is worth noting that this embodiment is only used to illustrate the specific implementation method of the present application. The present application does not specifically limit the structure of the display substrate. Those skilled in the art should understand that the required structure and film layer should be selected according to actual application requirements, and no further details will be given here.

[0055] In some examples, such as Figure 1A As shown, the first border area B1 of the display panel may include: a fan-out wiring area B11 and a signal access area B12 which are sequentially arranged in a direction away from the display area AA. Figure 1A In the figure, only a few routing lines in the first frame area are shown for illustration. This example does not limit the number of routing lines in the first frame area.

[0056] In some examples, such as Figure 1A As shown, the fan-out routing area B11 can be connected between the display area AA and the signal access area B12. The fan-out routing area B11 can be provided with at least a plurality of data fan-out lines 42. The plurality of data fan-out lines 42 can be electrically connected to the plurality of data lines DL in the display area AA. For example, the plurality of data fan-out lines 42 can be electrically connected to the plurality of data lines DL in a one-to-one correspondence. The plurality of data fan-out lines 42 can extend to the signal access area B12 in a fan-out routing manner. The plurality of data fan-out lines 42 and the plurality of data lines DL can be located in different film layers, and the data fan-out lines 42 can be connected to the data lines DL through vias opened in the insulating layer.

[0057] In some examples, such as Figure 1A As shown, the signal access area B12 may include at least one first signal access area B121. This example is illustrated and described by taking one first signal access area as an example. In other examples, the display panel is a large-size panel, and the display panel may include multiple first signal access areas, and the multiple first signal access areas may be arranged in sequence along the first direction X.

[0058] In some examples, such as Figure 1A As shown, the first signal access area B121 can also be referred to as a driver chip (IC) setting area. The first signal access area B121 can be provided with a plurality of first contact pads 31 and a plurality of second contact pads 32, and the plurality of first contact pads 31 and the plurality of second contact pads 32 can be configured to be bound and connected to at least one driver chip. The driver chip can be configured to generate a driving signal required for driving a sub-pixel, and provide the driving signal to the sub-pixel PX of the display area AA. For example, the driving signal can be a data signal for driving a sub-pixel. In some examples, the driver chip can be a central processing unit, a digital signal processor, a system chip (SoC), etc. For example, the driver chip can also include hardware circuits and computer executable codes, etc. The hardware circuit can include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit can also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0059] In some examples, such as Figure 1AAs shown, the signal access area B12 may be provided with at least a plurality of data connection lines 101, and the plurality of data connection lines 101 may be electrically connected to the plurality of data fan-out lines 42 of the fan-out routing area B11, for example, in a one-to-one electrical connection. For example, the data connection line 101 and the connected data fan-out line 42 may be an integrated structure connected to each other. That is, the plurality of data connection lines 101 are electrically connected to the plurality of data lines DL through the plurality of data fan-out lines 42, for example, in a one-to-one electrical connection. The plurality of data connection lines 101 may extend into the first signal access area B121 and be electrically connected to the plurality of first contact pads 31 in the first signal access area B121. For example, the plurality of data connection lines 101 may be electrically connected to the plurality of first contact pads 31 in a one-to-one electrical connection, or a data connection line 101 may be electrically connected to at least one first contact pad 31. The data connection line 101 and the data fan-out line 42 may transmit the data signal provided by the driver chip to the data line DL of the display area.

[0060] In some examples, such as Figure 1B As shown, the first frame area B1 of the display substrate may include: a fan-out wiring area B11, a bending area B13 and a signal access area B12 which are sequentially arranged in a direction away from the display area AA. Figure 1B In the figure, only a few routing lines in the first frame area are shown for illustration. This example does not limit the number of routing lines in the first frame area.

[0061] In some examples, such as Figure 1B As shown, the bending area B13 can be connected between the fan-out routing area B11 and the signal access area B12, and can be configured to bend the signal access area B12 to the back of the display area AA. The bending area B13 can be provided with at least a plurality of data bending connection lines 43. One end of the data bending connection line 43 can be connected to the data fan-out line 42 in the fan-out routing area B11, and the other end can be connected to the data connection line 101 in the signal access area B12. The multiple data bending connection lines 43 can be a same-layer structure, for example, located in the first source and drain metal layer or the second source and drain metal layer. The remaining structure of the first border area B1 of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0062] like Figure 1A and Figure 1B As shown, the signal access area B12 may also include a second signal access area B122, and a plurality of third contact pads 33 are provided in the second signal access area B122, and the plurality of third contact pads 33 are used to bind with the flexible circuit board. Figure 2As shown, the multiple first contact pads 31 and the second contact pads 32 of the first signal access area B121 can be arranged in multiple rows (for example, three rows of first contact pads 31 and one row of second contact pads 32). The multiple first contact pads 31 included in each row of first contact pads 31 can be arranged in sequence along the first direction X, and the multiple second contact pads 32 included in each row of second contact pads 32 can be arranged in sequence along the first direction X. Three rows of first contact pads 31 and one row of second contact pads 32 can be arranged in sequence along the second direction Y. The first contact pads 31 and the second contact pads 32 of two adjacent rows can be staggered in the first direction X. The multiple second contact pads 32 of the first signal access area B121 and the multiple third contact pads 33 of the second signal access area B122 are electrically connected through connecting wires 34.

[0063] like Figure 3 As shown, the signal access area position on the display substrate of the organic light emitting diode display device, in the signal access area B12, including multiple second contact pads 32, multiple third contact pads 33 and connecting lines 34 located on the substrate. During the preparation process, in order to prevent the signal access area position from absorbing water and causing corrosion, the flat layer at the signal access area position is etched away. However, in actual applications, it was found that the display device had dark spots.

[0064] In view of the existing dark spot problem, the inventors found through research and experiments that the etched portion of the flat layer exposes the connecting wire 34, causing the etching solution used in the subsequent display device anode layer preparation process to corrode the exposed connecting wire 34. Specifically, in the process of etching to form the anode, the metal Al of the connecting wire and the AgNO in the etching solution are etched. 3 A substitution reaction occurs to precipitate Ag, and the specific formula is as follows:

[0065] Al+3AgNO 3 =Al(NO 3 ) 3 +3Ag

[0066] The precipitated Ag particles enter the display area of ​​the display device, resulting in the formation of dark spots, which affects the display effect of the display device.

[0067] In view of the above problems and the causes thereof, an embodiment of the present invention provides a display substrate, comprising:

[0068] A substrate, comprising a display area and a peripheral area at least partially surrounding the display area, wherein the peripheral area comprises a signal access area located at one side of the display area, and the signal access area comprises a first signal access area and a second signal access area located at a side of the first signal access area away from the display area;

[0069] A plurality of sub-pixels are located on one side of the substrate and in the display area;

[0070] a plurality of data lines, located in the display area and extending to the signal access area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels;

[0071] a plurality of first contact pads, located in the first signal access area and connected to the plurality of data lines;

[0072] a plurality of second contact pads, located in the first signal access area and located on a side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound to a driving chip;

[0073] a plurality of third contact pads, located in the second signal access area and configured to be bound to the circuit board;

[0074] a plurality of connection lines, located between the plurality of second contact pads and the plurality of third contact pads and connecting the plurality of second contact pads and the plurality of third contact pads, at least one connection line among the plurality of connection lines comprises at least two conductive layers, and the at least two conductive layers are in direct contact;

[0075] The protective layer is located on the side of the multiple connecting lines away from the substrate, and the protective layer covers the surface and side of the multiple connecting lines away from the substrate to prevent the multiple connecting lines from being corroded by the etching solution for preparing the anode layer of the display substrate.

[0076] In this embodiment, if Figure 1A , Figure 1B , Figure 2 , Figure 4 and Figure 5As shown, the signal access area includes a first signal access area B121 bound to the driving chip, and a second signal access area B122 bound to a circuit board, such as a flexible circuit board. Among them, the first signal access area B121 includes a plurality of first contact pads 31 electrically connected to a plurality of data lines DL, and the plurality of data lines DL can be configured to provide data signals to a plurality of sub-pixels PX, for example, the data lines DL are electrically connected to the first contact pads 31 in a one-to-one correspondence; the first signal access area B121 also includes a plurality of second contact pads 32, and the plurality of first contact pads 31 and the plurality of second contact pads 32 are all bound to the driving chip; the second signal access area B122 includes a plurality of third contact pads 33. The second contact pads 32 and the third contact pads 33 are connected by a connecting line 34, that is, the signal provided by the circuit board is transmitted to the plurality of second contact pads 32 through the third contact pads 33 and the connecting line 34, and the signal input from the circuit board is converted by the driving chip and transmitted to the plurality of sub-pixels PX in the display area through the plurality of first contact pads 31. It is worth noting that each connection line 34 is connected to at least one second contact pad 32 and at least one third contact pad 33, and the plurality of connection lines 34 include a first connection line for transmitting a data signal and a second connection line for transmitting a power signal. The first connection line is connected to the second contact pad 32 and the third contact pad 33 in a one-to-one correspondence; one end of the second connection line can be connected to multiple second contact pads 32 at the same time, and the other end can be connected to multiple third contact pads 33 at the same time. The line width of the second connection line can be greater than or equal to the line width of the first connection line, thereby achieving a line width that is more suitable for stable transmission of electrical signals.

[0077] Considering Figure 3 The dark spot problem in the display substrate shown in FIG. Figure 4 FIG. 3 is a schematic diagram showing that the second contact pad 32 is electrically connected to the third contact pad 33 via a connecting line 34. Figure 5 Shown Figure 4 Cross-sectional view at two FF positions.

[0078] In the signal access area, a film layer is provided on the substrate 100, such as a first gate insulating layer 201, and a third flat layer 207 is provided on the first gate insulating layer 201. The third flat layer 207 includes an opening 2071. In the opening 2071, the connection line 34 is provided on the first gate insulating layer 201. To ensure the signal transmission capability of the connection line 34, the connection line 34 includes directly contacting at least two conductive layers, such as a first conductive layer 341 and a second conductive layer 342. The connection line 34 is at risk of being exposed to the anodic etching solution. By providing a protective layer 80 on the connection line 34 to prevent the anodic etching solution from corroding the connection line, that is, providing a protective layer 80 on a side of the connection line 34 away from the substrate 100, the protective layer 80 covers a surface 3421 and a side surface 3422 of the connection line 34 away from the substrate 100, thereby preventing the anodic etching solution from contacting the connection line 34, and further preventing the poor display caused by the metal particles precipitated during the corrosion process entering the display area, which can effectively improve the display effect of the display substrate and improve the user experience.

[0079] It is worth noting that this embodiment is only used to illustrate the specific implementation of the present application. Those skilled in the art should select an appropriate film layer according to actual application requirements, which will not be elaborated here.

[0080] In an optional embodiment, if Figure 5 As shown, the at least two conductive layers include a first conductive layer 341 and a second conductive layer 342 stacked in sequence on the substrate, and at least one of the at least two conductive layers contains aluminum and / or titanium; the second conductive layer 342 covers the surface 3411 and the side 3412 of the first conductive layer 341 away from the substrate 100, and the protective layer 80 covers the surface 3421 and the side 3422 of the second conductive layer 342 away from the substrate 100.

[0081] In this embodiment, if Figure 5As shown, the connecting line 34 includes a first conductive layer 341 and a second conductive layer 342 stacked on the substrate 100, the first conductive layer 341 and the second conductive layer 342 are in direct contact, the first conductive layer 341 includes a surface 3411 parallel to the substrate 100, and side surfaces 3412 located on both sides and forming a certain angle with the substrate 100, and the second conductive layer 342 includes a surface 3421 parallel to the substrate 100, and side surfaces 3422 located on both sides and forming a certain angle with the substrate 100. The second conductive layer 342 covers the first conductive layer 341, and the second conductive layer 342 covers the surfaces 3411 and 3412 of the first conductive layer 341, that is, the second conductive layer 342 covers the first conductive layer 341, that is, the surface 3411 and the side 3412 of the first conductive layer 341 away from the substrate 100 are in direct contact with the second conductive layer 342; similarly, the protective layer 80 covers the connecting wire 34, that is, the protective layer 80 covers the connecting wire 34, for example, the protective layer 80 covers the surfaces 3421 and 3422 of the second conductive layer 342, that is, the protective layer 80 covers the second conductive layer 342, that is, the protective layer 80 is in direct contact with the surface 3421 and the side 3422 of the second conductive layer 342 away from the substrate 100, so as to avoid the anode etching solution used in the subsequent production of the anode from contacting the connecting wire 34 and undergoing a replacement reaction, thereby avoiding the aluminum ions in the connecting wire from undergoing a replacement reaction with the silver ions in the anode etching solution, resulting in the precipitation of metal particles into the display area and causing dark spots.

[0082] It is worth mentioning that those skilled in the art should understand that "parallel to the substrate" in this embodiment refers to a situation in which the semiconductor is parallel to the substrate under semiconductor manufacturing conditions, for example, the angle formed with the substrate is above -10° and below 10°.

[0083] Considering the impedance requirements for the connecting wires, if the impedance is too large, it will affect the driving ability of the driver chip. In an optional embodiment, in a direction perpendicular to the substrate, the thickness of the connecting wires is greater than or equal to 9000 angstroms and less than or equal to 22000 angstroms.

[0084] In this embodiment, based on the impedance requirements for the connecting line, specific requirements are put forward for the thickness of the connecting line including at least two conductive layers, and the sum of the thicknesses of the at least two conductive layers is greater than or equal to 9000 angstroms and less than or equal to 22000 angstroms, so that the at least two conductive layers of the connecting line are connected in parallel to reduce the impedance of the connecting line.

[0085] like Figure 2As shown, the display substrate of this embodiment includes a circuit structure layer and a light-emitting structure layer stacked on the substrate, the circuit structure layer includes a first gate insulation layer 201, a first gate metal layer, a second gate insulation layer 202, a second gate metal layer, an interlayer insulation layer 203, a first source-drain metal layer, a passivation layer 204, a first flat layer 205, a second source-drain metal layer, a second flat layer 206, a third source-drain metal layer, a third flat layer 207 and an isolation layer 208 stacked in sequence on the substrate; the light-emitting structure layer includes an anode layer.

[0086] It is worth noting that this embodiment is only used to illustrate the specific implementation of the present application, and the present application does not specifically limit the structure of the actual substrate. Figure 2 The substrate shown shows more film layers, or there are more than Figure 2 The substrate shown has fewer film layers. For example, in an optional embodiment, the passivation layer 204 between the first source-drain metal layer and the first planar layer can be removed. For example, in another optional embodiment, the isolation layer 208 can be removed; for example, in another optional embodiment, the third source-drain metal layer and the third planar layer 207 can be removed; for example, in another optional embodiment, the second source-drain metal layer, the second planar layer 206, the third source-drain metal layer and the third planar layer 207 can be removed. Those skilled in the art should understand that selecting an appropriate film layer structure according to actual application requirements is within the scope of protection of this application and will not be repeated here.

[0087] based on Figure 2 The display substrate shown in the figure includes a plurality of metal layers, the metal layers mainly include a gate metal layer and a source-drain metal layer. In this embodiment, the circuit structure layer includes at least one gate metal layer and at least one source-drain metal layer, for example Figure 2 The first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer are shown. The material used for the gate metal layer of this embodiment is metal molybdenum, and the thickness of the gate metal layer is greater than or equal to 2000 angstroms and less than or equal to 6000 angstroms; the material used for the source-drain metal layer is titanium / aluminum / titanium stack, and the thickness of the source-drain metal layer is greater than or equal to 5000 angstroms and less than or equal to 10000 angstroms.

[0088] In this embodiment, the display substrate includes multiple metal layers, and the connecting wire includes at least two conductive layers, each conductive layer is arranged on the same layer as one of the multiple metal layers, that is, the existing structure of the display substrate is used to form the connecting wires while forming each conductive layer in the circuit structure layer, thereby forming the connecting wires connecting the second contact pad connected to the driver chip and the third contact pad connected to the flexible circuit board in the signal access area. At the same time, the circuit structure layer also includes an inorganic layer capable of blocking the anodic etching liquid, such as a passivation layer. When the connecting wire is located on the side of the passivation layer close to the substrate, the protective layer is the passivation layer; or, the circuit structure layer also includes an inorganic layer capable of blocking the anodic etching liquid, such as an isolation layer. When the connecting wire is located on the side of the isolation layer close to the substrate, the protective layer is the isolation layer; or, in the process of making the anode, the connecting wire is covered with a protective layer arranged on the same layer as the anode, and the anodic etching liquid is blocked by the photoresist covered thereon.

[0089] In an optional embodiment, if Figure 6 As shown, the at least two conductive layers include a first conductive layer 341 and a second conductive layer 342 which are sequentially stacked on the substrate 100 and in direct contact, wherein the first conductive layer 341 and the second source-drain metal layer are located on the same layer, the second conductive layer 342 and the third source-drain metal layer are located on the same layer, and the protective layer 80 and the anode layer or the isolation layer are located on the same layer.

[0090] In this embodiment, the second contact pad and the third contact pad are connected by a connection line including two conductive layers, that is, the second contact pad and the third contact pad are connected by a connection line including a first conductive layer and a second conductive layer to transmit a signal.

[0091] In one example of this embodiment, Figure 6 and Figure 2 As shown, in the signal access area, a first gate insulating layer 201, a first conductive layer 341, a second conductive layer 342 and a protective layer 80 are stacked on the substrate 100, wherein the first conductive layer 341 is arranged in the same layer as the first transfer electrode 231 of the second source-drain metal layer, the second conductive layer 342 is arranged in the same layer as the second transfer electrode 232 of the third source-drain metal layer, and the protective layer 80 is arranged in the same layer as the isolation layer 208. In this embodiment, the second conductive layer 342 is in direct contact with the first conductive layer 341, the second conductive layer 342 covers the surface and side of the first conductive layer 341 away from the substrate 100, and the second conductive layer 342 covers the first conductive layer 341; at the same time, the protective layer 80 covers the surface and side of the second conductive layer 342 away from the substrate 100, and the protective layer 80 covers the second conductive layer 342, that is, the protective layer 80 covers the connecting wire 34 to prevent the anodic etching solution from corroding the connecting wire, thereby effectively avoiding dark spots and improving the display effect of the display substrate.

[0092] In another example of this embodiment, Figure 7 and Figure 2 As shown, in the signal access area, a first gate insulating layer 201, a first conductive layer 341, a second conductive layer 342 and a protective layer 80 are stacked on the substrate 100, wherein the first conductive layer 341 is arranged on the same layer as the first transfer electrode 231 of the second source-drain metal layer, the second conductive layer 342 is arranged on the same layer as the second transfer electrode 232 of the third source-drain metal layer, and the protective layer 80 is arranged on the same layer as the first electrode 301, that is, the protective layer 80 is arranged on the same layer as the anode. In this embodiment, the second conductive layer 342 is in direct contact with the first conductive layer 341, and the second conductive layer 342 covers the surface and side of the first conductive layer 341 away from the substrate 100, and the second conductive layer 342 covers the first conductive layer 341; at the same time, the protective layer 80 covers the surface and side of the second conductive layer 342 away from the substrate 100, and the protective layer 80 covers the second conductive layer 342, as shown in FIG. Figure 7 As shown, considering the insulation requirements between adjacent connecting wires, the protective layer 80 is disconnected to ensure that adjacent connecting wires are insulated from each other. In this example, the photoresist covering the protective layer during the preparation of the anode prevents the anode etching solution from corroding the connecting wires, thereby effectively avoiding dark spots and improving the display effect of the display substrate.

[0093] In an optional embodiment, one of the at least two conductive layers is provided at the same layer as one of the first gate metal layer, the second gate metal layer and the first source-drain metal layer;

[0094] Another conductive layer of the at least two conductive layers is disposed on the same layer as one of the second source-drain metal layer and the third source-drain metal layer;

[0095] The protective layer is arranged on the same layer as the anode layer and is made of the same material.

[0096] The connection lines and protective layers formed in this embodiment are as follows Figure 7 The structure shown in FIG. 1 , the connecting line includes a first conductive layer and a second conductive layer. Figure 2As shown, in the signal access area, a first gate insulating layer 201, a first conductive layer 341, a second conductive layer 342 and a protective layer 80 are stacked on the substrate 100. The first conductive layer 341 is arranged on the same layer as the gate electrode 213 of the thin film transistor 21 of the first gate metal layer and the first electrode plate 221 of the capacitor 22, or is arranged on the same layer as the second electrode plate 222 of the capacitor 22 of the second gate metal layer, or is arranged on the same layer as the source electrode 211 and the drain electrode 212 of the thin film transistor 21 of the first source-drain metal layer, that is, the first conductive layer is arranged on the same layer as one of the first electrode plate 221, the second electrode plate 222 and the source electrode 211; the second conductive layer 342 is arranged on the same layer as the first transfer electrode 231 of the second source-drain metal layer, or is arranged on the same layer as the second transfer electrode 232 of the third source-drain metal layer, that is, the second conductive layer is arranged on the same layer as the first transfer electrode 231 or the second transfer electrode 232; the protective layer 80 is arranged on the same layer as the first electrode 301. In this embodiment, the second conductive layer 342 is in direct contact with the first conductive layer 341, and the second conductive layer 342 covers the surface and side of the first conductive layer 341 away from the substrate 100, and the second conductive layer 342 covers the first conductive layer 341; at the same time, the protective layer 80 covers the surface and side of the second conductive layer 342 away from the substrate 100, and the protective layer 80 covers the second conductive layer 342. Figure 7 As shown, considering the insulation requirements between adjacent connecting wires, the protective layer 80 is disconnected to ensure that adjacent connecting wires are insulated from each other. In this example, the photoresist covering the protective layer during the preparation of the anode prevents the anode etching solution from corroding the connecting wires, thereby effectively avoiding dark spots and improving the display effect of the display substrate.

[0097] It is worth noting that the connection line of this embodiment may include three or more conductive layers, for example, including two or three conductive layers arranged on the same layer as the first electrode 221, the second electrode 222 and the source 211, including two conductive layers arranged on the same layer as the first switching electrode 231 and the second switching electrode 232, respectively. Those skilled in the art should select a suitable number of conductive layers to form the connection line according to actual application requirements. Considering the position structure of each conductive layer, when the display substrate includes an isolation layer arranged between the third flat layer and the first electrode of the light-emitting structure layer, those skilled in the art should understand that the protective layer and the isolation layer can also be arranged on the same layer, which is also within the protection scope of this application and will not be repeated here.

[0098] In an optional embodiment, if Figure 8 As shown, the at least two conductive layers include a third conductive layer 343, a fourth conductive layer 344 and a fifth conductive layer 345, the third conductive layer 343 and the first gate metal layer are located in the same layer, the fourth conductive layer 344 and the second gate metal layer are located in the same layer, and the fifth conductive layer 345 and the first source-drain metal layer are located in the same layer;

[0099] The protection layer 80 is disposed on the same layer as the passivation layer, the isolation layer and one of the anode layers and is made of the same material.

[0100] In this embodiment, the second contact pad and the third contact pad are connected by a connection line including three conductive layers, that is, the second contact pad and the third contact pad are connected by a connection line including a third conductive layer, a fourth conductive layer and a fifth conductive layer to transmit signals.

[0101] In one example of this embodiment, Figure 8 and Figure 2 As shown, in the signal access area, a first gate insulating layer 201, a third conductive layer 343, a fourth conductive layer 344, a fifth conductive layer 345 and a protective layer 80 are stacked on the substrate 100. Among them, the third conductive layer 343 is arranged on the same layer as the gate electrode 213 of the thin film transistor 21 of the first gate metal layer and the first electrode plate 221 of the capacitor 22, the fourth conductive layer 344 is arranged on the same layer as the second electrode plate 222 of the capacitor 22 of the second gate metal layer, and the fifth conductive layer 345 is arranged on the same layer as the source electrode 211 and the drain electrode 212 of the thin film transistor 21 of the first source-drain metal layer; considering that the conductive layers of the connecting wires are located on the side of the passivation layer close to the substrate, the protective layer 80 is arranged on the same layer as the passivation layer 204. In this embodiment, the fourth conductive layer 344 is in direct contact with the third conductive layer 343, and the fifth conductive layer 345 is in direct contact with the fourth conductive layer 344. The fourth conductive layer 344 covers the surface and side of the third conductive layer 343 away from the substrate 100, and the fifth conductive layer 345 covers the surface and side of the fourth conductive layer 344 away from the substrate 100. The fourth conductive layer 344 encapsulates the third conductive layer 343, and the fifth conductive layer 345 encapsulates the fourth conductive layer 344. At the same time, the protective layer 80 covers the surface and side of the fifth conductive layer 345 away from the substrate 100, and the protective layer 80 encapsulates the fifth conductive layer 345. In this example, when preparing the anode, the protective layer covering the connecting line can prevent the anode etching solution from corroding the connecting line, thereby effectively avoiding dark spots and improving the display effect of the display substrate.

[0102] In another example of this embodiment, Figure 8 and Figure 2 As shown, considering that the conductive layers of the connecting wires are located on the side of the isolation layer close to the substrate, the protective layer 80 is provided in the same layer as the isolation layer 208. In this example, the protective layer covering the connecting wires during the preparation of the anodes prevents the anode etching solution from corroding the connecting wires, thereby effectively avoiding dark spots and improving the display effect of the display substrate. The specific implementation is similar to the above-mentioned embodiment and will not be repeated here.

[0103] In another example of this embodiment, Figure 2As shown, considering that the conductive layers of the connecting wires are located on the side of the isolation layer close to the substrate, the protective layer is arranged in the same layer as the first electrode 301, and considering the insulation requirements between adjacent connecting wires, the protective layer is disconnected to ensure that adjacent connecting wires are insulated from each other. In this example, when preparing the anode, the photoresist covering the protective layer is used to prevent the anode etching solution from corroding the connecting wires, thereby effectively avoiding dark spots and improving the display effect of the display substrate. The specific implementation is similar to the above-mentioned embodiment and will not be repeated here.

[0104] Based on the display substrate of the above embodiment, one embodiment of the present application further provides a display panel, including the display substrate of the above embodiment, a driving chip and a flexible circuit board.

[0105] Based on the display panel of the above embodiment, one embodiment of the present invention proposes a display device, which includes the display panel of the above embodiment of the present invention, wherein the display device can be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and this embodiment does not limit this.

[0106] In view of the existing problems, the present invention develops a display substrate and a display device. Considering the risk of connection lines arranged in the signal access area being exposed to the anodic etching solution, a protective layer in direct contact with the connection lines is arranged on the side of the connection lines away from the substrate to avoid the anodic etching solution from corroding the connection lines. In particular, the protective layer covers the surface and side of the connection lines away from the substrate, thereby avoiding poor display caused by metal particles precipitated during the corrosion process entering the display area. This can remedy the problems existing in the prior art, effectively improve the display effect of the display substrate, and has broad application prospects.

[0107] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area and a peripheral area at least partially surrounding the display area, wherein the peripheral area comprises a signal access area located at one side of the display area, and the signal access area comprises a first signal access area and a second signal access area located at a side of the first signal access area away from the display area; A plurality of sub-pixels are located on one side of the substrate and in the display area; a plurality of data lines, located in the display area and extending to the signal access area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; a plurality of first contact pads, located in the first signal access area and connected to the plurality of data lines; a plurality of second contact pads, located in the first signal access area and located on a side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound to a driving chip; a plurality of third contact pads, located in the second signal access area and configured to be bound to the circuit board; a plurality of connection lines, located between the plurality of second contact pads and the plurality of third contact pads and connecting the plurality of second contact pads and the plurality of third contact pads, at least one connection line among the plurality of connection lines comprises at least two conductive layers, and the at least two conductive layers are in direct contact; The protective layer is located on the side of the multiple connecting lines away from the substrate, and the protective layer covers the surface and side of the multiple connecting lines away from the substrate to prevent the multiple connecting lines from being corroded by the etching solution for preparing the anode layer of the display substrate.

2. The display substrate according to claim 1, characterized in that: The at least two conductive layers include a first conductive layer and a second conductive layer sequentially stacked on the substrate, and at least one of the at least two conductive layers contains aluminum and / or titanium; The second conductive layer covers a surface and a side surface of the first conductive layer away from the substrate, and the protective layer covers a surface and a side surface of the second conductive layer away from the substrate.

3. The display substrate according to claim 2, characterized in that: A surface and a side surface of the first conductive layer away from the substrate are in direct contact with the second conductive layer, and the protective layer is in direct contact with a surface and a side surface of the second conductive layer away from the substrate.

4. The display substrate according to claim 1, characterized in that: In a direction perpendicular to the substrate, a sum of thicknesses of the at least two conductive layers is greater than or equal to 9000 angstroms and less than or equal to 22000 angstroms.

5. The display substrate according to claim 3, characterized in that: The display substrate comprises a circuit structure layer and a light emitting structure layer stacked on the substrate, wherein the circuit structure layer comprises a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, a first source-drain metal layer, a passivation layer, a first flat layer, a second source-drain metal layer, a second flat layer, a third source-drain metal layer, a third flat layer and an isolation layer stacked in sequence on the substrate; The light emitting structure layer includes an anode layer.

6. The display substrate according to claim 5, characterized in that: The first conductive layer and the second source-drain metal layer are located in the same layer, the second conductive layer and the third source-drain metal layer are located in the same layer, and the protective layer and the anode layer or the isolation layer are located in the same layer.

7. The display substrate according to claim 5, characterized in that: One of the at least two conductive layers is disposed on the same layer as one of the first gate metal layer, the second gate metal layer and the first source-drain metal layer; Another conductive layer of the at least two conductive layers is disposed on the same layer as one of the second source-drain metal layer and the third source-drain metal layer; The protective layer is arranged on the same layer as the anode layer and is made of the same material.

8. The display substrate according to claim 5, characterized in that: The at least two conductive layers include a third conductive layer, a fourth conductive layer and a fifth conductive layer, the third conductive layer and the first gate metal layer are located in the same layer, the fourth conductive layer and the second gate metal layer are located in the same layer, and the fifth conductive layer and the first source-drain metal layer are located in the same layer; The protective layer is arranged on the same layer as the passivation layer, the isolation layer and one of the anode layers and is made of the same material.

9. The display substrate according to claim 8, characterized in that: The materials of the first gate metal layer and the second gate metal layer are both metal molybdenum, and the material of the first source-drain metal layer is a three-layer stack of titanium / aluminum / titanium.

10. A display device, characterized in that: It comprises a display substrate as described in any one of claims 1 to 9, as well as a driving chip and a circuit board.

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