Dynamic and shared CMB and HMB allocation

Abstract

A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device with a plurality of CMB buffers and a plurality of HMB buffers as a single buffer pool. The controller is further configured to allocate a CMB buffer or an HMB buffer to store data based on a trade-off between latency and performance between using the CMB or using the HMB. By fully utilizing the benefits of both the CMB and the HMB to store data, the overall performance of the data storage device can be improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of, and is hereby incorporated by reference in its entirety, U.S. Non-Provisional Application No. 17 / 949,132, filed on September 20, 2022, and entitled “Dynamic And Shared CMB And HMB Allocation,” for all purposes. Background Art Technical Field

[0003] Embodiments of the present disclosure relate generally to data storage devices, such as solid-state drives (SSDs), and more particularly, to utilizing capabilities of both a host memory buffer (HMB) and a controller memory buffer (CMB) in a storage system.

[0004] Related technical description

[0005] To fit into a data center environment, enterprise SSDs may have specific requirements that may include predictability and short latency for read operations. Additionally, enterprise workloads are typically not local, and expect reads from any portion of a logical address range to be maintained by the associated data storage device with the same quality of service. Due to the requirements for enterprise SSDs, logical-to-physical (L2P) tables may typically be stored in dynamic random access memory (DRAM), which may require an increase in the size of the DRAM or a larger size.

[0006] As DRAM increases in size or becomes larger, the cost of producing data storage devices may be negatively impacted. Furthermore, enterprise SSDs are consumables. Data storage devices may be rated based on a number of disk writes per day (DWPD) for the life of the data storage device. Customers may choose to exceed the DWPD for the data storage device, which may cause the data storage device to wear out faster. In other words, the cost of the data storage device is converted to a certain number of write cycles.

[0007] The host device may include a host memory buffer (HMB) for use with the data storage device, which may be used to store data that is typically stored in the data storage device. In some data storage devices, DRAM may not exist, so the HMB may be used to replace the DRAM. In addition, the controller of the data storage device may include a controller memory buffer (CMB), wherein the host device can access the CMB to place a submission queue, a completion queue, a physical region page (PRP) list, a scatter-gather list (SGL) fragment, a data buffer, etc. The CMB feature can reduce the number of memory read operations issued by the transmission link between the data storage device and the host device, which can reduce the latency of the computing system. Each of the CMB and the HMB has different benefits that do not exploit each other.

[0008] Therefore, there is a need in the art for improved data storage device operation that exploits the benefits of both a controller memory buffer and a host memory buffer. Summary of the invention

[0009] The present disclosure generally relates to data storage devices, such as solid-state drives (SSDs), and more specifically, to the utilization capabilities of both a host memory buffer (HMB) and a controller memory buffer (CMB) in a storage system. A data storage device includes a controller. The controller includes a CMB. The controller is configured to associate both a CMB and an HMB of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate a CMB buffer or an HMB buffer to store data based on a tradeoff between latency and performance between using CMBs or using HMBs. By fully utilizing the benefits of both CMBs and HMBs to store data, the overall performance of the data storage device can be improved.

[0010] In one embodiment, a data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to issue a write command to write data to a host memory buffer (HMB) of a host device, determine whether a utilization of the CMB is greater than or equal to a threshold utilization, and when the utilization of the CMB is less than the threshold utilization, allocate a buffer of the CMB and issue a write command to the CMB to cache the write data in the CMB.

[0011] In another embodiment, a data storage device includes a controller. The controller includes a controller memory buffer (CMB) and a CMB-host memory buffer (HMB) scheduler. The CMB-HMB scheduler is configured to associate both a CMB and an HMB of a host device as a single buffer pool, wherein the single buffer pool includes a plurality of CMB buffers and a plurality of HMB buffers, and associate CMB buffers from a plurality of CMB buffers or HMB buffers from a plurality of HMB buffers, wherein allocation is based on a tradeoff between latency and performance between using CMBs or using HMBs to store data.

[0012] In another embodiment, a storage system includes a data storage device configured to be coupled to a host device having a host memory buffer (HMB). The data storage device includes a controller. The controller includes a controller memory buffer (CMB). The storage system also includes means for associating both the CMB and the HMB as a single buffer pool, wherein the single buffer pool includes a plurality of CMB buffers and a plurality of HMB buffers, and means for allocating a CMB buffer from the plurality of CMB buffers or an HMB buffer from the plurality of HMB buffers, wherein the allocation is based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Thus, a detailed understanding of the manner in which the above-described features of the present disclosure are understood, a more particular description of the present disclosure, the above brief summary, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0014] Figure 1 is a schematic block diagram illustrating a storage system according to certain embodiments, in which a data storage device can be used as a storage device for a host device.

[0015] Figure 2 is an exemplary illustration of a memory system according to certain embodiments, the memory system including a host device having a host memory buffer (HMB) and a data storage device having a controller memory buffer (CMB).

[0016] Figure 3A is a flowchart illustrating a method of performing write access of a data storage device to an HMB of a host device according to certain embodiments.

[0017] Figure 3Bis a flowchart illustrating a method of performing read access of an HMB of a data storage device to a host device according to certain embodiments.

[0018] Figure 4 is a flow chart illustrating a method of performing write access from a host device to a CMB of a data storage device according to certain embodiments.

[0019] Figure 5 is a schematic block diagram illustrating a storage system according to certain embodiments, in which a controller of a data storage device can exploit the benefits of a CMB and an HMB of a host device.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0021] Hereinafter, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the following features and elements (whether or not related to different embodiments) is considered to realize and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a specific advantage is achieved by a given embodiment is not a limitation to the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative, and are not considered to be elements or limitations of the appended claims, unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein, and should not be considered to be elements or limitations of the appended claims, unless explicitly stated in the claims.

[0022] The present disclosure generally relates to data storage devices, such as solid-state drives (SSDs), and more specifically, to the utilization capabilities of both a host memory buffer (HMB) and a controller memory buffer (CMB) in a storage system. A data storage device includes a controller. The controller includes a CMB. The controller is configured to associate both a CMB and an HMB of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate a CMB buffer or an HMB buffer to store data based on a tradeoff between latency and performance between using CMBs or using HMBs. By fully utilizing the benefits of both CMBs and HMBs to store data, the overall performance of the data storage device can be improved.

[0023] Figure 11 is a schematic block diagram illustrating a storage system 100 having a data storage device 106 that can be used as a storage device for a host device 104 according to certain embodiments. For example, the host device 104 can utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138. In some examples, the storage system 100 can include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that are collectively used as a mass storage device for the host device 104.

[0024] Host device 104 may store data to and / or retrieve data from one or more storage devices, such as data storage device 106. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" tablet computer, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or other device capable of sending or receiving data from a data storage device.

[0025] The host DRAM 138 may optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 that is allocated to the data storage device 106 for exclusive use by the controller 108 of the data storage device 106. For example, the controller 108 may store mapping data, buffer commands, logical to physical (L2P) tables, metadata, etc. in the HMB 150. In other words, the HMB 150 may be used by the controller 108 to store data that would normally be stored in the volatile memory 112, the buffer 116, the internal memory of the controller 108 (such as static random access memory (SRAM)), etc. In examples where the data storage device 106 does not include DRAM (i.e., the optional DRAM 118), the controller 108 may utilize the HMB 150 as the DRAM of the data storage device 106.

[0026] Data storage device 106 includes controller 108, NVM 110, power supply 111, volatile memory 112, interface 114, write buffer 116, and optional DRAM 118. In some examples, for clarity, data storage device 106 may include Figure 1106. For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5" data storage device (e.g., an HDD or SSD), a 2.5" data storage device, a 1.8" data storage device, a peripheral component interconnect (PCI), a PCI extension (PCI-X), a PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini card, MiniPCI, etc.). In some examples, the data storage device 106 may be directly coupled (e.g., directly soldered or inserted into a connector) to a motherboard of the host device 104.

[0027] The interface 114 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the data storage device 106 to receive power from the host device 104. For example, as Figure 1 As shown, power supply 111 may receive power from host device 104 via interface 114 .

[0028] NVM 110 may include multiple memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of NVM 110 may receive data and a message from controller 108 indicating that the memory cell stores the data. Similarly, the memory cell may receive a message from controller 108 indicating that the memory cell retrieves data. In some examples, each of the memory cells may be referred to as a die. In some examples, NVM 110 may include multiple dies (e.g., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0029] In some examples, each memory cell may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0030] NVM 110 may include multiple flash memory devices or memory cells. NVM flash memory devices may include NAND or NOR-based flash memory devices, and may store data based on the charge contained in the floating gate of the transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into multiple dies, wherein each of the multiple dies includes multiple physical or logical blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. The rows of NVM cells may be electrically connected using word lines to define pages in multiple pages. The corresponding cells in each of the multiple pages may be electrically connected to the corresponding bit lines. In addition, the NVM flash memory device may be a 2D or 3D device, and may be a single-level cell (SLC), a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). The controller 108 may write data to and read data from the NVM flash memory device at the page level, and erase data from the NVM flash memory device at the block level.

[0031] The power supply 111 can provide power to one or more components of the data storage device 106. When operating in standard mode, the power supply 111 can use power provided by an external device such as the host device 104 to power one or more components. For example, the power supply 111 can use power received from the host device 104 via the interface 114 to power one or more components. In some examples, the power supply 111 may include one or more power storage components that are configured to power one or more components when operating in a shutdown mode, such as when power is stopped from being received from an external device. In this way, the power supply 111 can be used as an onboard backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of such one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0032] Volatile memory 112 may be used by controller 108 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 until the cached information is written to NVM 110. Figure 1 As shown, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Similarly, optional DRAM 118 can be used to store mapping data, buffered commands, logical to physical (L2P) tables, metadata, cached data, etc. in optional DRAM 118. In some examples, data storage device 106 does not include optional DRAM 118, so that data storage device 106 is DRAM-free. In other examples, data storage device 106 includes optional DRAM 118.

[0033] The controller 108 can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from the NVM 110 and / or writing data to the NVM. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110.

[0034] The controller 108 may include an optional second volatile memory 120. The optional second volatile memory 120 may be similar to the volatile memory 112. For example, the optional second volatile memory 120 may be an SRAM. The controller 108 may allocate a portion of the optional second volatile memory to the host device 104 as a controller memory buffer (CMB) 122. The CMB 122 may be directly accessible by the host device 104. For example, the host device 104 may utilize the CMB 122 to store one or more submission queues that are typically maintained in the host device 104 instead of maintaining one or more submission queues in the host device 104. In other words, the host device 104 may generate commands in the CMB 122 and store the generated commands, with or without associated data, wherein the controller 108 accesses the CMB 122 to retrieve the stored generated commands and / or associated data.

[0035] Figure 2 is an exemplary illustration of a storage system 200 according to certain embodiments, the storage system including a host device 202 having an HMB 204 and a data storage device 206 having a CMB 208. The HMB 204 stores address tables, mapping tables, logical to physical (L2P) tables, XOR binary numbers, etc. The CMB 208 may store a submission queue, a completion queue, a physical region page (PRP) list, a scatter gather list (SGL) fragment, a data buffer, a pointer, etc. The latency of the data storage device 206, or more specifically, the controller accessing the CMB 208, such as Figure 1 The controller 108 can be less than the latency of the data storage device 206 or the controller 108 accessing the HMB 204. For exemplary purposes, the following Table 1 shows the advantages and disadvantages of using CMB 208 or HMB 204.

[0036] HMB CMB Latency (data storage device access) high Low Capacity (non-DRAM data storage device) high Low Overhead (security and protection) yes no Additional PCIe traffic yes no

[0037] Table 1

[0038] The time delay of data storage device 206 accessing HMB204 is greater than the time delay of data storage device 206 accessing CMB208. Since data storage device 206 accesses CMB208 and does not increase the flow rate on the PCIe bus between host device 202 and data storage device 206, the time delay of accessing CMB208 can be less than the time delay of accessing HMB. In addition, since data is not transmitted between host device 202 and data storage device 206, additional overhead may not be required. Similarly, when data storage device 206 does not have DRAM, the capacity of HMB204 can be greater than the capacity of CMB208. Therefore, for performance purposes, CMB208 can be used for storing and retrieving data instead of using HMB204. However, if capacity is a consideration, HMB204 can be used for storing and retrieving data instead of using HMB208. In other words, in selecting to store data in HMB204 or CMB208, data storage device 206 can determine the compromise between one or more of time delay consideration, performance consideration and capacity consideration.

[0039] It should be understood that HMB 204 can be a plurality of HMBs. It should also be understood that CMB 208 can be a plurality of CMBs. Similarly, a controller such as Figure 1 The controller 108 can associate HMB204 and CMB208 as a single buffer pool, so that the single buffer pool includes multiple HMBs and multiple CMBs, wherein the CMB buffer or the HMB buffer is allocated according to the above-mentioned tradeoff. In addition, the controller 108 can dynamically determine the location of the stored data based on the access frequency of the data or the prompt associated with the data. In other words, if the data is very popular (e.g., the access time is equal to or greater than about 50%), the data can be stored in CMB208. On the contrary, if the data is very unpopular (e.g., the access time is less than about 50%), the data can be stored in HMB204. The controller 108 can dynamically move data from HMB204 to CMB208 or from CMB208 to HMB204 based on the access frequency of the data. Similarly, the controller 108 can determine to cache data in HMB204 or CMB208 based on previous access requests for similar data, which may be the same logical block address (LBA) range, data type, etc.

[0040] Figure 3A is a flow chart illustrating a method 300 for performing a write access of a data storage device to an HMB of a host device according to certain embodiments. The method 300 may be implemented by a controller, such as Figure 1 A controller 108 having a CMB such as Figure 2 For exemplary purposes, reference may be made here to CMB208. Figure 1 The data storage system 100 and Figure 2 Various aspects of the storage system 200.

[0041] At box 302, data storage device 206 initiates a write access to write data to HMB 204. At box 304, controller 108 determines whether CMB 208 is fully utilized. It should be understood that full utilization can refer to equal to or greater than a threshold utilization of CMB 208. For example, the size of the threshold utilization of CMB 208 can be less than the total capacity of CMB 208. If CMB 208 is fully utilized, so that the utilization of CMB 208 is equal to or greater than the threshold utilization at box 304, controller 108 issues an HMB write command to write data to HMB 204. However, if CMB is not fully utilized, so that the utilization of CMB 208 is less than the threshold utilization at box 304, controller 108 allocates CMB buffers at box 308. The allocated CMB buffers can come from a single buffer pool having one or more CMB buffers and one or more HMB buffers. At box 310, controller 108 issues a CMB write command to write data to CMB 208. Therefore, when an HMB write access is required and the CMB is not fully utilized, the controller 108 may issue a CMB write command instead of an HMB write command.

[0042] Figure 3B is a flow chart illustrating a method 350 for performing a read access of a data storage device to an HMB of a host device according to certain embodiments. The method 350 may be implemented by a controller such as Figure 1 A controller 108 having a CMB such as Figure 2 For exemplary purposes, reference may be made here to CMB208. Figure 1 The data storage system 100 and Figure 2 Various aspects of the storage system 200.

[0043] At block 352, the data storage device 206 initiates a read access to read data from the HMB 204. At block 354, the controller 108 determines whether the data associated with the accessed read is cached in the CMB 208. If at block 354, the data is not cached in the CMB 208, then at block 356, the controller 108 issues an HMB read command to read the associated data associated with the read access from the HMB 204. However, if at block 354, the data is cached in the CMB 208, then at block 358, the controller 108 locates the associated CMB address. At block 360, the controller 108 issues a CMB read command to read the data from the associated CMB address.

[0044] Figure 44 is a flow chart illustrating a method 400 for performing write access of a host device to a CMB of a data storage device according to certain embodiments. The method 400 may be implemented by a controller such as Figure 1 A controller 108 having a CMB such as Figure 2 For exemplary purposes, reference may be made here to CMB208. Figure 1 The data storage system 100 and Figure 2 Various aspects of the storage system 200.

[0045] At block 402, the host device 202 initiates a write access to write data to the CMB 208. At block 404, the controller 108 determines whether the CMB 208 or a related CMB buffer of a plurality of CMB buffers of the CMB 208 is allocated for the data storage device 106. In other words, the controller 108 may determine whether at least a portion of the CMB 208 is utilized to store / cache data for the data storage device 106. When at least a portion of the CMB 208 is utilized to store / cache data for the data storage device 106, the data may need to be evicted to the HMB 204 before the host data may be stored in the CMB 208. If at block 404, the CMB 208 or a related CMB buffer is allocated for the data storage device 106, then at block 406, the controller 108 issues a CMB write command to write the data associated with the write access to the CMB 208. However, if at block 404 a CMB 208 or associated CMB buffer is allocated for the data storage device 106 , then at block 408 the controller 108 stops the transaction (eg, stops write access).

[0046] At block 410, the controller 108 evicts the associated one or more CMB buffers or CMB 208 from the controller 108 to the HMB 204. For example, the evicted associated one or more CMB buffers may be associated with data that was originally scheduled to be programmed to the HMB 204, but based on latency, performance, and capacity tradeoffs, it is programmed to the CMB 208. At block 412, the controller 108 issues a CMB write command to write the data associated with the write access to the CMB 208. The issuance of the CMB write command may also include resuming or re-initiating the stopped transaction stopped at block 408.

[0047] Figure 55 is a schematic block diagram illustrating a storage system 500 according to certain embodiments, wherein a controller 514 of a data storage device 512 can take advantage of the benefits of a CMB 518 and an HMB 510 of a host device 502. The host device 502 includes a host memory 504. The host memory 504 includes a plurality of queues 506A-N, which may be a plurality of submission queues and / or a plurality of completion queues, a plurality of data buffers 508A-N, and an HMB 510. The host device 502 is coupled to the data storage device 512.

[0048] The data storage device 512 includes a controller 514 and an NVM 530. The controller 514 includes a PCIe / media access layer (MAC) / physical layer (PHY) 516 coupled to the CMB 518, a CMB-HMB scheduler 520, a control path 522, and a data path 524. The controller 514 also includes a flash interface module (FIM) 526 coupled to the control path 522 and the data path 524. The controller 514 also includes one or more processors 528.

[0049] The controller 514 receives data from the host device 502 and sends data to the host device via the PCIe / MAC / PHY 516, wherein the control path 522 may generate corresponding commands to process the data. For example, in response to receiving a read command from the host device 502, the control path 522 may generate a read and write command to read data from the NVM 530 or in response to receiving a write command from the host device 502, the control path may generate a read and write command to write data to the NVM 530. Similarly, the data path 524 may process data received from the host device 502 or the NVM 530. For example, the data path 524 may include direct memory access (DMA), error correction code (ECC), engine, encoder, decoder, encryption module, decryption module, etc.

[0050] In addition, the host device 502 can store at least a portion of the multiple queues 506A-N and at least a portion of the data buffers 508A-N in the CMB518. In other words, the controller 514 can grant direct access to the host device 502 to store write commands, read commands, and data associated with the write commands and read commands in the CMB518. The CMB-HMB scheduler 520 can be configured to dynamically allocate HMB510 (or an HMB buffer of multiple HMB buffers) or CMB518 (or a CBM buffer of multiple CMB buffers) to store related data that can be stored in CMB518 or HMB510. The allocation can be based on a tradeoff between capacity, latency, and one or more of the performance of storing data in CMB518 or the performance of storing data in HMB510. The CMB-HMB scheduler 520 can also be responsible for performing Figure 3A , Figure 3B and Figure 4 Similarly, the CMB-HMB scheduler 520 may be configured to manage the CMB 518 and the HMB 510. For example, the CMB-HMB scheduler 520 may be configured to evict data from the CMB 518 to the HMB 510 or to move hot data from the HMB 510 to the CMB 518 and to move cold data from the CMB 518 to the HMB 510.

[0051] By utilizing the advantages and disadvantages of both CMB and HMB, the performance and service quality of the data storage device can be improved.

[0052] In one embodiment, a data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to issue a write command to write data to a host memory buffer (HMB) of a host device, determine whether a utilization of the CMB is greater than or equal to a threshold utilization, and when the utilization of the CMB is less than the threshold utilization, allocate a buffer of the CMB and issue a write command to the CMB to cache the write data in the CMB.

[0053] The write data is not programmed to the HMB. The controller is further configured to issue a read command to read the write data from the HMB, determine whether the write data is cached in the CMB, and when the write data is cached in the CMB, find the CMB address of the write data and issue a read command to the CMB to read the write data from the CMB. The write data is not read from the HMB. The data storage device does not include a dynamic random access memory (DRAM). The controller also includes a CMB / HMB scheduler. The CMB / HMB scheduler is configured to dynamically allocate a buffer of the CMB or a buffer of the HMB based on at least one of a latency to access the CMB or the HMB and a capacity availability of the CMB or the HMB. The CMB / HMB scheduler is further configured to manage address translation of the CMB and the HMB and data eviction from the HMB to the CMB or from the CMB to the HMB.

[0054] In another embodiment, a data storage device includes a controller. The controller includes a controller memory buffer (CMB) and a CMB-host memory buffer (HMB) scheduler. The CMB-HMB scheduler is configured to associate both a CMB and an HMB of a host device as a single buffer pool, wherein the single buffer pool includes a plurality of CMB buffers and a plurality of HMB buffers, and associate CMB buffers from a plurality of CMB buffers or HMB buffers from a plurality of HMB buffers, wherein allocation is based on a tradeoff between latency and performance between using CMBs or using HMBs to store data.

[0055] The CMB-HMB scheduler is further configured to determine that an access request to write data to the HMB has been initiated, determine whether the utilization of the CMB is less than a utilization threshold, and when the utilization of the CMB is less than the utilization threshold, allocate the CMB buffer for the access request and issue a CMB write command to write the data to the CMB instead of the HMB. The CMB-HMB scheduler is further configured to determine that the utilization of the CMB is greater than or equal to the utilization threshold and issue an HMB write command to write the data to the HMB. The CMB-HMB scheduler is further configured to determine that an access request to read data from the HMB has been initiated, determine whether the data is cached in the CMB buffer, and when the data is cached in the CMB buffer, locate the CMB address of the CMB buffer associated with the data and use the CMB address from the CMB instead of the HMB to initiate a CMB read command to read the data. The CMB-HMB scheduler is further configured to determine that the data is not cached in the CMB buffer, and issue an HMB read command to read the data from the HMB. The CMB-HMB scheduler is further configured to receive a write command to write data from a host device to a CMB, determine whether at least a portion of a CMB buffer has been allocated to cache data by a controller, and stop writing to the CMB when at least a portion of a CMB buffer has been allocated to cache data by a controller. The CMB-HMB scheduler is further configured to evict at least a portion of data cached in the CMB to an HMB buffer. The CMB-HMB scheduler is further configured to issue a CMB write command to program the write data to the CMB when at least a portion of the write data cached in the CMB is evicted to an HMB buffer. At least a portion of the data cached in the CMB is associated with an HMB write command, and the HMB write command is programmed to the CMB instead of the HMB. The CMB-HMB scheduler is further configured to determine that at least a portion of a CMB buffer has been allocated to cache data by a controller and to issue a CMB write command to program the write data to the CMB. The CMB-HMB scheduler is further configured to move data stored in the CMB to the HMB or move data stored in the HMB to the CMB based on an access frequency of the data stored in the CMB or the data stored in the HMB.

[0056] In another embodiment, a storage system includes a data storage device configured to be coupled to a host device having a host memory buffer (HMB). The data storage device includes a controller. The controller includes a controller memory buffer (CMB). The storage system also includes means for associating both CMBs and HMBs as a single buffer pool, wherein the single buffer pool includes multiple CMB buffers and multiple HMB buffers, and means for allocating CMB buffers from multiple CMB buffers or HMB buffers from multiple HMB buffers, wherein the allocation is based on a tradeoff between latency and performance between using CMBs or using HMBs to store data. The controller also includes means for redirecting a write command to write data to the HMB or CMB based on the means for allocating.

[0057] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be envisaged without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A data storage device, comprising: A controller, wherein the controller comprises a controller memory buffer (CMB), and wherein the controller is configured to: issuing a write command to write data to a host memory buffer (HMB) of the host device; Determining whether the utilization rate of the CMB is greater than or equal to a threshold utilization rate; When the utilization of the CMB is less than the threshold utilization, allocating a buffer of the CMB; as well as A write command is issued to the CMB to cache the write data in the CMB. 2 . The data storage device of claim 1 , wherein the write data is not programmed to the HMB.

3. The data storage device according to claim 1, wherein the controller is further configured to: issuing a read command to read the write data from the HMB; determining whether the write data is cached in the CMB; When the write data is cached in the CMB, finding the CMB address of the write data; and A read command is issued to the CMB to read the write data from the CMB. The data storage device of claim 3 , wherein the write data is not read from the HMB.

5. The data storage device of claim 1, wherein the data storage device does not include dynamic random access memory (DRAM).

6. The data storage device according to claim 1, wherein the controller further comprises a CMB / HMB scheduler, wherein the CMB / HMB scheduler is configured to dynamically allocate a buffer of the CMB or a buffer of the HMB based on at least one of a latency of accessing the CMB or the HMB and a capacity availability of the CMB or the HMB. 7 . The data storage device of claim 6 , wherein the CMB / HMB scheduler is further configured to manage address translation of the CMB and the HMB and data eviction from the HMB to the CMB or from the CMB to the HMB.

8. A data storage device, comprising: A controller, wherein the controller comprises a controller memory buffer (CMB) and a CMB-host memory buffer (HMB) scheduler, and wherein the CMB-HMB scheduler is configured to: associating both the CMB and the HMB of the host device as a single buffer pool, wherein the single buffer pool includes a plurality of CMB buffers and a plurality of HMB buffers; and A CMB buffer from the plurality of CMB buffers or an HMB buffer from the plurality of HMB buffers is allocated, wherein the allocation is based on a tradeoff between latency and performance between using the CMB or using the HMB to store data.

9. The data storage device according to claim 8, wherein the CMB-HMB scheduler is further configured to: Determining that an access request to write data to the HMB has been initiated; Determining whether the utilization rate of the CMB is less than a utilization rate threshold; When the utilization of the CMB is less than the utilization threshold, allocating the CMB buffer for the access request; and A CMB write command is issued to write the data to the CMB instead of the HMB.

10. The data storage device according to claim 9, wherein the CMB-HMB scheduler is further configured to: determining that the utilization of the CMB is greater than or equal to the utilization threshold; and An HMB write command is issued to write the data to the HMB.

11. The data storage device according to claim 8, wherein the CMB-HMB scheduler is further configured to: Determining that an access request to read data from the HMB has been initiated; determining whether the data is cached in the CMB buffer; When the data is cached in the CMB buffer, locating a CMB address of the CMB buffer associated with the data; and A CMB read command is initiated using the CMB address from the CMB instead of the HMB to read the data.

12. The data storage device according to claim 11, wherein the CMB-HMB scheduler is further configured to: determining that the data is not cached in the CMB buffer; and An HMB read command is issued to read the data from the HMB.

13. The data storage device according to claim 8, wherein the CMB-HMB scheduler is further configured to: receiving a write command to write data from the host device to the CMB; determining whether at least a portion of the CMB buffer has been allocated by the controller to cache data; and When the at least a portion of the CMB buffer has been allocated by the controller to cache data, the writing to the CMB is stopped. 14 . The data storage device of claim 13 , wherein the CMB-HMB scheduler is further configured to evict at least a portion of the data cached in the CMB to the HMB buffer.

15. The data storage device of claim 14, wherein the CMB-HMB scheduler is further configured to issue a CMB write command to program the write data to the CMB when the at least a portion of the write data cached in the CMB is evicted to the HMB buffer.

16. The data storage device of claim 14, wherein the at least a portion of the data cached in the CMB is associated with an HMB write command, the HMB write command being programmed to the CMB instead of the HMB.

17. The data storage device according to claim 13, wherein the CMB-HMB scheduler is further configured to: determining that the at least a portion of the CMB buffer has been allocated by the controller to cache data; and A CMB write command is issued to program the write data to the CMB.

18. The data storage device of claim 8, wherein the CMB-HMB scheduler is further configured to move data stored in the CMB to the HMB or move data stored in the HMB to the CMB based on an access frequency of the data stored in the CMB or the data stored in the HMB.

19. A storage system, comprising: a data storage device configured to be coupled to a host device having a host memory buffer (HMB), wherein the data storage device includes a controller, and wherein the controller includes a controller memory buffer (CMB); means for associating both the CMB and the HMB as a single buffer pool, wherein the single buffer pool comprises a plurality of CMB buffers and a plurality of HMB buffers; and Means for allocating a CMB buffer from the plurality of CMB buffers or an HMB buffer from the plurality of HMB buffers, wherein the allocating is based on a tradeoff between latency and performance between using the CMB or using the HMB to store data.

20. The storage system according to claim 19, further comprising: Means for redirecting a write command to write data to the HMB or the CMB based on the means for allocating.

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