A battery management system and a battery management method

Abstract

The present application relates to a battery management system, including an MCU; a plurality of battery cell groups; a plurality of AFE chips, configured to sample data of the plurality of battery cell groups under the control of the MCU; after receiving a start sampling instruction from the MCU and before sampling the plurality of battery cell groups, at least one of the plurality of AFE chips is configured to wait for a corresponding number of delayed clock cycles; the corresponding number of delayed clock cycles is based at least on the number of the plurality of AFE chips, the order in which the plurality of AFE chips receive the start sampling instruction, the position of each AFE chip in the order, and the number of clock cycles between the MCU sending the start sampling instruction to the two preceding and succeeding AFE chips or the number of clock cycles between two adjacent AFE chips for transmitting the start sampling instruction. The present application also relates to a method for battery management. The battery management system of the present application enables all AFE chips to sample synchronously. The method for battery management of the present application is built into each AFE chip to automatically achieve synchronous sampling.

Description

Technical Field

[0001] The present application relates to the field of batteries, and in particular to a battery management system and a battery management method. Background Art

[0002] The battery management system (BMS) is one of the core components of the power battery system. It is responsible for monitoring and calculating the real-time status parameters and health status of the battery, and reporting relevant information to the vehicle controller. At the same time, it cooperates with the vehicle controller to perform power-on and power-off operations of the power battery high-voltage circuit and coordinates with other systems on the vehicle. With the continuous improvement of sampling frequency and synchronization requirements, the performance of the controller is getting better and better, the model for evaluating the battery status is becoming more and more complex, and more and more data dimensions are required. In this process, synchronous sampling is a key link to ensure data accuracy and system safety.

[0003] In practical applications, as more and more battery cells are connected in series, the collection of battery cell data is performed by many chips. Due to the limitations of technology, cost and other factors, completely synchronous sampling may be difficult to achieve. The current common solution is to try to ensure the synchronization of battery cell data collected by a single chip, but it is usually difficult to accurately control the synchronization between different chips. Summary of the invention

[0004] In view of the technical problems existing in the prior art, the present application proposes a battery management system, comprising: an MCU; a plurality of battery cell groups; a plurality of AFE chips, which are electrically connected to the plurality of battery cell groups one-to-one and configured to sample and report the battery cell data of the plurality of battery cell groups respectively under the control of the MCU; wherein, after receiving a start sampling instruction from the MCU and before sampling the plurality of battery cell groups, at least one of the plurality of AFE chips is configured to wait for a corresponding number of delayed clock cycles; wherein the corresponding number of delayed clock cycles is based at least on the number of the plurality of AFE chips, the order in which the plurality of AFE chips receive the start sampling instruction, the position of each AFE chip in the order, and the number of clock cycles between which the MCU sends the start sampling instruction to the two preceding and succeeding AFE chips or the number of clock cycles between which the start sampling instruction is transmitted between two adjacent AFE chips.

[0005] In particular, the last AFE chip that receives the start sampling instruction is configured to wait for the corresponding number of delay clock cycles to be zero before sampling the battery cell group electrically connected thereto.

[0006] In particular, wherein a plurality of AFE chips MCU are electrically connected in series, the corresponding number of delayed clock cycles is at least based on the number of clock cycles for transmitting a start sampling instruction between two adjacent AFE chips.

[0007] In particular, the plurality of AFE chips are electrically connected to the MCU respectively, and the corresponding number of delayed clock cycles is at least based on the number of interval clock cycles at which the MCU sends a start sampling instruction to the two preceding and succeeding AFE chips.

[0008] The present application also proposes a battery management method, including: initializing multiple AFE chips; determining, based on parameters in the initialization, the corresponding number of delayed clock cycles that each AFE chip needs to wait for after receiving a start sampling instruction and before sampling a battery cell group electrically connected to it; wherein the corresponding number of delayed clock cycles is based on at least the number of multiple AFE chips, the order in which the multiple AFE chips receive the start sampling instruction, the position of each AFE chip in the order, and the number of clock cycles between the MCU sending the start sampling instruction to the previous and next two AFE chips or the number of clock cycles between two adjacent AFE chips to transmit the start sampling instruction.

[0009] In particular, the initialization includes: determining the number of multiple AFE chips; when multiple AFE chips are electrically connected to the MCU in series, setting the order in which the start sampling instruction is transmitted in the series electrical connection; setting the position of each AFE chip in the order; and setting the number of clock cycles for transmitting the start sampling instruction between two adjacent AFE chips.

[0010] In particular, the corresponding number of delayed clock cycles that each AFE chip needs to wait for after receiving a start sampling instruction and before sampling a battery cell group electrically connected to the AFE chip is determined based on the parameters in the initialization, including: determining the difference between the number of multiple AFE chips and the position of one of the AFE chips in the sequence; obtaining the product of the difference and the number of clock cycles for transmitting the start sampling instruction between two adjacent AFE chips as the corresponding number of delayed clock cycles.

[0011] In particular, the initialization includes: determining the number of multiple AFE chips; when the multiple AFE chips are electrically connected to the MCU respectively, setting the order in which the MCU sends start sampling instructions to the multiple AFE chips; setting the position of each AFE chip in the order; setting the number of interval clock cycles between the MCU sending start sampling instructions to the front and rear two AFE chips.

[0012] In particular, the corresponding number of delayed clock cycles that each AFE chip needs to wait for after receiving a start sampling instruction and before sampling a battery cell group electrically connected to it is determined based on the parameters in the initialization, including: determining the difference between the number of multiple AFE chips and the position of one of the AFE chips in the sequence; obtaining the product of the difference and the number of interval clock cycles at which the MCU sends a start sampling instruction to the two previous and next AFE chips as the corresponding number of delayed clock cycles.

[0013] The battery management system proposed in this application enables all AFE chips in the system to perform synchronous sampling, and has a simple structure without adding additional chips or circuits. The battery management method proposed in this application is a method for automatically achieving synchronous sampling built into each AFE chip. While the MCU in the BMU completes the initialization operation of all AFE chips, each AFE chip adaptively adjusts its own synchronous sampling delay, thereby achieving automatic synchronous sampling with higher accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0015] Figure 1 is a schematic diagram of a BMS structure according to an embodiment of the present application;

[0016] Figure 2 According to an embodiment of the present application Figure 1 The schematic diagram of the synchronous sampling method flow chart of the BMS shown;

[0017] Figure 3 is a schematic diagram of a BMS structure according to an embodiment of the present application;

[0018] Figure 4 According to an embodiment of the present application Figure 3 Schematic diagram of the synchronous sampling method flow chart of BMS shown. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0021] The technologies, methods and devices known to those skilled in the art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only be able to communicate with each other through the signals shown in the figure.

[0022] In view of the problems existing in the solutions in current practical applications, the present application proposes a BMS and a corresponding method capable of synchronously sampling an analog front end (AFE) chip.

[0023] Figure 1 Schematic diagram of a BMS structure according to an embodiment of the present application.

[0024] According to one embodiment, Figure 1 The illustrated BMS 100 may include a battery management unit (BMU) 110 .

[0025] According to one embodiment, Figure 1 The illustrated BMU 110 may include a micro control unit (MCU) 111 .

[0026] According to one embodiment, Figure 1 The illustrated BMS 100 may include cell monitoring units (CMUs) 121 and CMUs 122 .

[0027] According to one embodiment, Figure 1 The illustrated CMU 121 may include an AFE chip 131 and an AFE chip 132 .

[0028] According to one embodiment, the AFE chip 131 is electrically connected to the BMU 110 .

[0029] According to one embodiment, the AFE chip 131 is electrically connected to the AFE chip 132 in series.

[0030] According to one embodiment, Figure 1 The illustrated CMU 122 may include an AFE chip 133 and an AFE chip 134 .

[0031] According to one embodiment, the AFE chip 132 is electrically connected to the AFE chip 133 in series.

[0032] According to one embodiment, the AFE chip 133 is electrically connected to the AFE chip 134 in series.

[0033] According to one embodiment, the AFE chip 134 is electrically connected to the BMU 110 .

[0034] That is to say, among the multiple AFE chips connected in series, only the two AFE chips at the two ends are electrically connected to the BMU respectively.

[0035] According to one embodiment, Figure 1 The BMS 100 shown may include a battery module 140, which may include a plurality of battery cell groups, each of which is electrically connected to an AFE chip; for example: Figure 1 In the illustrated BMS 100 , the battery module 140 may include four battery cell groups (not shown), and each battery cell group is electrically connected one-to-one with the AFE chips 131 to 134 .

[0036] According to one embodiment, the AFE chips 131 to 134 are configured to respectively sample cell data of corresponding cell groups electrically connected to themselves under the control of the MCU 111 , such as cell voltage, cell current, sensor data, etc.

[0037] According to one embodiment, the MCU 111 in the BMU 110 is configured to send instructions to the AFE chip 131 or the AFE chip 134, obtain data of all cells in the battery module 140, and monitor and evaluate the status of the battery module 140 in real time based on the cell data.

[0038] According to one embodiment, the evaluation of the battery module 140 status may include: state of charge estimation (SOC), state of health estimation (SOH), state of safety estimation (SOS), state of function estimation (SOF), and state of available energy estimation (SOE), etc.

[0039] According to one embodiment, the BMS of the present application may include at least one CMU.

[0040] According to one embodiment, the BMS of the present application may include at least two AFE chips, and the at least two AFE chips may be included in the same CMU or in different CMUs.

[0041] Figure 2 According to an embodiment of the present application Figure 1 Schematic diagram of the synchronous sampling method flow chart of BMS shown.

[0042] S101 : When the MCU 111 in the BMU 110 needs to monitor the cell data, the AFE chips 131 to 134 are powered on or awakened.

[0043] S102 : The MCU 111 in the BMU 110 initializes the AFE chips 131 to 134 .

[0044] For the purpose of reducing power consumption, the AFE chips 131 to 134 are generally in a default state after being powered on or awakened, and cannot perform effective communication and sampling, so the MCU 111 needs to initialize them.

[0045] According to one embodiment, initialization may include the following steps S1021 to S1023:

[0046] S1021 : the MCU 111 sets the communication direction between the AFE chips 131 to 134 , that is, the order in which the AFE chips 131 to 134 receive the start sampling instruction sent by the MCU 111 .

[0047] According to one embodiment, the communication between the AFE chips 131 to 134 may be performed in the direction of 131-132-133-134. At this time, the instruction of the MCU 111 is first sent to the AFE chip 131, and the AFE chip 131 internally determines whether the instruction needs to be forwarded. If it is determined that the instruction needs to be forwarded, it is forwarded to the AFE chip 132 according to a predetermined protocol, and so on, until the instruction is forwarded to the AFE chip 134.

[0048] According to another embodiment, the communication between the AFE chips 131 to 134 may be performed in the direction of 134-133-132-131. At this time, the instruction of the MCU 111 is first sent to the AFE chip 134, and the AFE chip 134 internally determines whether the instruction needs to be forwarded. If it is determined that the instruction needs to be forwarded, it is forwarded to the AFE chip 133 according to a predetermined protocol, and so on, until the instruction is forwarded to the AFE chip 131.

[0049] According to one embodiment, according to a predetermined communication protocol, the start sampling instruction is transmitted between two adjacent AFE chips with a fixed number of clock cycles T1, namely T1 system clock cycles.

[0050] S1022: MCU 111 sets an address identifier A for each of AFE chips 131 to 134 according to a predetermined protocol and the communication direction set in S1021; wherein the value range of A is a continuous integer starting from 1. The address identifier A of each AFE chip indicates the position of the chip in the sequence of all AFE chips receiving the start sampling instruction. For example: when the communication direction set in S1021 is 131-132-133-134, the address identifier A of AFE chip 131 can be set to 1, the address identifier A of AFE chip 132 can be set to 2, the address identifier A of AFE chip 133 can be set to 3, and the address identifier A of AFE chip 134 can be set to 4.

[0051] S1023: MCU 111 configures a stack number identifier N, and forwards the identifier N to all AFE chips according to a predetermined protocol and the communication direction set in S1021; wherein N is an integer not less than 2. The stack number identifier N represents the number of all AFE chips in the BMS; for example: Figure 1 In the BMS 100 shown, the number of stacks N=4.

[0052] S103: The AFE chips 131 to 134 calculate their corresponding delayed clock cycle number M according to the parameters received in the above initialization, such as communication direction, address identifier A, stack number identifier N, and clock cycle number T1; wherein,

[0053] M = T1 × (N - A) (1)

[0054] Wherein, M is an integer greater than or equal to zero.

[0055] According to one embodiment, when the communication direction is 131-132-133-134, the MCU 111 triggers a sampling, and the order of receiving the start sampling instruction is from the AFE chip 131 to the AFE chip 134. In order to achieve synchronous sampling, it is necessary to wait for the corresponding number of delayed clock cycles M for the sampling start time of the AFE chips 131 to 133, so that the sampling start time of the AFE chips 131 to 133 is synchronized with the sampling start time of the AFE chip 134.

[0056] According to one embodiment, when the communication direction is 134-133-132-131, the MCU 111 triggers a sampling, and the order of receiving the start sampling instruction is from the AFE chip 134 to the AFE chip 131. In order to achieve synchronous sampling, it is necessary to wait for the corresponding number of delayed clock cycles M for the sampling start time of the AFE chips 134 to 132, so that the sampling start time of the AFE chips 134 to 132 is synchronized with the sampling start time of the AFE chip 131.

[0057] According to other embodiments, the corresponding delayed clock cycle number M of each AFE chip may also be calculated by the MCU and then forwarded to each AFE chip respectively. In this case, the MCU only needs to send the corresponding delayed clock cycle number M to each AFE chip without sending the initialization parameters.

[0058] S104: MCU 111 sends a start sampling instruction as needed. After receiving the instruction, each AFE chip starts its own delay counter. When its own delay counter counts to M, the AFE chip automatically starts sampling.

[0059] According to one embodiment, all AFE chips in the BMS will start sampling synchronously, with the synchronization accuracy within one clock cycle.

[0060] S105 : After the sampling is completed, the AFE chips 131 to 134 update their respective states and sampled cell data, and the MCU 111 obtains the cell data after synchronous sampling by the AFE chips 131 to 134 according to a predetermined communication protocol.

[0061] Figure 3 Schematic diagram of a BMS structure according to an embodiment of the present application.

[0062] According to one embodiment, Figure 3 The illustrated BMS 200 may include a BMU 210 .

[0063] According to one embodiment, Figure 3 The illustrated BMU 210 may include an MCU 211 .

[0064] According to one embodiment, Figure 3 The illustrated BMS 200 may include a CMU 221 and a CMU 222 .

[0065] According to one embodiment, Figure 3 The illustrated CMU 221 may include an AFE chip 231 and an AFE chip 232 .

[0066] According to one embodiment, the AFE chip 231 is electrically connected to the BMU 210 .

[0067] According to one embodiment, the AFE chip 232 is electrically connected to the BMU 210 .

[0068] According to one embodiment, Figure 3 The illustrated CMU 222 may include an AFE chip 233 and an AFE chip 234 .

[0069] According to one embodiment, the AFE chip 233 is electrically connected to the BMU 210 .

[0070] According to one embodiment, the AFE chip 234 is electrically connected to the BMU 210 .

[0071] That is to say, the multiple AFE chips are electrically connected to the BMU respectively, but the multiple AFEs are not electrically connected to each other.

[0072] According to one embodiment, Figure 3 The BMS 200 shown may include a battery module 240, which may include a plurality of battery cell groups, each of which is electrically connected to an AFE chip; for example: Figure 3The BMS 200 shown may include four battery cell groups (not shown), each of which is electrically connected one-to-one with the AFE chips 231 to 234 .

[0073] According to one embodiment, the AFE chips 231 to 234 are configured to respectively sample the cell data of the corresponding cell groups connected to themselves under the control of the MCU 111 , for example, cell voltage, cell current, sensor data, etc.

[0074] According to one embodiment, the MCU 211 in the BMU 210 is configured to send instructions to the AFE chips 231 to 234 and obtain data of all cells in the battery module 240 , and monitor and evaluate the status of the battery module 240 in real time based on the cell data.

[0075] According to one embodiment, the evaluation of the battery module 240 status may include: state of charge estimation (SOC), state of health estimation (SOH), state of safety estimation (SOS), state of function estimation (SOF), and state of available energy estimation (SOE), etc.

[0076] According to one embodiment, the BMS of the present application may include at least one CMU.

[0077] According to one embodiment, the BMS of the present application may include at least two AFE chips, and the at least two AFE chips may be included in the same CMU or in different CMUs.

[0078] Figure 4 According to an embodiment of the present application Figure 3 Schematic diagram of the synchronous sampling method flow chart of BMS shown.

[0079] S201 : When the MCU 211 in the BMU 210 needs to monitor the cell data, the AFE chips 231 to 234 are powered on or awakened.

[0080] S202 : The MCU 211 in the BMU 210 performs an initialization operation on the AFE chips 231 to 234 .

[0081] For the purpose of reducing power consumption, the AFE chips 231 to 234 are generally in a default state after being powered on or awakened, and cannot perform effective communication and sampling, so the MCU 211 needs to initialize them.

[0082] According to one embodiment, initialization may include the following steps S2021 to S2024:

[0083] S2021: The MCU 211 sets a triggering sequence for sending a start sampling instruction to all AFE chips, that is, the sequence in which the AFE chips 231 to 234 receive the start sampling instruction.

[0084] According to one embodiment, the triggering sequence between the AFE chips 231 to 234 may be from 231 - 232 - 233 - 234. At this time, when the MCU 211 sends instructions, it will send them one by one in the order from the AFE chip 231 to the AFE chip 234.

[0085] According to another embodiment, the triggering sequence between the AFE chips 231 to 234 may be from 234-233-232-231. At this time, when the MCU 211 sends instructions, it will send them one by one in the order from the AFE chip 234 to the AFE chip 231.

[0086] According to an embodiment, the triggering sequence may also be other sequences, and the triggering sequence is irrelevant to the physical arrangement sequence of the AFE chips.

[0087] S2022: MCU 211 sets an address identifier A for each AFE chip 231 to 234 according to a predetermined protocol and the trigger sequence set in S2021; wherein the value range of A is a continuous integer starting from 1. The address identifier A of each AFE chip indicates the position of the chip in the trigger sequence. For example: when the trigger sampling sequence set in S2021 is from 231-232-233-234, the address identifier A of AFE chip 231 can be set to 1, the address identifier A of AFE chip 232 can be set to 2, the address identifier A of AFE chip 233 can be set to 3, and the address identifier A of AFE chip 234 can be set to 4.

[0088] S2023: MCU 211 configures the stack number identifier N, and forwards the identifier N to all AFE chips according to the predetermined protocol and the trigger sampling sequence set in S2021; wherein N is an integer not less than 2. The stack number identifier N represents the number of all AFE chips in the BMS, for example: Figure 3 In the BMS 200 shown, the number of stacks N=4.

[0089] S2024: The MCU 211 sets the number of interval clock cycles P, and forwards the number of interval clock cycles P to all AFE chips according to the triggering sequence set in S2021.

[0090] According to one embodiment, based on Figure 3The connection mode of the BMU 210 and each AFE chip in the BMS 200 shown in the figure, the interval clock cycle number P is the interval clock cycle number of the MCU 211 in the BMU 210 sending the start sampling instruction to the front and rear two AFE chips according to the trigger sequence set in S2021, that is, P system clock cycles.

[0091] S203: The AFE chips 231 to 234 calculate their corresponding delayed clock cycle number M according to the parameters received in the above initialization, such as trigger sequence, address identifier A, stack number identifier N, and interval clock cycle number P; wherein,

[0092] M=P×(N-A) (2)

[0093] Wherein, M is an integer greater than or equal to zero.

[0094] According to one embodiment, when the triggering sequence is from 231-232-233-234, the MCU 211 triggers a sampling, and the order of receiving the start sampling instruction is from the AFE chip 231 to the AFE chip 234. In order to achieve synchronous sampling, the sampling start time of the AFE chips 231 to 233 needs to wait for their corresponding number of delayed clock cycles M, so that the sampling start time of the AFE chips 231 to 233 is synchronized with the sampling start time of the AFE chip 234.

[0095] According to one embodiment, when the triggering sequence is from 234-233-232-231, the MCU 211 triggers a sampling, and the order of receiving the start sampling instruction is from the AFE chip 234 to the AFE chip 231. In order to achieve synchronous sampling, the sampling start time of the AFE chips 234 to 232 needs to wait for their own corresponding number of delayed clock cycles M, so that the sampling start time of the AFE chips 234 to 232 is synchronized with the sampling start time of the AFE chip 231.

[0096] According to other embodiments, the corresponding delayed clock cycle number M of each AFE chip may also be calculated by the MCU and then forwarded to each AFE chip respectively. In this case, the MCU only needs to send the delayed clock cycle number M to each AFE chip without sending the initialization parameter.

[0097] S204: MCU 211 sends a start sampling instruction as needed. After receiving the instruction, each AFE chip starts its own delay counter. When its own delay counter counts to M, the AFE chip automatically starts sampling.

[0098] According to one embodiment, all AFE chips in the BMS will start sampling synchronously, with the synchronization accuracy within one clock cycle.

[0099] S205 : After the sampling is completed, the AFE chips 231 to 234 update their respective states and sampled cell data, and the MCU 211 obtains the cell data after synchronous sampling by the AFE chips 231 to 234 according to a predetermined communication protocol.

[0100] The battery management system proposed in this application enables synchronous sampling of all AFE chips in the system, and has a simple structure without adding additional chips or circuits. The battery management method proposed in this application is a method for automatically realizing synchronous sampling built into each AFE chip. While the MCU in the BMU completes the initialization operation of all AFE chips, each AFE chip adaptively adjusts its own synchronous sampling delay, thereby achieving automatic synchronous sampling with higher accuracy.

[0101] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A battery management system, comprising: MCU; Multiple battery packs; A plurality of AFE chips are electrically connected to the plurality of battery cell groups one by one, and are configured to respectively sample and report the battery cell data of the plurality of battery cell groups under the control of the MCU; Wherein, after receiving the start sampling instruction of the MCU and before sampling the multiple battery cell groups, at least one of the multiple AFE chips is configured to wait for a corresponding number of delayed clock cycles; The corresponding number of delayed clock cycles is based at least on the number of the plurality of AFE chips, the sequence in which the plurality of AFE chips receive the start sampling instruction, and the position of each AFE chip in the sequence; wherein a plurality of first AFE chips among the plurality of AFE chips are electrically connected to the MCU respectively, and for the first AFE chip, the corresponding number of delayed clock cycles is also based on the number of interval clock cycles between the MCU sending the start sampling instruction to the two first AFE chips at the front and back; The MCU is configured to calculate the number of delayed clock cycles and send the number of delayed clock cycles to each AFE chip before sending the start sampling instruction. 2 . The system according to claim 1 , wherein the last AFE chip to receive the start sampling instruction is configured to wait for a corresponding number of delay clock cycles to be zero before sampling the battery cell group electrically connected thereto.

3. The system according to claim 2, wherein a plurality of second AFE chips among the plurality of AFE chips are respectively electrically connected in series with the corresponding first AFE chip, and the corresponding number of delayed clock cycles is also based on the number of clock cycles for transmitting the start sampling instruction between two adjacent series-connected AFE chips.

4. The system according to claim 1, wherein the number of delayed clock cycles that the multiple first AFE chips need to wait for includes the product of the difference between the number of the multiple first AFE chips and the position of the current first AFE chip in the sequence of the multiple first AFE chips receiving the start sampling instruction and the number of interval clock cycles between the MCU sending the start sampling instruction to the previous and next two first AFE chips.

5. The system according to claim 3, wherein the number of delayed clock cycles that the first AFE chip and the second AFE chip in series need to wait for comprises the product of the difference between the number of the first AFE chips and the second AFE chips in series and the position of the current AFE chip in the sequence of receiving the start sampling instruction by the first AFE chip and the second AFE chip in series and the number of clock cycles for transmitting the start sampling instruction between adjacent AFE chips in series.

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