Electronic paper array substrate and display device
By using amorphous silicon as the active layer material of the gate circuit transistor in the electronic paper array substrate, the problem that metal oxide Oxide is difficult to stably output high gate driving voltage is solved, and stable driving and efficient display are achieved.
Patent Information
- Application Number
- CN202411864313.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-02-07
AI Technical Summary
As a semiconductor material of the gate driving circuit, metal oxide Oxide is difficult to stably output a higher gate driving voltage for a long time, resulting in abnormal display.
Amorphous silicon is used as the active layer material of the gate circuit transistor, and the active layer material of the pixel transistor is different, reducing the risk of burning the gate circuit transistor during high-voltage driving.
The stable output of the gate driving circuit is realized, display abnormalities are avoided, and the refresh frequency and power consumption performance of electronic paper are improved.
Smart Images
Figure CN119395920A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technology, and in particular to an electronic paper array substrate and a display device. Background Art
[0002] With the rapid development of display technology, display panels are increasingly developing in the direction of high charging rate, low power consumption, and lightness. Among them, GOA (Gate Driver on Array) technology integrates the TFT (Thin Film Transistor) gate drive circuit on the array substrate of the electronic paper display to form a drive for the display panel, which can save a lot of wiring space and achieve a narrow frame. In order to meet the fast refresh and full-color display requirements of electronic paper displays, high-mobility metal oxide Oxide is usually used as a semiconductor material, but Oxide as a semiconductor material for the gate drive circuit cannot stably output a high gate drive voltage for a long time, and display abnormalities are prone to occur. Summary of the invention
[0003] The electronic paper array substrate provided in the embodiment of the present disclosure includes:
[0004] A substrate, comprising a display area and a non-display area;
[0005] A plurality of pixels are located in the display area of the base substrate; the pixels include pixel transistors and pixel electrodes connected to the pixel transistors;
[0006] A gate driving circuit is located in the non-display area of the substrate; the gate driving circuit includes a gate circuit transistor, the material of the active layer of the gate circuit transistor is amorphous silicon, and the material of the active layer of the pixel transistor is different from the material of the active layer of the gate circuit transistor.
[0007] In some examples, the material of the active layer of the pixel transistor is a metal oxide semiconductor material.
[0008] In some examples, the metal oxide semiconductor material includes: indium gallium zinc oxide.
[0009] In some examples, the gate of the gate circuit transistor is located between the active layer of the gate circuit transistor and the substrate, and the source and drain of the gate circuit transistor are located on a side of the active layer of the gate circuit transistor away from the substrate;
[0010] The gate of the pixel transistor is located between the active layer of the pixel transistor and the substrate, and the source and drain of the pixel transistor are located on a side of the active layer of the pixel transistor away from the substrate;
[0011] The gate of the gate circuit transistor is in the same layer and material as the source and drain of the pixel transistor.
[0012] In some examples, the gate of the gate circuit transistor is located between the active layer of the gate circuit transistor and the substrate, and the source and drain of the gate circuit transistor are located on a side of the active layer of the gate circuit transistor away from the substrate;
[0013] The gate of the pixel transistor is located between the active layer of the pixel transistor and the substrate, and the source and drain of the pixel transistor are located on a side of the active layer of the pixel transistor away from the substrate;
[0014] The source and drain of the gate circuit transistor are in the same layer and material as the gate of the pixel transistor.
[0015] In some examples, a semiconductor material layer is further included, the semiconductor material layer being located between the gate of the pixel transistor and the substrate;
[0016] The orthographic projection of the gate of the pixel transistor on the substrate covers the orthographic projection of the semiconductor material layer on the substrate.
[0017] In some examples, the semiconductor material layer is made of the same layer and material as the active layer of the gate circuit transistor.
[0018] In some examples, the gate driving circuit includes at least two gate circuit transistors, one gate circuit transistor of the at least two gate circuit transistors is electrically connected to another gate circuit transistor via a connection layer;
[0019] The connection layer is in the same layer and material as the source and drain of the pixel transistor.
[0020] In some examples, one of the source and drain of the pixel transistor is connected to the pixel electrode through a first transfer layer, and the first transfer layer is located between a layer where the source and drain of the pixel transistor are located and a layer where the pixel electrode is located;
[0021] The orthographic projection of the pixel electrode on the base substrate covers the orthographic projection of the first transfer layer on the base substrate.
[0022] In some examples, a first insulating layer is also included, where the first insulating layer is located between the layer where the source and drain of the pixel transistor are located and the first transfer layer, and the first transfer layer is connected to one of the source and drain of the pixel transistor through a first via hole that penetrates the first insulating layer.
[0023] In some examples, a second insulating layer is further included, where the second insulating layer is located between the first transfer layer and the layer where the pixel electrode is located, and the pixel electrode is connected to the first transfer layer through a second via hole penetrating the second insulating layer.
[0024] In some examples, a first common electrode and a second common electrode are stacked and arranged on one side of the pixel transistor;
[0025] The first common electrode and the second common electrode are located between the layer where the pixel electrode is located and the layer where the gate of the pixel transistor is located;
[0026] The first common electrode and the source and drain of the pixel transistor are in the same layer and made of the same material, and the second common electrode and the first transfer layer are in the same layer and made of the same material;
[0027] The second common electrode is connected to the first common electrode through a third via hole penetrating the first insulating layer.
[0028] In some examples, the source and drain of the gate circuit transistor are in the same layer and made of the same material as the first transfer layer.
[0029] In some examples, the first switching layer includes a first sub-switching layer and a second sub-switching layer, and the second sub-switching layer is located between the first sub-switching layer and the pixel electrode.
[0030] A third insulating layer is provided between the layer where the second sub-switch layer is located and the layer where the first sub-switch layer is located, and the second sub-switch layer is connected to the first sub-switch layer via a fourth via hole penetrating the third insulating layer;
[0031] A fourth insulating layer is provided between the layer where the second sub-switch layer is located and the layer where the pixel electrode is located, and the second sub-switch layer is connected to the pixel electrode via a fifth via hole penetrating the fourth insulating layer.
[0032] The electronic paper display device provided by the embodiment of the present disclosure includes the above-mentioned electronic paper array substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 Some structural schematic diagrams of electronic paper array substrates provided by embodiments of the present disclosure;
[0034] Figure 2 Some structural schematic diagrams of shift register units of gate drive circuits in related technologies;
[0035] Figures 3 to 7 Some structural schematic diagrams of electronic paper array substrates provided by embodiments of the present disclosure;
[0036] Figure 8A schematic diagram of a process for preparing an electronic paper array substrate provided in an embodiment of the present disclosure;
[0037] Figures 9 to 20 A schematic diagram of a process for preparing an electronic paper array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.
[0039] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
[0040] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.
[0041] In an electronic paper display device, a gate drive circuit formed by an array substrate drive (Gate Drive on Array, GOA) technology is used to drive the display area, which can achieve a narrow frame. At present, in order to achieve fast refresh and full-color display, electronic paper usually uses high-mobility metal oxide as a semiconductor material. However, when a higher gate drive voltage (for example, 38V) is provided, the semiconductor material of the transistor using metal oxide as the gate drive circuit is easily burned, causing display abnormalities.
[0042] In order to solve the above problems, the embodiments of the present disclosure provide an electronic paper array substrate, in which the active layer of the transistor in the gate drive circuit is made of amorphous silicon, and the active layer of the transistor in the pixel circuit is made of materials other than amorphous silicon, thereby improving the problem of burning of the transistor in the gate drive circuit when outputting a higher gate drive voltage, so that the gate drive circuit can output the gate drive voltage stably and improve display abnormalities.
[0043] In the embodiments of the present disclosure, Figure 1 As shown, the electronic paper array substrate may include:
[0044] The base substrate 1 includes a display area AA and a non-display area BB.
[0045] A plurality of pixels 2 are located in the display area AA of the base substrate 1 ; the pixels 2 include a pixel transistor 21 and a pixel electrode 22 connected to the pixel transistor 21 .
[0046] The gate drive circuit 3 is located in the non-display area BB of the substrate 1; the gate drive circuit 3 includes a gate circuit transistor ( Figure 1 not shown).
[0047] The material of the active layer of the gate circuit transistor is amorphous silicon, and the material of the active layer of the pixel transistor 21 is different from the material of the active layer of the gate circuit transistor.
[0048] The electronic paper array substrate provided in the embodiment of the present disclosure can reduce the risk of burning out of the gate circuit transistor during high-voltage driving by using amorphous silicon as the material of the active layer of the gate circuit transistor and other materials besides amorphous silicon as the material of the active layer of the pixel transistor, thereby enabling the gate driving circuit to stably output the gate driving voltage to the pixel, thereby achieving stable driving of the display area and avoiding display abnormalities.
[0049] The electronic paper array substrate provided by the embodiment of the present disclosure is as follows: Figure 1 As shown, it may further include a plurality of data lines 4 and a plurality of gate lines 5. The plurality of data lines 4 and the plurality of gate lines 5 are arranged to cross each other, and define a plurality of pixel areas.
[0050] Exemplarily, the data line 4 extends along a first direction, the gate line 5 extends along a second direction, and the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction.
[0051] The data line 4 is configured to transmit the data signal to the source of the pixel transistor 21 when the pixel transistor 21 is turned on.
[0052] The gate line 5 is configured to transmit a gate driving voltage output by the gate driving circuit to the gate of the pixel transistor 21 .
[0053] The gate drive circuit provided by the embodiment of the present disclosure may include a plurality of cascaded shift register units, each of which may include a plurality of transistors, and each transistor may be an N-type transistor or a P-type transistor. Figure 2 As shown, the shift register unit includes transistors T1-T11, wherein the gate of transistor T1 is coupled to the input signal terminal Input, the first electrode is coupled to the first reference signal terminal VDS, and the second electrode is coupled to the first node PU; the gate of transistor T2 is coupled to the reset signal terminal Reset, the first electrode is coupled to the first reference signal terminal VDS, and the second electrode is coupled to the first node PU; the gate of transistor T3 is coupled to the first node PU, the first electrode is coupled to the clock signal terminal CLK, and the second electrode is coupled to the output signal terminal Output; the gate of transistor T4 is coupled to the frame trigger signal terminal STV, the first electrode is coupled to the second reference signal terminal VGL, and the second electrode is coupled to the first node PU; the gate of transistor T5 is coupled to the second node P, the first electrode is coupled to the first power supply terminal GCH, and the second electrode is coupled to the third node PD; the gate of transistor T6 is coupled to the first node PU, the first electrode is coupled to the first power supply terminal GCH, and the second electrode is coupled to the third node PD; The second reference signal terminal VGL is coupled, and the second electrode is coupled to the third node PD; the gate of transistor T7 is coupled to the second power supply terminal GCL, the first electrode is coupled to the second reference signal terminal VGL, and the second electrode is coupled to the output signal terminal Output; the gate of transistor T8 is coupled to the first node PU, the first electrode is coupled to the second reference signal terminal VGL, and the second electrode is coupled to the second node P; the gate and the first electrode of transistor T9 are coupled to the first power supply terminal GCH, and the second electrode is coupled to the second node P; the gate of transistor T10 is coupled to the third node PD, the first electrode is coupled to the second reference signal terminal VGL, and the second electrode is coupled to the first node PU; the gate of transistor T11 is coupled to the third node PD, the first electrode is coupled to the second reference signal terminal VGL, and the second electrode is coupled to the output signal terminal Output; the first electrode of the capacitor is coupled to the first node PU, and the second electrode is coupled to the signal output terminal Output.
[0054] In specific implementation, according to the flow direction of the signal, the first electrode of the above transistors T1-T11 can be used as its source, and the second electrode can be used as its drain; or, the first electrode can be used as its drain, and the second electrode can be used as its source, without making a specific distinction here.
[0055] Exemplarily, the gate circuit transistor can be any one of the transistors T1-T11, that is, in the embodiment of the present disclosure, the active layer of each transistor T1-T11 in the gate drive circuit 3 can be formed of amorphous silicon, thereby reducing the risk of transistor burning during high-voltage transmission, and enabling the gate drive circuit to stably output a higher gate drive voltage for a long time, so that the pixel can be charged quickly, thereby increasing the refresh frequency, reducing power consumption, and realizing full-color display of the image.
[0056] The above is only an example to illustrate the specific structure of the shift register unit provided in the embodiment of the present invention. In specific implementation, the specific structure of the shift register unit is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.
[0057] In some embodiments of the present disclosure, the material of the active layer of the pixel transistor 21 is a metal oxide semiconductor material, so that when the gate drive circuit provides high-voltage drive, the pixel can be quickly charged, the response time can be shortened, the refresh frequency can be increased, and full-color display of the image can be achieved.
[0058] Exemplarily, the metal oxide semiconductor material includes but is not limited to indium gallium zinc oxide (IGZO). In other embodiments of the present application, the metal oxide semiconductor material may also be other materials, which are not limited here.
[0059] In some embodiments of the present disclosure, Figure 3 As shown, the gate 312 of the gate circuit transistor 31 is located between the active layer 311 of the gate circuit transistor 31 and the substrate 1 , and the source and drain 313 of the gate circuit transistor 31 are located on the side of the active layer 311 of the gate circuit transistor 31 away from the substrate 1 .
[0060] The gate electrode 212 of the pixel transistor 21 is located between the active layer 211 of the pixel transistor 21 and the substrate 1 , and the source and drain electrode 213 of the pixel transistor 21 is located on the side of the active layer 211 of the pixel transistor 21 away from the substrate 1 ;
[0061] The gate 312 of the gate circuit transistor 31 and the source and drain 213 of the pixel transistor 21 are in the same layer and material, so the gate of the gate circuit transistor and the source and drain of the pixel transistor can be formed by the same patterning process, which simplifies the process flow and improves production efficiency.
[0062] For example, Figure 3 As shown, the electronic paper array substrate further includes a gate insulating layer 210, which is located between the gate 212 of the pixel transistor 21 and the active layer of the pixel transistor 21, so that the gate insulating layer 210 can be used to isolate the charge between the gate and the source and drain of the pixel transistor 21, thereby preventing the generation of reverse current and leakage current. The gate insulating layer 210 is also located between the gate 312 of the gate circuit transistor 31 and the base substrate 1, so that the film thickness of the non-display area is kept the same as that of the display area, so that the gate 312 of the gate circuit transistor 31 can be formed by the same patterning process when the source and drain 213 of the pixel transistor 21 are formed later.
[0063] In some embodiments of the present disclosure, Figure 3As shown, one of the source and drain electrodes 213 of the pixel transistor 21 is connected to the pixel electrode 22 through the first transfer layer 215, and the first transfer layer 215 is located between the layer where the source and drain electrodes 213 of the pixel transistor 21 are located and the layer where the pixel electrode 22 is located; the orthographic projection of the pixel electrode 22 on the base substrate 1 covers the orthographic projection of the first transfer layer 215 on the base substrate 1. Therefore, the pixel electrode 22 can be overlapped with the source and drain electrodes 213 of the pixel transistor 21 through the first transfer layer 215.
[0064] Exemplarily, the material of the pixel electrode 22 includes, but is not limited to, a transparent conductive material, such as indium tin oxide (ITO).
[0065] In some embodiments of the present disclosure, Figure 3 As shown, the pixel transistor 21 also includes a first insulating layer 216, which is located between the layer where the source and drain electrodes 213 of the pixel transistor 21 are located and the first transfer layer 215, and the first transfer layer 215 is connected to one of the source and drain electrodes 213 of the pixel transistor 21 through a first via 001 that penetrates the first insulating layer 216.
[0066] By providing the first insulating layer 216 , the charges between the gate and the source and drain of the gate circuit transistor 31 can be isolated, thereby preventing the generation of reverse current and leakage current.
[0067] Exemplarily, the first transfer layer 215 is connected to the source of the pixel transistor 21 through the first via hole 001 penetrating the first insulating layer 216 , or the first transfer layer 215 is connected to the drain of the pixel transistor 21 through the first via hole 001 penetrating the first insulating layer 216 .
[0068] In some embodiments of the present disclosure, Figure 3 As shown, the source and drain 313 of the gate circuit transistor 31 and the first transfer layer 215 are in the same layer and made of the same material, so the source and drain of the gate circuit transistor and the first transfer layer can be formed by the same patterning process, simplifying the process flow and improving production efficiency.
[0069] In some embodiments of the present disclosure, Figure 3 As shown, the pixel transistor 21 further includes a second insulating layer 217 , which is located between the first transfer layer 215 and the layer where the pixel electrode 22 is located. The pixel electrode 22 is connected to the first transfer layer 215 through a second via hole 002 penetrating the second insulating layer 217 .
[0070] Providing the second insulating layer on the first transfer layer can prevent the metal material of the first transfer layer from being corroded by the external environment, such as oxidation, corrosion, etc., thereby ensuring the stability and reliability of the first transfer layer.
[0071] In some embodiments of the present disclosure, Figure 3 As shown, one of the source and drain electrodes of the pixel transistor 21 is connected to the layer where the gate of the pixel transistor 21 is located through a via hole penetrating the gate insulating layer, so that the voltage of the pixel electrode 22 can be provided to the layer where the gate of the pixel transistor 21 is located.
[0072] In some embodiments of the present disclosure, Figure 3 As shown, the pixel 2 further includes a first common electrode 231 and a second common electrode 232 which are stacked and located on one side of the pixel transistor 21 .
[0073] The first common electrode 231 and the second common electrode 232 are located between the layer where the pixel electrode 22 is located and the layer where the gate of the pixel transistor 21 is located.
[0074] The first common electrode 231 and the source / drain 213 of the pixel transistor 21 are in the same layer and made of the same material. The second common electrode 232 and the first transfer layer 215 are in the same layer and made of the same material.
[0075] The second common electrode 232 is connected to the first common electrode 231 through a third via hole 003 penetrating the first insulating layer 216 .
[0076] like Figure 3 As shown, the layer where the gate of the pixel transistor 21 is located, the first common electrode 231, the second common electrode 232, and the pixel electrode 22 are all insulated and spaced apart, and the orthographic projection of the pixel electrode 22 on the base substrate 1 covers the orthographic projection of the first common electrode 231 on the base substrate 1, and the orthographic projection of the pixel electrode 22 on the base substrate 1 covers the orthographic projection of the second common electrode 232 on the base substrate 1. The layer where the gate of the pixel transistor 21 is located can form a storage capacitor with the first common electrode 231, and the pixel electrode 22 can form a storage capacitor with the second common electrode 232.
[0077] In some embodiments of the present disclosure, Figure 3 As shown, at least two storage capacitors can be formed in the pixel 2, so as to improve the voltage stability on the pixel electrode 22, so that the display effect of the electronic paper prepared by using the electronic paper array substrate is better.
[0078] In some embodiments of the present disclosure, Figure 3 As shown, one of the source and drain electrodes of the gate circuit transistor 31 is connected to the layer where the gate of the gate circuit transistor 31 is located through a via hole penetrating the first insulating layer 216, so that the source or drain of the gate circuit transistor can be electrically connected to the gate of other gate circuit transistors, such as Figure 2 As shown, the drain of the gate circuit transistor T8 can be electrically connected to the gate of the gate circuit transistor T5 through the via hole.
[0079] For example, Figure 4As shown, the second insulating layer 217 may include a planarization layer 2171 and an organic material layer 2172, for example, the planarization layer 2171 is located on the side of the first transfer layer 215 away from the base substrate 1, and the organic material layer 2172 is located on the side of the planarization layer 2171 away from the base substrate 1, wherein in the display area, the orthographic projection of the pixel electrode 22 on the base substrate 1 covers the orthographic projection of the organic material layer 2172 on the base substrate 1. The film layer of the electronic paper array substrate can be planarized by the planarization layer, and the organic material layer can reduce the coupling between adjacent signal lines.
[0080] Figure 5 FIG. 2 shows a structural diagram of another electronic paper array substrate provided in an embodiment of the present application. Figure 5 In this embodiment, the implementation method in the above embodiment is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
[0081] In some embodiments of the present disclosure, Figure 5 As shown, the gate 312 of the gate circuit transistor 31 is located between the active layer 311 of the gate circuit transistor and the substrate 1 , and the source and drain 313 of the gate circuit transistor 31 are located on the side of the active layer 311 of the gate circuit transistor 31 away from the substrate 1 .
[0082] The gate 212 of the pixel transistor 21 is located between the active layer 211 of the pixel transistor 21 and the substrate 1 , and the source and drain 213 of the pixel transistor 21 is located on the side of the active layer 211 of the pixel transistor 21 away from the substrate 1 .
[0083] The source and drain 313 of the gate circuit transistor 31 and the gate 212 of the pixel transistor 21 are in the same layer and material, so the source and drain of the gate circuit transistor and the gate of the pixel transistor can be formed by the same patterning process, simplifying the process flow and improving production efficiency.
[0084] For example, Figure 5 As shown, an insulating layer is also included, which is located between the layer where the source and drain of the pixel transistor 21 are located and the layer where the gate of the pixel transistor 21 is located, and can isolate the charges between the gate and the source and drain of the pixel transistor 21 to prevent the generation of reverse current and leakage current.
[0085] Exemplarily, the first insulating layer 216 may include a planarization layer and an organic material layer, wherein the planarization layer is located on the side of the layer where the source and drain of the pixel transistor are located away from the base substrate, and the organic material layer is located on the side of the planarization layer away from the base substrate. The planarization layer can planarize the film layer of the electronic paper array substrate, and the organic material layer can reduce the coupling between adjacent signal lines.
[0086] For example, Figure 5As shown, the electronic paper array substrate may further include a gate insulating layer 210 , a gate 212 of the pixel transistor 21 is located between the gate insulating layer 210 and the active layer 211 of the pixel transistor 21 , and a gate 312 of the gate circuit transistor 31 is located between the gate insulating layer 210 and the base substrate 1 .
[0087] The gate insulating layer 210 is located between the gate 312 and the source and drain 313 of the gate circuit transistor 31, so that the gate insulating layer 210 can be used to isolate the charges between the gate and the source and drain of the gate circuit transistor 31, thereby preventing the generation of reverse current and leakage current. The gate insulating layer 210 is also located between the gate 212 of the pixel transistor 21 and the base substrate 1, so that the film thickness of the display area is kept the same as that of the non-display area, so that the gate 212 of the pixel transistor 21 can be formed by the same patterning process when the source and drain 313 of the gate circuit transistor 31 are formed later.
[0088] Figure 6 FIG. 2 shows a structural diagram of another electronic paper array substrate provided in an embodiment of the present application. Figure 6 In this embodiment, the implementation method in the above embodiment is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
[0089] In some embodiments of the present disclosure, Figure 6 As shown, the first switching layer 215 may include a first sub-switching layer 2151 and a second sub-switching layer 2152, and the second sub-switching layer 2152 is located between the first sub-switching layer 2151 and the pixel electrode 22;
[0090] A third insulating layer 218 is provided between the layer where the second sub-switching layer 2152 is located and the layer where the first sub-switching layer 2151 is located, and the second sub-switching layer 2152 is connected to the first sub-switching layer 2151 via a fourth via hole 004 penetrating the third insulating layer 218;
[0091] A fourth insulating layer 219 is provided between the layer where the second sub-switch layer 2152 is located and the layer where the pixel electrode 22 is located. The second sub-switch layer 2152 is connected to the pixel electrode 22 via a fifth via hole 005 penetrating the fourth insulating layer 219 .
[0092] The pixel electrode is connected to the source and drain of the pixel transistor through the first sub-switching layer and the second sub-switching layer, and the second sub-switching layer is isolated from the first sub-switching layer and the pixel electrode by adding a third insulating layer and a fourth insulating layer to prevent current leakage and short circuit and protect the normal operation of the device.
[0093] For example, Figure 6As shown, the third insulating layer 218 may include a planarization layer 2181 and an organic material layer 2182. For example, the planarization layer 2181 may be located on the side of the first sub-transfer layer 2151 away from the base substrate 1, and the organic material layer 2182 is located on the side of the planarization layer 2181 away from the base substrate 1. The film layer can be planarized by the planarization layer, and the organic material layer can reduce the coupling between adjacent signal lines.
[0094] In some embodiments of the present disclosure, Figure 6 As shown, the pixel 2 may further include a first common electrode 231 , a second common electrode 232 , and a third common electrode 233 which are stacked and located on one side of the pixel transistor 21 .
[0095] The first common electrode 231 , the second common electrode 232 and the third common electrode 233 are located between the layer where the pixel electrode 22 is located and the layer where the gate electrode 212 of the pixel transistor 21 is located.
[0096] The first common electrode 231 and the source and drain 213 of the pixel transistor 21 are in the same layer and material. The second common electrode 232 and the first sub-transfer layer 2151 are in the same layer and material. The third common electrode 233 and the second sub-transfer layer 2152 are in the same layer and material.
[0097] The third common electrode 233 is connected to the second common electrode 232 through a via hole penetrating the third insulating layer 218 , and the second common electrode 232 is connected to the first common electrode 231 through a via hole penetrating the first insulating layer 216 .
[0098] Figure 7 FIG. 2 shows a structural diagram of another electronic paper array substrate provided in an embodiment of the present application. Figure 7 In this embodiment, the implementation method in the above embodiment is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
[0099] In some embodiments of the present disclosure, Figure 7 As shown, the electronic paper array substrate further includes a semiconductor material layer 214, and the semiconductor material layer 214 is located between the layer where the gate electrode 212 of the pixel transistor 21 is located and the base substrate 1;
[0100] The orthographic projection of the gate 212 of the pixel transistor 21 on the base substrate 1 covers the orthographic projection of the semiconductor material layer 214 on the base substrate 1 .
[0101] Illustratively, a semiconductor material layer and a source and drain of a gate circuit transistor are formed using a half-tone mask, so that the non-display (ie, GOA region) transistor channel can be exposed, facilitating subsequent etching processes to form a channel region.
[0102] Exemplarily, the material of the semiconductor material layer 214 is amorphous silicon a-Si.
[0103] In some embodiments of the present disclosure, Figure 7 As shown, the semiconductor material layer 214 and the active layer 311 of the gate circuit transistor 31 are of the same layer and material, so the semiconductor material layer and the active layer of the gate circuit transistor can be formed by the same patterning process, simplifying the process flow and improving production efficiency.
[0104] Exemplarily, the materials of the semiconductor material layer 214 and the active layer 311 of the gate circuit transistor 31 are both amorphous silicon a-Si.
[0105] In some embodiments of the present disclosure, Figure 7 As shown, the gate driving circuit 3 includes at least two gate circuit transistors, and one gate circuit transistor of the at least two gate circuit transistors is electrically connected to another gate circuit transistor through a connection layer 314;
[0106] The connection layer 314 and the source and drain electrodes 213 of the pixel transistor 21 are of the same layer and material, so the connection layer and the source and drain electrodes of the pixel transistor can be formed by the same patterning process, which simplifies the process flow and improves production efficiency.
[0107] For example, Figure 7 As shown, the electronic paper array substrate may further include a planarization layer, which is located between the active layer 211 of the pixel transistor 21 and the layer where the gate 212 is located. This layer can not only planarize the film layer of the electronic paper array substrate, but also isolate the charge between the source, drain and gate of the pixel transistor to prevent the generation of reverse current and leakage current.
[0108] For example, Figure 7 As shown, the connection layer 314 is connected to one of the source and drain electrodes 313 of the gate circuit transistor 31 through the sixth via hole 006 penetrating the planarization layer, and is connected to the gate 312 of the gate circuit transistor 31 through the seventh via hole 007 penetrating the planarization layer, so that the gate of one gate circuit transistor in the gate driving circuit can be connected to the source or drain of another gate circuit transistor through the connection layer 314, for example Figure 2 The transistor T5 and the transistor T8 are shown.
[0109] The disclosed embodiment also provides an electronic paper display device, comprising the electronic paper array substrate described above. Exemplarily, the electronic paper display device further comprises an opposite substrate disposed on the light emitting side of the electronic paper array substrate.
[0110] The present disclosure also provides Figure 7 The preparation method of the electronic paper array substrate shown in Figure 8 As shown, the following steps may be included:
[0111] Step S800: providing a substrate 1, such as Fig. 9 As shown;
[0112] Step S801: forming a gate 312 of a gate circuit transistor 31 in a non-display area of a base substrate 1, such as Fig.10 As shown;
[0113] Step S802: forming a gate insulating layer 210 on the side of the gate 312 of the gate circuit transistor 31 away from the substrate 1, such as Fig.11 As shown;
[0114] Step S803: On the side of the gate insulating layer away from the substrate 1, a semiconductor material layer 214, a gate 212 of the pixel transistor 21, an active layer 311 and a source and drain 313 of the gate circuit transistor 31 are formed by using a half-tone mask. Fig.12 As shown;
[0115] Step S804: forming a planarization layer on the side of the gate electrode 212 of the pixel transistor 21 away from the substrate 1, such as Fig.13 As shown;
[0116] Step S805: forming an active layer 211 of the pixel transistor 21 on the side of the planarization layer away from the base substrate 1, such as Fig.14 As shown;
[0117] Step S806: forming a sixth via hole 006 and a seventh via hole 007 penetrating the planarization layer in the thickness direction of the gate circuit transistor, wherein the seventh via hole 007 also penetrates the gate insulation layer of the non-display area, and forming a via hole penetrating the planarization layer in the thickness direction of the pixel transistor, such as Fig.15 As shown;
[0118] Step S807: forming the source and drain electrodes 213, the first common electrode 231 and the connection layer 314 of the pixel transistor 21 on the side of the active layer 211 of the pixel transistor 21 away from the substrate 1, such as Fig.16 As shown;
[0119] Step S808: forming a first insulating layer 216 on the side of the connecting layer 314 away from the base substrate 1, and forming two via holes penetrating the first insulating layer 216 along the thickness direction of the pixel transistor 21, wherein one of the via holes is a first via hole 001. Fig.17 As shown;
[0120] Step S809: forming a first transfer layer 215 and a second common electrode 232 on a side of the first insulating layer 216 away from the substrate. Fig.18 As shown;
[0121] Step S810: forming a second insulating layer 217 on a side of the first transfer layer 215 away from the base substrate, and forming a second via hole 002 penetrating the second insulating layer 217 along the thickness direction of the pixel transistor 21. Fig.19 As shown;
[0122] Step S811: forming a pixel electrode 22 on the side of the second insulating layer 217 away from the base substrate 1. Fig. 20 shown.
[0123] The electronic paper array substrate and electronic paper display device provided by the embodiments of the present disclosure use different materials to form the active layers of the pixel transistors and the gate circuit transistors, which can reduce the risk of burning out the gate circuit transistors during high-voltage driving, thereby enabling the gate driving circuit to stably output the gate driving voltage to the pixels, thereby achieving stable driving of the display area and avoiding display abnormalities.
[0124] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.
[0125] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.
Claims
1. An electronic paper array substrate, characterized in that: include: A substrate, comprising a display area and a non-display area; A plurality of pixels are located in the display area of the base substrate; The pixel comprises a pixel transistor and a pixel electrode connected to the pixel transistor; A gate driving circuit is located in the non-display area of the substrate; the gate driving circuit includes a gate circuit transistor, the material of the active layer of the gate circuit transistor is amorphous silicon, and the material of the active layer of the pixel transistor is different from the material of the active layer of the gate circuit transistor.
2. The electronic paper array substrate according to claim 1, characterized in that: The material of the active layer of the pixel transistor is a metal oxide semiconductor material.
3. The electronic paper array substrate according to claim 2, characterized in that: The metal oxide semiconductor material includes: indium gallium zinc oxide.
4. The electronic paper array substrate according to claim 3, characterized in that: The gate of the gate circuit transistor is located between the active layer of the gate circuit transistor and the substrate, and the source and drain of the gate circuit transistor are located on a side of the active layer of the gate circuit transistor away from the substrate; The gate of the pixel transistor is located between the active layer of the pixel transistor and the substrate, and the source and drain of the pixel transistor are located on a side of the active layer of the pixel transistor away from the substrate; The gate of the gate circuit transistor is in the same layer and material as the source and drain of the pixel transistor.
5. The electronic paper array substrate according to claim 3, characterized in that: The gate of the gate circuit transistor is located between the active layer of the gate circuit transistor and the substrate, and the source and drain of the gate circuit transistor are located on a side of the active layer of the gate circuit transistor away from the substrate; The gate of the pixel transistor is located between the active layer of the pixel transistor and the substrate, and the source and drain of the pixel transistor are located on a side of the active layer of the pixel transistor away from the substrate; The source and drain of the gate circuit transistor are in the same layer and material as the gate of the pixel transistor.
6. The electronic paper array substrate according to claim 5, characterized in that: Also included is a semiconductor material layer, the semiconductor material layer is located between the gate of the pixel transistor and the substrate; The orthographic projection of the gate of the pixel transistor on the substrate covers the orthographic projection of the semiconductor material layer on the substrate.
7. The electronic paper array substrate according to claim 6, characterized in that: The semiconductor material layer is of the same layer and material as the active layer of the gate circuit transistor.
8. The electronic paper array substrate according to claim 5, characterized in that: The gate driving circuit comprises at least two gate circuit transistors, one gate circuit transistor of the at least two gate circuit transistors is electrically connected to another gate circuit transistor via a connection layer; The connection layer is in the same layer and material as the source and drain of the pixel transistor.
9. The electronic paper array substrate according to claim 4 or 5, characterized in that: One of the source and drain electrodes of the pixel transistor is connected to the pixel electrode through a first transfer layer, and the first transfer layer is located between a layer where the source and drain electrodes of the pixel transistor are located and a layer where the pixel electrode is located; The orthographic projection of the pixel electrode on the base substrate covers the orthographic projection of the first transfer layer on the base substrate.
10. The electronic paper array substrate according to claim 9, characterized in that: It also includes a first insulating layer, which is located between the layer where the source and drain of the pixel transistor are located and the first transfer layer, and the first transfer layer is connected to one of the source and drain of the pixel transistor through a first via hole that penetrates the first insulating layer.
11. The electronic paper array substrate according to claim 10, characterized in that: It also includes a second insulating layer, which is located between the first transfer layer and the layer where the pixel electrode is located, and the pixel electrode is connected to the first transfer layer through a second via hole that penetrates the second insulating layer.
12. The electronic paper array substrate according to claim 10, characterized in that: Also includes a first common electrode and a second common electrode stacked and located on one side of the pixel transistor; The first common electrode and the second common electrode are located between the layer where the pixel electrode is located and the layer where the gate of the pixel transistor is located; The first common electrode and the source and drain of the pixel transistor are in the same layer and made of the same material, and the second common electrode and the first transfer layer are in the same layer and made of the same material; The second common electrode is connected to the first common electrode through a third via hole penetrating the first insulating layer.
13. The electronic paper array substrate according to claim 10, characterized in that: The source and drain of the gate circuit transistor are in the same layer and made of the same material as the first transfer layer.
14. The electronic paper array substrate according to claim 13, characterized in that: The first switching layer includes a first sub-switching layer and a second sub-switching layer, and the layer where the second sub-switching layer is located is located between the layer where the first sub-switching layer is located and the layer where the pixel electrode is located; A third insulating layer is provided between the layer where the second sub-switch layer is located and the layer where the first sub-switch layer is located, and the second sub-switch layer is connected to the first sub-switch layer via a fourth via hole penetrating the third insulating layer; A fourth insulating layer is provided between the layer where the second sub-switch layer is located and the layer where the pixel electrode is located, and the second sub-switch layer is connected to the pixel electrode via a fifth via hole penetrating the fourth insulating layer.
15. An electronic paper display device, characterized in that: The electronic paper array substrate comprises the electronic paper array substrate according to any one of claims 1 to 14.