Preparation method of solar cell, solar cell and photovoltaic module

Abstract

The invention discloses a preparation method of a solar cell, the solar cell and a photovoltaic module. The preparation method comprises the following steps: depositing a first tunneling oxide layer on a silicon substrate; depositing a first intrinsic amorphous silicon layer on the first tunneling oxide layer; depositing a doped amorphous silicon layer on the first intrinsic amorphous silicon layer; and annealing the silicon substrate on which the first tunneling oxide layer, the first intrinsic amorphous silicon layer and the doped amorphous silicon layer are deposited to form a doped polycrystalline silicon layer stacked on the first tunneling oxide layer. Through the characteristic of island-shaped growth of amorphous silicon, the first intrinsic amorphous silicon layer is provided with holes, so that the doped amorphous silicon layer not only can completely cover the first intrinsic amorphous silicon layer, but also can be in direct contact with the first tunneling oxide layer through the holes; therefore, the doping element can achieve a good diffusion effect in the subsequent annealing process, and the working performance of the solar cell can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a method for preparing a solar cell, a solar cell and a photovoltaic module. Background Art

[0002] At present, the back structure of existing solar cells is silicon substrate, tunnel oxide layer, doped polysilicon layer and back passivation layer from inside to outside. Among them, the doped polysilicon layer is doped with a certain concentration of doping elements to change the conductivity of the doped polysilicon layer, thereby realizing the selective transmission of carriers. However, in the process of preparing the doped polysilicon layer, the doping concentration of the doping elements is not easy to control, so that the concentration of the doping elements is too high or too low, resulting in poor tunneling effect and passivation effect of the solar cell, thereby affecting the overall performance of the solar cell. Summary of the invention

[0003] In view of this, the present application provides a method for preparing a solar cell, a solar cell and a photovoltaic module to solve the technical problems of poor tunneling effect and passivation effect of solar cells in the prior art.

[0004] The present application provides a method for preparing a solar cell, the method comprising: depositing a first tunneling oxide layer on a silicon substrate; depositing a first intrinsic amorphous silicon layer on the first tunneling oxide layer, during the deposition process, the first intrinsic amorphous silicon layer covers at least part of the first tunneling oxide layer, and a hole is formed in the part of the first intrinsic amorphous silicon layer that does not cover the first tunneling oxide layer; depositing a doped amorphous silicon layer on the first intrinsic amorphous silicon layer, at least part of the doped amorphous silicon layer can extend into the hole and contact the first tunneling oxide layer; annealing the silicon substrate on which the first tunneling oxide layer, the first intrinsic amorphous silicon layer and the doped amorphous silicon layer are deposited, so as to form a doped polycrystalline silicon layer stacked on the first tunneling oxide layer.

[0005] In the embodiment of the present application, due to the island-like growth characteristics of amorphous silicon, the first intrinsic amorphous silicon layer deposited on the first tunneling oxide layer has holes, so that the doped amorphous silicon layer can not only completely cover the first intrinsic amorphous silicon layer, but also directly contact the first tunneling oxide layer through the holes, so that the doping elements can achieve a good diffusion effect during the subsequent annealing process, which is beneficial to improve the working performance of the solar cell.

[0006] In a possible implementation, the area of ​​the first tunnel oxide layer is S, the contact area between the first intrinsic amorphous silicon layer and the first tunnel oxide layer is S1, and S1 / S satisfies 70%≤S1 / S<100%.

[0007] In a possible implementation, the area of ​​the first tunnel oxide layer is S, the contact area between the doped amorphous silicon layer and the first tunnel oxide layer is S2, and S2 / S satisfies 0%<S2 / S≤25%.

[0008] In a possible embodiment, the hole includes a first hole and a second hole, a portion of the doped amorphous silicon layer extends into the first hole and contacts the first tunneling oxide layer, and another portion of the doped amorphous silicon layer covers the second hole, so that there is a cavity between the first tunneling oxide layer, the first intrinsic amorphous silicon layer and the doped amorphous silicon layer; wherein the area of ​​the first tunneling oxide layer is S, the area of ​​the second hole projected onto the first tunneling oxide layer is S3, and S3 / S satisfies 0%<S3 / S≤5%.

[0009] In a possible implementation manner, before depositing the doped amorphous silicon layer on the first intrinsic amorphous silicon layer, the preparation method further includes: depositing a second tunneling oxide layer on the first intrinsic amorphous silicon layer.

[0010] When depositing a doped amorphous silicon layer on the first intrinsic amorphous silicon layer, the preparation method also includes: depositing a second intrinsic amorphous silicon layer on the second tunneling oxide layer; diffusing elements into the second intrinsic amorphous silicon layer to form a doped amorphous silicon layer stacked on the second tunneling oxide layer; wherein the thickness of the first intrinsic amorphous silicon layer is H1, the thickness of the second intrinsic amorphous silicon layer is H2, and H1 and H2 satisfy H1<H2.

[0011] In a possible implementation, H1 satisfies 10 nm≤H1≤30 nm, the total thickness of the first intrinsic amorphous silicon layer, the second tunnel oxide layer, and the second intrinsic amorphous silicon layer is H3, and H3 satisfies 50 nm<H3.

[0012] In a possible embodiment, the hole includes a first hole and a second hole, the radial dimension of the first hole is D1, and D1 satisfies 5nm<D1≤50nm, the radial dimension of the second hole is D2, and D2 satisfies 0nm<D2≤5nm, and the distance between two adjacent holes is L, and L satisfies 0nm<L≤30nm.

[0013] The present application also provides a solar cell, which includes a silicon substrate, a first tunneling oxide layer and a doped polysilicon layer, wherein the first tunneling oxide layer is located on one side of the silicon substrate, and the doped polysilicon layer is located on a side of the first tunneling oxide layer away from the silicon substrate; wherein, along the thickness direction of the solar cell, the doped polysilicon layer has a plurality of recessed portions on a side facing the first tunneling oxide layer.

[0014] In the embodiment of the present application, a recess is provided on the side of the doped polysilicon layer facing the silicon substrate to shorten the local thickness of the doped polysilicon layer, so that during the operation of the solar cell, the recess can serve as a migration channel for carriers to improve the transmission efficiency of carriers, thereby improving the photoelectric conversion efficiency of the solar cell. In the process of depositing the doped amorphous silicon layer, the doping elements and the film layer materials can be mixed together to simplify the process and improve the preparation efficiency. This preparation method is also convenient for controlling the overall thickness of the solar cell so that the thickness of the solar cell is within a reasonable range.

[0015] In a possible embodiment, the doped polysilicon layer includes a first doped polysilicon layer and a second doped polysilicon layer, and the solar cell also includes a second tunneling oxide layer, and along the thickness direction of the solar cell, the first doped polysilicon layer, the second tunneling oxide layer and the second doped polysilicon layer are sequentially stacked on the first tunneling oxide layer; wherein, along the thickness direction of the solar cell, there is a cavity between the first tunneling oxide layer, the first doped polysilicon layer and the second tunneling oxide layer.

[0016] An embodiment of the present application also provides a photovoltaic module, which includes a cover plate, a packaging layer and a battery string, wherein the battery string is formed by connecting a plurality of solar cells as described in any of the above items, wherein, along the height direction of the photovoltaic module, the packaging layer is connected to one side of the battery string, and the cover plate is connected to the side of the packaging layer away from the battery string.

[0017] In an embodiment of the present application, the cover plate includes a first cover plate and a second cover plate, the encapsulation layer includes a first encapsulation layer and a second encapsulation layer, and along the height direction of the photovoltaic component, the first cover plate, the first encapsulation layer, the battery string, the second encapsulation layer and the second cover plate are stacked in sequence.

[0018] Specifically, the first cover plate and the second cover plate can be transparent and / or opaque cover plates, such as glass cover plates and plastic cover plates, and along the height direction of the photovoltaic module, the surface of each cover plate facing each packaging layer can be a concave-convex surface to increase the utilization rate of incident light.

[0019] Specifically, the photovoltaic module also includes a welding ribbon, which connects two adjacent solar cells to form a cell string, wherein the connection between the solar cells can be partial stacking or splicing.

[0020] Specifically, along the height direction of the photovoltaic module, the two sides of the first packaging layer are respectively in contact with the first cover plate and the battery string, and the two sides of the second packaging layer are respectively in contact with the second cover plate and the battery string, wherein the first packaging layer and the second packaging layer can be organic packaging films such as ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene elastomer (POE) film or polyethylene terephthalate (PET) film.

[0021] Specifically, the photovoltaic module can adopt a side-wrap-around packaging, that is, the side of the photovoltaic module is completely covered and packaged with a packaging film to reduce the possibility of lamination deviation of the photovoltaic module during the lamination process.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 It is a schematic structural diagram of the silicon substrate, the first tunneling oxide layer and the first intrinsic amorphous silicon layer provided by the present application;

[0025] Figure 2 is a schematic structural diagram of the doped amorphous silicon layer provided by the present application in a first embodiment;

[0026] Figure 3 is a schematic structural diagram of the battery cell provided in the present application in the first embodiment;

[0027] Figure 4 is a schematic structural diagram of the doped amorphous silicon layer provided by the present application in a second embodiment;

[0028] Figure 5 It is a schematic diagram of the structure of the battery cell provided in the present application in the second embodiment.

[0029] Description of reference numerals:

[0030] 1-Silicon substrate;

[0031] 2-first tunnel oxide layer;

[0032] 3-a first intrinsic amorphous silicon layer;

[0033] 31-first hole;

[0034] 32-second hole;

[0035] 4-doped amorphous silicon layer;

[0036] 5-second tunnel oxide layer;

[0037] 6-a second intrinsic amorphous silicon layer;

[0038] 7- doped polysilicon layer;

[0039] 71-depression;

[0040] 72-a first doped polysilicon layer;

[0041] 73-a second doped polysilicon layer;

[0042] 74-Cavity.

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION

[0044] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0045] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0046] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0047] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0048] The embodiment of the present application provides a method for preparing a solar cell. Figure 1 , Figure 2 and Figure 3 As shown, the preparation method includes: firstly depositing a first tunneling oxide layer 2 on a silicon substrate 1; then depositing a first intrinsic amorphous silicon layer 3 on the first tunneling oxide layer 2, during the deposition process, the first intrinsic amorphous silicon layer 3 covers at least a portion of the first tunneling oxide layer 2, and a hole is formed in the portion of the first intrinsic amorphous silicon layer 3 not covering the first tunneling oxide layer 2; then depositing a doped amorphous silicon layer 4 on the first intrinsic amorphous silicon layer 3, at least a portion of the doped amorphous silicon layer 4 can extend into the hole and contact the first tunneling oxide layer 2; finally, annealing the silicon substrate 1 on which the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4 are deposited to form a doped polysilicon layer 7 stacked on the first tunneling oxide layer 2.

[0049] In the embodiment of the present application, along the thickness direction of the solar cell, a first tunneling oxide layer 2, a first intrinsic amorphous silicon layer 3 and a doped amorphous silicon layer 4 are first prepared in sequence on one side of the silicon substrate 1, and then the silicon substrate 1 deposited with the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4 is annealed to form a doped polycrystalline silicon layer 7 stacked on the first tunneling oxide layer 2.

[0050] During the deposition of the first intrinsic amorphous silicon layer 3, the island-like growth characteristics of amorphous silicon can be utilized so that a plurality of silicon atoms deposited on the first tunneling oxide layer 2 are combined with each other to form a plurality of independent island structures. The plurality of independent island structures are continuously grown and merged to form the first intrinsic amorphous silicon layer 3 deposited on the first tunneling oxide layer 2.

[0051] Among them, due to the characteristics of island growth, the first intrinsic amorphous silicon layer 3 cannot completely cover the first tunnel oxide layer 2, resulting in the formation of holes in the part of the first intrinsic amorphous silicon layer 3 that does not cover the first tunnel oxide layer 2, and the number of the holes can be multiple, and the multiple holes are distributed at intervals on the first intrinsic amorphous silicon layer 3.

[0052] During the deposition of the doped amorphous silicon layer 4 , the doped amorphous silicon layer 4 can completely cover the first intrinsic amorphous silicon layer 3 , and at least a portion of the doped amorphous silicon layer 4 can extend into the hole and directly contact the first tunneling oxide layer 2 .

[0053] Among them, the doped amorphous silicon layer 4 may include a first part (not marked in the figure) and a second part (not marked in the figure) that are connected, the first part of the doped amorphous silicon layer 4 can extend into the hole of the first intrinsic amorphous silicon layer 3 and directly contact the first tunneling oxide layer 2, and the second part of the doped amorphous silicon layer 4 covers the first intrinsic amorphous silicon layer 3.

[0054] During the annealing process, the crystallinity of the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4 changes from amorphous to polycrystalline, and the doping elements in the doped amorphous silicon layer 4 begin to diffuse toward the silicon substrate 1 to form a doped polycrystalline silicon layer 7 stacked on the first tunneling oxide layer 2.

[0055] Among them, since the first part of the doped amorphous silicon layer 4 extends into the hole of the first intrinsic amorphous silicon layer 3 and is in direct contact with the first tunneling oxide layer 2, the contact area between the doped amorphous silicon layer 4 and the first intrinsic amorphous silicon layer 3 is increased, which is beneficial to improving the efficiency of diffusion of doping elements from the doped amorphous silicon layer 4 to the first intrinsic amorphous silicon layer 3.

[0056] Specifically, the doping elements in the doped amorphous silicon layer 4 can diffuse into the first intrinsic amorphous silicon layer 3 in the thickness direction perpendicular to the solar cell through the first part, and can also diffuse into the first intrinsic amorphous silicon layer 3 in the thickness direction of the solar cell through the second part, so as to improve the diffusion efficiency of the doping elements while making the diffusion depth of the doping elements deeper, so that the concentration of the doping elements can form a better gradient distribution inside the doped polycrystalline silicon layer 7, that is, along the direction of the doped polycrystalline silicon layer 7 toward the silicon substrate 1, the concentration of the doping elements gradually decreases, so that the film layer of the solar cell has a good passivation effect, and the rate of electron-hole recombination is effectively reduced.

[0057] In the process of diffusion of doped elements, since the first part of the doped amorphous silicon layer 4 extends into the hole of the first intrinsic amorphous silicon layer 3 and directly contacts the first tunneling oxide layer 2, a small amount of doped elements can cause a penetration phenomenon in the area where the two are in contact with each other, which is beneficial to the transmission efficiency of carriers, thereby improving the tunneling effect. At the same time, since the second part of the doped amorphous silicon layer 4 covers the first intrinsic amorphous silicon layer 3, the first intrinsic amorphous silicon layer 3 can play a buffering role in the diffusion of a large amount of doped elements, so as to reduce the possibility of a large amount of doped elements passing through the first tunneling oxide layer 2 during the diffusion process, thereby avoiding a large amount of penetration phenomenon on the first tunneling oxide layer 2 and reducing passivation damage.

[0058] In addition, the first tunneling oxide layer 2 and the doped polysilicon layer 7 can form a good passivation contact structure. The doped polysilicon layer 7 can form an energy band bending on the surface of the silicon substrate 1. The first tunneling oxide layer 2 causes the energy band on the surface of the silicon substrate 1 to be asymmetrically offset, so that the potential barrier of the majority carriers is lower than the potential barrier of the minority carriers, so that the majority carriers can easily pass through the first tunneling oxide layer 2, and the minority carriers are not easy to pass through the first tunneling oxide layer 2, thereby realizing the selective transmission of carriers.

[0059] Among them, a good built-in electric field can be formed between the silicon substrate 1 and the doped polysilicon layer 7, so that the minority carriers are separated from the cross-section of the silicon substrate 1, thereby reducing the concentration of minority carriers, and further reducing the electron-hole recombination rate at the interface of the silicon substrate 1, which is beneficial to improving the open circuit voltage and short circuit current of the solar cell, thereby improving the photoelectric conversion efficiency, and improving the photoelectric conversion efficiency of the solar cell.

[0060] Therefore, in this embodiment, through the characteristics of amorphous silicon island growth, the first intrinsic amorphous silicon layer 3 deposited on the first tunneling oxide layer 2 has holes, so that the doped amorphous silicon layer 4 can not only completely cover the first intrinsic amorphous silicon layer 3, but also can directly contact the first tunneling oxide layer 2 through the holes, so that the doping elements can achieve a good diffusion effect during the subsequent annealing process, which is beneficial to improve the working performance of the solar cell.

[0061] In a specific embodiment, Figure 2 As shown, the area of ​​the first tunnel oxide layer 2 is S, the contact area between the first intrinsic amorphous silicon layer 3 and the first tunnel oxide layer 2 is S1, and S1 / S satisfies 70%≤S1 / S<100%.

[0062] In the embodiment of the present application, S1 / S can specifically be 70%, 72%, 74%, 76%, 78%, 80%, 82%, 84%, 86%, 88%, 90%, 92%, 94%, 96%, 98%, etc. And when S1 / S satisfies 70%≤S1 / S<100%, the number of holes on the first intrinsic amorphous silicon layer 3 is moderate, so as to improve the diffusion effect of the doping elements during the annealing process, so that the doping elements can diffuse deeper to form a better gradient distribution, which is conducive to forming a stacked passivation structure with excellent passivation effect and good contact performance, and can effectively reduce the resistance of the contact interface.

[0063] In a specific embodiment, Figure 2 As shown, the contact area between the doped amorphous silicon layer 4 and the first tunnel oxide layer 2 is S2, and S2 / S satisfies 0%<S2 / S≤25%.

[0064] In the embodiment of the present application, S2 / S can be specifically 1%, 3%, 5%, 7%, 9%, 11%, 13%, 15%, 17%, 19%, 21%, 23%, 25%, etc. And when S2 / S satisfies 0%<S2 / S≤25%, the contact area between the doped amorphous silicon layer 4 and the first tunneling oxide layer 2 is moderate, so that in the process of diffusion of the doped elements, a small amount of doped elements can be diffused to the first tunneling oxide layer 2 through the first part of the doped amorphous silicon layer 4, so as to improve the transmission efficiency of carriers by generating a local diffusion phenomenon, and at the same time, a large amount of doped elements can be blocked by the first intrinsic amorphous silicon layer 3 to avoid excessive diffusion phenomenon, reduce passivation damage, and ensure the passivation effect of the film layer.

[0065] In a specific embodiment, Figure 1 , Figure 2 and Figure 3 As shown, the holes include a first hole 31 and a second hole 32, a portion of the doped amorphous silicon layer 4 extends into the first hole 31 and contacts the first tunneling oxide layer 2, and another portion of the doped amorphous silicon layer 4 covers the second hole 32, so that a cavity 74 is provided between the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4.

[0066] In the embodiment of the present application, during the process of depositing the doped amorphous silicon layer 4, the first portion of the doped amorphous silicon layer 4 can only extend into part of the holes of the first intrinsic amorphous silicon layer 3. Specifically, the first portion of the doped amorphous silicon layer 4 can extend into the first hole 31 and contact the first tunneling oxide layer 2. The second portion of the doped amorphous silicon layer 4 covers the first intrinsic amorphous silicon layer 3 and blocks the second hole 32, so that there is a cavity 74 between the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4.

[0067] After the silicon substrate 1 on which the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4 are deposited is annealed to form a doped polysilicon layer 7 stacked on the first tunneling oxide layer 2, the cavity 74 is the recessed portion 71 on the doped polysilicon layer 7, and along the thickness direction of the solar cell, the recessed portion 71 is located on the side of the doped polysilicon layer 7 facing the silicon substrate 1, so as to shorten the local thickness of the doped polysilicon layer 7 and serve as a carrier migration channel to improve the carrier transmission efficiency, thereby improving the photoelectric conversion efficiency of the solar cell. At the same time, the second hole 32 can further reduce the contact area between the doped amorphous silicon layer 4 and the first tunneling oxide layer 2, thereby further avoiding excessive penetration on the first tunneling oxide layer 2, reducing passivation damage, and improving the stability and reliability of the solar cell during operation.

[0068] In a specific embodiment, Figure 2As shown, along the thickness direction of the solar cell, the area of ​​the second hole 32 projected onto the first tunnel oxide layer 2 is S3, and S3 / S satisfies 0%<S3 / S≤5%.

[0069] In the embodiment of the present application, S3 / S can be 1%, 1.2%, 1.4%, 1.6%, 1.8%, 2%, 2.2%, 2.4%, 2.6%, 2.8%, 3%, 3.2%, 3.4%, 3.6%, 3.8%, 4%, 4.2%, 4.4%, 4.6%, 4.8%, 5%, etc. When S3 / S satisfies 0%<S3 / S≤5%, the number of the second holes 32 is moderate to avoid excessive contact area between the doped amorphous silicon layer 4 and the first tunnel oxide layer 2, so as to ensure the passivation effect of the solar cell, and after the annealing is completed, along the thickness direction of the solar cell, the side of the doped polycrystalline silicon layer 7 facing the silicon substrate 1 has a reasonable number of recessed portions 71, so as to ensure the strength and passivation performance of the doped polycrystalline silicon layer 7 itself, so as to reduce the loss of carriers in the transmission process during the operation of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0070] In a specific embodiment, Figure 1 and Figure 2 As shown, the radial dimension of the first hole 31 is D1, and D1 satisfies 5nm<D1≤50nm, the radial dimension of the second hole 32 is D2, and D2 satisfies 0nm<D2≤5nm, and the distance between two adjacent holes is L, and L satisfies 0nm<L≤30nm.

[0071] Specifically, the radial dimension D1 of the first hole 31 can be 5nm, 7nm, 9nm, 10nm, 11nm, 13nm, 15nm, 17nm, 19nm, 20nm, 21nm, 23nm, 25nm, 27nm, 29nm, 30nm, 31nm, 33nm, 35nm, 37nm, 39nm, 40nm, 41nm, 43nm, 45nm, 47nm, 49nm, 50nm, etc.

[0072] When the radial dimension of the first hole 31 is too small (for example, D1 is less than 5 nm), during the deposition of the doped amorphous silicon layer 4, the first portion of the doped amorphous silicon layer 4 is not easy to flow into the first hole 31, so that the first portion of the doped amorphous silicon layer 4 cannot contact the first tunneling oxide layer 2, resulting in a shallow diffusion depth of the doped element, thereby making the overall passivation effect of the solar cell poor. At the same time, due to the barrier property of the first tunneling oxide layer 2, the transmission of carriers is more difficult, thereby making the overall tunneling effect of the solar cell poor.

[0073] When the radial dimension of the first hole 31 is too large (for example, D1 is greater than 50 nm), during the deposition of the doped amorphous silicon layer 4, although the first portion of the doped amorphous silicon layer 4 easily flows into the first hole 31 and directly contacts the first tunneling oxide layer 2, the contact area therebetween is too large, making it easy for the first tunneling oxide layer 2 to expand over a larger area, thereby easily causing large-area passivation damage, and thus making the overall passivation effect of the solar cell relatively poor.

[0074] Therefore, when the radial dimension of the first hole 31 satisfies 5nm<D1≤50nm, the radial dimension of the first hole 31 is moderate, so that the first portion of the doped amorphous silicon layer 4 can flow more smoothly into the first hole 31 during the deposition process and directly contact the first tunneling oxide layer 2. At the same time, it can also avoid the contact area between the two being too large, thereby reducing the possibility of degradation of the performance of the solar cell, so as to ensure the stability and reliability of the solar cell during operation.

[0075] Specifically, the radial dimension D2 of the second hole 32 can be 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm, 2.2nm, 2.4nm, 2.6nm, 2.8nm, 3nm, 3.2nm, 3.4nm, 3.6nm, 3.8nm, 4nm, 4.2nm, 4.4nm, 4.6nm, 4.8nm, 5nm, etc.

[0076] When the radial dimension D2 of the second hole 32 is equal to 0 nm, there is no cavity 74 between the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4 along the thickness direction of the solar cell, so that the carrier transmission efficiency is reduced, thereby reducing the photoelectric conversion efficiency of the solar cell.

[0077] When the radial dimension of the second hole 32 is too large (for example, D2 is greater than 5 nm), during the deposition of the doped amorphous silicon layer 4, the first portion of the doped amorphous silicon layer 4 is likely to flow into the second hole 32 and directly contact the first tunneling oxide layer 2, and is likely to cause the overall strength of the first intrinsic amorphous silicon layer 3 to be reduced, thereby making it possible for the first intrinsic amorphous silicon layer 3 to be damaged, thereby affecting the working performance of the solar cell.

[0078] Therefore, when the radial dimension of the second hole 32 satisfies 0nm<D2≤5nm, there is a cavity 74 between the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4 along the thickness direction of the solar cell. During the operation of the solar cell, the recessed portion 71 (i.e., the cavity 74) can serve as a migration channel for carriers, which is beneficial to improving the transmission efficiency of carriers, thereby improving the photoelectric conversion efficiency of the solar cell. In addition, during the deposition of the doped amorphous silicon layer 4, the strength of the first intrinsic amorphous silicon layer 3 itself can be ensured while avoiding the doped amorphous silicon layer 4 from extending therein, thereby ensuring the stability and reliability of the solar cell during operation.

[0079] In the embodiment of the present application, the distance between two adjacent first holes 31 , the distance between two adjacent second holes 32 , and the distance between adjacent first holes 31 and second holes 32 can all be L.

[0080] Specifically, the distance L between two adjacent holes can be 2nm, 4nm, 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm, 22nm, 24nm, 26nm, 28nm, 30nm, etc. When the distance between two adjacent holes satisfies 0nm<L≤30nm, the holes are distributed more evenly along the thickness direction perpendicular to the solar cell, which is beneficial to ensure the strength of the first intrinsic amorphous silicon layer 3, thereby effectively avoiding the risk of self-damage, so as to improve the stability and reliability of the solar cell during operation.

[0081] In a possible implementation manner, the shape of the hole may be circular or elliptical, or may be a polygonal structure such as a triangle or rectangle.

[0082] In a specific embodiment, Figure 4 and Figure 5 As shown, before depositing the doped amorphous silicon layer 4 on the first intrinsic amorphous silicon layer 3 , the preparation method further includes: depositing a second tunneling oxide layer 5 on the first intrinsic amorphous silicon layer 3 .

[0083] When depositing the doped amorphous silicon layer 4 on the first intrinsic amorphous silicon layer 3 , the preparation method further includes: depositing a second intrinsic amorphous silicon layer 6 on the second tunneling oxide layer 5 ; diffusing elements into the second intrinsic amorphous silicon layer 6 to form the doped amorphous silicon layer 4 stacked on the second tunneling oxide layer 5 .

[0084] The thickness of the first intrinsic amorphous silicon layer 3 is H1, the thickness of the second intrinsic amorphous silicon layer 6 is H2, and H1 and H2 satisfy H1<H2.

[0085] In the embodiment of the present application, in the process of preparing the doped polycrystalline silicon layer 7, the second tunneling oxide layer 5 and the second intrinsic amorphous silicon layer 6 can be deposited in sequence on the side of the first intrinsic amorphous silicon layer 3 away from the first tunneling oxide layer 2, and then elements are diffused into the second intrinsic amorphous silicon layer 6 to form a doped amorphous silicon layer 4. Finally, the silicon substrate 1 deposited with the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3, the second tunneling oxide layer 5 and the doped amorphous silicon layer 4 is annealed to form a doped polycrystalline silicon layer 7 stacked on the first tunneling oxide layer 2.

[0086] Among them, along the thickness direction of the solar cell, the second tunneling oxide layer 5 can divide the doped polysilicon layer 7 into a first doped polysilicon layer 72 and a second doped polysilicon layer 73, and the first doped polysilicon layer 72 is located between the first tunneling oxide layer 2 and the second tunneling oxide layer 5, and the above-mentioned recessed portion 71 is arranged on the side of the first doped polysilicon layer 72 facing the silicon substrate 1. And because the thickness of the first intrinsic amorphous silicon layer 3 is less than the thickness of the second intrinsic amorphous silicon layer 6, after the annealing is completed, the thickness of the first doped polysilicon layer 72 is less than the thickness of the second doped polysilicon layer 73.

[0087] Specifically, during the deposition of the second tunnel oxide layer 5 , the second tunnel oxide layer 5 can completely cover the first intrinsic amorphous silicon layer 3 , and at least a portion of the second tunnel oxide layer 5 can extend into the hole and directly contact the first tunnel oxide layer 2 .

[0088] Among them, the second tunneling oxide layer 5 can also include a first part (not marked in the figure) and a second part (not marked in the figure) that are connected. The first part of the second tunneling oxide layer 5 can extend into the first hole 31 of the first intrinsic amorphous silicon layer 3 and directly contact the first tunneling oxide layer 2. The second part of the second tunneling oxide layer 5 covers the first intrinsic amorphous silicon layer 3 and blocks the second hole 32, so that there is a cavity 74 between the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the second tunneling oxide layer 5.

[0089] At the same time, by depositing the second tunneling oxide layer 5 on the first intrinsic amorphous silicon layer 3, the possibility of the second intrinsic amorphous silicon layer 6 filling the holes in the first intrinsic amorphous silicon layer 3 during the subsequent deposition of the second intrinsic amorphous silicon layer 6 can be avoided, so that the second tunneling oxide layer 5 plays an isolation role to ensure that the finally formed doped polycrystalline silicon layer 7 has a recessed portion 71.

[0090] Specifically, during the deposition of the second intrinsic amorphous silicon layer 6, the second intrinsic amorphous silicon layer 6 can completely cover the second tunnel oxide layer 5, and at least a portion of the second intrinsic amorphous silicon layer 6 can extend into the first hole 31 and directly contact the first portion of the second tunnel oxide layer 5, so that the second intrinsic amorphous silicon layer 6 is tightly fitted to the second tunnel oxide layer 5.

[0091] Among them, the second intrinsic amorphous silicon layer 6 can be deposited on the second tunneling oxide layer 5 using the same preparation method as the first intrinsic amorphous silicon layer 3, but in the process of depositing the second intrinsic amorphous silicon layer 6, the thickness of the second intrinsic amorphous silicon layer 6 needs to be greater than the thickness of the first intrinsic amorphous silicon layer 3 to avoid the possibility of generating holes in the second intrinsic amorphous silicon layer 6 during the formation process, thereby ensuring the structural strength of the second intrinsic amorphous silicon layer 6.

[0092] Specifically, in the process of diffusing elements into the second intrinsic amorphous silicon layer 6, only the second intrinsic amorphous silicon layer 6 can be transformed into the doped amorphous silicon layer 4, so as to better control the amount of input doping element concentration, which is beneficial to improve the control accuracy of the doping element concentration and reduce the possibility of too low or too high doping element concentration.

[0093] During the annealing process, the crystallinity of the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4 changes from amorphous to polycrystalline, and the doping elements in the doped amorphous silicon layer 4 begin to diffuse toward the silicon substrate 1 to form a doped polycrystalline silicon layer 7 stacked on the first tunneling oxide layer 2 and including the second tunneling oxide layer 5.

[0094] Among them, since the first part of the second tunneling oxide layer 5 extends into the first hole 31 of the first intrinsic amorphous silicon layer 3 and is in direct contact with the first tunneling oxide layer 2, the first part of the doped amorphous silicon layer 4 can also extend into the first hole 31, which is beneficial to improving the efficiency of diffusion of doping elements from the doped amorphous silicon layer 4 toward the first intrinsic amorphous silicon layer 3.

[0095] Specifically, the doping elements in the doped amorphous silicon layer 4 can diffuse into the first intrinsic amorphous silicon layer 3 through the first portion through the second tunneling oxide layer 5 in the thickness direction perpendicular to the solar cell, and can also diffuse into the first intrinsic amorphous silicon layer 3 through the second portion through the second tunneling oxide layer 5 in the thickness direction of the solar cell, so as to improve the diffusion efficiency of the doping elements while making the diffusion depth of the doping elements deeper, so that the concentration of the doping elements can form a better gradient distribution inside the doped polycrystalline silicon layer 7, that is, along the direction of the doped polycrystalline silicon layer 7 toward the silicon substrate 1, the concentration of the doping elements gradually decreases, so that the film layer of the solar cell has a good passivation effect, and the rate of electron-hole recombination is effectively reduced.

[0096] During the diffusion of doping elements, since there are two tunneling oxide layers between the doped amorphous silicon layer 4 and the silicon substrate 1, when the first part of the doped amorphous silicon layer 4 extends into the hole of the first intrinsic amorphous silicon layer 3 and directly contacts the second tunneling oxide layer 5, part of the doping elements can cause a diffusion phenomenon in the area where the two are in contact with each other, which is beneficial to the transmission efficiency of carriers, thereby ensuring the tunneling effect of the solar cell and thus ensuring the photoelectric conversion efficiency of the solar cell.

[0097] In a specific implementation, H1 satisfies 10 nm≤H1≤30 nm, the total thickness of the first intrinsic amorphous silicon layer 3 , the second tunneling oxide layer 5 and the second intrinsic amorphous silicon layer 6 is H3, and H3 satisfies 50 nm<H3.

[0098] In the embodiment of the present application, the thickness H1 of the first intrinsic amorphous silicon layer 3 can be 10 nm, 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, 30 nm, etc.

[0099] When the thickness of the first intrinsic amorphous silicon layer 3 is too small (for example, H1 is less than 10 nm), the first intrinsic amorphous silicon layer 3 is too thin, resulting in a large number of holes on the first intrinsic amorphous silicon layer 3, and the radial size of each hole is large. In the subsequent annealing process, more expansion phenomena are likely to occur, resulting in a reduction in the passivation effect of the solar cell.

[0100] When the thickness of the first intrinsic amorphous silicon layer 3 is too large (for example, H1 is greater than 30 nm), the first intrinsic amorphous silicon layer 3 is too thick, so that the first holes 31 on the first intrinsic amorphous silicon layer 3 disappear, the number of the second holes 32 is large, or all the holes disappear, which is easy to affect the diffusion effect of the doping elements during the subsequent annealing process.

[0101] Therefore, when the thickness of the first intrinsic amorphous silicon layer 3 satisfies 10nm≤H1≤30nm, the first intrinsic amorphous silicon layer 3 can have a first hole 31 and a second hole 32 at the same time, so that the first part of the doped amorphous silicon layer 4 can extend into the first hole 31 and directly contact the first tunneling oxide layer 2 or the second tunneling oxide layer 5, which is beneficial to improve the diffusion effect of the doping elements during the annealing process, and cause the contact position of the doped amorphous silicon layer 4 and the tunneling oxide layer to produce a penetration phenomenon, so as to improve the tunneling effect.

[0102] At the same time, the total thickness of the first intrinsic amorphous silicon layer 3, the second tunnel oxide layer 5 and the second intrinsic amorphous silicon layer 6 satisfies 50nm<H3, so that the second intrinsic amorphous silicon layer 6 is thicker than the first intrinsic amorphous silicon layer 3, thereby avoiding the possibility of generating holes in the second intrinsic amorphous silicon layer 6 during the formation process, thereby ensuring the structural strength of the second intrinsic amorphous silicon layer 6.

[0103] In a possible implementation, the thickness H2 of the second intrinsic amorphous silicon layer 6 may be 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, etc.

[0104] The embodiment of the present application also provides a solar cell, such as Figure 3 As shown, the cell comprises a silicon substrate 1, a first tunneling oxide layer 2 and a doped polysilicon layer 7, wherein the first tunneling oxide layer 2 is located on one side of the silicon substrate 1, and the doped polysilicon layer 7 is located on the side of the first tunneling oxide layer 2 away from the silicon substrate 1.

[0105] Wherein, along the thickness direction of the solar cell, a side of the doped polysilicon layer 7 facing the first tunnel oxide layer 2 has a plurality of recessed portions 71 .

[0106] In the embodiment of the present application, a recessed portion 71 is provided on the side of the doped polysilicon layer 7 facing the silicon substrate 1 to shorten the local thickness of the doped polysilicon layer 7, so that during the operation of the solar cell, the recessed portion 71 can serve as a migration channel for carriers, thereby improving the transmission efficiency of carriers and thus improving the photoelectric conversion efficiency of the solar cell.

[0107] In the process of preparing the solar cell provided in this embodiment, a first tunneling oxide layer 2 is first deposited on the silicon substrate 1, and then a first intrinsic amorphous silicon layer 3 is deposited on the first tunneling oxide layer 2, and then a doped amorphous silicon layer 4 is deposited on the first intrinsic amorphous silicon layer 3. Finally, the silicon substrate 1 on which the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3 and the doped amorphous silicon layer 4 are deposited is annealed to form a doped polycrystalline silicon layer 7 stacked on the first tunneling oxide layer 2.

[0108] In the process of depositing the doped amorphous silicon layer 4, the doping elements and the film material can be mixed together to simplify the process and improve the preparation efficiency. This preparation method is also convenient for controlling the overall thickness of the solar cell so that the thickness of the solar cell is within a reasonable range.

[0109] In a specific embodiment, Figure 5 As shown, the doped polysilicon layer 7 includes a first doped polysilicon layer 72 and a second doped polysilicon layer 73, and the solar cell also includes a second tunneling oxide layer 5. Along the thickness direction of the solar cell, the first doped polysilicon layer 72, the second tunneling oxide layer 5 and the second doped polysilicon layer 73 are stacked in sequence on the first tunneling oxide layer 2.

[0110] There is a cavity 74 between the first tunneling oxide layer 2 , the first doped polysilicon layer 72 and the second tunneling oxide layer 5 along the thickness direction of the solar cell.

[0111] In the embodiment of the present application, by setting a cavity 74 between the first tunneling oxide layer 2, the first doped polysilicon layer 72 and the second tunneling oxide layer 5, the local thickness of the first doped polysilicon layer 72 can be shortened, so that during the operation of the solar cell, the cavity 74 can serve as a migration channel for carriers to improve the transmission efficiency of carriers, thereby improving the photoelectric conversion efficiency of the solar cell.

[0112] In the process of preparing the solar cell provided in this embodiment, a first tunneling oxide layer 2 is first deposited on the silicon substrate 1, and then a first intrinsic amorphous silicon layer 3 is deposited on the first tunneling oxide layer 2, and then a second tunneling oxide layer 5 is deposited on the first intrinsic amorphous silicon layer 3, and then a second intrinsic amorphous silicon layer 6 is deposited on the second tunneling oxide layer 5, and then doping elements are diffused into the second intrinsic amorphous silicon layer 6 to form a doped amorphous silicon layer 4, and finally the silicon substrate 1 on which the first tunneling oxide layer 2, the first intrinsic amorphous silicon layer 3, the second tunneling oxide layer 5 and the doped amorphous silicon layer 4 are deposited is annealed to form a first doped polycrystalline silicon layer 72, a second tunneling oxide layer 5 and a second doped polycrystalline silicon layer 73 which are sequentially stacked on the first tunneling oxide layer 2.

[0113] Among them, in the process of preparing the doped amorphous silicon layer 4, first preparing the second tunneling oxide layer 5 can avoid the diffusion of silicon atoms into the first intrinsic amorphous silicon layer 3 during the deposition of the second intrinsic amorphous silicon layer 6, thereby reducing the possibility of the second hole 32 disappearing, and further allowing the second hole 32 to form a cavity 74 after annealing is completed.

[0114] At the same time, by first depositing the second intrinsic amorphous silicon layer 6 and then diffusing the doping elements into it, the amount of the input doping elements can be better controlled to reduce the possibility of the doping element concentration being too high or too low, so that the doping elements can achieve a better diffusion effect during the annealing process, thereby improving the working performance of the solar cell.

[0115] In a possible implementation, the first intrinsic amorphous silicon layer 3 and the second intrinsic amorphous silicon layer 6 can be prepared by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), hot-wire chemical vapor deposition (HWCVD), physical vapor deposition (PVD), etc.

[0116] In one possible implementation, chemical vapor deposition (CVD) is used for source deposition, which can not only improve the uniformity of distribution of film materials during the deposition process to deposit a film with uniform thickness, but also reduce the possibility of defects in the film during the deposition process to improve the working performance of the solar cell.

[0117] An embodiment of the present application also provides a photovoltaic module, which includes a cover plate, a packaging layer and a battery string, wherein the battery string is formed by connecting a plurality of solar cells as described in any of the above items, wherein, along the height direction of the photovoltaic module, the packaging layer is connected to one side of the battery string, and the cover plate is connected to the side of the packaging layer away from the battery string.

[0118] In an embodiment of the present application, the cover plate includes a first cover plate and a second cover plate, the encapsulation layer includes a first encapsulation layer and a second encapsulation layer, and along the height direction of the photovoltaic component, the first cover plate, the first encapsulation layer, the battery string, the second encapsulation layer and the second cover plate are stacked in sequence.

[0119] Specifically, the first cover plate and the second cover plate can be transparent and / or opaque cover plates, such as glass cover plates and plastic cover plates, and along the height direction of the photovoltaic module, the surface of each cover plate facing each packaging layer can be a concave-convex surface to increase the utilization rate of incident light.

[0120] Specifically, the photovoltaic module also includes a welding ribbon, which connects two adjacent solar cells to form a cell string, wherein the connection between the solar cells can be partial stacking or splicing.

[0121] Specifically, along the height direction of the photovoltaic module, the two sides of the first packaging layer are respectively in contact with the first cover plate and the battery string, and the two sides of the second packaging layer are respectively in contact with the second cover plate and the battery string, wherein the first packaging layer and the second packaging layer can be organic packaging films such as ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene elastomer (POE) film or polyethylene terephthalate (PET) film.

[0122] Specifically, the photovoltaic module can adopt a side-wrap-around packaging, that is, the side of the photovoltaic module is completely covered and packaged with a packaging film to reduce the possibility of lamination deviation of the photovoltaic module during the lamination process.

[0123] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises: Depositing a first tunneling oxide layer (2) on a silicon substrate (1); Depositing a first intrinsic amorphous silicon layer (3) on the first tunneling oxide layer (2), wherein during the deposition process, the first intrinsic amorphous silicon layer (3) covers at least a portion of the first tunneling oxide layer (2), and a hole is formed in a portion of the first intrinsic amorphous silicon layer (3) not covering the first tunneling oxide layer (2); Depositing a doped amorphous silicon layer (4) on the first intrinsic amorphous silicon layer (3), wherein at least a portion of the doped amorphous silicon layer (4) is able to extend into the hole and contact the first tunneling oxide layer (2); The silicon substrate (1) on which the first tunneling oxide layer (2), the first intrinsic amorphous silicon layer (3) and the doped amorphous silicon layer (4) are deposited is annealed to form a doped polysilicon layer (7) stacked on the first tunneling oxide layer (2).

2. The preparation method according to claim 1, characterized in that: The area of ​​the first tunneling oxide layer (2) is S, the contact area between the first intrinsic amorphous silicon layer (3) and the first tunneling oxide layer (2) is S1, and S1 / S satisfies 70%≤S1 / S<100%.

3. The preparation method according to claim 1, characterized in that: The area of ​​the first tunneling oxide layer (2) is S, the contact area between the doped amorphous silicon layer (4) and the first tunneling oxide layer (2) is S2, and S2 / S satisfies 0%<S2 / S≤25%.

4. The preparation method according to claim 1, characterized in that: The hole comprises a first hole (31) and a second hole (32); a portion of the doped amorphous silicon layer (4) extends into the first hole (31) and contacts the first tunneling oxide layer (2); another portion of the doped amorphous silicon layer (4) covers the second hole (32), so that a cavity (74) is formed between the first tunneling oxide layer (2), the first intrinsic amorphous silicon layer (3) and the doped amorphous silicon layer (4); The area of ​​the first tunnel oxide layer (2) is S, the area of ​​the second hole (32) projected onto the first tunnel oxide layer (2) is S3, and S3 / S satisfies 0%<S3 / S≤5%.

5. The preparation method according to claim 1, characterized in that: Before depositing the doped amorphous silicon layer (4) on the first intrinsic amorphous silicon layer (3), the preparation method further comprises: Depositing a second tunneling oxide layer (5) on the first intrinsic amorphous silicon layer (3); When depositing the doped amorphous silicon layer (4) on the first intrinsic amorphous silicon layer (3), the preparation method further comprises: Depositing a second intrinsic amorphous silicon layer (6) on the second tunneling oxide layer (5); diffusing elements into the second intrinsic amorphous silicon layer (6) to form the doped amorphous silicon layer (4) stacked on the second tunneling oxide layer (5); The thickness of the first intrinsic amorphous silicon layer (3) is H1, the thickness of the second intrinsic amorphous silicon layer (6) is H2, and H1 and H2 satisfy H1<H2.

6. The preparation method according to claim 5, characterized in that: H1 satisfies 10nm≤H1≤30nm, the total thickness of the first intrinsic amorphous silicon layer (3), the second tunneling oxide layer (5) and the second intrinsic amorphous silicon layer (6) is H3, and H3 satisfies 50nm<H3.

7. The preparation method according to any one of claims 1 to 6, characterized in that The holes comprise a first hole (31) and a second hole (32), the radial dimension of the first hole (31) is D1, and D1 satisfies 5nm<D1≤50nm, the radial dimension of the second hole (32) is D2, and D2 satisfies 0nm<D2≤5nm, and the distance between two adjacent holes is L, and L satisfies 0nm<L≤30nm.

8. A solar cell, characterized in that: The battery cell comprises: Silicon substrate (1); A first tunneling oxide layer (2), wherein the first tunneling oxide layer (2) is located on one side of the silicon substrate (1); a doped polysilicon layer (7), the doped polysilicon layer (7) being located on a side of the first tunnel oxide layer (2) facing away from the silicon substrate (1); Wherein, along the thickness direction of the solar cell, the doped polysilicon layer (7) has a plurality of recessed portions (71) on a side facing the first tunneling oxide layer (2).

9. The solar cell according to claim 8, characterized in that: The doped polysilicon layer (7) comprises a first doped polysilicon layer (72) and a second doped polysilicon layer (73); the solar cell further comprises a second tunneling oxide layer (5); along the thickness direction of the solar cell, the first doped polysilicon layer (72), the second tunneling oxide layer (5) and the second doped polysilicon layer (73) are sequentially stacked on the first tunneling oxide layer (2); Wherein, along the thickness direction of the solar cell, a cavity (74) is provided between the first tunneling oxide layer (2), the first doped polysilicon layer (72) and the second tunneling oxide layer (5).

10. A photovoltaic module, characterized in that: The photovoltaic module comprises: Cover plate; Encapsulation layer; A battery string, wherein the battery string is formed by connecting a plurality of solar cells according to any one of claims 8 to 9; Wherein, along the height direction of the photovoltaic module, the encapsulation layer is connected to one side of the battery string, and the cover plate is connected to a side of the encapsulation layer away from the battery string.

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