Back contact solar cell and preparation method thereof

Abstract

The invention discloses a back contact solar cell and a preparation method thereof, the back contact solar cell comprises a semiconductor substrate, the semiconductor substrate is provided with a first surface and a second surface which are opposite to each other, the first surface comprises a plurality of non-groove areas and a plurality of groove areas, the non-groove areas and the groove areas are alternately arranged on the first surface; a tunneling oxide layer and an N-type doped crystalline silicon layer; a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer; and the isolation structure comprises an isolation layer and an isolation groove. According to the invention, the preparation process window of the back contact solar cell is enlarged, the process difficulty is reduced, and the surface passivation effect of the P region is improved, so that the performance of the solar cell can reach the effect equivalent to that of the existing HBC cell structure.

Description

[0001] This case is a divisional application of the parent case with the application number 202211062923.0 and the filing date of August 31, 2022, named "Back Contact Solar Cell and Its Preparation Method". Technical Field The present invention belongs to the technical field of solar cells, and particularly relates to a back contact solar cell and a preparation method thereof. Background Art

[0002] The selective passivation contact technology separates the metal from the semiconductor, avoiding the serious recombination caused by the direct contact between the metal and the semiconductor. At the same time, this selective passivation structure has obvious selectivity for the passage of specific carriers. One type of carrier can effectively pass through while shielding the other type of carrier, avoiding the recombination of the two types of carriers in the electrode collection region, thereby effectively improving the photoelectric conversion efficiency of the solar cell device. The typical representatives of the application of this selective passivation contact structure in solar technology are the tunnel oxide passivated contact solar cell (TOPCon) and the hetero-junction with intrinsic thin-layer (HIT) solar cell. Both of these cell structures are double-sided electrode structures, and the common efficiency bottleneck they face is the unavoidable light shielding caused by the front metal. For the TOPCon structure, the front is still the direct contact between the metal and the silicon substrate, and in addition to light shielding, the problem of serious metal recombination still exists; for the HIT structure, although the front metal recombination is effectively suppressed, the parasitic absorption of the incident light by the amorphous silicon / ITO layer causes a serious loss of the short-circuit current density.

[0003] The interdigitated back contact (IBC) cell technology moves the front electrode of the cell to the back, thus avoiding the light shielding and recombination of the front metal and effectively improving the conversion efficiency of the cell. The TBC (Tunnel oxide Back Contact) or HBC (Hetero-Junction Back Contact) technology that combines the IBC technology with the TOPCon or HJT technology further reduces the recombination of the IBC back metal. In 2017, Kaneka announced a conversion efficiency of up to 26.7% for the HBC cell, demonstrating the strong efficiency advantage of this structure.

[0004] In the traditional HBC cell structure, the back n-region and p-region respectively adopt i / n a-Si:H and i / p a-Si:H to form an interdigitated pattern. During the manufacturing process, the damage of the laser to the n-region and p-region needs to be strictly controlled. Especially for the n-region, the process window of the laser is narrow, which increases the process difficulty. The HBC cell also has the following disadvantages in the manufacturing process: a large amount of masking and demasking techniques are used to form patterns, such as the commonly used photolithography technique in the semiconductor field, with high production costs and great process control difficulty; in terms of fixed equipment investment, the CVD equipment for depositing amorphous silicon thin films has high costs and low production capacity. These aspects restrict the efficiency improvement and cost reduction of the HBC cell and limit its industrial application.

[0005] Since the TOPCon cell process has matured, the TBC cell, which absorbs the key technical processes of the TOPCon cell, has become the most cost-effective IBC cell process route. SunPower and domestic enterprises that have tried to mass-produce IBC cells have all transformed to this technical route. On the basis of the IBC cell structure, the TBC replaces the phosphorus diffusion and boron diffusion doping matrix silicon in the back n-region and p-region structures of the IBC with SiOx / n+ poly Si and SiOx / p+ poly Si structures. This structure solves the serious metal recombination in the n-region and p-region. In addition, this tunneling oxide layer passivation contact structure also effectively suppresses the serious Auger recombination problem caused by the direct doping of impurities in the matrix in the traditional IBC structure. However, the TBC cell has the following disadvantages: the preparation process route is long, and the two high-temperature preparations of p poly and n poly result in serious concentric circles on the silicon wafer. Among them, the p poly passivation is at 10fa, and the n poly can reach 4fa; after the back interdigitated structure is completed, the P-region and N-region need to be isolated separately, and the preparation process is relatively complex. Summary of the Invention

[0006] The present invention aims to solve at least one of the technical problems in the related art to some extent. For this purpose, the object of the present invention is to provide a back-contact solar cell and a preparation method thereof. The present invention not only enlarges the preparation process window of the back-contact solar cell, reduces the process difficulty, but also improves the surface passivation effect of the P-region, so that the energy conversion efficiency Eta, open-circuit voltage Uoc, short-circuit current Isc, fill factor FF, and shunt resistance Rsh of the solar cell can all reach the same effect as the existing HBC cell structure.

[0007] In one aspect of the present invention, a back-contact solar cell is provided. According to an embodiment of the present invention, the back-contact solar cell includes: A semiconductor substrate having opposite first and second surfaces, the first surface including a plurality of non-groove regions and a plurality of groove regions, the non-groove regions and the groove regions being alternately arranged on the first surface; Tunnel through the oxide layer and the N-type doped crystalline silicon layer, the tunnel oxide layer is on the non-groove region, and the N-type doped crystalline silicon layer is on the surface of the tunnel oxide layer away from the semiconductor substrate; The first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer, the N-type doped crystalline silicon layer and the P-type doped amorphous silicon layer have opposite conduction types, the first intrinsic amorphous silicon layer is on the groove region and extends on a partial surface of the N-type doped crystalline silicon layer away from the tunnel oxide layer, and the P-type doped amorphous silicon layer is on the surface of the first intrinsic amorphous silicon layer away from the semiconductor substrate, forming an interleaved stacking region of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer with the tunnel oxide layer and the P-type doped polycrystalline silicon layer; Isolation structure, the isolation structure includes an isolation layer and an isolation groove, the isolation layer is between the first intrinsic amorphous silicon layer and the N-type doped crystalline silicon layer in the interleaved stacking region, and the isolation groove penetrates through the P-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the interleaved stacking region.

[0008] The back-contact solar cell according to the embodiment of the present invention, compared with the HBC cell structure in the prior art, the present invention uses a tunneling oxide layer + n-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in the existing HBC cell structure. Since the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the N region can be reduced during the laser opening process, further increasing the process window and reducing the process difficulty. Compared with the TBC cell structure in the prior art, the present invention uses an intrinsic amorphous silicon layer i-a-Si + p-a-Si layer passivation contact to replace SiO in the existing TBC cell structure x + p-poly-Si, avoiding the problem of serious silicon wafer concentric circles caused by the two high-temperature preparations of p poly and n poly in the TBC cell, thereby improving the surface passivation effect of the P region and improving the electrical performance of the solar cell. Thus, the present invention not only increases the preparation process window of the back-contact solar cell, reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open-circuit voltage Uoc, short-circuit current Isc, fill factor FF, and shunt resistance Rsh of the solar cell can all reach the same effect as the existing HBC cell structure.

[0009] In addition, the back-contact solar cell according to the above embodiment of the present invention may further have the following additional technical features: In some embodiments of the present invention, the non-groove region is a suede structure; and / or, the groove region is a suede structure; and / or, the second surface is a suede structure; and / or, the edge of the groove region in contact with the non-groove region is inclined.

[0010] In some embodiments of the present invention, the back-contact solar cell further includes: a first electrode layer and a second electrode layer. The first electrode layer is on one side of the isolation groove, and the first electrode layer covers the P-type doped amorphous silicon layer. The second electrode layer is on the other side of the isolation groove, and the second electrode layer covers the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer.

[0011] In some embodiments of the present invention, the first electrode layer and the second electrode layer are transparent conductive layers, and the materials of the first electrode layer and the second electrode layer are independently selected from at least one of indium tin oxide, zinc aluminum oxide, indium hydroxide-doped indium oxide, and indium tungsten oxide.

[0012] In some embodiments of the present invention, the isolation layer includes an insulating layer, and the insulating layer is between the first intrinsic amorphous silicon layer and the N-type doped crystalline silicon layer; Or, the isolation layer includes a silicon nitride layer and a PSG layer. The PSG layer is on the surface of the N-type doped crystalline silicon layer away from the tunneling oxide layer, and the silicon nitride layer is on the surface of the PSG layer away from the N-type doped crystalline silicon layer.

[0013] In some embodiments of the present invention, the thickness of the silicon nitride layer is 50 - 110 nm; and / or, the thickness of the PSG layer is 25 - 35 nm.

[0014] In some embodiments of the present invention, the back-contact solar cell further includes a passivation layer. The passivation layer includes a second intrinsic amorphous silicon layer and a silicon nitride passivation layer. The second intrinsic amorphous silicon layer is disposed on the second surface, and the silicon nitride passivation layer is disposed on the surface of the second intrinsic amorphous silicon layer away from the semiconductor substrate.

[0015] In some embodiments of the present invention, the semiconductor substrate is an N-type semiconductor substrate, and the size of the groove region in the width direction is greater than the size of the non-groove region in the width direction; Or, the semiconductor substrate is a P-type semiconductor substrate, and the size of the groove region in the width direction is less than the size of the non-groove region in the width direction.

[0016] In some embodiments of the present invention, the tunneling oxide layer is a tunneling SiO2 layer; and / or, the thickness of the tunneling oxide layer is 1 to 4 nm, preferably 1 to 1.8 nm; and / or, the thickness of the N-type doped crystalline silicon layer is 30 to 250 nm, preferably 40 to 200 nm; and / or, the phosphorus doping concentration in the N-type doped crystalline silicon layer is 8E19 to 5E20 cm -3 , preferably 3 to 9E20 cm -3 ; and / or, the thickness of the first intrinsic amorphous silicon layer is 10 to 20 nm; and / or, the thickness of the P-type doped amorphous silicon layer is 5 to 45 nm, preferably 10 to 20 nm; and / or, the boron doping concentration in the P-type doped amorphous silicon layer is 10e20 cm -3 ~10e21 cm -3 .

[0017] In another aspect of the present invention, the present invention provides a method for manufacturing a back-contact solar cell. According to an embodiment of the present invention, the method includes: Providing a semiconductor substrate having opposite first and second surfaces, the first surface including a plurality of alternately arranged first regions and second regions; Successively forming a tunneling oxide layer, an N-type doped crystalline silicon layer, and an isolation layer on the first surface; Using a laser to open the isolation layer in the second region to expose the semiconductor substrate in the second region, and leaving the tunneling oxide layer and the N-type doped crystalline silicon layer in the first region; Successively forming a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on the surface of the prepared intermediate member away from the second surface; Removing a part of the first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer, and the isolation layer at one end away from the second region, and leaving the first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer to be alternately arranged with the tunneling oxide layer and the N-type doped crystalline silicon layer to form an interleaved overlapping region; Grooving the interleaved overlapping region to form isolation grooves, the isolation grooves penetrating through the P-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the interleaved overlapping region so as to divide the interleaved overlapping region into a first interleaved overlapping region and a second interleaved overlapping region.

[0018] According to the method of an embodiment of the present invention, compared with the preparation process of an HBC cell in the prior art, this method uses a tunneling oxide layer + n-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in the existing HBC cell structure. Since the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the N region can be reduced during the laser opening process, further increasing the process window and reducing the process difficulty. Compared with the preparation process of a TBC cell in the prior art, this method uses an intrinsic amorphous silicon layer i-a-Si + p-a-Si layer passivation contact to replace SiO x + p-poly-Si in the existing TBC cell structure, avoiding the serious problem of silicon wafer concentric circles caused by the two high-temperature preparations of p poly and n poly in the TBC cell, thereby improving the surface passivation effect of the P region and the electrical performance of the solar cell. Thus, this method combines the tunneling oxide layer + n-poly-Si layer passivation and the intrinsic amorphous silicon layer i-a-Si + p-a-Si layer passivation, which not only increases the preparation process window of the back-contact solar cell and reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open-circuit voltage Uoc, short-circuit current Isc, fill factor FF, and shunt resistance Rsh of the solar cell can all reach the same effect as that of the existing HBC cell structure. In addition, this method combines the texturing process with local etching, saving the previous texturing process.

[0019] In addition, the method according to the above embodiment of the present invention may further have the following technical solutions: In some embodiments of the present invention, the method further includes: after exposing the second region, performing alkaline texturing on the semiconductor substrate to form a pyramid-like textured surface structure on the second surface and the second region.

[0020] In some embodiments of the present invention, after forming a pyramid-like textured surface structure on the second surface and the second region, a second intrinsic amorphous silicon layer and a silicon nitride passivation layer are sequentially formed on the second surface.

[0021] In some embodiments of the present invention, after grooving the interleaved stacked region, a first electrode layer is formed on one side of the isolation groove, and the first electrode layer covers the P-type doped amorphous silicon layer. A second electrode layer is formed on the other side of the isolation groove, and the second electrode layer covers the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer.

[0022] In some embodiments of the present invention, a first grid line is formed on a part of the surface of the first electrode layer, and a second grid line is formed on a part of the surface of the second electrode layer.

[0023] In some embodiments of the present invention, the tunneling oxide layer and the N-type doped crystalline silicon layer are deposited by LPCVD.

[0024] In some embodiments of the present invention, the isolation layer includes an insulating layer; Alternatively, the isolation layer includes a silicon nitride layer and a PSG layer, the PSG layer is formed on the surface of the N-type doped crystalline silicon layer away from the tunneling oxide layer, and the silicon nitride layer is formed on the surface of the PSG layer away from the N-type doped crystalline silicon layer.

[0025] In some embodiments of the present invention, a part of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer at one end away from the second region are removed by laser, and the power of the laser is 6 - 15W.

[0026] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where: Figure 1 is a schematic structural diagram of a back-contact solar cell according to an embodiment of the present invention; Figure 2 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell according to an embodiment of the present invention; Figure 3 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell according to an embodiment of the present invention; Figure 4 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell according to an embodiment of the present invention; Figure 5 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell according to an embodiment of the present invention; Figure 6 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell according to an embodiment of the present invention; Figure 7 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell according to an embodiment of the present invention; Figure 8 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell according to an embodiment of the present invention; Figure 9 is a schematic structural diagram of an intermediate in the process of manufacturing a back-contact solar cell according to an embodiment of the present invention.

[0028] Reference Signs in the Drawings: 1 - Silicon nitride passivation layer, 2 - Second intrinsic amorphous silicon layer, 3 - Semiconductor substrate, 3-1 - First surface, 3-2 - Second surface, 4 - Tunneling oxide layer, 5 - N-type doped crystalline silicon layer, 6 - Second electrode layer, 7 - Second gate line, 8 - First intrinsic amorphous silicon layer, 9 - P-type doped amorphous silicon layer, 10 - First gate line, 11 - PSG layer, 12 - Insulating layer, 13 - Isolation groove, 14 - First electrode layer, B - Non-groove region, C - Groove region, A - Interleaved stacking region, A1 - First interleaved stacking region, A2 - Second interleaved stacking region. Detailed implementation manners

[0029] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present invention, and should not be construed as a limitation to the present invention.

[0030] In one aspect of the present invention, the present invention provides a back contact solar cell. According to an embodiment of the present invention, with reference to the attached Figure 1, the back-contact solar cell includes: a semiconductor substrate 3 having opposite first and second surfaces 3-1 and 3-2, the first surface 3-1 including a plurality of non-grooved regions (Region B) and a plurality of grooved regions (Region C), the non-grooved regions (Region B) and the grooved regions (Region C) being alternately arranged on the first surface 3-1, and the distance between the non-grooved region and the center line of the semiconductor substrate in the width direction being greater than the distance between the grooved region and the center line of the semiconductor substrate in the width direction; a tunneling oxide layer 4 and an N-type doped crystalline silicon layer 5, the tunneling oxide layer 4 being on the non-grooved region (Region B), and the N-type doped crystalline silicon layer 5 being on the surface of the tunneling oxide layer 4 away from the semiconductor substrate 3; a first intrinsic amorphous silicon layer 8 and a P-type doped amorphous silicon layer 9, the N-type doped crystalline silicon layer 5 and the P-type doped amorphous silicon layer 9 having opposite conduction types, the first intrinsic amorphous silicon layer 8 being on the grooved region (Region C) and extending on a partial surface of the N-type doped crystalline silicon layer 5 away from the tunneling oxide layer 4, and the P-type doped amorphous silicon layer 9 being on the surface of the first intrinsic amorphous silicon layer 8 away from the semiconductor substrate 3, forming an interleaved stacked region of the first intrinsic amorphous silicon layer 8 and the P-type doped amorphous silicon layer 9 with the tunneling oxide layer 4 and the P-type doped polycrystalline silicon layer; an isolation structure including an isolation layer and an isolation groove 13, the isolation layer being between the first intrinsic amorphous silicon layer 8 and the N-type doped crystalline silicon layer 5 in the interleaved stacked region, and the isolation groove 13 penetrating through the P-type doped amorphous silicon layer 9 and the first intrinsic amorphous silicon layer 8 in the interleaved stacked region. Thus, compared with the HBC cell structure in the prior art, the present invention uses a tunneling oxide layer + n-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in the existing HBC cell structure. Since the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the N region can be reduced during the laser opening process, further increasing the process window and reducing the process difficulty. Compared with the TBC cell structure in the prior art, the present invention uses an intrinsic amorphous silicon layer i-a-Si + p-a-Si layer passivation contact to replace SiO x + p-poly-Si in the existing TBC cell structure, avoiding the serious problem of silicon wafer concentric circles caused by the two high-temperature preparations of p poly and n poly in the TBC cell, thereby improving the surface passivation effect of the P region and the electrical performance of the solar cell. Thus, this application not only increases the preparation process window of the back-contact solar cell, reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open-circuit voltage Uoc, short-circuit current Isc, fill factor FF, and shunt resistance Rsh of the solar cell can all achieve effects comparable to those of the existing HBC cell structure.

[0031] In an embodiment of the present invention, the distance between the non-groove region and the center line of the semiconductor substrate in the width direction is greater than the distance between the groove region and the center line of the semiconductor substrate in the width direction, that is, the groove region (Region C) is recessed into the non-groove region (Region B). The reason is that during the preparation process of the back-contact solar cell, the groove region (Region C) is subjected to texturing etching, thereby forming the depression of the groove region (Region C). Therefore, the boundary region between the groove region (Region C) and the non-groove region (Region B) is discontinuous. For example, the groove region (Region C) and the non-groove region (Region B) are vertically misaligned. And the interface between the groove region (Region C) and the non-groove region (Region B) is inclined (that is, the edge of the groove region in contact with the non-groove region is inclined). The reason for its formation is that wet etching is used for local texturing, resulting in the depression of the laser region and the formation of a textured surface.

[0032] It should be explained that the back-contact solar cell includes a plurality of non-groove regions (Region B) and a plurality of groove regions (Region C). The non-groove regions (Region B) and the groove regions (Region C) are alternately arranged on the first surface. Only one non-groove region (Region B) and one groove region (Region C) are schematically drawn in the figure. Figure 1 Only one non-groove region (Region B) and one groove region (Region C) are schematically drawn in the figure.

[0033] In an embodiment of the present invention, the material of the above-mentioned semiconductor substrate 3 can be selected from materials such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs). It should be noted that the first surface 3-1 of the semiconductor substrate 3 refers to the backlight surface, and the second surface 3-2 of the semiconductor substrate 3 refers to the light-facing surface.

[0034] In an embodiment of the present invention, the specific type of the above-mentioned tunneling oxide layer 4 is not particularly limited. As a specific example, the tunneling oxide layer 4 is a tunneling SiO2 layer. According to some specific embodiments of the present invention, the thickness of the tunneling oxide layer 4 is 1 to 4 nm (for example, it can be 1 / 1.8 / 2 / 3 / 4 nm), preferably 1 to 1.8 nm. Thus, by limiting the thickness of the above-mentioned tunneling oxide layer 4 within the above range, a better surface passivation effect can be further ensured, and at the same time, the multi-carrier tunneling effect can be ensured.

[0035] According to still some specific embodiments of the present invention, the thickness of the N-type doped crystalline silicon layer 5 is 30 to 250 nm (for example, it can be 30 / 50 / 100 / 150 / 200 / 250 nm), preferably 40 to 200 nm. Thus, by limiting the thickness of the above-mentioned N-type doped crystalline silicon layer 5 within the above range, while ensuring a better field passivation effect, the poly thickness is minimized as much as possible to reduce parasitic absorption.

[0036] According to yet some specific embodiments of the present invention, the phosphorus doping concentration in the N-type doped crystalline silicon layer 5 is 8E19 to 5E20 cm -3(for example, it can be 8E19 / 9E19 / 1E20 / 2E20 / 3E20 / 4E20 / 5E20 cm -3 ), preferably 3 - 9E20 cm -3 , thus, the phosphorus doping concentration in the N-type doped crystalline silicon layer 5 is limited within the above range, while ensuring a good field passivation effect, it also improves the contact performance between the subsequent metal paste and the poly.

[0037] According to some further specific embodiments of the present invention, the thickness of the first intrinsic amorphous silicon layer 8 is 10 - 20 nm, for example, it can be 10 / 11 / 12 / 13 / 14 / 15 / 16 / 17 / 18 / 19 / 20 nm. Thus, the thickness of the above-mentioned first intrinsic amorphous silicon layer 8 is limited within the above range, which has a good passivation effect on the silicon-based surface.

[0038] According to some further specific embodiments of the present invention, the thickness of the P-type doped amorphous silicon layer 9 is 5 - 45 nm (for example, it can be 5 / 10 / 20 / 30 / 40 / 45 nm), preferably 10 - 20 nm. Thus, the thickness of the above-mentioned P-type doped amorphous silicon layer 9 is limited within the above range, which is beneficial to matching the subsequent laser and cleaning steps.

[0039] According to some further specific embodiments of the present invention, the boron doping concentration in the P-type doped amorphous silicon layer 9 is 10e20 cm -3 ~ 10e21 cm -3 ; (for example, it can be 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10e21 cm -3 ), thus, the boron doping concentration in the P-type doped amorphous silicon layer 9 is limited within the above range, while taking into account the passivation effect, it also has good contact performance.

[0040] According to some further specific embodiments of the present invention, the semiconductor substrate is an N-type semiconductor substrate, and the size of the groove region in the width direction is greater than the size of the non-groove region in the width direction; or, the semiconductor substrate is a P-type semiconductor substrate, and the size of the groove region in the width direction is less than the size of the non-groove region in the width direction. Thus, the series resistance of the back-contact solar cell is further reduced, and the fill factor of the back-contact solar cell is larger.

[0041] According to some further specific embodiments of the present invention, the isolation layer includes an insulating layer 12, and the insulating layer 12 is between the first intrinsic amorphous silicon layer and the N-type doped crystalline silicon layer. In some examples, the insulating layer 12 can be a mask protection layer. The isolation groove 13 penetrates through the first intrinsic amorphous silicon layer 8 and the P-type doped amorphous silicon layer 9 to the mask protection layer. This mask protection layer serves as a laser energy absorption layer, which has the effect of reducing the influence of the laser film opening process on the passivation effect of the corresponding doping region in the non-groove area, and also has the effect of providing a hydrogen source to further passivate the polysilicon and the substrate, improving the passivation effect, and protecting the N-type doped crystalline silicon layer 5 from being corroded by alkali in the texturing process. It should be noted that the isolation groove can penetrate through the above-mentioned insulating layer 12 or not penetrate through the above-mentioned insulating layer 12.

[0042] According to some further specific embodiments of the present invention, the isolation layer includes an insulating layer 12 (such as a silicon nitride layer) and a PSG layer 11. The PSG layer 11 is on the surface of the N-type doped crystalline silicon layer away from the tunneling oxide layer, and the insulating layer 12 is on the surface of the PSG layer 11 away from the N-type doped crystalline silicon layer. In some examples, the isolation layer includes at least one of a silicon nitride layer, an aluminum nitride layer, a silicon oxide layer, and a PSG layer. It should be noted that the above-mentioned PSG layer 11 is naturally formed under the action of oxygen during the phosphorus doping process of the N-type doped crystalline silicon layer 5, its thickness is 25 - 35 nm, and its composition is silicon oxide doped with phosphorus. Similarly, the isolation groove can penetrate through the above-mentioned insulating layer 12 and the PSG layer 11 or not penetrate through the above-mentioned insulating layer 12 and the PSG layer 11.

[0043] In the embodiments of the present invention, the specific type of the above-mentioned mask protection layer is not particularly limited. As some specific examples, the mask protection layer can be a SiNx layer. In some examples, the thickness of the mask protection layer can be 50 - 110 nm, thereby further ensuring the above-mentioned effects of the mask protection layer. In some examples, the refractive index of the mask protection layer can be 1.8 - 2.6%, preferably 2.2 - 2.4%, thereby further ensuring the above-mentioned effects of the mask protection layer.

[0044] Further, referring to the attached Figure 1 , the back contact solar cell further includes: a first electrode layer 14 and a second electrode layer 6. The first electrode layer 14 is on one side of the isolation groove, and the first electrode layer 14 covers the P-type doped amorphous silicon layer. The second electrode layer 6 is on the other side of the isolation groove, and the second electrode layer 6 covers the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer. The function of the first electrode layer 14 is to enhance the conductivity between the P-type doped amorphous silicon layer 9 and the first gate line 10, and the second electrode layer 6 enhances the conductivity between the N-type doped crystalline silicon layer 5 and the second gate line 7.

[0045] In an embodiment of the present invention, the first electrode layer 14 and the second electrode layer 6 are transparent conductive layers. The specific materials of the first electrode layer 14 and the second electrode layer 6 are not particularly limited. As some specific examples, the materials of the first electrode layer 14 and the second electrode layer 6 are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium oxide, and indium tungsten oxide. In some examples, the thicknesses of the first electrode layer 14 and the second electrode layer 6 can be independently 50-110 nm.

[0046] Further, referring to the attached Figure 1 , the back-contact solar cell further includes: a passivation layer, the passivation layer includes a second intrinsic amorphous silicon layer 2 and a silicon nitride passivation layer 1. The second intrinsic amorphous silicon layer 2 is disposed on the second surface 3-2, and the silicon nitride passivation layer 1 is disposed on the surface of the oxide passivation layer away from the semiconductor substrate 3. The silicon nitride passivation layer 1 functions as an antireflection film and a protective film, and at the same time functions as a passivation film for suppressing photo-carrier recombination. The second intrinsic amorphous silicon layer 2 functions to suppress photo-carrier recombination at the bonding interface with the second surface 3-2. In some examples, a textured structure is provided on at least a part of the second surface 3-2, that is, many pyramid-like structures are provided on at least a part of the second surface 3-2. Thus, the light-receiving surface of the second surface 3-2 is increased. In still other examples, the non-groove region is a textured structure; and / or, the groove region is a textured structure. The textured structures on the non-groove region and the groove region are formed in the cleaning step during the preparation process of the back-contact solar cell.

[0047] In yet another aspect of the present invention, the present invention proposes a method for manufacturing a back-contact solar cell. According to an embodiment of the present invention, the method includes: S100: Providing a semiconductor substrate In this step, a semiconductor substrate 3 is provided. The semiconductor substrate 3 has opposite first surface 3-1 and second surface 3-2. The first surface includes a plurality of alternately arranged first regions and second regions, as shown in the attached Figure 2 . The first surface 3-1 of the semiconductor substrate 3 refers to the backlight surface, and the second surface 3-2 of the semiconductor substrate 3 refers to the light-facing surface. In an embodiment of the present invention, the material of the semiconductor substrate 3 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs).

[0048] To ensure the cleanliness of the semiconductor substrate 3, in some examples, the semiconductor substrate 3 can be polished and cleaned. Specifically, the semiconductor substrate 3 is put into a tank-type polishing and cleaning machine for polishing, the cutting damage layer on the surface of the semiconductor substrate 3 is removed, and the double-sided micro-topography is prepared. The square size of the polishing is regulated by controlling the concentration, temperature, and cleaning time of the cleaning solution (generally an alkaline solution, such as potassium hydroxide / sodium hydroxide solution).

[0049] S200: Sequentially form a tunneling oxide layer, an N-type doped crystalline silicon layer, and an isolation layer on the first surface. In this step, a low-pressure chemical vapor deposition furnace (LPCVD), PECVD, PVD, PEALD, etc. can be used to prepare the tunneling oxide layer 4 and the intrinsic or in-situ doped poly Si. Preferably, LPCVD is used to deposit the back tunneling oxide layer 4 and the polysilicon (poly) layer at a high temperature of 600 - 800°C. In the existing HBC cell structure, the deposition of the intrinsic a-si:H + a-si:H(N) film layer mostly uses expensive CVD equipment, while in this application, inexpensive LPCVD equipment is used to replace the expensive CVD equipment, effectively reducing the equipment investment cost.

[0050] Then, the intermediate after depositing the polysilicon (poly) layer is placed in a tube diffusion furnace, and a phosphorus-containing compound (such as phosphorus oxychloride) is introduced. At a high temperature of 750 - 880°C, the polysilicon is converted into an N-type doped crystalline silicon layer 5. It should be noted that during the phosphorus doping process of poly-Si, a PSG layer 11 is naturally formed under the action of oxygen, and its thickness is about 25 - 35 nm. The PSG layer 11 has the effect of enhancing the mask. In some examples, the phosphorus doping concentration in the N-type doped crystalline silicon layer 5 is 8E19 - 5E20 cm -3 (for example, it can be 8E19 / 9E19 / 1E20 / 2E20 / 3E20 / 4E20 / 5E20 cm -3 ), preferably 3 - 9E20 cm -3 . In some examples, the thickness of the N-type doped crystalline silicon layer 5 is 30 - 250 nm), preferably 40 - 200 nm. In some examples, the thickness of the tunneling oxide layer 4 is 1 - 4 nm, preferably 1 - 1.8 nm.

[0051] In the embodiments of the present invention, the specific type of the above-mentioned tunneling oxide layer 4 is not particularly limited. For example, the tunneling oxide layer 4 is a tunneling SiO2 layer.

[0052] Finally, an insulating layer is formed on the surface of the PSG layer. In some examples, this insulating layer can be a mask protection layer. The mask protection layer is deposited by a PECVD device at a temperature of 400 - 600°C. This mask protection layer serves as a laser energy absorption layer, which has the effect of reducing the influence of the laser opening film process on the passivation effect of the N region, and also has the effect of providing a hydrogen source to further passivate the polysilicon and the substrate, improving the passivation effect, and protecting the N-type doped crystalline silicon layer 5 from being corroded by alkali during the texturing process. The structure of the intermediate prepared by S200 is as shown in the appendix Figure 3 as shown.

[0053] In an embodiment of the present invention, the specific type of the above-mentioned mask protection layer is not particularly limited. For example, the mask protection layer can be SiN x layer. In some examples, the thickness of the mask protection layer can be 50 - 110 nm, thereby further ensuring the above-mentioned effects of the mask protection layer 12. In some examples, the refractive index of the mask protection layer can be 1.8 - 2.6%, preferably 2.2 - 2.4%, thereby further ensuring the above-mentioned effects of the mask protection layer.

[0054] S300: Use a laser to open the isolation layer in the second region In this step, use a laser to open the isolation layer in the second region to expose the semiconductor substrate in the second region. The remaining tunneling oxide layer and N-type doped polycrystalline silicon layer are in the first region, and its structure is as shown in the appendix Figure 4 shown. Since in this application, the tunneling oxide layer + n-poly-Si layer passivation contact is used to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in the existing HBC cell structure, and the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage, therefore, in this step, a laser process can be directly used for opening the film. The laser film opening process can reduce the impact on the passivation effect of the N region, further increase the process window, and reduce the process difficulty. In the existing HBC cell structure, in this step, a large amount of masking and demasking techniques are generally used to form patterns, with high production costs and great difficulty in process control. The present invention saves the steps of masking and demasking during the laser film opening process in this step, improving production efficiency.

[0055] S400: Sequentially form a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on the surface of the intermediate prepared in step S300 that is far from the second surface In this step, use a CVD device to sequentially form a first intrinsic amorphous silicon layer 8 and a P-type doped amorphous silicon layer 9 on the surface of the intermediate prepared in step S300 that is far from the second surface 3 - 2 at 220 - 300 °C. This application uses the intrinsic amorphous silicon layer i-a-Si + p-a-Si layer passivation contact to replace SiO in the existing TBC cell structure x + p-poly-Si, improving the surface passivation effect of the P region, thereby improving the electrical performance of the solar cell. In some examples, the thickness of the first intrinsic amorphous silicon layer 8 is 10 - 20 nm. In some examples, the thickness of the P-type doped amorphous silicon layer 9 is 5 - 45 nm, preferably 10 - 20 nm.

[0056] According to a specific embodiment of the present invention, step S400 further includes: sequentially forming a second intrinsic amorphous silicon layer and a silicon nitride passivation layer 1 on the second surface 3 - 2, and the prepared intermediate is as shown in the appendix Figure 6As shown. The silicon nitride passivation layer 1 functions as an antireflection film and a protective film, and also functions as a passivation film for suppressing photo-carrier recombination. The second intrinsic amorphous silicon layer 2 functions to suppress photo-carrier recombination at the bonding interface with the second surface 3-2.

[0057] Further, between steps S300 and S400, the above method further includes: performing alkaline texturing on the surface of the intermediate prepared in step S300, so as to form a pyramidal texture structure on the second surface and the second region, and at the same time removing the residual mask protection layer, tunneling oxide layer 4 or N-type doped crystalline silicon layer 5 in the second region after laser treatment. The solution used for cleaning can be an acid solution, such as hydrofluoric acid. Specifically, the intermediate after step S300 is successively placed in a hydrofluoric acid tank - texturing tank - SC1 cleaning tank - CP circular sliding tank - SC2 cleaning tank - pickling tank. The function of the hydrofluoric acid tank is to remove the residual mask protection layer 12, tunneling oxide layer 4 or N-type doped crystalline silicon layer 5 in the second region after laser treatment. The function of the texturing tank is to complete texturing simultaneously in the laser region and the second surface 3-2 region. The main function of the SC1 cleaning tank is to remove the contamination and chemical residues on the surface of the intermediate. The function of the CP circular sliding tank is to smooth the tips and valleys of the pyramids to prevent epitaxial growth of amorphous silicon deposition. The function of the SC2 cleaning tank is to remove the metal residues on the silicon wafer. The function of the pickling tank is to chemically passivate the intermediate and form a hydrophobic structure. Thus, this step not only completes the removal of the residues in the second region after laser treatment, but also completes the texturing of the second region, making the laser region concave and forming a textured surface, and at the same time completes the texturing of the second surface 3-2, as shown in the appendix Figure 5 As shown. Among them, the second region after texturing is the groove region, and the first region is the non-groove region.

[0058] In some examples, the preparation of the silicon nitride passivation layer 1 can be the preparation of a multi-layer sub-silicon nitride passivation layer 1. For example, the multi-layer sub-silicon nitride passivation layer 1 can be designed such that the thickness of the first layer is 20 ± 3 nm, the refractive index is 2.4%, the thickness of the second layer is 15 ± 5 nm, the refractive index is 2.2%, the thickness of the third layer is 40 ± 5 nm, and the refractive index is 2.0%; the thickness of the fourth sacrificial layer is 80 ± 10 nm, and the refractive index is 2.4%. Among them, the function of the fourth sacrificial layer is that the intermediate prepared in step S300 will inevitably consume the above sacrificial layer during the process of alkaline texturing, and the total thickness of the remaining first, second, and third layers is the thickness of the finally formed silicon nitride passivation layer 1.

[0059] S500: Remove a part of the first intrinsic amorphous silicon layer, P-type doped amorphous silicon layer, and isolation layer at one end away from the second region In this step, a part of the first intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer, and the isolation layer at one end far from the second region are removed, and the remaining first intrinsic amorphous silicon layer, P-type doped amorphous silicon layer are alternately arranged with the tunneling oxide layer and the N-type doped crystalline silicon layer to form an interleaved stacked region.

[0060] Specifically, first, a part of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer at one end far from the second region are removed by laser to expose the isolation layer. In some examples, it can be completed by using 532nm green light nanosecond picosecond or 355nm ultraviolet nanosecond picosecond laser. In some examples, the power of the laser is 6 - 15W. Then, the exposed isolation layer is removed by an acid solution (such as HF solution) to expose the remaining N-type doped crystalline silicon layer 5, and the remaining first intrinsic amorphous silicon layer 8, P-type doped amorphous silicon layer 9 are alternately arranged with the tunneling oxide layer 4 and the N-type doped crystalline silicon layer 5 to form an interleaved stacked region (Region A), and the structure of the intermediate part is as shown in the appendix Figure 7 shown. The purpose of step S500 is to expose a part of the N-type doped crystalline silicon layer 5 in the grooved area, which is convenient for preparing the second electrode layer and the second gate line in the subsequent steps.

[0061] S600: Grooving the interleaved stacked region In this step, the interleaved stacked region (Region A) is grooved by laser ablation technology to expose a part of the isolation layer and form an isolation groove 13. The isolation groove 13 divides the stacked region (Region A) into a first interleaved stacked region (Region A1) and a second interleaved stacked region (Region A2), and the structure of the intermediate part is as shown in the appendix Figure 9 shown. In some examples, the width of the isolation groove 13 is 20 - 200μm, preferably 80 - 120μm.

[0062] Furthermore, after grooving the interleaved stacked region, the method further includes: forming a first electrode layer on one side of the isolation groove, and the first electrode layer covers the P-type doped amorphous silicon layer; forming a second electrode layer on the other side of the isolation groove, and the second electrode layer covers the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer. The function of the first electrode layer is to enhance the conductivity between the P-type doped amorphous silicon layer 9 and the first gate line 10, and the second electrode layer enhances the conductivity between the N-type doped crystalline silicon layer 5 and the second gate line 7. In some embodiments, an electrode layer can also be formed on the surface of the P-type doped amorphous silicon layer first (the structure of the intermediate part is as shown in the appendix Figure 8 shown), and then the interleaved stacked region is grooved.

[0063] In an embodiment of the present invention, the first electrode layer and the second electrode layer are transparent conductive layers. The specific materials of the first electrode layer and the second electrode layer are not particularly limited. As some specific examples, the materials of the first electrode layer and the second electrode layer are each independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium oxide, and indium tungsten oxide. In some examples, the thicknesses of the first electrode layer and the second electrode layer can each independently be 50 to 110 nm.

[0064] Further, the method further includes: forming a first gate line 10 on a partial surface of the first electrode layer 14, and forming a second gate line 7 on a partial surface of the second electrode layer 6. Specifically, screen printing, inkjet printing, laser transfer printing, electroless plating, electroplating, or PVD method can be used to form the first gate line on the partial surface of the first electrode layer and the second gate line on the partial surface of the second electrode layer.

[0065] According to the method of the embodiment of the present invention, compared with the preparation process of the HBC battery in the prior art, this method uses a tunneling oxide layer + n-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in the existing HBC battery structure, and the tunneling oxide layer + n-poly-Si layer is relatively less sensitive to laser thermal damage. Therefore, in step S300, a laser process can be directly used for film opening, and the laser film opening process can reduce the influence on the passivation effect of the N region, further increasing the process window and reducing the process difficulty. In the existing HBC battery structure, a large amount of masking and demasking techniques are generally used to form a pattern in this step, with high production costs and great difficulty in process control. In this application, the formation region of the first doping region can be directly formed by using a laser. Compared with the preparation process of the TBC battery in the prior art, this method uses an intrinsic amorphous silicon layer i-a-Si + p-a-Si layer passivation contact to replace SiO in the existing TBC battery structure. x+p-poly-Si avoids the serious problem of concentric circles on the silicon wafer caused by the high-temperature preparation of p poly and n poly in the TBC cell, thereby improving the surface passivation effect of the P region and the electrical performance of the solar cell. Therefore, this method combines the tunneling oxide layer + n-poly-Si layer passivation with the intrinsic amorphous silicon layer i-a-Si + p-a-Si layer passivation, which not only increases the preparation process window of the back-contact solar cell, reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open-circuit voltage Uoc, short-circuit current Isc, fill factor FF, and shunt resistance Rsh of the solar cell can all reach the same effect as the existing HBC cell structure. In addition, during the deposition of the tunneling oxide layer and the N-type doped crystalline silicon layer n-poly-Si, an inexpensive LPCVD device is used to replace the expensive CVD device, effectively reducing the equipment investment cost. In addition, this method combines the texturing process with local etching, saving the previous texturing process.

[0066] The embodiments of the present invention will be described in detail below. It should be noted that the embodiments described below are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0067] Example 1 This embodiment provides a solar cell, and its preparation method is as follows: 1) Provide a 166*166 silicon wafer with N-type 1.3 Ωcm and a thickness of 165 μm.

[0068] 2) Polishing and cleaning: Put the above silicon wafer into a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the cleaning machine tank is 360 L. First, pre-clean the silicon wafer to remove organic and other contaminants generated during the cutting and transportation of the silicon wafer; in this embodiment, standard RCA cleaning solution is used for cleaning to remove particles on the silicon wafer, and can oxidize and remove a small amount of organic matter and metal atom contaminants such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr on the surface; after washing the residual chemicals, perform alkaline polishing treatment. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80 °C, and the alkaline polishing treatment time is 300 s to remove damage and polish. Then perform SC1 cleaning, ozone cleaning, and finally pickling and dehydration to complete polishing and cleaning.

[0069] 3) Send the polished silicon wafer into low-pressure chemical vapor deposition LPCVD, and deposit a tunneling SiO2 with a thickness of 1.4 nm and an intrinsic polysilicon poly Si with a thickness of 50 nm at a temperature of 640 °C.

[0070] 4) Place the intermediate after depositing the polycrystalline silicon (poly) layer in a tube diffusion furnace, introduce phosphorus oxychloride, and perform phosphorus doping on the poly Si region at 870 °C and complete the crystallization of poly, with a doping concentration of 5E20 cm -3 . During this process, a PSG layer with a thickness of approximately 30 nm is formed.

[0071] 5) Deposit a single-layer SiNx film with a thickness of 80 nm and a refractive index of 2.4% on the surface of the N-type doped crystalline silicon layer n-poly-Si by PECVD. This single-layer SiNx film serves as a mask layer.

[0072] 6) Use a 532 nm green light nanosecond laser with a power of 15 W to open the SiNx film in the P region, exposing the backlight side of the silicon wafer.

[0073] 7) Place the laser-treated silicon wafer in a texturing machine. The working volume of the machine tank is 360 L. Its main processes and functions are as follows: ① The first functional tank uses 1% wt HF at a constant temperature of 25 °C to remove residues. ② After cleaning, the silicon wafer enters the next texturing tank. The texturing solution is a 3.29% wt KOH solution, the texturing temperature is 82 °C, and the texturing time is 570 s, thus completing the texturing treatment of the front and back laser regions. ③ Then perform high-efficiency SC1 cleaning. The cleaning solution is NH4OH - H2O2 - H2O, and the volume ratio of the three is 1:1:5. The cleaning temperature is 65 °C, and the cleaning time is 300 s. ④ Use 50 ppm O3 water plus HF for pyramid rounding treatment, and the concentration of hydrofluoric acid is 0.31% wt. ⑤ Perform SC2 cleaning to remove metal residues. The cleaning solution is HCL - H2O2 - H2O, and the volume ratio of the three is 1:1:5. The cleaning temperature is 65 °C, and the cleaning time is 200 s. ⑥ Finally, complete the texturing after cleaning with 5% wt hydrofluoric acid.

[0074] 8) Use a CVD device to deposit a 7 nm thick a-si:H (i.e., the first intrinsic amorphous silicon layer i-a-Si) and a 15 nm thick a-si:H (P) (i.e., the P-type doped amorphous silicon layer p-a-Si) on the back side in sequence at 250 °C. And through flipping, deposit a 12 nm thick a-si:H and a 160 nm thick SiNx on the front side in sequence, where the SiNx sacrificial layer is 80 nm and the refractive index of the SiNx sacrificial layer is 2.4%.

[0075] 9) Use a nanosecond laser to open one end of the P-type doped amorphous silicon layer p-a-Si far from the P doping region to expose the SiNx mask layer.

[0076] 10) Clean the exposed SiNx mask layer in step 9) with 8%wt hydrofluoric acid, thereby removing the SiNx mask layer and the PSG layer in the grooving area to expose the remaining part of the N-type doped polycrystalline silicon layer n-poly-Si. At the same time, after the hydrofluoric acid treatment, the front SiNx sacrificial layer is removed, and the front SiNx thickness is reserved to 80 nm.

[0077] 11) Deposit an ITO (indium tin oxide) layer on the back with a thickness of 50 nm.

[0078] 12) Use ultraviolet picosecond laser to groove to expose the SiNx mask layer, form isolation grooves, insulate the N region and the P region, and prevent leakage caused by N / P region interconnection. Test the insulation resistance of the insulation area > 2 MΩ, and the laser width is 100 μm.

[0079] 13) Use metallic silver to complete the preparation of the back metallization electrode through screen printing technology.

[0080] Example 2 This example provides a solar cell. The difference between this example and Example 1 is only that: 3) Feed the polished silicon wafer into low-pressure chemical vapor deposition LPCVD, and deposit tunneling SiO2 with a thickness of 1.4 nm and intrinsic polycrystalline silicon poly Si with a thickness of 70 nm at a temperature of 640 °C.

[0081] All other steps are the same as those in Example 1.

[0082] Example 3 This example provides a solar cell. The difference between this example and Example 1 is only that: 3) Feed the polished silicon wafer into low-pressure chemical vapor deposition LPCVD, and deposit tunneling SiO2 with a thickness of 1.4 nm and intrinsic polycrystalline silicon poly Si with a thickness of 90 nm at a temperature of 640 °C.

[0083] All other steps are the same as those in Example 1.

[0084] Example 4 This example provides a solar cell. The difference between this example and Example 1 is only that: 6) Use 532 nm green light nanoseconds with a laser power of 12 W to open the SiNx film in the P region to expose the backlight surface of the silicon wafer.

[0085] Example 5 This example provides a solar cell. The difference between this example and Example 1 is only that: 6) Use 532 nm green light nanoseconds and a laser power of 10 W to open the SiNx film in the P region, exposing the backlight side of the silicon wafer.

[0086] Example 6 This example provides a solar cell. The difference between this example and Example 1 is only that: 6) Use 532 nm green light nanoseconds and a laser power of 8 W to open the SiNx film in the P region, exposing the backlight side of the silicon wafer.

[0087] Example 7 This example provides a solar cell. The difference between this example and Example 1 is only that: 6) Use 532 nm green light nanoseconds and a laser power of 6 W to open the SiNx film in the P region, exposing the backlight side of the silicon wafer.

[0088] Comparative Example 1 This comparative example provides a method for preparing an HBC solar cell, including the following steps: 1) Provide an N-type 1.3 Ωcm 166*166 silicon wafer with a thickness of 165 μm.

[0089] 2) Polishing and cleaning: Put the above silicon wafer into a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the cleaning machine tank is 360 L. First, pre-clean the silicon wafer to remove organic and other contaminants generated during the cutting and transportation of the silicon wafer. In this example, standard RCA cleaning solution is used for cleaning to remove particles on the silicon wafer, and can oxidize and remove a small amount of organic matter and metal atom contaminants such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr on the surface. After washing the residual chemicals, perform alkaline polishing treatment. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80 °C, and the alkaline polishing treatment time is 300 s to remove damage and polish. Then perform SC1 cleaning, ozone cleaning, and finally pickling and dehydration to complete the polishing and cleaning.

[0090] 3) Use PECVD equipment to deposit a layer of SiNx mask on the back of the silicon wafer, with a thickness of 200 nm and a refractive index of 2.4%; 4) In the trough cleaning machine, first, the silicon wafer is put into the HF trough. The mass concentration of the HF solution is 1%, and it is treated at room temperature for 30 s to remove the SiNx on the side and front of the battery by wrap plating. Subsequently, it enters the alkali trough for texturing treatment. The texturing solution is a KOH + texturing additive solution with a mass concentration of 2.5%. The texturing temperature is 82 °C, and the texturing time is 780 s. Then it enters the HNO3 / HF trough for surface smoothing treatment of the texture. The volume ratio of the solution is HNO3:HF = 1:100, and the total etching amount is 1.8 g, so that the reflectivity of the front is 12%, and the size of the texture pyramid on the surface is a large texture microstructure of 4 μm. Finally, it is treated at room temperature for 300 s in an 8%wt HF trough to completely remove the remaining SiNx mask on the back.

[0091] 5) In the CVD equipment, an intrinsic a-si:H layer with a thickness of 15 nm, a doped phosphorus a-si:H(N) layer with a thickness of 25 nm, a SiNx layer with a thickness of 200 nm, and an intrinsic a-si:H layer with a thickness of 15 nm are sequentially deposited on the back of the silicon wafer.

[0092] 6) Using a 532 laser with a power of 6 w, the outermost intrinsic a-si:H on the back is grooved to create a P+ region, which is the region for the deposition of intrinsic a-si:H and a-si:H(P) in the subsequent steps. The width of the grooved P+ region is the same as that of the non-grooved N+ region along the arranged direction.

[0093] 7) In the trough cleaning machine, first, the silicon wafer is put into the HF trough. The mass concentration of the HF solution is 8%, and the treatment time is 200 s to remove the SiNx in the laser grooved area; then it enters the alkali trough for etching treatment. The solution is a 0.5 wt% KOH + 0.15 wt% H2O2 solution, the solution temperature is 25 °C, and the etching time is 400 s to remove the remaining intrinsic a-si:H and doped phosphorus a-si:H(N) layers.

[0094] 8) In the CVD equipment, an intrinsic a-si:H layer with a thickness of 15 nm and a doped B a-si:H(P) layer with a thickness of 25 nm are sequentially plated on the back of the silicon wafer.

[0095] 9) In the CVD equipment, an intrinsic a-si:H layer with a thickness of 15 nm and a SiNx layer with a thickness of 85 nm are sequentially plated on the front of the silicon wafer.

[0096] 10) Use a laser to etch the intrinsic a-si:H and a-si:H(P) in the back N+ region.

[0097] 11) Remove the exposed SiNx layer in the N+ region after laser treatment with an HF solution. The mass concentration of the solution is 8%, and the time is 400 s to expose the doped phosphorus a-si:H(N) layer.

[0098] 12) Deposit an ITO (Indium Tin Oxide) layer on the back, with a thickness of 80 nm.

[0099] 13) Use a 355 nm ultraviolet picosecond laser to open slots to expose the SiNx mask layer, form isolation grooves, insulate the N region and the P region, and prevent leakage caused by the interconnection of the N / P regions. Test the insulation resistance of the insulation region > 10 MΩ, and the laser width is 100 μm.

[0100] 14) Use metallic silver through screen printing technology to complete the preparation of the back metallization electrode, and perform curing and annealing.

[0101] Comparative Example 2 The difference between Comparative Example 2 and Comparative Example 1 is only that: 6) Use a 532 laser with a power of 8 w to open slots in the outermost layer of intrinsic a-si:H on the back to open the P+ region, which is the deposition region of intrinsic a-si:H and a-si:H(P) in the subsequent steps.

[0102] Comparative Example 3 The difference between Comparative Example 3 and Comparative Example 1 is only that: 6) Use a 532 laser with a power of 10 w to open slots in the outermost layer of intrinsic a-si:H on the back to open the P+ region, which is the deposition region of intrinsic a-si:H and a-si:H(P) in the subsequent steps.

[0103] Comparative Example 4 The difference between Comparative Example 4 and Comparative Example 1 is only that: 6) Use a 532 laser with a power of 12 w to open slots in the outermost layer of intrinsic a-si:H on the back to open the P+ region, which is the deposition region of intrinsic a-si:H and a-si:H(P) in the subsequent steps.

[0104] Perform performance tests on the energy conversion efficiency Eta, open circuit voltage Uoc (volt, V), short circuit current Isc (ampere, A), fill factor FF (%), and series resistance Rsh (ohm, Ω) of the solar cells prepared in Examples 1-3 and Comparative Example 1. The results are shown in Table 1.

[0105] Table 1

[0106] It can be seen that in Comparative Examples 1-4, the patterning is formed by using the mask and demasking techniques multiple times, resulting in high production costs and great difficulty in process control. In Examples 1-7, the tunneling SiO2 layer + N-type crystalline silicon layer n-poly-Si passivation contact is used to replace the intrinsic a-si:H + a-si:H(N) film layer passivation in Comparative Examples 1-4. Since the tunneling SiO2 layer + N-type crystalline silicon layer n-poly-Si in Examples 1-7 is relatively less sensitive to laser thermal damage, in this step, the laser process can be directly used for film opening without using the mask and demasking techniques multiple times to form the patterning. Specifically, Comparative Examples 1-2 produced higher efficiency at lower laser powers, but at greater laser powers, Comparative Examples 3-4 showed a significant decrease in efficiency. It can be seen that the tunneling SiO2 layer + N-type crystalline silicon layer n-poly-Si is relatively less sensitive to laser thermal damage, and the influence on the passivation effect of the corresponding doped region in the first region can be reduced during the laser film opening process. Examples 1-7 all had high efficiency at laser powers of 6-15W, indicating that the preparation process window of the present invention is relatively wide. Moreover, as can also be seen from Table 1, compared with Comparative Examples 1-2, the energy conversion efficiency Eta, open circuit voltage Uoc, and fill factor FF of Examples 1-7 all reached levels comparable to those of Comparative Examples 1-2.

[0107] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0108] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A back-contact solar cell, characterized in that, Comprising: A semiconductor substrate having opposite first and second surfaces, the first surface including a plurality of groove regions and a plurality of non-groove regions, the non-groove regions and the groove regions being alternately arranged on the first surface; A tunneling oxide layer and an N-type doped polycrystalline silicon layer, the tunneling oxide layer being on the non-groove regions, and the N-type doped polycrystalline silicon layer being on the surface of the tunneling oxide layer away from the semiconductor substrate; A first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer, the N-type doped polycrystalline silicon layer having a conductivity type opposite to that of the P-type doped amorphous silicon layer, the first intrinsic amorphous silicon layer being on the groove regions and extending on a partial surface of the N-type doped polycrystalline silicon layer away from the tunneling oxide layer, the P-type doped amorphous silicon layer being on the surface of the first intrinsic amorphous silicon layer away from the semiconductor substrate, forming an interleaved stacking region of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer with the tunneling oxide layer and the P-type doped polycrystalline silicon layer; An isolation structure including an isolation layer and an isolation groove, the isolation layer being between the first intrinsic amorphous silicon layer and the N-type doped polycrystalline silicon layer in the interleaved stacking region, and the isolation groove penetrating through the P-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the interleaved stacking region.

2. The back-contact solar cell according to claim 1, characterized in that, The groove regions are of a matte structure; And / or, the non-groove regions are of a matte structure; And / or, the second surface is of a matte structure; And / or, the edges of the groove regions in contact with the non-groove regions are inclined.

3. The back-contact solar cell according to claim 1, characterized in that, Further comprising: A first electrode layer and a second electrode layer, the first electrode layer being on one side of the isolation groove and covering the P-type doped amorphous silicon layer, and the second electrode layer being on the other side of the isolation groove and covering the P-type doped amorphous silicon layer and the N-type doped polycrystalline silicon layer.

4. The back-contact solar cell according to claim 3, characterized in that, The first electrode layer and the second electrode layer are transparent conductive layers, and the materials of the first electrode layer and the second electrode layer are independently selected from at least one of indium tin oxide, zinc aluminum oxide, indium hydroxide-doped, and indium tungsten oxide.

5. The back-contact solar cell according to claim 1, characterized in that, The isolation layer includes an insulating layer between the first intrinsic amorphous silicon layer and the N-type doped polycrystalline silicon layer; Or, the isolation layer includes a silicon nitride layer and a PSG layer, the PSG layer being on the surface of the N-type doped polycrystalline silicon layer away from the tunneling oxide layer, and the silicon nitride layer being on the surface of the PSG layer away from the N-type doped polycrystalline silicon layer.

6. The back-contact solar cell according to claim 5, wherein The thickness of the silicon nitride layer is 50 - 110 nm; and / or The thickness of the PSG layer is 25 - 35 nm.

7. The back contact solar cell according to claim 1, characterized in that, Further comprising a passivation layer including a second intrinsic amorphous silicon layer and a silicon nitride passivation layer, the second intrinsic amorphous silicon layer being disposed on the second surface, and the silicon nitride passivation layer being disposed on the surface of the second intrinsic amorphous silicon layer away from the semiconductor substrate.

8. The back contact solar cell according to claim 1, wherein The semiconductor substrate is an N-type semiconductor substrate, and the size of the groove regions in the width direction is greater than the size of the non-groove regions in the width direction; Alternatively, the semiconductor substrate is a P-type semiconductor substrate, and the size of the groove region in the width direction is smaller than the size of the non-groove region in the width direction.

9. The back-contact solar cell according to any one of claims 1-8, characterized in that the tunneling oxide layer is a tunneling SiO2 layer; and / or the thickness of the tunneling oxide layer is 1-4 nm, preferably 1-1.8 nm; and / or the thickness of the N-type doped crystalline silicon layer is 30-250 nm, preferably 40-200 nm; and / or The phosphorus doping concentration in the N-type doped crystalline silicon layer is 8E19 to 5E20 cm -3 , preferably 3 to 9E20 cm -3 ; and / or the thickness of the first intrinsic amorphous silicon layer is 10-20 nm; and / or the thickness of the P-type doped amorphous silicon layer is 5-45 nm, preferably 10-20 nm; and / or The boron doping concentration in the P-type doped amorphous silicon layer is 10e20 cm -3 ~10e21 cm -3 .

10. A method for fabricating a back-contact solar cell, characterized in that, comprising: providing a semiconductor substrate having opposite first and second surfaces, the first surface including a plurality of alternately arranged first regions and second regions; successively forming a tunneling oxide layer, an N-type doped crystalline silicon layer, and an isolation layer on the first surface; using a laser to open the isolation layer in the second region to expose the semiconductor substrate in the second region, and the remaining tunneling oxide layer and N-type doped crystalline silicon layer are in the first region; successively forming a first intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on the surface of the prepared intermediate member away from the second surface; removing a part of the first intrinsic amorphous silicon layer, P-type doped amorphous silicon layer, and isolation layer at one end away from the second region, and the remaining first intrinsic amorphous silicon layer, P-type doped amorphous silicon layer are alternately arranged with the tunneling oxide layer and N-type doped crystalline silicon layer to form an interleaved stacking region; grooving the interleaved stacking region to form isolation grooves, the isolation grooves penetrating through the P-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in the interleaved stacking region so as to divide the interleaved stacking region into a first interleaved stacking region and a second interleaved stacking region.

11. The method according to claim 10, characterized in that, Further comprising: after exposing the second region, performing alkali texturing on the semiconductor substrate so as to form a pyramidal-like textured surface structure on the second surface and the second region.

12. The method according to claim 11, wherein after forming the pyramidal-like textured surface structure on the second surface and the second region, successively forming a second intrinsic amorphous silicon layer and a silicon nitride passivation layer on the second surface.

13. The method according to claim 10, wherein after grooving the interleaved stacking region, forming a first electrode layer on one side of the isolation groove, and the first electrode layer covering the P-type doped amorphous silicon layer, and forming a second electrode layer on the other side of the isolation groove, and the second electrode layer covering the P-type doped amorphous silicon layer and the N-type doped crystalline silicon layer.

14. The method according to claim 13, characterized in that, forming a first grid line on a part of the surface of the first electrode layer, and forming a second grid line on a part of the surface of the second electrode layer.

15. The method according to claim 10, wherein depositing the tunneling oxide layer and the N-type doped crystalline silicon layer by LPCVD.

16. The method according to claim 10, wherein The isolation layer includes an insulating layer; or, the isolation layer includes a silicon nitride layer and a PSG layer, the PSG layer is formed on the surface of the N-type doped crystalline silicon layer away from the tunneling oxide layer, and the silicon nitride layer is formed on the surface of the PSG layer away from the N-type doped crystalline silicon layer.

17. The method according to claim 10, wherein Use a laser to remove a part of the first intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer away from one end of the second region, and the power of the laser is 6-15W.

Images