Low dropout regulator and radio frequency module
By introducing a detection tube and a current source current limiting circuit in the low dropout regulator, the current limiting problem of LDO in overcurrent situations is solved, the power tube is turned off in a timely manner, and the safety of the voltage regulator is improved. reliability.
Patent Information
- Application Number
- CN202411495943.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2025-02-07
AI Technical Summary
When the load current is large or the output is short-circuited, the power tube gate and source voltage difference is large, which is prone to avalanche breakdown and device burning, resulting in current limiting problems.
A low dropout voltage regulator including a power tube, a detection tube and a current source type current limiting circuit is designed. The current is copied through the detection tube and a current subtractor and current mirror are used in the current source current limit circuit to obtain the recharge current to achieve current limit control to ensure that the power tube can be turned off in time in the case of overcurrent.
It effectively solves the current limiting problem of LDO in overcurrent situations, prevents avalanche breakdown and device burning, and improves the safety and reliability of the voltage regulator.
Smart Images
Figure CN119396241A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic technology, and in particular to a low voltage dropout regulator and a radio frequency module. Background Art
[0002] In electronic devices such as mobile devices, there are usually analog modules and RF modules that are sensitive to noise. Therefore, the power supply for these modules must meet the stability requirements.
[0003] A low dropout regulator (LDO) is a linear regulator that can convert the battery voltage into a low-noise, stable and accurate voltage to meet the above power supply requirements. In addition, LDO can be integrated with CMOS technology. Because it occupies a small chip area, it is also commonly used in SOC systems, and is also beneficial for crosstalk resistance and miniaturization.
[0004] However, the power tube in the LDO is a high-power load device with limited current capacity. When the LDO is working with a large load current or the output is short-circuited, the gate-source voltage difference of the power tube is large, and the current flowing through the power tube is large, which is prone to avalanche breakdown and device burnout. Therefore, current limiting of the LDO is crucial. Summary of the invention
[0005] In view of this, the embodiments of the present application provide a low voltage dropout regulator and a radio frequency module to solve at least one problem existing in the background technology.
[0006] In a first aspect, an embodiment of the present application provides a low voltage dropout regulator, the low voltage dropout regulator comprising a power tube, a detection tube and a current source type current limiting circuit;
[0007] The detection tube is configured to copy the current flowing through the power tube based on a set first ratio to obtain a detection current;
[0008] The current source type current limiting circuit is configured to obtain a supply current to increase the response current in the current response branch supplied by the output current of the second current source under the condition that the detection current exceeds the first constant current, under the compulsion of changing synchronously with the increase of the detection current; and in the case of the output of the supply current, the current source type current limiting circuit outputs a low-level current limiting control voltage determined according to the supply current;
[0009] The power tube is configured as an output transistor of the low voltage dropout regulator to provide a stable output voltage; and is turned off under the control of the low-level current limiting control voltage to turn off the output of the low voltage dropout regulator.
[0010] In combination with the first aspect, in an optional implementation,
[0011] The current source type current limiting circuit includes a current subtractor, which is configured to perform current subtraction operation on the detection current and the first constant current, so that the response current in the current response branch obtains a supply current to increase under the pressure of changing synchronously with the difference current between the detection current and the first constant current.
[0012] In combination with the first aspect, in an optional implementation,
[0013] The current source type current limiting circuit includes a first current mirror configured to obtain the response current that changes synchronously with the difference current in the current response branch by replicating the difference current and providing the supplementary current.
[0014] In combination with the first aspect, in an optional implementation,
[0015] The current source type current limiting circuit includes a fifth PMOS tube, which is configured to provide the supply current to the current response branch from the gate terminal of the fifth PMOS tube based on the capacitance of the fifth PMOS tube when the detection current exceeds the first constant current, and provide a low-level current limiting control voltage at the source terminal of the fifth PMOS tube.
[0016] In combination with the first aspect, in an optional implementation,
[0017] The current source type current limiting circuit further includes a control module configured to determine a power pull-down signal based on the current limiting control voltage, so as to implement at least one of the following controls through the power pull-down signal when the detection current exceeds the first constant current:
[0018] Turning off the output voltage of the low-dropout regulator;
[0019] Turn off the power supply to the low dropout regulator.
[0020] In combination with the first aspect, in an optional implementation,
[0021] The power tube includes an NMOS tube; the detection tube includes an NMOS tube;
[0022] The current source type current limiting circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth PMOS tube, a first current source and a second current source;
[0023] The drain end of the first NMOS tube is configured to obtain a detection current and is respectively connected to the drain end of the second NMOS tube, the gate end of the second NMOS tube, and the gate end of the third NMOS tube;
[0024] The drain terminal of the third NMOS tube is configured to obtain the output current of the second current source and is connected to the gate terminal of the fifth PMOS tube;
[0025] The drain terminal of the fourth NMOS tube is configured to obtain the output current of the first current source, and is respectively connected to the gate terminal of the fourth NMOS tube and the gate terminal of the first NMOS tube;
[0026] The source end of the first NMOS tube, the source end of the second NMOS tube, the source end of the third NMOS tube, the source end of the fourth NMOS tube and the drain end of the fifth PMOS tube are respectively connected to the circuit ground end; the source end of the fifth PMOS tube is configured to provide a current limiting control voltage to the gate end of the power tube.
[0027] In combination with the first aspect, in an optional implementation,
[0028] The current source type current limiting circuit also includes a digital control module;
[0029] The digital control module includes a first inverter and a second inverter;
[0030] The input end of the first inverter is connected to the gate end of the fifth PMOS tube; the output end of the first inverter is connected to the input end of the second inverter and is configured to provide a first power pull-down signal; the output end of the second inverter is configured to provide a second power pull-down signal.
[0031] In combination with the first aspect, in an optional implementation,
[0032] The low dropout voltage regulator also includes an error amplifier and a feedback circuit;
[0033] The first input terminal of the error amplifier is configured to obtain a reference voltage, the second input terminal of the error amplifier is connected to the output terminal of the feedback circuit, and the output terminal of the error amplifier is connected to the gate terminal of the power tube;
[0034] The input end of the feedback circuit is connected to the output end of the low voltage dropout regulator.
[0035] In combination with the first aspect, in an optional implementation,
[0036] The error amplifier includes a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube and a compensation capacitor;
[0037] The gate terminal of the twenty-first PMOS tube is configured as the second input terminal of the error amplifier, and the gate terminal of the twenty-second PMOS tube is configured as the first input terminal of the error amplifier;
[0038] The drain end of the twenty-first PMOS tube is respectively connected to the drain end of the twenty-third NMOS tube, the gate end of the twenty-third NMOS tube and the gate end of the twenty-fourth NMOS tube, the drain end of the twenty-second PMOS tube is respectively connected to the drain end of the twenty-fifth NMOS tube, the gate end of the twenty-fifth NMOS tube and the gate end of the twenty-sixth NMOS tube; the drain end of the twenty-fourth NMOS tube is connected to the source end of the twenty-seventh NMOS tube, the drain end of the twenty-sixth NMOS tube is connected to the source end of the twenty-eighth NMOS tube; the drain end of the twenty-seventh NMOS tube is respectively connected to the drain end of the twenty-ninth PMOS tube, the gate end of the twenty-ninth PMOS tube and the gate end of the thirtieth PMOS tube, the drain end of the twenty-eighth NMOS tube is connected to the drain end of the thirtieth PMOS tube and is configured as the output end of the error amplifier;
[0039] The source end of the twenty-first PMOS tube and the source end of the twenty-second PMOS tube are respectively connected to the drain end of the thirty-first PMOS tube; the source end of the thirty-first PMOS tube, the source end of the twenty-ninth PMOS tube and the source end of the thirtieth PMOS tube are respectively connected to the first power supply end; the source end of the twenty-third NMOS tube, the source end of the twenty-fourth NMOS tube, the source end of the twenty-fifth NMOS tube and the source end of the twenty-sixth NMOS tube are respectively connected to the second power supply end;
[0040] The gate terminal of the twenty-seventh NMOS tube and the gate terminal of the twenty-eighth NMOS tube are respectively configured to obtain the second low bias voltage, and the gate terminal of the thirty-first PMOS tube is configured to obtain the first high bias voltage;
[0041] The first end of the compensation capacitor is connected to the drain end of the twenty-sixth NMOS tube and the source end of the twenty-eighth NMOS tube respectively, and the second end of the compensation capacitor is connected to the output end of the low voltage dropout regulator;
[0042] And / or, the feedback circuit includes a first resistor and a second resistor;
[0043] The second input end of the error amplifier is connected to the second end of the first resistor and the first end of the second resistor respectively, the first end of the first resistor is connected to the output end of the low voltage dropout regulator; the second end of the second resistor is connected to the circuit ground.
[0044] In combination with the first aspect, in an optional implementation,
[0045] The digital control module further includes at least one of the following: a first switch PMOS tube; a second switch NMOS tube; a third switch NMOS tube; a fourth switch NMOS tube;
[0046] The gate end of the first switch PMOS tube is configured to obtain the second power pull-down signal, the source end of the first switch PMOS tube is connected to the first power end, and the drain end of the first switch PMOS tube is connected to the gate end of the thirty-first PMOS tube;
[0047] The gate end of the second switch NMOS tube is configured to obtain the first power pull-down signal, the source end of the second switch NMOS tube is connected to the second power end, and the drain end of the second switch NMOS tube is respectively connected to the gate end of the twenty-third NMOS tube and the gate end of the twenty-fourth NMOS tube;
[0048] The gate end of the third switch NMOS tube is configured to obtain the first power pull-down signal, the source end of the third switch NMOS tube is connected to the second power end, and the drain end of the third switch NMOS tube is respectively connected to the gate end of the twenty-fifth NMOS tube and the gate end of the twenty-sixth NMOS tube;
[0049] The gate end of the fourth switch NMOS tube is configured to obtain the first power pull-down signal, the source end of the fourth switch NMOS tube is connected to the second power end, and the drain end of the fourth switch NMOS tube is connected to the output end of the low voltage difference regulator.
[0050] In a second aspect, an embodiment of the present application provides a radio frequency module, wherein the radio frequency module includes the low voltage dropout regulator as described in the first aspect.
[0051] The beneficial effects brought about by the technical solution provided in the embodiment of the present application include: through the detection tube and the current source type current limiting circuit, the current response branch supplied by the second constant current output by the second current source can be enabled. When an overcurrent occurs in the LDO, the current flowing through the branch is increased synchronously with the increase of the detection current through the inflow of the supply current, and by providing the supply current, the current source type current limiting circuit can output a low-level current limiting control voltage determined according to the supply current, and feed it back to the gate end of the power tube to control the power tube to shut down, so that the LDO turns off the output, thereby achieving a current limiting effect.
[0052] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0054] Figure 1A schematic circuit block diagram of a specific example of a low voltage dropout regulator in an embodiment of the present application;
[0055] Figure 2 A circuit diagram of a specific example of a current source type current limiting circuit in an embodiment of the present application;
[0056] Figure 3 A circuit diagram of a specific example of the first current mirror in the embodiment of the present application;
[0057] Figure 4 Schematic diagram of a circuit of a specific example of a low voltage dropout regulator in an embodiment of the present application. DETAILED DESCRIPTION
[0058] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.
[0059] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.
[0060] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.
[0061] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0062] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.
[0063] In the embodiments of the present application, "plurality" refers to two or more.
[0064] In some embodiments, the terms "at least one", "one or more", "a plurality of", "multiple", etc. can be used interchangeably.
[0065] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.
[0066] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.
[0067] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", "above", and "exceed" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "no more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.
[0068] In some embodiments, high voltage and low voltage, or high level and low level, or high voltage and low voltage may be relative values and are not limited to absolute values.
[0069] In some embodiments, the transistor may be a single transistor; or a plurality of transistors connected in series and / or in parallel, and have functional terminals corresponding to the functional terminals of a single transistor, and also have the same working state as the single transistor, such as an on state and an off state, etc. For example, a single transistor may be a MOSFET (metal oxide semiconductor field effect transistor, MOS for short), and its functional terminals may include a gate terminal G, a source terminal S, a drain terminal D, and a substrate terminal B, then the plurality of transistors connected in series and / or in parallel have a gate terminal G, a source terminal S, a drain terminal D, and a substrate terminal B corresponding to the gate terminal G, the source terminal S, the drain terminal D, and the substrate terminal B of the single transistor, respectively, and the working state of the MOS. The MOS may include a P-type MOS (PMOS for short) and an N-type MOS (NMOS for short).
[0070] In some embodiments, the LDO circuit may have different names, such as LDO, low-dropout voltage regulator circuit, low-dropout linear regulator, low-dropout voltage regulator, low-dropout linear voltage regulator circuit, etc., and the names are not limited here.
[0071] The embodiment of the present application provides a low voltage dropout regulator. Figure 1 A circuit block diagram of a specific example of a low voltage dropout regulator in an embodiment of the present application is shown. As shown in the figure, the low voltage dropout regulator includes a power tube Mn, a detection tube Ms and a current source type current limiting circuit 10;
[0072] The detection tube Ms is configured to copy the current flowing through the power tube Mn based on a set first ratio to obtain a detection current Isense;
[0073] The current source type current limiting circuit 10 is configured to obtain a supply current I4 to increase the response current in the current response branch supplied by the second current source output current Iref2 under the condition that the detection current Isense exceeds the first constant current I1, under the compulsion of changing synchronously with the increase of the detection current Isense; and when the supply current I4 is output, the current source type current limiting circuit 10 outputs a low-level current limiting control voltage V determined according to the supply current I4. G,Mn ;
[0074] The power tube Mn is configured as an output transistor of the low voltage dropout regulator to provide a stable output voltage vout; and G,Mn The low dropout regulator is shut down under control to turn off the output.
[0075] In this way, the embodiment of the present application can enable the current response branch supplied by the second constant current output by the second current source to increase synchronously with the increase of the detection current through the inflow of the supply current through the detection tube and the current source type current limiting circuit when an overcurrent occurs in the LDO. In addition, by providing the supply current, the current source type current limiting circuit can output a low-level current limiting control voltage determined according to the supply current, and feed it back to the gate end of the power tube to control the power tube to shut down, so that the LDO turns off the output, thereby achieving a current limiting effect.
[0076] In the embodiment of the present application, the current source type current limiting circuit 10 is a peripheral circuit of the LDO, so it will not cause the stability problem of the LDO.
[0077] In some possible implementations, the first ratio can be set according to the parameters of the power tube Mn and the detection tube Ms, such as the width-to-length ratio, etc., according to actual needs. For example, the ratio of Mn to Ms is K:1, and a MOS tube can be used to form a current mirror, ignoring the mismatch effect, then when the current flowing through Mn is Iout, the current flowing through Ms is Isense=Iout / K. Among them, K can be greater than or much greater than 1.
[0078] The power tube Mn and the detection tube Ms may include at least one of the following: MOSFET; BJT (bipolar junction transistor, abbreviated as triode); IGBT (insulated gate bipolar transistor); GTO (gate turn-off thyristor); SCR (silicon controlled thyristor); MCT (MOS controlled thyristor); IGCT (integrated gate commutated thyristor); IEGT (electron injection enhanced gate transistor). The power tube Mn and the detection tube Ms may include a control terminal, a first signal terminal and a second signal terminal, and the working principle is that under the control of the control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off to connect or block the signal transmission between the first signal terminal and the second signal terminal. For example, the first signal terminal may be a source terminal, and correspondingly, the second signal terminal may be a drain terminal; or conversely, the first signal terminal may be a drain terminal, and correspondingly, the second signal terminal may be a source terminal.
[0079] Exemplarily, the power transistor Mn may be an NMOS transistor, and correspondingly, the detection transistor Ms may be an NMOS transistor.
[0080] In the embodiment of the present application, the first constant current I1 and the second current source output current Iref2 may have stable and constant characteristics, for example, they are generally not affected by changes in other currents or voltages and thus will not change.
[0081] The first constant current I1 may be derived from an output of a first current source.
[0082] Since the current response branch provides current through the second current source, and the current value of the current provided by the second current source is constant, the response current in the current response branch needs to change synchronously with the increase of the detection current Isense, which can prompt the supply current I4 to be generated and flow into the current response branch.
[0083] The method for generating the supply current I4 can be set according to actual needs, for example, it can include at least one of the following: utilizing the charging and discharging performance of the energy storage device, such as discharging through the capacitor to provide the supply current; utilizing the capacitor of the MOS tube to provide the supply current; and so on.
[0084] The implementation method of the response current in the current response branch changing synchronously with the increase of the detection current Isense can be set according to actual needs, for example, it can include at least one of the following: current replication using a current mirror; implementation through controlled output, such as using circuits with signal processing capabilities, including CPU (Central Processing Unit), GPU (graphics processing unit) and other circuits with instruction reading and execution capabilities, FPGA and other circuits that implement certain functions through fixed or reconfigurable logical relationships of hardware circuits, or other circuits, using the circuit to output control response current according to the change of the acquired detection current; and so on.
[0085] The overall architecture of the low voltage dropout regulator provided in the embodiment of the present application mainly includes two parts: an LDO main structure mainly composed of an error amplifier EA and a power tube Mn; and a current limiting structure mainly composed of a detection tube Ms and a current source type current limiting circuit 10.
[0086] For example, if an overcurrent occurs in the LDO, the detection current Isense increases. At this time, the response current in the current response branch can increase with the increase of the detection current Isense due to the absorption of the supply current I4, thereby causing the current limiting control voltage V determined according to the supply current I4 to increase. G,Mn The reduction of the current limiting control voltage V G,Mn , which is used to provide power to the gate terminal of the power tube Mn, pull down the gate terminal voltage, and turn off the output of LDO to achieve the current limiting effect.
[0087] Figure 2A circuit diagram of a specific example of a current source type current limiting circuit in an embodiment of the present application is shown. As shown in the figure, in an optional embodiment, the current source type current limiting circuit 10 includes a current subtractor 101, which is configured to perform a current subtraction operation on the detection current Isense and the first constant current I1, so that the response current I3 in the current response branch is forced to change synchronously with the difference current between the detection current Isense and the first constant current I1, and obtains a supply current I4 to increase.
[0088] In this way, the embodiment of the present application can obtain the precise current value of the detection current Isense exceeding the first constant current I1, that is, the difference current, by performing a current subtraction operation between the detection current Isense and the first constant current I1. Then, when an overcurrent occurs, direct detection of the overcurrent condition based on the current value is achieved, thereby improving the accuracy and timeliness of the overcurrent detection, thereby improving the accuracy and safety of the current limiting circuit.
[0089] In the embodiment of the present application, the first constant current I1 may be derived from the first current source, for example, may be copied from the output current Iref1 of the first current source.
[0090] For example, Figure 2 As shown, the current response branch may be a branch from node Y to the circuit ground, and the current I flowing through the current response branch Y , the branch may include a third NMOS tube M3. When an overcurrent occurs in the LDO, the increased current in the branch in a transient state may be a response current I3, that is, the current I of the current response branch at this time Y The response current I3 is included.
[0091] When the LDO is working normally, the transient response current I3=0, so it will not affect the LDO.
[0092] Figure 3 A circuit diagram of a specific example of the first current mirror in the embodiment of the present application is shown. As shown in the figure, in an optional implementation, the current source type current limiting circuit 10 includes a first current mirror 102, which is configured to obtain the response current I3 that changes synchronously with the difference current in the current response branch under the replication of the difference current and the provision of the supplementary current I4.
[0093] In this way, through the strong current replication effect of the first current mirror 102, the response current I3 is forced to change synchronously with the difference current, so that when an overcurrent occurs, the supply current I4 can be generated, and a low-level current limiting control voltage is obtained to lower the gate voltage of the power tube, so that the LDO turns off the output.
[0094] In the embodiment of the present application, the current values in the mirror branches of the first current mirror 102 are equal, for example, I2=I Y , then, when overcurrent occurs, in the transient state, since Isense>I1, I2 increases, that is, I2 can increase the current value of the difference current, so I Y Also increases, that is, I Y The current value of the response current I3 can be increased.
[0095] In an optional embodiment, the current source type current limiting circuit 10 includes a fifth PMOS tube M5, which is configured to provide the supply current I4 from the gate terminal of the fifth PMOS tube M5 to the current response branch based on the capacitance of the fifth PMOS tube M5 when the detection current Isense exceeds the first constant current I1, and provide a low level current limiting control voltage V at the source terminal of the fifth PMOS tube M5. G,Mn .
[0096] Thus, the embodiment of the present application can discharge the gate terminal of the fifth PMOS tube M5 to generate a supply current I4 when an LDO overcurrent occurs through the capacitance of the fifth PMOS tube M5, such as a gate-source capacitance, and can be merged into the current response branch together with the second current source output current Iref2, so that the response current I3 can increase synchronously with the increase of the detection current Isense, thereby improving the timeliness of the overcurrent response. In addition, the generation of the supply current I4 reduces the gate terminal voltage of the fifth PMOS tube M5, thereby reducing the source terminal voltage of the fifth PMOS tube M5, thereby improving the timeliness of the overcurrent response control, simplifying the circuit structure, and facilitating miniaturization.
[0097] In an alternative embodiment, if Figure 2 As shown, the current source type current limiting circuit 10 further includes a control module 103 configured to control the current limiting voltage V G,Mn A power pull-down signal is determined, so that when the detection current Isense exceeds the first constant current I1, at least one of the following controls is implemented through the power pull-down signal:
[0098] Turning off the output of the output voltage vout of the low voltage dropout regulator;
[0099] Turn off the power supply to the low dropout regulator.
[0100] In some possible implementations, the power pull-down signal may be used to control the closing of a current mirror in the LDO circuit, so as to close the LDO.
[0101] Thus, the embodiment of the present application can control the LDO through the control module 103 when an overcurrent occurs, not only through the low-level current limiting control voltage V G,MnThe LDO can be controlled to be turned off, and the LDO can be further controlled to be turned off through a power pull-down signal, thereby improving the safety of the LDO.
[0102] In the case of overcurrent, the power pull-down signal is activated, and the protection measures taken for the LDO are implemented through the control logic to achieve overcurrent protection for the LDO. For example, the LDO can be turned off by turning off the output of the LDO, disconnecting the power connection of the LDO, etc., thereby improving the safety of the LDO; and by disconnecting the power connection of the LDO, the overall power consumption of the circuit can also be reduced, and the power consumption can be kept below a safe value.
[0103] In the embodiment of the present application, the power pull-down signal may include a current limiting control voltage V G,Mn The first power pull-down signal with the same level as the current limiting control voltage V G,Mn At least one of the second power pull-down signals having opposite levels.
[0104] In some possible implementations, based on the current limiting control voltage V G,Mn The method of determining the power pull-down signal may include at least one of the following: using one or more inverters; using a level conversion circuit; etc., which can be set according to actual needs.
[0105] In an optional implementation, the power tube Mn includes an NMOS tube; the detection tube Ms includes an NMOS tube;
[0106] The current source type current limiting circuit 10 includes a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth PMOS tube M5, a first current source and a second current source;
[0107] The drain terminal of the first NMOS tube M1 is configured to obtain the detection current Isense, and is respectively connected to the drain terminal of the second NMOS tube M2, the gate terminal of the second NMOS tube M2, and the gate terminal of the third NMOS tube M3;
[0108] The drain terminal of the third NMOS transistor M3 is configured to obtain the second current source output current Iref2 and is connected to the gate terminal of the fifth PMOS transistor M5;
[0109] The drain terminal of the fourth NMOS transistor M4 is configured to obtain the first current source output current Iref1, and is respectively connected to the gate terminal of the fourth NMOS transistor M4 and the gate terminal of the first NMOS transistor M1;
[0110] The source end of the first NMOS tube M1, the source end of the second NMOS tube M2, the source end of the third NMOS tube M3, the source end of the fourth NMOS tube M4 and the drain end of the fifth PMOS tube M5 are respectively connected to the circuit ground end; the source end of the fifth PMOS tube M5 is configured to provide a current limiting control voltage V G,Mn To the gate terminal of the power tube Mn.
[0111] In the embodiment of the present application, the first NMOS tube M1 and the second NMOS tube M2 can form a current subtractor, the fourth NMOS tube M4 and the first NMOS tube M1 can form a second current mirror, and the second NMOS tube M2 and the third NMOS tube M3 can form a first current mirror. Exemplarily, the ratio of M4 to M1 can be 1:M, and the ratio of M2 to M3 can be 1:N, wherein both M and N can be greater than or much greater than 1.
[0112] Then, through the second current mirror, the first current source output current Iref1 is copied to obtain the first constant current I1=M×Iref1, so the current value of the first constant current I1 depends on the current value of Iref1; the detection current Isense enters the current subtractor and is compared with the first constant current I1, so that the magnitude of the detection current Isense exceeding the first constant current I1 can be accurately determined, thereby improving the accuracy and timeliness of overcurrent detection.
[0113] The current I flowing in the current response branch is obtained by copying the current I2 (including the difference current when overcurrent) through the first current mirror 102. Y (In case of overcurrent, including I3) = N × I2, so the response current I3 in the current response branch changes synchronously with the difference current between the detection current Isense and the first constant current I1. Therefore, in the case of overcurrent, the detection current Isense increases, generating a difference current = Isense-I1 (because Isense>I1 at this time) flowing through M2, and copied to M3 through the first current mirror 102 with a mirror coefficient of N, so that the response current I3 is added to the current response branch. Then, I3 is compared with the output current Iref2 of the second current source. In the case of overcurrent, I Y >Iref2, at this time, the gate voltage of M5 discharges the drain of M3, that is, there is a replenishment current I4 between node X and node Y, so the gate voltage of M5 decreases, and at the same time, the source voltage of M5 also decreases, thereby obtaining a low-level current limiting control voltage V G,Mn . Under normal circumstances, I3=0 in transient state.
[0114] In an optional implementation, the current source type current limiting circuit 10 further includes a digital control module;
[0115] The digital control module includes a first inverter U1 and a second inverter U2;
[0116] The input end of the first inverter U1 is connected to the gate end of the fifth PMOS tube M5; the output end of the first inverter U1 is connected to the input end of the second inverter U2 and is configured to provide a first power pull-down signal PD; the output end of the second inverter U2 is configured to provide a second power pull-down signal PDB.
[0117] In this way, the embodiment of the present application can obtain two mutually inverted first power pull-down signals PD and second power pull-down signals PDB according to the current limiting control voltage through the first inverter U1 and the second inverter U2, and can realize signal localization, thereby improving the stability of the power pull-down signal, thereby realizing stable control of shutting down the LDO.
[0118] When an overcurrent occurs in the LDO, a low-level current limiting control voltage is generated, and the first power pull-down signal PD and the second power pull-down signal PDB are activated, and after a delay, the system control logic can take a protection action to shut down the LDO.
[0119] In an alternative embodiment, if Figure 1 As shown, the low voltage dropout regulator also includes an error amplifier EA and a feedback circuit;
[0120] The first input terminal of the error amplifier EA is configured to obtain a reference voltage vref, the second input terminal of the error amplifier EA is connected to the output terminal of the feedback circuit, and the output terminal of the error amplifier EA is connected to the gate terminal of the power tube Mn;
[0121] The input end of the feedback circuit is connected to the output end of the low voltage dropout regulator.
[0122] Figure 4 The circuit diagram of a specific example of a low voltage dropout regulator in the embodiment of the present application is shown. In the embodiment of the present application, the specific circuit structure of the error amplifier can be set according to actual needs and is not limited to Figure 4 As shown in the figure, in an optional implementation manner, the error amplifier EA includes a twenty-first PMOS tube M21, a twenty-second PMOS tube M22, a twenty-third NMOS tube M23, a twenty-fourth NMOS tube M24, a twenty-fifth NMOS tube M25, a twenty-sixth NMOS tube M26, a twenty-seventh NMOS tube M27, a twenty-eighth NMOS tube M28, a twenty-ninth PMOS tube M29, a thirtieth PMOS tube M30, a thirty-first PMOS tube M31 and a compensation capacitor Cc;
[0123] The gate terminal of the twenty-first PMOS tube M21 is configured as the second input terminal of the error amplifier EA, and the gate terminal of the twenty-second PMOS tube M22 is configured as the first input terminal of the error amplifier EA;
[0124] The drain end of the twenty-first PMOS tube M21 is respectively connected to the drain end of the twenty-third NMOS tube M23, the gate end of the twenty-third NMOS tube M23 and the gate end of the twenty-fourth NMOS tube M24, the drain end of the twenty-second PMOS tube M22 is respectively connected to the drain end of the twenty-fifth NMOS tube M25, the gate end of the twenty-fifth NMOS tube M25 and the gate end of the twenty-sixth NMOS tube M26; the drain end of the twenty-fourth NMOS tube M24 is connected to the source end of the twenty-seventh NMOS tube M27, the drain end of the twenty-sixth NMOS tube M26 is connected to the source end of the twenty-eighth NMOS tube M28; the drain end of the twenty-seventh NMOS tube M27 is respectively connected to the drain end of the twenty-ninth PMOS tube M29, the gate end of the twenty-ninth PMOS tube M29 and the gate end of the thirtieth PMOS tube M30, the drain end of the twenty-eighth NMOS tube M28 is connected to the drain end of the thirtieth PMOS tube M30 and is configured as the output end of the error amplifier;
[0125] The source end of the twenty-first PMOS tube M21 and the source end of the twenty-second PMOS tube M22 are respectively connected to the drain end of the thirty-first PMOS tube M31; the source end of the thirty-first PMOS tube M31, the source end of the twenty-ninth PMOS tube M29 and the source end of the thirtieth PMOS tube M30 are respectively connected to the first power supply end vdda; the source end of the twenty-third NMOS tube M23, the source end of the twenty-fourth NMOS tube M24, the source end of the twenty-fifth NMOS tube M25 and the source end of the twenty-sixth NMOS tube M26 are respectively connected to the second power supply end vssa;
[0126] The gate terminal of the twenty-seventh NMOS tube M27 and the gate terminal of the twenty-eighth NMOS tube M28 are respectively configured to obtain the second low bias voltage vbn2, and the gate terminal of the thirty-first PMOS tube M31 is configured to obtain the first high bias voltage vbp1;
[0127] A first end of the compensation capacitor Cc is connected to the drain end of the twenty-sixth NMOS transistor M26 and the source end of the twenty-eighth NMOS transistor M28 respectively, and a second end of the compensation capacitor Cc is connected to the output end of the low voltage dropout regulator;
[0128] And / or, the feedback circuit includes a first resistor R1 and a second resistor R2;
[0129] The second input end of the error amplifier EA is connected to the second end of the first resistor R1 and the first end of the second resistor R2 respectively. The first end of the first resistor R1 is connected to the output end of the low dropout regulator; the second end of the second resistor R2 is connected to the circuit ground.
[0130] In the embodiment of the present application, the first power terminal vdda may be a circuit power terminal vin, and the second power terminal vsa may be a circuit ground terminal.
[0131] The first input terminal of the error amplifier EA may be a positive input terminal, and the second input terminal of the error amplifier EA may be a negative input terminal. M21 and M22 may be input pairs of the error amplifier EA, the gate terminal of M22 may obtain a reference voltage vref, the gate terminal of M21 may obtain a feedback signal vfb, and may be connected to a connection node between the first resistor R1 and the second resistor R2. The gate terminal of the power tube Mn and the gate terminal of the detection tube Ms may be connected to the drain terminal of M28 and the drain terminal of M30, respectively.
[0132] In the embodiment of the present application, the specific circuit structure of the feedback circuit can be set according to actual needs and is not limited to Figure 4 The structure shown.
[0133] The first resistor R1, the second resistor R2, etc. may be a single resistor, or a plurality of resistors connected in series and / or in parallel, or may include a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.
[0134] The second low-bit bias signal vbn2 and the first high-bit bias signal vbp1 can both be provided by external bias circuits, which can be controlled by logic control circuits. These are not the inventive points of the invention, and the bias circuits and logic control circuits are both prior art, and the present invention will not introduce them in detail.
[0135] In an optional implementation, the digital control module further includes at least one of the following: a first switch PMOS tube Mc1; a second switch NMOS tube Mc2; a third switch NMOS tube Mc3; a fourth switch NMOS tube Mc4;
[0136] The gate end of the first switch PMOS tube Mc1 is configured to obtain the second power pull-down signal PDB, the source end of the first switch PMOS tube Mc1 is connected to the first power end vdda, and the drain end of the first switch PMOS tube Mc1 is connected to the gate end of the thirty-first PMOS tube M31;
[0137] The gate end of the second switch NMOS tube Mc2 is configured to obtain the first power pull-down signal PD, the source end of the second switch NMOS tube Mc2 is connected to the second power supply end vssa, and the drain end of the second switch NMOS tube Mc2 is respectively connected to the gate end of the twenty-third NMOS tube M23 and the gate end of the twenty-fourth NMOS tube M24;
[0138] The gate end of the third switch NMOS tube Mc3 is configured to obtain the first power pull-down signal PD, the source end of the third switch NMOS tube Mc3 is connected to the second power end vsa, and the drain end of the third switch NMOS tube Mc3 is respectively connected to the gate end of the twenty-fifth NMOS tube M25 and the gate end of the twenty-sixth NMOS tube M26;
[0139] The gate end of the fourth switch NMOS tube Mc4 is configured to obtain the first power pull-down signal PD, the source end of the fourth switch NMOS tube Mc4 is connected to the second power end vssa, and the drain end of the fourth switch NMOS tube Mc4 is connected to the output end of the low voltage difference regulator.
[0140] In this way, the embodiment of the present application can control the on-off of the error amplifier power supply through the first switch PMOS tube Mc1, thereby realizing the on-off control of the power supply of the low voltage dropout regulator. And the on-off of the current mirror composed of M23 and M24 can be controlled through the second switch NMOS tube Mc2, the on-off of the current mirror composed of M25 and M26 can be controlled through the third switch NMOS tube Mc3, and the output of the LDO can be turned on or off through the fourth switch NMOS tube Mc4.
[0141] When overcurrent occurs, the gate voltage of the power tube Mn decreases, PD is at a high potential, and PDB is at a low potential. At this time, the switch tubes Mc1, Mc2, Mc3, and Mc4 are turned on, so that the power supply, current mirror, and output of the LDO are turned off, reducing the overall power consumption of the system.
[0142] In some possible implementations, the switch tubes Mc1, Mc2, Mc3, and Mc4 may also adopt at least one of devices including BJT (triode), SCR (silicon controlled thyristor), GTO (gate turn-off thyristor), IGBT (insulated gate bipolar transistor), MCT (MOS controlled thyristor), and SIT (static induction transistor) to realize the function of the switch.
[0143] An embodiment of the present application also provides a radio frequency module, which includes a low voltage dropout regulator as described in the above embodiment, thereby improving the safety of LDO current limiting control and further improving the safety of the module.
[0144] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.
Claims
1. A low voltage dropout regulator, characterized in that: The low voltage dropout regulator includes a power tube, a detection tube and a current source type current limiting circuit; The detection tube is configured to copy the current flowing through the power tube based on a set first ratio to obtain a detection current; The current source type current limiting circuit is configured to obtain a supply current to increase the response current in the current response branch supplied by the output current of the second current source under the condition that the detection current exceeds the first constant current, under the compulsion of changing synchronously with the increase of the detection current; and in the case of the output of the supply current, the current source type current limiting circuit outputs a low-level current limiting control voltage determined according to the supply current; The power tube is configured as an output transistor of the low voltage dropout regulator to provide a stable output voltage; and is turned off under the control of the low-level current limiting control voltage to turn off the output of the low voltage dropout regulator.
2. The low voltage dropout regulator according to claim 1, characterized in that: The current source type current limiting circuit includes a current subtractor, which is configured to perform current subtraction operation on the detection current and the first constant current, so that the response current in the current response branch obtains a supply current to increase under the pressure of changing synchronously with the difference current between the detection current and the first constant current.
3. The low voltage dropout regulator according to claim 2, characterized in that: The current source type current limiting circuit includes a first current mirror configured to obtain the response current that changes synchronously with the difference current in the current response branch by replicating the difference current and providing the supplementary current.
4. The low voltage dropout regulator according to claim 1, characterized in that: The current source type current limiting circuit includes a fifth PMOS tube, which is configured to provide the supply current to the current response branch from the gate terminal of the fifth PMOS tube based on the capacitance of the fifth PMOS tube when the detection current exceeds the first constant current, and provide a low-level current limiting control voltage at the source terminal of the fifth PMOS tube.
5. The low voltage dropout regulator according to claim 1, characterized in that: The current source type current limiting circuit further includes a control module configured to determine a power pull-down signal based on the current limiting control voltage, so as to implement at least one of the following controls through the power pull-down signal when the detection current exceeds the first constant current: Turning off the output voltage of the low-dropout regulator; Turn off the power supply to the low dropout regulator.
6. The low voltage dropout regulator according to claim 1, characterized in that: The power tube includes an NMOS tube; the detection tube includes an NMOS tube; The current source type current limiting circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth PMOS tube, a first current source and a second current source; The drain end of the first NMOS tube is configured to obtain a detection current and is respectively connected to the drain end of the second NMOS tube, the gate end of the second NMOS tube, and the gate end of the third NMOS tube; The drain terminal of the third NMOS tube is configured to obtain the output current of the second current source and is connected to the gate terminal of the fifth PMOS tube; The drain terminal of the fourth NMOS tube is configured to obtain the output current of the first current source, and is respectively connected to the gate terminal of the fourth NMOS tube and the gate terminal of the first NMOS tube; The source end of the first NMOS tube, the source end of the second NMOS tube, the source end of the third NMOS tube, the source end of the fourth NMOS tube and the drain end of the fifth PMOS tube are respectively connected to the circuit ground end; the source end of the fifth PMOS tube is configured to provide a current limiting control voltage to the gate end of the power tube.
7. The low voltage dropout regulator according to claim 6, characterized in that: The current source type current limiting circuit also includes a digital control module; The digital control module includes a first inverter and a second inverter; The input end of the first inverter is connected to the gate end of the fifth PMOS tube; the output end of the first inverter is connected to the input end of the second inverter and is configured to provide a first power pull-down signal; The output terminal of the second inverter is configured to provide a second power pull-down signal.
8. The low voltage dropout regulator according to any one of claims 1 to 7, characterized in that: The low dropout voltage regulator also includes an error amplifier and a feedback circuit; The first input terminal of the error amplifier is configured to obtain a reference voltage, the second input terminal of the error amplifier is connected to the output terminal of the feedback circuit, and the output terminal of the error amplifier is connected to the gate terminal of the power tube; The input end of the feedback circuit is connected to the output end of the low voltage dropout regulator.
9. The low voltage dropout regulator according to claim 8, characterized in that: The error amplifier includes a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third NMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth PMOS tube, a thirtieth PMOS tube, a thirty-first PMOS tube and a compensation capacitor; The gate terminal of the twenty-first PMOS tube is configured as the second input terminal of the error amplifier, and the gate terminal of the twenty-second PMOS tube is configured as the first input terminal of the error amplifier; The drain end of the twenty-first PMOS tube is respectively connected to the drain end of the twenty-third NMOS tube, the gate end of the twenty-third NMOS tube and the gate end of the twenty-fourth NMOS tube, the drain end of the twenty-second PMOS tube is respectively connected to the drain end of the twenty-fifth NMOS tube, the gate end of the twenty-fifth NMOS tube and the gate end of the twenty-sixth NMOS tube; the drain end of the twenty-fourth NMOS tube is connected to the source end of the twenty-seventh NMOS tube, the drain end of the twenty-sixth NMOS tube is connected to the source end of the twenty-eighth NMOS tube; the drain end of the twenty-seventh NMOS tube is respectively connected to the drain end of the twenty-ninth PMOS tube, the gate end of the twenty-ninth PMOS tube and the gate end of the thirtieth PMOS tube, the drain end of the twenty-eighth NMOS tube is connected to the drain end of the thirtieth PMOS tube and is configured as the output end of the error amplifier; The source end of the twenty-first PMOS tube and the source end of the twenty-second PMOS tube are respectively connected to the drain end of the thirty-first PMOS tube; the source end of the thirty-first PMOS tube, the source end of the twenty-ninth PMOS tube and the source end of the thirtieth PMOS tube are respectively connected to the first power supply end; the source end of the twenty-third NMOS tube, the source end of the twenty-fourth NMOS tube, the source end of the twenty-fifth NMOS tube and the source end of the twenty-sixth NMOS tube are respectively connected to the second power supply end; The gate terminal of the twenty-seventh NMOS tube and the gate terminal of the twenty-eighth NMOS tube are respectively configured to obtain the second low bias voltage, and the gate terminal of the thirty-first PMOS tube is configured to obtain the first high bias voltage; The first end of the compensation capacitor is connected to the drain end of the twenty-sixth NMOS tube and the source end of the twenty-eighth NMOS tube respectively, and the second end of the compensation capacitor is connected to the output end of the low voltage dropout regulator; And / or, the feedback circuit includes a first resistor and a second resistor; The second input end of the error amplifier is connected to the second end of the first resistor and the first end of the second resistor respectively, the first end of the first resistor is connected to the output end of the low voltage dropout regulator; the second end of the second resistor is connected to the circuit ground.
10. The low voltage dropout regulator according to claim 9, characterized in that: The digital control module further includes at least one of the following: a first switch PMOS tube; a second switch NMOS tube; a third switch NMOS tube; a fourth switch NMOS tube; The gate end of the first switch PMOS tube is configured to obtain the second power pull-down signal, the source end of the first switch PMOS tube is connected to the first power end, and the drain end of the first switch PMOS tube is connected to the gate end of the thirty-first PMOS tube; The gate end of the second switch NMOS tube is configured to obtain the first power pull-down signal, the source end of the second switch NMOS tube is connected to the second power end, and the drain end of the second switch NMOS tube is respectively connected to the gate end of the twenty-third NMOS tube and the gate end of the twenty-fourth NMOS tube; The gate end of the third switch NMOS tube is configured to obtain the first power pull-down signal, the source end of the third switch NMOS tube is connected to the second power end, and the drain end of the third switch NMOS tube is respectively connected to the gate end of the twenty-fifth NMOS tube and the gate end of the twenty-sixth NMOS tube; The gate end of the fourth switch NMOS tube is configured to obtain the first power pull-down signal, the source end of the fourth switch NMOS tube is connected to the second power end, and the drain end of the fourth switch NMOS tube is connected to the output end of the low voltage difference regulator.
11. A radio frequency module, characterized in that: The radio frequency module includes a low voltage dropout regulator as described in any one of claims 1-10.