Frequency adjustment method, device, equipment, program medium and chip

Abstract

The invention discloses a frequency adjustment method, device and equipment, a program medium and a chip. In the frequency adjustment method, after the current working parameter of the processor of the electronic equipment in the running state and the current frequency of the memory are obtained, the first target frequency of the processor is obtained according to the current working parameter and the current frequency of the memory, and the first target frequency of the processor is adjusted according to the first target frequency and the current load of the processor. Obtaining the second target frequency of the memory, adjusting the frequency of the processor according to the first target frequency, and adjusting the frequency of the memory according to the second target frequency, so that the influence of the frequency of the cache and / or the memory on the execution efficiency of the processor is comprehensively considered when the target frequency of the processor is calculated; therefore, linkage adjustment of the frequency of the processor and the memory is realized, the influence of the frequency of the cache and / or the memory on the performance of the CPU can be comprehensively considered, and the power consumption is reduced on the basis of ensuring the performance.

Description

Technical Field

[0001] The embodiments of the present application relate to electronic technology, and relate to but are not limited to a frequency adjustment method, device, equipment, program medium and chip. Background Art

[0002] In the frequency modulation strategy of current mobile devices, the frequency adjustment of each module is independent. For example, the processor has its own frequency modulator, and the processor's access to its memory access link is an independent frequency modulator. The memory access link includes cache and / or memory, and the two are independent of each other.

[0003] Moreover, in the processor frequency adjustment strategy of current mobile devices, when adjusting the processor frequency, the processor often regards the performance as a linear relationship proportional to the processor frequency, without considering the impact of the components on the memory access link on the performance. This will cause the frequency of the adjusted processor to be unable to be 100% converted into actual performance, resulting in power consumption and performance loss. Summary of the invention

[0004] In view of this, the frequency adjustment method, apparatus, device, program medium and chip provided in the embodiments of the present application can comprehensively consider the impact of the frequency of the cache and / or memory on the performance of the processor, and reduce power consumption while ensuring performance.

[0005] In a first aspect, a frequency adjustment method provided in an embodiment of the present application is applied to an electronic device, and the method includes:

[0006] Acquire current operating parameters of the processor of the electronic device in a running state and a current frequency of a memory of the electronic device, wherein the current operating parameters include a current load of the processor and a current frequency of the processor, the memory includes a cache and / or a memory, and the current frequency of the memory is used to indicate an amount of data that can be transmitted per unit time;

[0007] Obtaining a first target frequency of the processor according to the current operating parameter and the current frequency of the memory;

[0008] Obtaining a second target frequency of the memory according to the first target frequency and a current load of the processor;

[0009] The frequency of the processor is adjusted according to the first target frequency, and the frequency of the memory is adjusted according to the second target frequency.

[0010] In the above-mentioned frequency adjustment method, after obtaining the current operating parameters of the processor of the electronic device in the running state and the current frequency of the memory, the first target frequency of the processor is obtained according to the current operating parameters and the current frequency of the memory, and the second target frequency of the memory is obtained according to the first target frequency and the current load of the processor, and then the frequency of the processor is adjusted according to the first target frequency, and the frequency of the memory is adjusted according to the second target frequency, so that when calculating the target frequency of the processor, the influence of the frequency of the cache and / or memory on the execution efficiency of the processor is comprehensively considered, that is, the linkage adjustment of the frequency of the processor and the memory is realized, and the influence of the frequency of the cache and / or memory on the performance of the processor can be comprehensively considered, so as to reduce power consumption while ensuring performance.

[0011] In a second aspect, the frequency adjustment device provided in the embodiment of the present application includes:

[0012] a parameter acquisition module, used to acquire current operating parameters of the processor of the electronic device in a running state and a current frequency of a memory of the electronic device, wherein the current operating parameters include a current load of the processor and a current frequency of the processor, the memory includes a cache and / or a memory, and the current frequency of the memory is used to indicate an amount of data that can be transmitted per unit time;

[0013] A first frequency obtaining module, used for obtaining a first target frequency of the processor according to the current operating parameters and the current frequency of the memory;

[0014] A second frequency obtaining module, configured to obtain a second target frequency of the memory according to the first target frequency and a current load of the processor;

[0015] A frequency adjustment module is used to adjust the frequency of the processor according to the first target frequency, and to adjust the frequency of the memory according to the second target frequency.

[0016] In a third aspect, an electronic device provided in an embodiment of the present application includes the frequency adjustment device described in the second aspect.

[0017] In a fourth aspect, the computer program medium provided in the embodiments of the present application stores a computer program thereon, and when the computer program is executed by a processor, the method provided in the embodiments of the present application is implemented.

[0018] In the fifth aspect, the chip provided in the embodiment of the present application includes a processor, and the processor is connected to the memory and is used to execute the computer program or instructions stored in the memory. When the computer program or instructions are executed, the method provided in the embodiment of the present application is executed.

[0019] It should be understood that the second to fifth aspects of the embodiments of the present application are consistent with the technical solutions of the first aspect of the embodiments of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application.

[0021] Figure 1 One of the structural schematic diagrams of the electronic device provided in the embodiment of the present application;

[0022] Figure 2 A second structural diagram of an electronic device provided in an embodiment of the present application;

[0023] Figure 3 One of the flow charts of the frequency adjustment method provided in the embodiment of the present application;

[0024] Figure 4 A schematic diagram of a process for obtaining the current load of a processor provided in an embodiment of the present application;

[0025] Figure 5 A schematic diagram of a process for obtaining a first target frequency according to a first network model provided in an embodiment of the present application;

[0026] Figure 6 One of the flow charts of obtaining predicted load provided in the embodiment of the present application;

[0027] Figure 7 A second schematic diagram of a process for obtaining a predicted load provided in an embodiment of the present application;

[0028] Figure 8 A schematic diagram of a process for obtaining a second target frequency according to a second network model provided in an embodiment of the present application;

[0029] Fig. 9 A second flow chart of the frequency adjustment method provided in an embodiment of the present application;

[0030] Fig.10 A schematic diagram of an implementation flow of a frequency adjustment method provided in an embodiment of the present application;

[0031] Fig.11 A schematic diagram of the structure of a frequency adjustment device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the present application will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0034] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are used to distinguish similar or different objects, and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0035] In the current frequency modulation strategy of mobile devices, the frequency adjustment of each device is independent. For example, the CPU has its own frequency modulator, and the CPU uses another independent frequency modulator to access its memory access link. CPU frequency modulators include performance, interactive, schedutil, WALT and other frequency modulation tools for CPU, and the CPU has an independent frequency modulator for its memory access link (such as Level 3 Cache (L3) / System Level Cache (SLC) / Double Data Rate SDRAM (DDR)), such as the interconnect subsystem, Bus DCVS (such as memory latency) frequency modulation module and other frequency modulation tools for CPU memory access links.

[0036] In the related art, the CPU frequency regulator uses the pre-set linear relationship between CPU frequency and performance as the load tracking target, and directly obtains the CPU target frequency by querying the correspondence, thereby performing CPU frequency regulation according to the target frequency.

[0037] At the same time, after obtaining the target frequency of the processor, the frequency of L3 / SLC / DDR is mapped through the mapping relationship between the preset optimal CPU frequency and the frequency of the memory on the memory access link, such as L3 / SLC / DDR, to obtain the target frequency of L3 / SLC / DDR, and then the frequency of L3 / SLC / DDR is adjusted according to the target frequency.

[0038] However, due to the different complexity of instructions corresponding to different loads, the speed of searching for instructions in the memory is also different when running different loads. When the CPU runs the load, it will search for instructions related to the current load through the memory in turn, so as to realize the operation of the load. In the process of searching for instructions, since the data transmission speed in the cache is greater than the data transmission speed in the memory, the CPU will first enter the cache for searching. When there is no load-related instruction in the cache, it will enter the memory for searching. Among them, the cache can include SLC, first-level cache (L1 Cache, L1), second-level cache (L2 Cache, L2) and third-level cache (L3 Cache, L3), etc., and the rate of L1 is greater than the rate of L2, and the rate of L2 is greater than the rate of L3, and the rate of L3 is greater than the rate of SLC, so the CPU generally searches for load-related instructions or data in the first-level cache first, but the cache data may be missing. When the instruction or data is not in the first-level cache, the CPU can only obtain it through the slower second-level cache, third-level cache, SLC, or even memory (such as DDR). The whole waiting process takes too long, which will cause significant performance degradation.

[0039] Therefore, although the frequency of L3 / SLC / DDR will affect the frequency of CPU to a certain extent, the demand of the current load for the frequency of L3 / SLC / DDR cannot be ignored. In the above process, when adjusting the CPU frequency, the CPU performance is often regarded as a linear relationship proportional to the CPU frequency, without considering the impact of the speed of L3 / SLC / DDR searching for relevant instructions or data of the current load on the CPU performance. This has two effects. On the one hand, the CPU often overestimates its own performance due to the linear relationship when adjusting the frequency, but the provided frequency cannot be 100% converted into actual performance, resulting in waste; on the other hand, since the frequency of the memory on the memory access link is not considered when adjusting the CPU frequency, the performance cannot be optimized.

[0040] Although the frequency adjustment tool for the CPU memory access link takes into account both the memory access characteristics and the CPU frequency when adjusting the frequency, the CPU frequency is often mapped through a simple fixed mapping table. However, the mapping relationship often differs under different load scenarios. In addition, since there is a time difference between CPU frequency adjustment and memory access link frequency adjustment, the frequency adjustment method of the existing frequency adjustment tool for the CPU memory access link is often difficult to form a truly coordinated adjustment with the CPU frequency, which in turn causes power consumption and performance loss.

[0041] In view of this, an embodiment of the present application provides a frequency adjustment method, in which the server adjusts the frequency of the processor core in the frequency modulation domain based on the load value of each processor core in the frequency modulation domain when running a task and the frequency of the memory, combined with the current frequency value when the processor core in the frequency modulation domain reports a load event, and then adjusts the frequency of the memory according to the frequency and load value of the processor core after the frequency modulation, thereby realizing coordinated frequency modulation of the processor and the memory, which helps to improve the energy efficiency ratio of the electronic device.

[0042] The electronic device can be any type of device with information processing capability during the implementation process. For example, the electronic device can include a personal computer, a laptop, a PDA or an electronic device, etc.; the electronic device can also be a mobile terminal, for example, the mobile terminal can include a mobile phone, a car computer, a tablet computer or a projector, etc. The function implemented by the method can be implemented by calling the program code by the processor in the electronic device, and of course the program code can be stored in a computer storage medium. It can be seen that the electronic device at least includes a processor and a storage medium.

[0043] For example, Figure 1 As shown, the electronic device may include a processor 101, a memory 102 and a communication interface 103. Among them, any two of the processor 101, the memory 102 and the communication interface 103 may be connected via a bus 104.

[0044] It is to be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0045] The processor 101 may include one or more processing units, for example: the processor 101 may include a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processors can be independent devices or integrated into one or more processors. Exemplarily, the processor 101 can be a smart terminal CPU, such as a Snapdragon series processor, etc. In some embodiments, the processor 101 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0046] It is understandable that the interface connection relationship between the modules illustrated in the embodiments of the present application is only a schematic illustration and does not constitute a structural limitation on the electronic device. In other embodiments of the present application, the electronic device may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0047] It should be noted that in actual applications, there may be multiple processors 101, and the multiple processors 101 may include multiple processors of the same type or multiple processors of different types. For example, multiple processors 101 are multiple CPUs; for another example, the multiple processors 101 include one or more CPUs and one or more GPUs; for another example, the multiple processors 101 include one or more CPUs and one or more NPUs. Among them, the processor 101 (such as CPU, NPU, etc.) may include one or more processor cores.

[0048] The memory 102 refers to a device for storing data, which can be a memory or a hard disk.

[0049] Memory refers to an internal memory that directly exchanges data with the processor 101. It can read and write data at any time and at a very fast speed. It serves as a temporary data storage for the operating system or other running programs running on the processor 101. Memory includes volatile memory (vola tile memory), such as random access memory (RAM), dynamic random access memory (DRAM), etc., and may also include non-volatile memory (non-volatile memory), such as storage class memory (SCM), etc., or a combination of volatile memory and non-volatile memory. In practical applications, multiple memories can be configured in an electronic device, and optionally, the multiple memories can be of different types. This embodiment does not limit the number and type of memories. In addition, the memory can be configured to have a power-saving function. The power-saving function means that when the system loses power and then powers on again, the data stored in the memory will not be lost. Memory with a power-saving function is called a non-volatile memory.

[0050] Hard disk is used to provide storage resources. Hard disk includes but is not limited to: non-volatile memory (non-volatile memory), such as read-only memory (ROM), hard disk drive (HDD) or solid state drive (SSD), etc. The difference from memory is that the hard disk has a slower read and write speed and is usually used to store data persistently. In one embodiment, the data, program instructions, etc. in the hard disk need to be loaded into the memory first, and then the processor obtains these data and / or program instructions from the memory.

[0051] The communication interface 103 is used to communicate with other devices.

[0052] In one possible manner, the electronic device adopts a symmetrical multi-processing (SMP) architecture, that is, a plurality of processors 101 are gathered in one electronic device, and each processor 101 shares a memory 102 and a bus 104. In the SMP architecture, the electronic device evenly distributes the task queues on the plurality of processors 101, thereby greatly improving the data processing capability of the entire electronic device. All processors 101 can equally access memory, input / output (IO), external interrupts, etc.

[0053] In addition, the electronic device involved in the embodiments of the present application may also be installed with an operating system, and application programs may be installed and run on the operating system, which is not limited in the embodiments of the present application.

[0054] Figure 2 This is a schematic diagram of another electronic device provided in this application. It can be understood that the Figure 2 Specifically, it is based on Figure 1 The hardware structure shown in FIG. 1 provides a software structure that can implement the frequency adjustment method. Figure 2 As shown, the electronic device includes a user space, a kernel space, and a hardware layer. The software codes corresponding to the user space, the kernel space, and the hardware layer can be stored in the memory 102. Accordingly, when the processor 101 reads and executes the software codes corresponding to the user space, the kernel space, and the hardware layer from the memory 102, it has the functions of the user space, the kernel space, and the hardware layer.

[0055] The kernel space includes a scheduler, a load tracking module and a frequency management module. The scheduler is used to divide the tasks being executed in the electronic device into multiple threads, and then schedule the multiple threads to multiple processor cores more evenly based on the load balancing mechanism. The load tracking module is used to track the load of the electronic device / processor core. The frequency management module is used to provide the user space with interfaces such as frequency query and control of the processor core and / or memory in the form of a virtual file system. The frequency management module is also used to interact with the hardware layer.

[0056] Furthermore, the frequency management module may include a frequency governor, a frequency core unit and a frequency driver unit.

[0057] The frequency management unit is used to configure the frequency modulation strategy. Exemplary frequency modulation strategies include performance priority, power consumption priority, user self-setting, on-demand allocation, smooth adjustment, load frequency modulation, etc. These frequency modulation strategies can be applied to different load application scenarios.

[0058] The frequency management unit is also used to select a frequency modulation strategy for each frequency modulation domain with the frequency modulation domain as the granularity during the electronic device running tasks. The frequency management unit is also used to obtain the estimated load value on the previous scheduling cycle from the load tracking module, determine the estimated load value on the next scheduling cycle in combination with the frequency modulation strategy corresponding to the frequency modulation domain, and then determine the target frequency of the processor core for the frequency modulation domain; and send the determined target frequency to the frequency core unit.

[0059] Furthermore, after determining the target frequency of the processor core, the frequency management unit will also determine the target frequency of the memory based on the target frequency of the processor core, and then combine the load value in the current scheduling cycle to determine the target frequency of the memory for the frequency modulation domain; and send the determined target frequency of the memory to the frequency core unit.

[0060] The frequency driver unit is used to read the target frequency of the processor core and the memory from the frequency core unit. Furthermore, the frequency driver unit integrates a driver for interacting with the hardware layer. The frequency driver unit can interact with the hardware layer to adjust the frequency of the processor core according to the target frequency of the processor core, and adjust the frequency of the memory according to the target frequency of the memory. Exemplarily, the frequency driver unit integrates a driver for interacting with frequency-related registers.

[0061] The hardware layer includes power consumption related registers, basic input output system (BIOS) and power management module. Among them, the BIOS power management module provides power management options for the frequency management module, which can authorize the frequency management module to control the frequency of the processor core and memory.

[0062] Combination Figure 1 and Figure 2 The electronic device structure diagram shown in FIG. Figure 3 A flow chart of a frequency adjustment method provided by the present application is further shown. For example, the frequency adjustment method may be specifically composed of Figure 1 Executed by the processor 101 in; or Figure 2The frequency adjustment method is specifically that the electronic device performs frequency adjustment on N processor cores and corresponding memories in a frequency modulation domain, where N is an integer greater than or equal to 1. Exemplarily, the N processor cores are processor cores of the same type, such as all CPU cores, or all DSP cores. Exemplarily, an operating system based on the Linux kernel is installed in the electronic device, that is, the frequency adjustment method is implemented on the operating system of the Linux kernel. The specific method may include the following steps:

[0063] Step S101, obtaining current operating parameters of a processor of the electronic device in a running state and a current frequency of a memory of the electronic device, wherein the current operating parameters include a current load of the processor and a current frequency of the processor, the memory includes a cache and / or a memory, and the current frequency of the memory is used to indicate an amount of data that can be transmitted per unit time;

[0064] Step S102, obtaining a first target frequency of the processor according to the current working parameters and the current frequency of the memory;

[0065] Step S103, obtaining a second target frequency of the memory according to the first target frequency and the current load of the processor;

[0066] Step S104, adjusting the frequency of the processor according to the first target frequency, and adjusting the frequency of the memory according to the second target frequency.

[0067] It should be understood that when the processor of an electronic device runs different loads, the amount of computing that the processor needs to process per unit time is also different, and the actual load value of the corresponding processor core is also different. Therefore, it is necessary to distinguish the different loads that need to be run according to the load value of the processor core, and then further distinguish them according to the load value, the current frequency of the processor and the current frequency of the memory.

[0068] The current frequency of the above memory can be acquired through the software node when the processor core runs the current load. The specific acquisition process adopts common technical means in the prior art, which will not be repeated here.

[0069] The load of the processor refers to the statistical information of the sum of the number of processes or process groups that the processor is processing and waiting to be processed by the processor within a period of time, that is, the statistical information of the length of the processor usage queue. In some embodiments, the load can be characterized by the event count collected by the performance monitoring unit (PMU), which can be used to track and measure various hardware-related events, such as processor cycle counts, cache hits, branch predictions, etc.; the utilization rate of the processor core can also be used to characterize the load.

[0070] The PMU data collected by the PMU may include at least one of the following:

[0071] The total number of CPU cycles spent executing instructions, the number of instructions executed, the number of instructions issued in parallel, the number of cache misses, the maximum value of memory level parallelism (MLP) corresponding to cache misses, the number of TLB misses, the maximum value of memory level parallelism corresponding to TLB misses, the number of CPU cycles of frontend stalls, the number of CPU cycles of backend stalls, the number of CPU cycles of backend memory stalls, the number of branch mispredicted, and the frequency of frequency components.

[0072] In the process of actually obtaining the processor load, take PMU data to represent the load as an example, such as Figure 4 As shown, the process of obtaining the current working parameters of the processor may include:

[0073] 1. Initialize the events of the specified PMU when the system is initialized;

[0074] 2. Bind the PMU events to be collected to the corresponding processor cores to collect PMU data of each core at a regular time, and use the software node to obtain the processor frequency and processor running time;

[0075] 3. Determine whether to enter the acquisition cycle, wherein the acquisition cycle can be a scheduling cycle set by the processor core, or a vsync cycle in units of drawing frames;

[0076] 4. When it is determined that the acquisition cycle has begun, the statistical data set is output, which includes the PMU count corresponding to each processor core and the frequency of each processor core;

[0077] 5. When it is determined that the acquisition cycle has not yet begun, proceed to step 2.

[0078] From the above content, it can be seen that in the embodiment of the present application, when the frequency of the processor is adjusted, the current load and the current frequency of the memory will be used as the basis, so there will be obvious differences in the frequency adjustment tendency for loads with different data processing requirements. For example, for memory-intensive loads, the frequency of the processor after frequency adjustment will be significantly lower than the frequency corresponding to the compute-intensive load, where the compute-intensive load refers to an application that consumes a lot of computing resources and has a large amount of computing, and mainly pursues computing speed; memory-intensive loads usually have low computing resource utilization, and most of the time is spent waiting for input / output (I / O) operations, such as Internet tasks.

[0079] At the same time, the embodiment of the present application also takes into account the impact of the memory frequency on the load when obtaining the first target frequency of the processor, but in the related art, when executing processor frequency modulation, the frequency adjustment is basically performed based on the processor utilization, and the memory frequency is not considered. That is, when executing a certain load task or running a certain application, the specific value of the first target frequency will be different for different memory frequencies.

[0080] In some embodiments, the above-mentioned processor may be at least one or more of a CPU, an AP, a modem processor, a GPU, an ISP, a video codec, a DSP, a baseband processor, and an NPU. The specific configuration may be performed by technicians in the field according to actual conditions, and this application does not impose any limitation thereto.

[0081] Generally, when performing frequency modulation of a processor, the performance of the processor needs to be considered, and the performance of the processor can be represented by cycles per instruction (CPI), wherein the CPI can be represented by the following formula:

[0082] CPI=base_CPI+stall_SPI*cpu_freq;

[0083] Among them, cpu_freq is the frequency of the processor, base_CPI is the number of cycles consumed by a unit instruction when the load itself does not stall, and stall_SPI is the unit instruction stall time of the load on the corresponding architecture CPI. This stall time is not related to the CPU frequency, but to the memory frequency. Taking the memory including L3 / DDR / SLC as an example, stall_SPI can be represented by the frequency of L3 / DDR / SLC:

[0084] stall_SPI=A / L3_freq+B / SLC_freq+C / DDR_freq+D;

[0085] Among them, A, B and C are the acceleration factor of the load under the L3 / SLC / DDR frequency under this architecture, and D is the fixed memory access cost of the load. It can be seen from the above formula that CPI is related to the frequency of the processor, the load and the frequency of the memory, so before specifically executing the above step S102, you can first fit A, B, C, D and base_CPI based on the above formula for stall_SPI through historical PMU events, and then you can get the corresponding relationship between CPI and processor frequency when the processor executes the current load task, and then get the first target frequency of the processor according to the target CPI required by the processor.

[0086] The above fitting process can adopt the fitting method in the prior art, such as decision trees and random forests, and this application does not make any limitation.

[0087] After obtaining the corresponding fitting function through the above fitting method, the first target frequency can be obtained directly according to the fitting function, the current working parameters and the current frequency of the memory when the frequency modulation is actually performed. However, the amount of calculation consumed in the process of determining the fitting function is too large, which is not conducive to improving the frequency modulation efficiency of the processor.

[0088] In order to reduce the computational complexity, the present application embodiment can also adopt the neural network model to perform fitting, and the specific process is as follows: Figure 5 As shown, this may include:

[0089] (1) collecting a first sample data set, where the first sample data set may include a plurality of sample operating parameters of the processor, a plurality of sample frequencies of the memory, and a preset relationship between the frequency of the processor under each sample load and the CPI, where the sample operating parameters include the sample frequency and the sample load;

[0090] The sample load may be represented by PMU data, and the multiple sample frequencies of the processor may be a certain value or a range value, which is not limited in the embodiment of the present application;

[0091] (2) constructing a neural network model framework. When constructing the neural network model framework, it is usually necessary to construct the number of layers of the neural network model, the number of nodes in each layer, the upper limit of the number of iterative training times, and the training method. The training method may include the gradient descent method, Newton algorithm, conjugate gradient method, quasi-Newton method, and attenuated least squares method, etc., which are not limited in the embodiments of the present application;

[0092] When constructing a neural network model framework, one training method may be selected, or multiple training methods may be used for training, and an optimal training method may be selected according to the training results as the training method of the neural network model framework;

[0093] (3) refreshing the training data, that is, removing the noise data in the first sample data set, wherein the method for cleaning the noise data may be a normalization method, etc., which is not limited in the present application;

[0094] In order to avoid a small amount of remaining training data after removing the noise data, in this step, the load scenario of the processor can be simulated to obtain new training data, and after the new training data is cleaned, it is added to the remaining training data to ensure that the neural network model can be trained with sufficient sample data;

[0095] (4) Iterative training using the refreshed training data and neural network model framework;

[0096] (5) Obtain training results of iterative training;

[0097] (6) Determine the comparison between the error of the training result and the tolerance of the training data;

[0098] Among them, if the error of the training result is greater than the tolerance, it indicates that there may be a large error when the CPI corresponding to the sample frequency is determined by the neural network model. In this case, it can be further determined whether the training process needs to be corrected. Usually, when the error of the training result is greater than the tolerance of the training data and the difference is greater than a certain threshold, it is determined that the training process needs to be corrected;

[0099] If the training process needs to be corrected, the training method of the neural network model can be adjusted, and / or the number of layers of the neural network model framework and the nodes of each layer can be adjusted, and iterative training can be performed again using the adjusted training method until the adjusted neural network model is a valid neural network model, and then the training is determined to be completed, so as to determine the computing power of the chip through the adjusted neural network model;

[0100] (7) If the error of the training result is not greater than the tolerance of the training data, the effectiveness of the neural network model can be further evaluated;

[0101] When evaluating the effectiveness of the neural network model, the simulation of the business scenario of the operating system can be combined to determine whether the error between the sample working parameters and CPI determined in the business scenario is within the allowable range. Generally, if the error is within the allowable range, it means that the error in determining the corresponding relationship between frequency and CPI through the neural network model is small, and the neural network model can be determined to be effective.

[0102] (8) If the neural network model is determined to be effective through evaluation, the training is completed and the first network model is obtained.

[0103] In some embodiments, after obtaining the first network model, the corresponding relationship between CPI and frequency can be obtained through the first network model, and then the first target frequency of the processor can be further obtained by determining the target value of CPI, that is, the above step S102 may include:

[0104] Step S1021, inputting the current load and the current frequency of the memory into the first network model, and outputting the corresponding relationship between the frequency of the processor and the number of cycles per instruction CPI under the current load;

[0105] Step S1022, obtaining a target CPI value of the processor according to a predicted load of the processor, where the predicted load is obtained according to a current load prediction;

[0106] Step S1023: Obtain a first target frequency according to the target value and the corresponding relationship of the CPI.

[0107] In a specific implementation, in order to accurately reflect the actual performance requirements of the device and reduce power consumption losses while meeting the performance requirements of the device, the electronic device can use the predicted load as the target value of the target working parameter, that is, after each actual load is obtained, the predicted load of the processor core can be determined according to the load prediction algorithm, and then the processor frequency can be adjusted according to the predicted load.

[0108] Generally, CPI can be expressed by processor utilization or instructions per second (IPS). Generally, the following steps are included to calculate processor utilization through CPI:

[0109] 1. Determine the CPI value: First, you need to know the CPI value corresponding to the execution of the load task, that is, the average number of clock cycles required for each instruction. This value can be calculated by analyzing the instruction type and proportion of the load program. For example, if a program contains 50% type A instructions, its CPI is 2, and 20% type B instructions, its CPI is 3, then the average CPI of the entire program is 0.5×2+0.2×3=1.7.

[0110] 2. Calculate the total number of clock cycles: Multiply the total number of instructions (IC) of the program by the CPI value to get the total number of clock cycles (TC), that is, TC = IC × CPI.

[0111] 3. Determine the current frequency of the processor.

[0112] 4. Calculate the processor execution time: Use the formula:

[0113] 5. Calculate processor utilization: If the ratio of the processor execution time to the total time in a monitoring cycle is the processor device utilization. The formula is:

[0114] The following formula can be used to calculate IPS through CPI:

[0115]

[0116] It should be understood that the above calculation formula between CPI and IPS assumes that all cores of the CPU are running at full speed and there are no other limiting factors such as memory bandwidth or I / O operations. In actual applications, IPS may be lower than the theoretical maximum value due to these factors.

[0117] Based on the calculation process between the CPI and the processor utilization or the calculation process between the CPI and the IPS, if the load can be indicated by the number of instructions per second IPS and / or the processor utilization, the step S1022 may include:

[0118] Step S10221, obtaining a target value of the number of instructions per second IPS of the processor and / or the utilization of the processor, where the target value is used to indicate a predicted value of the number of instructions per second IPS and / or the utilization of the processor;

[0119] Step S10222, determining the target value of CPI according to the correspondence between the preset value of the target working parameter and the preset value of CPI and the target value.

[0120] Among them, the above-mentioned target value can be obtained by estimating the value of the number of instructions per second IPS and / or the processor utilization in the next time period based on the value of the number of instructions per second IPS and / or the processor utilization in the target time period, and the target time period includes at least one historical time period and a current time period; it can also be obtained by increasing or decreasing a certain value according to the current load based on the current value of the number of instructions per second IPS and / or the processor utilization, which is specifically set by technical personnel in this field according to actual conditions, and this application does not impose any restrictions.

[0121] Taking the target value as the predicted value of the number of instructions per second IPS and / or the utilization rate of the processor in the next time period as an example, the above-mentioned current working parameter also includes the running time, and the step of obtaining the above-mentioned predicted load may include:

[0122] Obtaining the value of the target working parameter in the previous time period and the value of the target working parameter in the current time period, where the previous time period and the current time period are determined according to the running time, and the value of the target working parameter in the current time period is determined according to the current working parameter;

[0123] According to the values ​​of the target working parameters in the previous time period, the values ​​of the target working parameters in the current time period and the weights corresponding to each time period, the values ​​of the target working parameters in the next time period are predicted;

[0124] The value of the target operating parameter in the next time period is used as the target value of the target operating parameter.

[0125] For example, Figure 6As shown, after obtaining the value of IPS / processor utilization util in the N-1th time window and the value of IPS / util in the Nth time window, the value of IPS / util in the N+1th time window can be predicted based on the value of IPS / util in the N-1th time window and the value of IPS / util in the Nth time window and the weight value A1 of the N-1th time window and the weight value A2 of the Nth time window, so that the predicted value is used as the target value.

[0126] The weight corresponding to each of the above time periods can be determined based on the prediction error of the target operating parameters in each time period, or can be manually set by a technician, which is specifically set by a technician in this field according to actual conditions, and this application does not limit it. However, determining the corresponding weight value based on the prediction error of the target operating parameters in each time period can improve the accuracy of the predicted load value.

[0127] For example, Figure 7 As shown, taking the example that the weight corresponding to each time period is determined according to the prediction error of IPS in each time period, after obtaining the actual value of IPS in the N-1th time window and the actual value of IPS in the Nth time window, the predicted value of IPS in the N+1th time window can be predicted based on the actual value of IPS in the N-1th time window and the actual value of IPS in the Nth time window, and the predicted value of IPS in the N+2th time window can be predicted based on the actual value of IPS in the Nth time window and the actual value of IPS in the N+1th time window, that is, Figure 7 In method 1, the target value of IPS is pred_IPS n+1 The calculation process may include:

[0128]

[0129]

[0130] Among them, pred_rate is the weight value corresponding to the Nth time window, pred_IPS n is the predicted value of IPS in the Nth time window, IPS n is the actual value of IPS in the Nth time window, and α is a fixed prediction error coefficient.

[0131] Among them, when the prediction accuracy of IPS in the Nth time window predicted by the actual value of IPS in the N-2th time window and the actual value of IPS in the N-1th time window reaches 100%, the predicted value of IPS in the Nth time window can be directly used to predict the predicted value of IPS in the N+1th time window, that is, Figure 7Method 2 in .

[0132] In some embodiments, the predicted load may also be calculated by other prediction algorithms trained according to an artificial intelligence (AI) model. Specifically, the prediction algorithm is used to predict the estimated load value of the processor core in the N+1th time window based on actual load values ​​of multiple time windows before (including the Nth time window) the Nth time window.

[0133] In order to meet the user's sensitivity to processor performance, generally after obtaining the predicted value of the next time window, a certain proportion of processor computing power can be given on the basis of this predicted value, that is, on the basis of this predicted value, a certain value is increased, and the increased predicted value is used as the target value. The specific value of this increase can be set by technical personnel in this field according to actual conditions, and this application does not impose any restrictions.

[0134] In some embodiments, such as Figure 8 As shown, the above step S1023 may include:

[0135] The first target frequency and the current load are input into the second network model, and the second target frequency of the memory is output. The second network model is trained based on the second sample data set, and the second sample data set includes multiple sample frequencies of the processor, multiple sample frequencies of the memory, and multiple sample loads.

[0136] The above-mentioned second network model can use the performance (IPS / Watt) that can be obtained within the unit power consumption as an indicator to measure the second target frequency of the memory. By inputting a sample frequency of the processor and multiple sample loads into the second network model, the optimal memory frequency can be found from the multiple sample frequencies of the memory.

[0137] In some embodiments, the multiple sample frequencies of the memory in the second sample data set may be obtained by the following steps:

[0138] Fix the processor frequency, get the performance and power consumption (IPS / Watt) of different memory frequencies, select the memory frequency with the best energy efficiency under the performance constraint (10% lower than the highest performance) as a sample frequency. And so on, you can get a sample frequency set including the best memory frequency under different processor frequencies.

[0139] Among them, the training process of the above-mentioned second network model is similar to the training process of the first network model, which will not be repeated here.

[0140] Since usually, the flash memory, cache and memory in the memory may exist at the same time, and each component has multiple frequency bands to choose from, the second target frequency here can be simply expressed as a frequency band range, and the second network model selects the target frequency band corresponding to the current load and the first target frequency from the multiple sample frequencies of the memory, and thus uses the target frequency band as the second target frequency.

[0141] From the above content, it can be seen that when the processor executes different load tasks, in addition to the difference in processor frequency, the memory frequency is also different, that is, when the processor runs at the same first target frequency and executes compute-intensive loads, the memory frequency is different from the memory frequency when executing memory-intensive loads. This is different from the single mapping relationship between processor frequency and memory frequency in the related art.

[0142] Based on hardware design, the electronic device can divide multiple processor cores in the electronic device into one or more frequency modulation domains, each frequency modulation domain includes one or more processor cores, and each processor core is divided into a frequency modulation domain. Furthermore, the processor cores in the same frequency modulation domain need to adopt the same frequency modulation strategy; the processor cores in different frequency modulation domains can adopt the same or different frequency modulation strategies.

[0143] For example, the electronic device includes processor cores 1 to 64, wherein processor cores 1 to 16 are divided into frequency modulation domain 1, processor cores 17 to 32 are divided into frequency modulation domain 2, processor cores 33 to 48 are divided into frequency modulation domain 3, and processor cores 49 to 64 are divided into frequency modulation domain 4. The frequency management unit can determine a frequency modulation strategy for each frequency modulation domain in frequency modulation domains 1 to 4 according to the user's requirements for the processor cores in the frequency modulation domain to run tasks. For example, if the user sets the processor cores in frequency modulation domains 1 to 3 to run tasks with performance as the priority, the frequency management unit can set the frequency modulation strategy of the frequency modulation domains 1 to 3 to be performance priority; if the user sets the processor cores in frequency modulation domain 4 to run tasks according to the load value of the processor cores, the frequency management unit can set the frequency modulation strategy of the frequency modulation domain 4 to be load frequency modulation.

[0144] Furthermore, when the frequency modulation domain includes multiple processor cores, the multiple processor cores may be located in the same processor or in multiple different processors. Still in combination with the above example, the electronic device includes processors 1 to 3, processor cores 1 to 8 in frequency modulation domain 1 are located in processor 1, processor cores 9 to 16 are located in processor 2, and processor cores 17 to 32 in frequency modulation domain 2 are all located in processor 3.

[0145] In addition, since the processor cores in the same frequency modulation domain need to adopt the same frequency modulation strategy, the target frequencies of the processor cores in the same frequency modulation domain are the same. When different frequency modulation domains adopt the same frequency modulation strategy, the target frequencies of the processor cores in the different frequency modulation domains can be the same; when different frequency modulation domains adopt different frequency modulation strategies, that is, when two processor cores in different frequency modulation domains adopt different frequency modulation strategies, the target frequencies adopted by the two processor cores in the different frequency modulation domains can be different.

[0146] Among them, the above-mentioned frequency modulation strategy may include a performance-oriented strategy and a power consumption-oriented strategy. Under the performance tendency, in order to meet the performance requirements of each core, the maximum value of the target CPU frequency calculated by each core will be taken as the final processor frequency of the frequency modulation domain; under the power consumption tendency, the weighted frequency of each core target frequency weighted by utilization will be taken as the final processor frequency of the frequency modulation domain.

[0147] That is, if there are multiple processor cores in the same frequency modulation domain, then the first target frequency including the first sub-frequency corresponding to each processor core can be obtained through the above steps S101 to S102, such as Fig. 9 As shown, the process of adjusting the frequency of the processor according to the first target frequency in the above step S104 may include:

[0148] S1041, obtaining a final frequency of the processor according to a plurality of first sub-frequencies of a plurality of processor cores and a preset determination strategy;

[0149] S1042: Adjust the frequency of each processor core according to the final frequency of the processor.

[0150] Among them, the above-mentioned preset determination strategy can be pre-set by technical personnel in this field according to the situation, or it can be determined according to the current power of the electronic device. For example, when the current power is greater than or equal to the power threshold, a performance-oriented strategy is adopted, and when the current power is greater than or equal to the power threshold, a power consumption-oriented strategy is adopted. The specific setting is made by technical personnel in this field according to the actual situation, and this application does not impose any restrictions.

[0151] In some embodiments, if the preset determination strategy includes taking the maximum value among multiple first sub-frequencies of multiple processor cores as the final frequency, the S1041 may include:

[0152] The final frequency of the processor is determined from the multiple first sub-frequencies, and the final frequency of the processor is the maximum value of the multiple first sub-frequencies.

[0153] In some other embodiments, if the preset determination strategy includes taking a weighted average of a plurality of first sub-frequencies of a plurality of processor cores weighted according to the magnitude of the target operating parameter as the final frequency, the S1041 may include:

[0154] A final frequency of the processor is obtained according to the multiple first sub-frequencies, and a frequency value of the final frequency of the processor is a weighted average value of the multiple first sub-frequencies weighted according to the magnitude of the target operating parameter.

[0155] For example, taking the target operating parameter as the processor utilization util as an example, the calculation formula for the frequency value target_freq of the final frequency of the processor is:

[0156]

[0157] Sum_util=util0+util1+…+utiln.

[0158] Among them, util0 to utiln refer to the util of the nth processor core, and target_freqi is the first sub-frequency corresponding to the ith processor core.

[0159] As for the frequency decision of the memory, the final frequency of the memory is usually determined by a voting mechanism. Therefore, the final frequency of the memory in the embodiment of the present application is also determined by voting. The target frequency of the memory corresponding to each processor core participates in the voting. When performance is preferred, the maximum value of all votes is taken for frequency adjustment. When power consumption is preferred, the minimum value of all intervals is taken for frequency adjustment.

[0160] That is, the second target frequency includes a plurality of second sub-frequencies, and the plurality of first sub-frequencies correspond one to one with the plurality of second sub-frequencies. The step of adjusting the frequency of the memory according to the second target frequency in step S104 may include:

[0161] Determining a final frequency of the memory from the plurality of second sub-frequencies, the final frequency of the memory being one of the plurality of second sub-frequencies;

[0162] Adjust the frequency of the memory according to the final frequency of the memory.

[0163] It should be understood that the final frequency of the above-mentioned memory can be the second sub-frequency corresponding to the target first sub-frequency, and the target first sub-frequency is the one that appears the most times among multiple first sub-frequencies, or it can be the minimum value among multiple second sub-frequencies. The specific setting is made by technical personnel in this field according to actual conditions, and this application does not impose any restrictions.

[0164] The following describes an exemplary application of the embodiments of the present application in a practical application scenario.

[0165] Fig.10 Schematic diagram of the implementation process of the frequency adjustment method provided in the embodiment of the present application. Fig.10As shown in the figure, the method can be divided into three stages from the functional framework: data collection, load prediction and frequency decision, among which:

[0166] The data collection phase may include the following steps:

[0167] When the system is initialized, the designated PMU event is initialized through the PMU, and when the electronic device is running under the current load, the PMU event is collected, and the collected PMU event is bound to the corresponding CPU core for periodic collection of PMU data of each CPU core, and the frequency and running time of the CPU are obtained by using the software node. Among them, the collection cycle in this embodiment can be a scheduling cycle specified by the kernel or a vsync cycle in units of drawing frames. Each CPU core independently maintains its own collection data, and when the cycle arrives, it will obtain the required data from each CPU core.

[0168] Among them, the specified PMU event may include at least one or more of CPU operation data and memory operation data, the CPU operation data may include the number of executed instructions, the number of captured exceptions and the number of clock cycles, etc., and the memory operation data may include the number of memory accesses and the number of memory misses, etc.

[0169] Load forecasting can include the following steps:

[0170] 1. Load tracking:

[0171] According to the PMU data and running time of each CPU core, the IPS / util values ​​of N time windows of each CPU core are obtained, and the target IPS / util value of the N+1 window of the corresponding CPU core is predicted by using the IPS / util values ​​of the N-1th and Nth windows of each CPU core and the prediction error of the Nth window.

[0172] 2. Calculation of target frequency of CPU core:

[0173] Then, the L3 / SLC / DDR frequency and the PMU information of each CPU core are input into the first network model, and the performance (CPI) of the corresponding load at different CPU frequencies is output. Finally, the target frequency of each CPU core can be determined by combining the CPI of the corresponding load at different CPU frequencies and the target IPS / util value.

[0174] 3. Calculation of target frequency of L3 / SLC / DDR:

[0175] The PMU data of each CPU core and the target frequency of each CPU core are input into the second network model, and the target frequency of L3, the target frequency of DDR and the target frequency of SLC corresponding to each CPU core are output respectively.

[0176] Frequency decision making can include the following steps:

[0177] The CPU frequency decision logic is mainly divided into performance tendency and power consumption tendency. Under performance tendency, in order to meet the performance requirements of each core, the maximum value of the target CPU frequency calculated by each CPU core will be taken as the final CPU frequency of the cluster; under power consumption tendency, the weighted frequency of the target frequency of each CPU core weighted by utilization will be taken as the final CPU frequency of the cluster.

[0178] For the frequency decision of the memory access architecture, the memory access frequency is determined by a voting mechanism. The SLC / L3 / DDR frequencies corresponding to each CPU core all participate in the voting. When performance is preferred, the maximum value of all votes is taken for frequency adjustment. When power consumption is preferred, the minimum value of all intervals is taken for frequency adjustment.

[0179] Compared with the related art, the frequency adjustment method of this embodiment has the following advantages:

[0180] (1) This application takes into account the load characteristics, CPU architecture and memory access link frequency when performing CPU frequency adjustment, making the CPU frequency decision more reasonable.

[0181] (2) This application implements coordinated frequency modulation of the memory access link frequency to ensure that both the load and the CPU frequency are taken into account, so that the memory access link frequency decision is more in line with actual needs.

[0182] (3) The present application realizes the coordinated frequency modulation of CPU and memory access link through two major models. In the decision cycle of the present application, the optimal CPU frequency for the next cycle is calculated first, and then the optimal memory access link frequency based on this frequency and load is calculated to ensure the coordinated work of CPU resources and memory access resources.

[0183] (4) This application uses a sliding window to predict CPU load, and uses the prediction error as a reward and penalty coefficient to improve the load prediction effect.

[0184] It should be understood that although Figure 3-10 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3-10 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0185] Based on the foregoing embodiments, an embodiment of the present application provides a frequency adjustment device, which includes the modules included and the units included in the modules, which can be implemented by a processor; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0186] Fig.11 A schematic diagram of the structure of the frequency adjustment device provided in the embodiment of the present application is shown in FIG. Fig.11 As shown, the device comprises:

[0187] The parameter acquisition module 1101 is used to acquire the current working parameters of the processor of the electronic device in the running state and the current frequency of the memory of the electronic device, the current working parameters include the current load of the processor and the current frequency of the processor, the memory includes a cache and / or a memory, and the current frequency of the memory is used to indicate the amount of data that can be transmitted per unit time;

[0188] A first frequency obtaining module 1102, configured to obtain a first target frequency of the processor according to current operating parameters and a current frequency of the memory;

[0189] A second frequency obtaining module 1103 is used to obtain a second target frequency of the memory according to the first target frequency and the current load of the processor;

[0190] The frequency adjustment module 1104 is configured to adjust the frequency of the processor according to the first target frequency, and adjust the frequency of the memory according to the second target frequency.

[0191] In some embodiments, the first frequency obtaining module 1102 may be specifically used for:

[0192] Inputting the current load and the current frequency of the memory into the first network model, and outputting the corresponding relationship between the frequency of the processor and the number of cycles per instruction CPI under the current load, wherein the first network model is obtained by training based on the first sample data set, and the first sample data set includes multiple sample operating parameters of the processor, multiple sample frequencies of the memory, and a preset relationship between the frequency of the processor under each sample load and the CPI, and the sample operating parameters include the sample frequency and the sample load;

[0193] According to the predicted load of the processor, a target value of the CPI of the processor is obtained, where the predicted load is obtained based on the current load prediction;

[0194] According to the target value of CPI and the corresponding relationship, a first target frequency is obtained.

[0195] In some embodiments, the first frequency obtaining module 1102 may be specifically used for:

[0196] Obtaining a target value of a target operating parameter of the processor, the target operating parameter including instructions per second IPS and / or processor utilization, the target operating parameter being used to indicate a predicted load;

[0197] The target value of the CPI is determined based on the correspondence between the preset value of the target working parameter and the preset value of the CPI and the target value.

[0198] In some embodiments, the current operating parameter also includes the operating time, and the first frequency obtaining module 1102 can be specifically used for:

[0199] Obtaining the value of the target working parameter in the previous time period and the value of the target working parameter in the current time period, where the previous time period and the current time period are determined according to the running time, and the value of the target working parameter in the current time period is determined according to the current working parameter;

[0200] According to the values ​​of the target working parameters in the previous time period, the values ​​of the target working parameters in the current time period and the weights corresponding to each time period, the values ​​of the target working parameters in the next time period are predicted;

[0201] The value of the target operating parameter in the next time period is used as the target value of the target operating parameter.

[0202] In some embodiments, the weight corresponding to each of the above time periods is determined according to the prediction error of the target operating parameter in each time period.

[0203] In some embodiments, the second frequency obtaining module 1103 may be specifically used for:

[0204] The first target frequency and the current load are input into the second network model, and the second target frequency of the memory is output. The second network model is trained based on the second sample data set, and the second sample data set includes multiple sample frequencies of the processor, multiple sample frequencies of the memory, and multiple sample loads.

[0205] In some embodiments, the processor includes multiple processor cores, the first target frequency includes a first sub-frequency corresponding to each processor core in the multiple processor cores, and the frequency adjustment module 1104 may be specifically used to:

[0206] Obtaining a final frequency of the processor according to a plurality of first sub-frequencies of a plurality of processor cores and a preset determination strategy;

[0207] Adjust the frequency of each processor core according to the final frequency of the processor.

[0208] In some embodiments, the preset determination strategy includes taking the maximum value among the multiple first sub-frequencies of the multiple processor cores as the final frequency, and the frequency adjustment module 1104 may be specifically used to:

[0209] A final frequency of the processor is determined from the multiple first sub-frequencies, where the final frequency of the processor is one of the multiple first sub-frequencies.

[0210] In some embodiments, the preset determination strategy includes taking a weighted average of a plurality of first sub-frequencies of a plurality of processor cores weighted according to the magnitude of the second operating parameter as the final frequency, and the frequency adjustment module 1104 may be specifically used for:

[0211] A final frequency of the processor is obtained according to the multiple first sub-frequencies, and a frequency value of the final frequency of the processor is a weighted average value of the multiple first sub-frequencies weighted according to the magnitude of the target operating parameter.

[0212] In some embodiments, the second target frequency includes a plurality of second sub-frequencies, and the plurality of first sub-frequencies correspond one-to-one to the plurality of second sub-frequencies. The frequency adjustment module 1104 may be specifically used for:

[0213] Determining a final frequency of the memory from the plurality of second sub-frequencies, the final frequency of the memory being one of the plurality of second sub-frequencies;

[0214] Adjust the frequency of the memory according to the final frequency of the memory.

[0215] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0216] It should be noted that in the embodiments of this application Fig.11 The division of the modules in the frequency adjustment device shown is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, or may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit. It may also be implemented in the form of a combination of software and hardware.

[0217] It should be noted that in the embodiment of the present application, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product that contributes to the relevant technology. The computer software product is stored in a storage medium, including several instructions to enable an electronic device to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific combination of hardware and software.

[0218] An embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the method provided in the above embodiment are implemented.

[0219] An embodiment of the present application provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the steps of the method provided in the above method embodiment.

[0220] In one embodiment, the frequency adjustment device provided by the present application can be implemented in the form of a computer program, and the computer program can be run on a computer device. The memory of the computer device can store various program modules constituting the electronic device. The computer program composed of various program modules enables the processor to execute the steps of the frequency adjustment method of each embodiment of the present application described in this specification.

[0221] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above frequency adjustment method when executing the computer program.

[0222] In one embodiment, a chip and a processor are provided. The processor is connected to a memory and is used to execute a computer program or instruction stored in the memory. When the computer program or instruction is executed, the above-mentioned frequency adjustment method is executed.

[0223] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium, storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0224] It should be understood that "one embodiment" or "an embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in one embodiment" or "in some embodiments" appearing throughout the specification may not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. The above description of each embodiment tends to emphasize the differences between the various embodiments, and the same or similarities can be referenced to each other. For the sake of brevity, this article will not repeat them.

[0225] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist at the same time, and object B exists alone.

[0226] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0227] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or modules can be electrical, mechanical or other forms.

[0228] The modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules; they may be located in one place or distributed on multiple network units; some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0229] In addition, all functional modules in the embodiments of the present application may be integrated into one processing unit, or each module may be a separate unit, or two or more modules may be integrated into one unit; the above-mentioned integrated modules may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0230] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0231] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling an electronic device to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0232] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0233] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0234] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0235] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A frequency adjustment method, characterized in that: Applied to electronic equipment, the method comprises: Acquire current operating parameters of the processor of the electronic device in a running state and a current frequency of a memory of the electronic device, wherein the current operating parameters include a current load of the processor and a current frequency of the processor, the memory includes a cache and / or a memory, and the current frequency of the memory is used to indicate an amount of data that can be transmitted per unit time; Obtaining a first target frequency of the processor according to the current operating parameter and the current frequency of the memory; Obtaining a second target frequency of the memory according to the first target frequency and a current load of the processor; The frequency of the processor is adjusted according to the first target frequency, and the frequency of the memory is adjusted according to the second target frequency.

2. The method according to claim 1, characterized in that The obtaining, according to the current operating parameter and the current frequency of the memory, a first target frequency of the processor includes: Inputting the current load and the current frequency of the memory into a first network model, and outputting a corresponding relationship between the frequency of the processor and the number of cycles per instruction (CPI) under the current load, wherein the first network model is obtained by training based on a first sample data set, wherein the first sample data set includes a plurality of sample operating parameters of the processor, a plurality of sample frequencies of the memory, and a preset relationship between the frequency of the processor under each sample load and the CPI, wherein the sample operating parameters include a sample frequency and a sample load; Obtaining a target value of the CPI of the processor according to a predicted load of the processor, wherein the predicted load is obtained according to the current load prediction; The first target frequency is obtained according to the target value of the CPI and the corresponding relationship.

3. The method according to claim 2, characterized in that The obtaining, according to the predicted load of the processor, a target value of the CPI of the processor includes: Obtaining a target value of a target operating parameter of the processor, wherein the target operating parameter includes instructions per second IPS and / or processor utilization, and the target operating parameter is used to indicate the predicted load; The target value of the CPI is determined according to the corresponding relationship between the preset value of the target operating parameter and the preset value of the CPI and the target value.

4. The method according to claim 3, characterized in that The current operating parameter also includes the running time, and obtaining the target value of the target operating parameter of the processor includes: Obtaining a value of a target operating parameter in a previous time period and a value of a target operating parameter in a current time period, wherein the previous time period and the current time period are determined according to the running time, and the value of the target operating parameter in the current time period is determined according to the current operating parameter; Predicting the value of the target operating parameter in the next time period according to the value of the target operating parameter in the previous time period, the value of the target operating parameter in the current time period, and the weight corresponding to each time period; The value of the target operating parameter in the next time period is used as the target value of the target operating parameter.

5. The method according to claim 4, characterized in that The weight corresponding to each time period is determined according to the prediction error of the target operating parameter in each time period.

6. The method according to claim 1, characterized in that The obtaining, according to the first target frequency and the current load of the processor, a second target frequency of the memory includes: The first target frequency and the current load are input into a second network model, and a second target frequency of the memory is output. The second network model is trained based on a second sample data set, and the second sample data set includes multiple sample frequencies of the processor, multiple sample frequencies of the memory, and multiple sample loads.

7. The method according to claim 1, characterized in that The processor includes a plurality of processor cores, the first target frequency includes a first sub-frequency corresponding to each processor core in the plurality of processor cores, and adjusting the frequency of the processor according to the first target frequency includes: Obtaining a final frequency of the processor according to the plurality of first sub-frequencies of the plurality of processor cores and a preset determination strategy; The frequency of each processor core is adjusted according to the final frequency of the processor.

8. The method according to claim 7, characterized in that The preset determination strategy includes taking the maximum value of the multiple first sub-frequencies of the multiple processor cores as the final frequency, and obtaining the final frequency of the processor according to the multiple first sub-frequencies of the multiple processor cores and the preset determination strategy includes: A final frequency of the processor is determined from the multiple first sub-frequencies, where the final frequency of the processor is a maximum value of the multiple first sub-frequencies.

9. The method according to claim 7, characterized in that The preset determination strategy includes taking a weighted average of the multiple first sub-frequencies of the multiple processor cores weighted according to the size of the target operating parameter as the final frequency, and obtaining the final frequency of the processor according to the multiple first sub-frequencies of the multiple processor cores and the preset determination strategy, including: A final frequency of the processor is obtained according to the multiple first sub-frequencies, wherein a frequency value of the final frequency of the processor is a weighted average of the multiple first sub-frequencies weighted according to the magnitude of the target operating parameter.

10. The method according to claim 7, characterized in that The second target frequency includes a plurality of second sub-frequencies, the plurality of first sub-frequencies correspond one-to-one to the plurality of second sub-frequencies, and the step of adjusting the frequency of the memory according to the second target frequency includes: Determining a final frequency of the memory from the plurality of second sub-frequencies, the final frequency of the memory being one of the plurality of second sub-frequencies; The frequency of the memory is adjusted according to the final frequency of the memory.

11. A frequency adjustment device, characterized in that: The frequency adjustment device comprises: A parameter acquisition module, used to acquire current operating parameters of a processor of an electronic device in a running state and a current frequency of a memory of the electronic device, wherein the current operating parameters include a current load of the processor and a current frequency of the processor, the memory includes a cache and / or a memory, and the current frequency of the memory is used to indicate an amount of data that can be transmitted per unit time; A first frequency obtaining module, used for obtaining a first target frequency of the processor according to the current operating parameters and the current frequency of the memory; A second frequency obtaining module, configured to obtain a second target frequency of the memory according to the first target frequency and a current load of the processor; A frequency adjustment module is used to adjust the frequency of the processor according to the first target frequency, and to adjust the frequency of the memory according to the second target frequency.

12. An electronic device, characterized in that: The electronic device comprises the frequency adjustment device according to claim 11.

13. A computer program medium, characterized in that The computer program medium includes a computer program or an instruction. When the computer program or the instruction is executed on a computer, the computer is caused to execute the frequency adjustment method according to any one of claims 1 to 10.

14. A chip, characterized in that: The chip includes a processor, which is connected to a memory and is used to execute a computer program or instruction stored in the memory. When the computer program or instruction is executed, the frequency adjustment method according to any one of claims 1 to 10 is executed.

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