A high efficiency data exchange system and method for a digital inkjet printer

Abstract

The application discloses a high-efficiency data exchange system and method for a digital ink-jet printer, and relates to the technical field of printers. The system comprises an MCU and an FPGA, wherein the MCU serves as a device controller to provide a command and a buffer address and triggers automatic address increase; the FPGA is responsible for reading buffer content and performing relevant processing; the system further comprises a DRAM used for storing printing data; the DRAM is located between the MCU and the FPGA; the application introduces a high-speed dynamic random access memory chip as a data exchange medium between the MCU and the FPGA, so that the problems of bandwidth bottleneck, unmatched data transmission rate and low system response speed existing in a traditional data bus architecture are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of printers, and particularly relates to a high-efficiency data exchange system and method for a digital inkjet printer. BACKGROUND

[0002] In modern digital inkjet printer systems, data exchange between the microcontroller unit (MCU) and the field programmable gate array (FPGA) is crucial for achieving high-efficiency printing. However, with the improvement of printing functions and speed, traditional data bus architectures face bandwidth bottlenecks, mismatched data transmission rates, and low system response speeds, which limit the performance and application range of the printer. In order to address these challenges, there is an urgent need for a new data exchange architecture to improve data transmission rates, alleviate bandwidth limitations, and reduce system latency, thereby improving the overall performance and printing efficiency of digital inkjet printers. SUMMARY

[0003] The present application relates to the technical field of printers, and particularly relates to a high-efficiency data exchange system and method for a digital inkjet printer.

[0004] The object of the present application can be achieved by the following technical solutions:

[0005] The present application provides a high-efficiency data exchange system for a digital inkjet printer, comprising an MCU and an FPGA, wherein the MCU serves as a device controller to provide commands and buffer addresses and trigger automatic address increment; the FPGA is responsible for reading buffer content and performing related processing; further comprising a DRAM for storing printing data; the DRAM is located between the MCU and the FPGA;

[0006] The MCU and the FPGA are connected to the DRAM through a parallel 16-bit bus.

[0007] Further, a control line multiplexing module is included for bidirectional access of the MCU and the FPGA to the DRAM through the control line multiplexing module.

[0008] Further, when the MCU and the FPGA access the DRAM through the control line multiplexing module, a timing control algorithm is used to monitor access requests of the MCU and the FPGA to the DRAM and dynamically switch control signals between the two; the specific content includes:

[0009] S11, use the logic inside the FPGA to build a request arbitration logic, and dynamically give the MCU or the FPGA access permission according to the preset priority rules;

[0010] S12, transmit data from the internal buffer of MCU or FPGA to the address of DRAM directly through the DMA controller, or read from DRAM to the specified buffer;

[0011] S13, generate the control signal with accurate timing by using the programmable logic of FPGA, determine the opening and closing of the corresponding signal to execute the read and write operation of DRAM; after determining the access sequence and preparing the address and data, dynamically switch the control signal to allow the current device to read and write the operation of DRAM;

[0012] S14, after the control signal is correctly set, the data will be transmitted from MCU to the write operation of DRAM, or from DRAM to the read operation of FPGA.

[0013] Further, it also includes a data exchange and synchronization module, the MCU writes data blocks in batch mode to DRAM, and sends a write completion signal to FPGA through the control line, FPGA reads data from DRAM for processing after receiving the signal, and feeds back the signal to MCU after processing.

[0014] Further, according to the data exchange and synchronization module, the dynamic data exchange and synchronization optimization algorithm optimizes the bidirectional data exchange process of MCU and FPGA to DRAM, and the specific content includes:

[0015] S21, use data flow analysis technology to monitor data access mode, and obtain relevant information about how data flows along the program execution path by constructing control flow graph and data flow graph;

[0016] S22, based on the result of data flow analysis, dynamically adjust the access priority of DRAM according to the real-time data processing requirements of MCU and FPGA through dynamic scheduler; wherein the scheduler uses advanced data flow analysis technology to predict data access mode and optimize access sequence;

[0017] S23, after optimizing the access sequence, the size and management strategy of data block will be dynamically adjusted according to the characteristics of data and the current load condition by realizing version control and conflict detection mechanism.

[0018] Further, the minimum cost maximum flow algorithm is used to adjust the data transmission path for optimizing data flow; specifically, by constructing a directed weighted graph, the data transmission scheme with the lowest output cost is found under the premise of meeting the maximum flow, which specifically includes:

[0019] Set G=(V,E) as a network, where V is the vertex set, E is the edge set, each edge (u,v) ∈ E has two attributes: capacity c(u,v) and unit flow cost a(u,v); the flow f(u,v) represents the data amount through the edge (u,v).

[0020] The objective of the minimum cost maximum flow is to find a flow distribution scheme f such that the total flow from the source s to the sink t is maximized while the total cost is minimized, the minimum total cost B(f) is expressed as:

[0021]

[0022] Where f(u, v) is the flow on edge (u, v) and a(u, v) is the unit flow cost of edge (u, v).

[0023] Further, the constraint condition of the minimum cost maximum flow is limited as:

[0024] Capacity constraint: for each edge (u, v) e E, 0 < f(u, v) < c(u, v);

[0025] Flow conservation: for each vertex v e V \ {s, t},

[0026] Σ (u，υ)∈E f(u, v) = Σ (u，w)∈E f(u, v);

[0027] Flow range: for all edges (u, v) e E, f(u, v) > 0.

[0028] Further, the network service support module is further included, data is transmitted through the network and stored into the DRAM, the FPGA accesses the DRAM in time according to the demand, and the required ink output data is obtained.

[0029] Further, after the data is transmitted through the network and stored into the DRAM, and the FPGA accesses the DRAM in time according to the demand, the required ink output data is obtained, the method further includes that the FPGA uses the edge computing technology to perform real-time processing on the data received through the network, stores the processing result into the DRAM, and reads the data in time according to the specific demand of the printing task, through the closed loop control mechanism, the FPGA monitors the processing result in real time after processing the data, and sends the processing state back to the MCU through the feedback path, and adjusts.

[0030] A method for efficient data exchange of a digital inkjet printer, using the above-mentioned efficient data exchange system for a digital inkjet printer, comprising the following steps:

[0031] S1, initialization: the MCU and the FPGA initialize the hardware resources respectively, including registers, buffers and clocks;

[0032] S2, load configuration code: the MCU and the FPGA load the respective configuration codes;

[0033] S3, MCU sends data: for each data block of transmission, the MCU first calculates the address and activates the address automatic increase mode, and then starts the write transmission operation to write data to the address; then, the MCU enables the FPGA to read the data of the address region;

[0034] S4, FPGA sends data: the FPGA reads the data block at the specified address according to the instruction of the MCU, writes the data result back to the original address or a new address after completing the specified processing task; when new data is written, the old data will be overwritten.

[0035] The beneficial effects of the present application are:

[0036] The present application effectively solves the bandwidth bottleneck and data transmission rate mismatch problem in the traditional architecture by introducing high-speed DRAM as the data buffer area between the microcontroller unit (MCU) and the field programmable gate array (FPGA); using the control line multiplexing module and the timing control algorithm, the MCU and the FPGA can efficiently and synchronously access the DRAM in both directions, optimizing the continuity of the data flow and the smoothness of the printing process; the data exchange and synchronization module further ensures the batch and fast writing and reading of data blocks, and the dynamic data exchange and synchronization optimization algorithm dynamically adjusts the access priority according to the real-time data processing requirements, optimizing the access order; in addition, the use of the minimum cost maximum flow algorithm provides a cost-minimized flow allocation scheme for the data transmission path, reducing the overall transmission cost and improving the utilization efficiency of network resources; the network service support module enables the MCU to run the standard protocol stack, transmit data through the network and store it in the DRAM, and the FPGA accesses the DRAM according to the requirements to obtain the required ink data, enhancing the scalability and flexibility of the system; the FPGA uses edge computing technology to process the received data in real time, and monitors the processing results in real time through a closed-loop control mechanism, ensuring the accuracy of data processing and the continuity of printing tasks; the combination of these technologies not only improves the printing quality and production efficiency, but also reduces the cost and complexity of hardware changes, enabling the system to adapt to more complex application scenarios and meet the demand of modern digital inkjet printers for high-speed and large data volume printing tasks. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to better understand and implement, the technical solutions of the present application are described in detail below with reference to the accompanying drawings.

[0038] Fig. 1 A structure diagram of an efficient data exchange system for a digital inkjet printer provided by Embodiment 1 of the present application;

[0039] Fig. 2A high-efficiency data exchange system for a digital inkjet printer provided in Embodiment 1 of the present application monitors the steps of the access request of MCU and FPGA to DRAM through a timing control algorithm;

[0040] Fig. 3 A high-efficiency data exchange method for a digital inkjet printer provided in Embodiment 1 of the present application is shown in a step flow chart. DETAILED DESCRIPTION

[0041] To further illustrate the technical means and effects adopted by the present application to achieve the predetermined application purposes, exemplary embodiments will be described in detail herein, which are shown in the accompanying drawings. In the following description related to the drawings, the same numerals in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all the implementations consistent with the present application. Instead, they are merely examples of methods and systems consistent with some aspects of the present application as detailed in the appended claims.

[0042] The terms used in the present application are merely for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a," "said," and "the" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein means and includes any or all possible combinations of one or more associated listed items.

[0043] The specific embodiments, features and effects according to the present application are described in detail below in combination with the accompanying drawings and preferred embodiments.

[0044] Embodiment 1

[0045] Please refer to Figs. 1-3 The present embodiment provides a high-efficiency data exchange system and method for a digital inkjet printer, which introduces a high-speed dynamic random access memory (DRAM) chip as a data exchange medium between a microcontroller unit (MCU) and a field programmable gate array (FPGA), solving the problems of bandwidth bottleneck, mismatch of data transmission rate and low system response speed existing in the traditional data bus architecture.

[0046] The present application provides a high-efficiency data exchange system for a digital inkjet printer, comprising a microprocessor (MCU) and a programmable gate array (FPGA), wherein the MCU serves as a device controller to provide commands and buffer addresses and triggers automatic address increment; the FPGA is responsible for reading the buffer content and performing related processing; the FPGA comprises a dynamic random access memory (DRAM) for storing printing data. The DRAM is located between the MCU and the FPGA, and its reading and writing are controlled by the two respectively.

[0047] Specifically, high-speed DRAM is introduced as a data buffer zone between the MCU and the FPGA. Due to the difference in data processing speed between the MCU and the FPGA, direct data exchange will cause rate mismatch, thereby causing data congestion or delay. Through the high-bandwidth characteristics of the DRAM, the MCU can quickly write the data to be processed into the DRAM, and the FPGA can read and process the data from the DRAM, thereby solving the problem of rate mismatch. This step provides a basis for subsequent control line multiplexing and data exchange and synchronization.

[0048] Further, the MCU and the FPGA are connected to the DRAM through a parallel 16-bit bus.

[0049] Further, a control line multiplexing module is further included, and on the basis of the high-speed DRAM, the MCU and the FPGA perform bidirectional access to the DRAM through the control line multiplexing module. This multiplexing mechanism allows the MCU and the FPGA to take turns to access the DRAM under different control signals, thereby realizing efficient and synchronous exchange of data. The multiplexing of the control lines not only improves the utilization rate of the DRAM, but also ensures the synchronous exchange of data between the MCU and the FPGA, thereby providing precise timing control for the operation of the data exchange and synchronization module.

[0050] Further, when the MCU and the FPGA perform bidirectional access to the DRAM through the control line multiplexing module, a timing control algorithm is used to monitor the access requests of the MCU and the FPGA to the DRAM and dynamically switch the control signals between the MCU and the FPGA, so as to realize efficient and alternating access to the DRAM. The specific content includes:

[0051] S11, a request arbitration logic is constructed using the internal logic of the FPGA, and the MCU or the FPGA is dynamically given access permission according to a preset priority rule. Specifically, an arbitrator is used to determine which request has a higher priority, thereby determining the access order. The arbitrator is realized based on priority coding, and the device with a higher priority obtains access permission;

[0052] S12, a DMA (Direct Memory Access) controller is used to directly transmit data from the internal buffer of the MCU or the FPGA to the address of the DRAM, or to read data from the DRAM to a specified buffer. Specifically, when the arbitrator determines which device (MCU or FPGA) has access permission, the device will prepare the address and data of the DRAM to be accessed. If it is a write operation, the data will be prepared. If it is a read operation, the address of the read data will be prepared.

[0053] S13, using the programmable logic of FPGA to generate precise timing control signals, to ensure that the corresponding signals are turned on and off at the right time to perform read and write operations on DRAM; Specifically, after determining the access sequence and preparing the address and data, the control signals will be dynamically switched to allow the current device to read and write to the DRAM. Using the programmable logic of FPGA to generate precise timing control signals, to ensure that the corresponding signals are turned on and off at the right time to perform read and write operations on DRAM;

[0054] S14, after the control signals are correctly set, the data will be transmitted from the MCU to the DRAM (write operation), or from the DRAM to the FPGA (read operation). This step requires precise timing control to ensure data integrity.

[0055] Specifically, through the timing control algorithm, MCU and FPGA realize efficient bidirectional data access to DRAM, through precise timing management and dynamic control signal switching, it ensures that when transmitting a large amount of data at high speed, MCU and FPGA can not only coordinate to share DRAM resources, but also ensure the continuity and accuracy of data transmission, thereby significantly improving the overall performance and data processing capacity of the system. In addition, the algorithm also optimizes data flow and reduces system resource waste, reduces system energy consumption, improves energy efficiency, and meets the demand of modern digital inkjet printers for high-speed and large-data printing tasks.

[0056] Further, it also includes a data exchange and synchronization module, which further optimizes the data exchange process based on the control line multiplexing module. MCU writes data blocks in batches to DRAM and sends a write completion signal to FPGA through the control line. FPGA immediately reads data from DRAM for processing after receiving the signal and feeds back the signal to MCU after processing. This asynchronous transmission and synchronous exchange mode ensures the continuity of data flow and the smoothness of the printing process, greatly improving the parallel processing capacity of the system.

[0057] Further, according to the data exchange and synchronization module, the dynamic data exchange and synchronization optimization algorithm further optimizes the bidirectional data exchange process of MCU and FPGA to DRAM, including:

[0058] S21, using data flow analysis technology to monitor data access mode, through the construction of control flow graph (CFG) and data flow graph to realize, so as to obtain the relevant information about how data flows along the program execution path, the purpose of data flow analysis is to infer the relevant information of program dynamic execution through static code, so as to provide the algorithm with a global view of data access;

[0059] S22, based on the results of data stream analysis, dynamically adjust the access priority of DRAM by dynamic scheduler according to the real-time data processing requirements of MCU and FPGA; wherein the scheduler is to predict the data access mode using advanced data stream analysis technology, and optimize the access order accordingly;

[0060] S23, after optimizing the access order, the size and management strategy of the data block are dynamically adjusted by implementing version control and conflict detection mechanism according to the characteristics of the data (such as size, frequency, type) and the current load of the system; ensure data consistency while optimizing data access order.

[0061] Specifically, through the dynamic data exchange and synchronization optimization algorithm (Dynamic Data Exchange and Synchronization Optimization Algorithm), the bidirectional data exchange process of MCU and FPGA to DRAM is significantly optimized. This algorithm first uses data stream analysis technology (such as S21 technology) to monitor data access mode, and constructs control flow graph (CFG) and data flow graph to provide a global view of data access for the algorithm. Then, based on the analysis results, the dynamic scheduler dynamically adjusts the access priority of DRAM according to the real-time data processing requirements of MCU and FPGA, and optimizes the access order. Then according to the characteristics of the data and the current load, through the version control and conflict detection mechanism, the size and management strategy of the data block are dynamically adjusted, ensuring data consistency while optimizing data access order. The system not only improves the efficiency and accuracy of data transmission, but also enhances the scalability and flexibility, supports more complex network services and data processing functions, reduces the cost and complexity of hardware changes.

[0062] Further, the data transmission path is adjusted by the minimum cost maximum flow algorithm for further optimization of data flow; specifically, by constructing a directed weighted graph, the data transmission scheme with the lowest cost under the premise of meeting the maximum flow is found. This method can reduce the overall cost of data transmission and improve the utilization efficiency of network resources, which specifically includes:

[0063] Set G = (V, E) as a network, where V is the vertex set and E is the edge set, each edge (u, υ) ∈ E has two attributes: capacity c(u, υ) and cost of unit flow a(u, υ); the flow f(u, υ) represents the amount of data passing through the edge (u, υ);

[0064] The goal of the minimum cost maximum flow is to find a flow distribution scheme f that maximizes the total flow from the source point s to the sink point t while minimizing the total cost, and the minimum total cost B(f) is represented as:

[0065]

[0066] where f(u, v) is the flow on edge (u, v) and a(u, v) is the unit flow cost of edge (u, v).

[0067] Specifically, by applying the minimum cost maximum flow algorithm, the data transmission path can be effectively adjusted to maximize data flow while minimizing overall transmission cost. Specifically, by constructing a directed weighted graph, where each edge represents a potential data transmission channel with two attributes: capacity and unit flow cost. By iteratively finding the minimum cost augmentation path, the algorithm gradually optimizes the data flow until the maximum flow is reached. This method not only reduces the overall cost of data transmission, but also improves the utilization efficiency of network resources. The purpose of optimizing data flow through the minimum cost maximum flow algorithm is to adapt to more complex network services and data processing needs, ensuring efficient and low-cost data flow in high-speed printing tasks, thereby improving printing quality and production efficiency.

[0068] Further, the constraint condition of the minimum cost maximum flow is represented as:

[0069] Capacity constraint: for each edge (u, v) ∈ E, 0 ≤ f(u, v) ≤ c(u, v);

[0070] Flow conservation: for each vertex v ∈ V \ {s, t},

[0071] ∑ (u，υ)∈E f(u, v) = ∑ (υ，w)∈E f(v, w);

[0072] Flow range: for all edges (u, v) ∈ E, f(u, v) ≥ 0.

[0073] Specifically, u is the starting vertex of the edge and v is the ending vertex of the edge, each edge (u, v) represents a directed connection from one vertex to another, and this connection has associated capacity and cost attributes. In this network, data can flow from u to v, but not vice versa.

[0074] By solving this optimization problem, a path from the source point s to the sink point t is found, which maximizes the flow on this path while minimizing the total cost. Through an iterative algorithm to find the minimum cost augmentation path and gradually increase the flow until it can no longer be increased.

[0075] Further, a network service support module is also included, which utilizes the increased bandwidth to enable the MCU to run a standard protocol stack, transmit data over the network and store it into the DRAM, and the FPGA accesses the DRAM on a time-sharing basis as needed to obtain the required ink-out data. This module not only enhances the scalability and flexibility of the system, but also supports more complex network services and data processing functions, such as receiving print tasks over the network and directly storing them into the DRAM for processing by the FPGA. This design enables the system to adapt to more complex application scenarios while reducing the cost and complexity of hardware modifications.

[0076] Further, after transmitting data over the network and storing it into the DRAM, and the FPGA accesses the DRAM on a time-sharing basis as needed to obtain the required ink-out data, the system further includes: the FPGA utilizes edge computing technology to perform real-time processing on the data received over the network, stores the processing results into the DRAM, and reads the data on a time-sharing basis according to the specific requirements of the print task. Through a closed-loop control mechanism, the FPGA can monitor the processing results in real time after processing the data and send the processing status back to the MCU through a feedback path to make necessary adjustments, ensuring the accuracy of data processing and the continuity of the print task. The MCU makes decisions based on the feedback from the FPGA and dynamically adjusts the subsequent data transmission and processing strategy, forming an efficient closed-loop control system to optimize the entire print process and improve response speed and processing efficiency.

[0077] Specifically, the efficient data exchange system of the present application is aimed at the MCU and FPGA in a digital inkjet printer. By introducing a high-speed DRAM as a data cache area, it solves the rate matching problem between them. By using control line multiplexing technology, it realizes bidirectional data access. Through a timing control algorithm, it dynamically manages the access requests of the MCU and FPGA to the DRAM, optimizing the continuity of the data stream and the parallel processing capability of the system. In addition, the system uses data flow analysis technology to monitor and predict data access patterns, dynamically adjusts data block size and access priority, optimizes data transmission paths through the minimum cost maximum flow algorithm, reduces costs and improves network resource utilization. Finally, combined with edge computing technology, the FPGA can process data received over the network in real time and work collaboratively with the MCU through a closed-loop control mechanism to dynamically adjust data transmission and processing strategies to adapt to complex network service and data processing requirements, improve print quality and efficiency, and reduce the cost and complexity of hardware modifications.

[0078] An efficient data exchange method for a digital inkjet printer using the above-mentioned efficient data exchange system for a digital inkjet printer, comprising the following steps:

[0079] S1, initialization: the MCU and FPGA each initialize hardware resources, including registers, buffers and clocks;

[0080] S2, load configuration code: MCU and FPGA load respective configuration codes;

[0081] S3, MCU sends data: for each data block of transmission, the MCU first calculates the address and activates the address automatic increase mode, and then starts the write transmission operation to write data to the address; then, the MCU enables the FPGA to read the data of the address region;

[0082] S4, FPGA sends data: FPGA reads the data block at the specified address according to the instruction of MCU, writes the data result back to the original address or a new address after completing the specified processing task; when new data is written, the old data will be overwritten.

[0083] In the present application, by introducing high-speed DRAM as a data cache area and optimizing the data transmission architecture between MCU and FPGA, the bandwidth bottleneck problem of traditional data bus is effectively solved, so that the overall system response speed and printing efficiency of the digital inkjet printer are greatly improved; the control line multiplexing technology is adopted to ensure that the data exchange between MCU and FPGA can be efficiently synchronized, significantly reducing the delay of data transmission, improving the continuity of data flow and the fluency of the printing process, and the new architecture allows higher data transmission rate and more complex application scenarios without changing the hardware, while reducing the cost and complexity of hardware changes. This provides convenience for future system upgrade and function expansion; the optimized data flow management reduces the waste of system resources, reduces energy consumption, and realizes higher energy efficiency. It meets the development direction of green environmental protection technology and provides technical support for the sustainable development of modern digital inkjet printers; through the efficient data exchange mechanism and the improvement of real-time processing capability, the printer can better control the ink output and printing precision, thereby improving the quality of printing output and meeting the high-end printing demand.

[0084] The above is only the preferred embodiment of the present application, not any form of limitation on the present application, although the present application has been disclosed as above with the preferred embodiment, however, it is not intended to limit the present application, any person skilled in the art, without departing from the scope of the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to make equivalent embodiments with equivalent changes, but as long as it does not deviate from the technical solution of the present application, any simplification, modification, equivalent change and modification of the above embodiments according to the technical essence of the present application, all still belong to the scope of the technical solution of the present application.

Claims

1. A high efficiency data exchange system for a digital inkjet printer, characterized by: The device comprises an MCU and an FPGA, wherein the MCU provides commands and buffer addresses as a device controller and triggers automatic address increment; the FPGA is responsible for reading buffer content and performing relevant processing; the device further comprises a DRAM for storing printing data; The DRAM is located between the MCU and the FPGA; The device further comprises a control line multiplexing module for bidirectional access of the MCU and the FPGA to the DRAM, specifically comprising: S11, using internal logic of the FPGA to build request arbitration logic, and dynamically giving access permission to the MCU or the FPGA according to preset priority rules; S12, using a DMA controller to directly transmit data from an internal buffer of the MCU or the FPGA to an address of the DRAM, or read data from the DRAM to a specified buffer; specifically, when the arbitrator determines which device has access permission; S13, using programmable logic of the FPGA to generate precise timing control signals to ensure that corresponding signals are turned on and off at the correct time to perform read and write operations of the DRAM; specifically, after the access sequence is determined and the address and data are prepared, the control signals are dynamically switched to allow the current device to perform read and write operations on the DRAM; S14, after the control signals are correctly set, data will be transmitted from the MCU to the DRAM to perform a write operation, or from the DRAM to the FPGA to perform a read operation; The device further comprises a data exchange and synchronization module for optimizing the data exchange process based on the control line multiplexing module; the MCU writes data blocks to the DRAM in batches and sends a write completion signal to the FPGA through the control line; the FPGA reads data from the DRAM for processing after receiving the signal and feeds back a signal to the MCU after processing is completed; The data exchange system optimizes the bidirectional data exchange process of the MCU and the FPGA to the DRAM according to the data exchange and synchronization module and a dynamic data exchange and synchronization optimization algorithm, specifically comprising: S21, using data flow analysis technology to monitor data access patterns, and achieving relevant information about how data flows along the program execution path by constructing control flow graphs and data flow graphs; S22, based on the results of data flow analysis, dynamically adjusting the access priority of the DRAM according to real-time data processing requirements of the MCU and the FPGA through a dynamic scheduler; wherein the scheduler uses advanced data flow analysis technology to predict data access patterns and optimize access sequences accordingly; S23, after optimizing the access sequence, the size and management strategy of data blocks are dynamically adjusted according to the characteristics of the data and the current load of the system by implementing version control and conflict detection mechanisms.

2. A high efficiency data exchange system for a digital inkjet printer according to claim 1, characterized in that: The device further comprises a network service support module for transmitting data through a network and storing the data in the DRAM; the FPGA accesses the DRAM in time according to requirements to obtain required ink data.

3. A high efficiency data exchange system for a digital inkjet printer according to claim 2, characterized in that: Through network transmission data and storage to DRAM, FPGA according to the demand time-sharing access DRAM, obtain the required ink data after, still include: FPGA utilizes edge computing technology to the data received through network real-time processing, storage processing result to DRAM, and according to the specific demand of printing task time-sharing read data, through closed loop control mechanism, FPGA after processing data real-time monitoring processing result, and through feedback path will send processing state back to MCU, and carry out adjustment.

4. A high efficiency data exchange method for a digital inkjet printer, applied to a high efficiency data exchange system for a digital inkjet printer as claimed in any one of claims 1-3, characterized in that: Comprise the following steps: S1, initialization: MCU and FPGA initialize hardware resources respectively, including register, buffer and clock; S2, load configuration code: MCU and FPGA load respective configuration code respectively; S3, MCU sends data: for each data block transmission, MCU first calculates the address and activates the address automatic increase mode, and then starts the write transmission operation to write data to the address; then, MCU enables FPGA to read the data of the address corresponding region; S4, FPGA sends data: FPGA reads the data block at the specified address according to the instruction of MCU, writes the data result back to the original address or new address after completing the specified processing task; when new data is written, the old data will be overwritten.

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