A reconfigurable miniaturized, low-cost, highly integrated SiP chip module

Abstract

The present invention discloses a reconfigurable, miniaturized, low-cost, and highly integrated SiP chip module, comprising an FPGA unit, a PROM configuration storage unit, a reconfigurable FPGA functional unit, an RS-485 communication unit, an M-LVDS hardware interface receiving unit, an M-LVDS hardware interface transmitting unit, a level conversion unit, an SRAM unit, and a reset unit. The SiP chip module utilizes SiP packaging technology to achieve miniaturization, low cost, and high integration for multifunctional integration. The module reconfigures FPGA software functions by adding reconfigurable unit circuits, supports online, real-time upgrades of configuration memory, and offers advantages such as a reduced number of lead-out points and high reliability. Furthermore, the module optimizes the number of chips used for the common functions of the original productized functional modules.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic device packaging, and in particular relates to a reconfigurable miniaturized, low-cost, highly integrated SiP chip module. Background Art

[0002] Integrated electronic products for aerospace tracking and control systems typically consist of a comprehensive processing module paired with multiple data acquisition modules. These modules are uniformly planned and designed, utilizing a "five-unified" architecture: unified power supply, unified control, unified interface, unified backplane, and unified protocol. This achieves modular standardization for data acquisition, editing, and transmission products. Based on unified hardware and a flexible, programmable software architecture, these integrated electronic products for aerospace tracking and control systems achieve reliable interconnection between modules, enabling flexible configuration of different functional modules to meet diverse mission requirements.

[0003] With the mass production and use of productized functional modules characterized by "modularization, combination, and serialization", a prominent problem has gradually been exposed: the core hardware architecture of existing productized functional modules adopts a board form composed of discrete components with FPGA chips as the core. Each component is independently packaged, which occupies a large board area and has a high cost per chip, and cannot meet the needs of miniaturization, low cost and high integration.

[0004] Different modules have the same peripheral circuit hardware architecture with FPGA chip as the core. It is urgent to extract these same circuits and chips and design a miniaturized, low-cost chip module based on SiP packaging technology with reconfigurable characteristics, driven by the application requirements of miniaturization, low cost, FPGA software reconfiguration and high integration. Summary of the Invention

[0005] The technology of the present invention solves the problem: Overcoming the shortcomings of the existing technology, providing a reconfigurable miniaturized, low-cost, highly integrated SiP chip module, aiming to achieve miniaturized, integrated, low-cost packaging of the minimum system circuit with FPGA as the core.

[0006] In order to solve the above technical problems, the present invention discloses a reconfigurable miniaturized, low-cost, highly integrated SiP chip module, including: an FPGA unit, a PROM configuration storage unit, a reconfigurable FPGA function unit, an RS-485 communication unit, an M-LVDS hardware interface receiving unit, an M-LVDS hardware interface transmitting unit, a level conversion unit, an SRAM unit and a reset unit;

[0007] During the normal operation of the SiP chip module's logical functions: the SiP chip module uses the FPGA unit as the core module of the data flow, the PROM configuration storage unit is responsible for storing the program configuration file of the FPGA unit, and provides configuration data to the FPGA unit when powered on or reset to initialize the FPGA unit, so that the FPGA unit can perform the established functions; the M-LVDS hardware interface receiving unit and the M-LVDS hardware interface sending unit are responsible for the 4-receive and 4-transmit interface communication between the FPGA unit and the outside world, realizing the conversion between the M-LVDS differential signal and the CMOS signal; the level conversion unit is responsible for the 64-channel interface communication between the FPGA unit and the outside world, and is responsible for the conversion between the external signal and the FPGA unit signal; the SRAM unit is responsible for the effective storage of data during the application process of the SiP chip module; the reset unit is responsible for providing a reset signal to the FPGA unit when the SiP chip module works abnormally;

[0008] When the SiP chip module executes the FPGA software reconfigurable function:

[0009] One end of the RS-485 communication unit is connected to the host computer through a differential signal to achieve half-duplex communication with the host computer's UART, and the other end of the RS-485 communication unit communicates with the reconfigurable FPGA functional unit; the reconfigurable FPGA functional unit responds to the commands and data of the host computer, implements frame protocol parsing and verification, and uses the JTAG conventional interface to operate the read, write, erase, and verification functions of the PROM configuration storage unit to complete remote online reconfiguration; after the SiP chip module is powered on, the FPGA unit automatically triggers the reading of the configuration file in the PROM configuration storage unit to complete the loading and running of the program.

[0010] In the above-mentioned reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the FPGA unit is implemented using the BQ2V1000 bare core, which internally contains a programmable logic module CLB, a general-purpose input / output module IOB, and various IP resources. Among them, the programmable logic module CLB contains 10,240 logic cells LC, each of which consists of a 4-input lookup table and a user trigger to implement the logic functions required by the user. The general-purpose input / output module IOB supports a variety of single-ended and differential protocols under multi-voltage conditions, with a maximum data transmission speed of 622Mb / s, providing a bidirectional path between external pins and internal signals. The IP resources include a multiplier, a block memory BRAM, and a digital clock manager DCM. The multiplier is an 18-bit by 18-bit signed complement multiplier. The block memory BRAM supports a variable bit width of 1 to 36 bits, with a single block capacity of 18Kbit. The digital clock manager DCM provides clock phase shifting, de-skew, and frequency synthesis functions, with a maximum output frequency of 360MHz.

[0011] In the above-mentioned reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the PROM configuration storage unit is implemented using the BQ18V04 bare core to store the configuration file of the FPGA unit; at the same time, it supports serial configuration output mode and 8-bit parallel configuration mode.

[0012] In the above-mentioned reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the reconfigurable FPGA functional unit is implemented using the BM2166 bare core ASIC chip that supports remote upgrades, and supports remote online upgrades of FPGA configuration files through the UART bus.

[0013] In the above-mentioned reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the RS-485 communication unit is implemented using the B3362 bare core, with a maximum data transmission rate of 20Mbps, completing half-duplex serial port communication between the host computer and the reconfigurable FPGA functional unit.

[0014] In the reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the M-LVDS hardware interface sending unit is implemented using the B91M047 bare core. The B91M047 bare core is responsible for converting the CMOS signal output by the FPGA unit into an M-LVDS differential signal and sending it to other units.

[0015] In the above-mentioned reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the M-LVDS hardware interface receiving unit is implemented using the BMLVD048 bare core. The BMLVD048 bare core is responsible for converting the received M-LVDS differential signal into a CMOS signal and outputting it to the FPGA unit.

[0016] In the above-mentioned reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the level conversion unit is implemented using the BM2716 bare core, which serves as a bridge for communication between the FPGA unit and the outside world. It is used to realize the conversion between signals of different voltage logic levels and supports up to 64 channels of 5V / 3.3V / 1.8V level conversion.

[0017] In the above-mentioned reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the SRAM unit is implemented using the B8R512K32 bare core with a maximum capacity of 4MB; it uses an asynchronous read method, with a maximum data read time within 20ns to 25ns; at the same time, it has the ability to retain data under low voltage.

[0018] In the above-mentioned reconfigurable miniaturized, low-cost, highly integrated SiP chip module, the reset unit is implemented using a B706 bare core, which is used to monitor the power supply voltage and the working status of the FPGA unit; when the power supply voltage is monitored to be lower than the specified threshold, a reset signal is generated to ensure that the system will not have abnormalities during unstable power supply or startup; when the rising edge of the DONE signal of the FPGA unit is monitored, a high level is provided as the initial reset signal of the FPGA unit after the DONE signal is pulled high to achieve the reset of the FPGA unit.

[0019] The present invention has the following advantages:

[0020] (1) The present invention discloses a reconfigurable miniaturized, low-cost, highly integrated SiP chip module, which uses SiP packaging technology to achieve miniaturized, low-cost, highly integrated multifunctional integration, and optimizes the number of chips used for the common functions of the original productized functional modules. Through statistical calculations, the board-level area occupied by the productized functional modules after using the SiP chip module of the present invention is reduced by more than 60%, and the cost of the common functional chips is reduced by more than 50%.

[0021] (2) The present invention discloses a reconfigurable miniaturized, low-cost, highly integrated SiP chip module, which completes the reconstruction of FPGA software functions by adding reconfigurable unit circuits; builds a hardware path by encapsulating dedicated unit circuits and RS-485 communication units, supports online real-time upgrades of PROM configuration storage units, and has the advantages of fewer lead-out contacts and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the internal architecture design of a reconfigurable miniaturized, low-cost, highly integrated SiP chip module in an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of reconfigurable functional data flow in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments disclosed in the present invention will be described in further detail below with reference to the accompanying drawings.

[0025] One of the core ideas of the present invention is to combine the common functions of different functional modules in the product, carry out chip selection and optimization, and design a reconfigurable miniaturized, low-cost, highly integrated SiP chip module, which for the first time integrates functional units with FPGA as the core.

[0026] In this embodiment, if Figure 1As shown, this reconfigurable, miniaturized, low-cost, and highly integrated SiP chip module includes an FPGA unit, a PROM configuration storage unit, a reconfigurable FPGA functional unit, an RS-485 communication unit, an M-LVDS hardware interface receiving unit, an M-LVDS hardware interface transmitting unit, a level shifter, an SRAM unit, and a reset unit. The entire SiP chip module comprises nine functional units (FPGA unit, PROM configuration storage unit, reconfigurable FPGA functional unit, RS-485 communication unit, M-LVDS hardware interface receiving unit, M-LVDS hardware interface transmitting unit, level shifter, SRAM unit, and reset unit). These units implement programmable logic, configuration parameter reconfiguration, M-LVDS signal transmission and reception, and level shifter functions within a single chip package, completely replacing the functionality of 17 chips in the original discrete device design.

[0027] In this embodiment, the SiP chip module involves seven functional unit modules (FPGA functional unit, PROM configuration storage unit, M-LVDS hardware interface receiving unit, M-LVDS hardware interface sending unit, level conversion unit, SRAM unit, reset unit) during the normal operation of the logic function. Specifically, the SiP chip module uses the FPGA unit as the core module of the data flow. The PROM configuration storage unit is responsible for storing the program configuration file of the FPGA unit and providing configuration data to the FPGA unit when power is turned on or reset to initialize the FPGA unit so that the FPGA unit can perform the established function (by receiving the data input by the M-LVDS receiving unit to complete the logic processing, and sending the processed data through the M-LVDS sending unit). Output); the M-LVDS hardware interface receiving unit and the M-LVDS hardware interface sending unit are responsible for the 4-receive and 4-transmit interface communication between the FPGA unit and the outside world (directly connected to the FPGA unit, cooperating to complete data input and output and logic processing), and realize the conversion between M-LVDS differential signals and CMOS signals; the level conversion unit is responsible for the 64-channel interface communication between the FPGA unit and the outside world, and is responsible for the conversion between external signals (5V / 3.3V / 2.5V / 1.8V voltage logic level signals) and FPGA unit signals (3.3V voltage logic level signals); the SRAM unit is responsible for effectively storing data during the application process of the SiP chip module; the reset unit is responsible for providing a reset signal to the FPGA unit when the SiP chip module is malfunctioning.

[0028] In this embodiment, the SiP chip module involves three functional unit modules (PROM configuration storage unit, reconfigurable FPGA functional unit, and RS-485 communication unit) during the execution of the FPGA software reconfiguration function. Specifically, one end of the RS-485 communication unit is connected to the host computer via a differential signal to achieve half-duplex UART communication with the host computer, and the other end of the RS-485 communication unit communicates with the reconfigurable FPGA functional unit. The reconfigurable FPGA functional unit responds to commands and data from the host computer, implements frame protocol parsing and verification, and uses the conventional JTAG interface to operate the read, write, erase, and verification functions of the PROM configuration storage unit, completing remote online reconfiguration. After the SiP chip module is powered on, the FPGA unit automatically triggers the reading of the configuration file in the PROM configuration storage unit to complete the loading and running of the program. The RS-485 communication functional unit, the reconfigurable FPGA functional unit, and the PROM configuration storage unit effectively support the reconfiguration function of the SiP chip module.

[0029] In this embodiment, the FPGA unit is implemented using a BQ2V1000 bare chip with approximately 1 million logic gates. It internally includes a programmable logic block (CLB), a general-purpose input / output (IOB), and various IP resources. The CLB contains 10,240 logic cells (LCs), each consisting of a 4-input lookup table and a user trigger, implementing the desired logic functions. The IOB supports a variety of single-ended and differential protocols under multiple voltage conditions, with a maximum data transmission speed of 622 Mbps (LVDS level standard), providing bidirectional paths between external pins and internal circuits. IP resources include a multiplier, block RAM (BRAM), and a digital clock manager (DCM). The multiplier is an 18-bit by 18-bit signed two's complement multiplier. The BRAM supports variable bit widths from 1 to 36 bits, with a single block capacity of 18 kilobits. The DCM provides clock phase shifting, deskewing, and frequency synthesis functions, with a maximum output frequency of 360 MHz, making it suitable for a variety of applications such as logic control and data processing. The FPGA unit supports on-site configuration through the JTAG port, and the development EDA tool is Xilinx ISE software, which can flexibly implement the required functions.

[0030] In this embodiment, the PROM configuration storage unit is implemented using a BQ18V04 bare chip, which is used to store the configuration file of the FPGA unit. It has fast configuration and reconfiguration capabilities, which can significantly shorten the system startup and update time. At the same time, it supports serial configuration output mode and 8-bit parallel (SELECT-MAP) configuration mode. The specific working mode is determined by the internal user control register.

[0031] In this embodiment, the reconfigurable FPGA functional unit is implemented using the ASIC chip BM2166 bare core that supports remote upgrades, and supports remote online upgrades of FPGA configuration files through the UART bus.

[0032] In this embodiment, the RS-485 communication unit is implemented using a B3362 bare core with a maximum data transmission rate of 20 Mbps, completing half-duplex serial communication between the host computer and the reconfigurable FPGA functional unit.

[0033] In this embodiment, the M-LVDS hardware interface sending unit and the M-LVDS hardware interface receiving unit are implemented using the B91M047 bare core (transmitting) and the BMLVD048 (receiving) bare core respectively, supporting 4-receive and 4-transmit interface communication; the B91M047 bare core is responsible for converting the CMOS signal output by the FPGA unit into an M-LVDS differential signal and sending it to other units; the BMLVD048 bare core is responsible for converting the received M-LVDS differential signal into a CMOS signal and outputting it to the FPGA unit.

[0034] In this embodiment, the level conversion unit is implemented using the BM2716 bare core, which serves as a bridge for communication between the FPGA unit and the outside world. It is used to realize the conversion between signals of different voltage logic levels. It supports up to 64 channels of 5V / 3.3V / 1.8V level conversion and is suitable for communication between multiple voltage domains. It effectively solves the matching problem of the level standards of the FPGA unit and the peripheral control circuit.

[0035] In this embodiment, the SRAM unit is implemented using a B8R512K32 bare chip, which is the core component for data processing and storage during chip application, with a maximum capacity of 4MB. It adopts an asynchronous reading method, with a maximum data reading time within 20ns to 25ns. It has the characteristics of large storage capacity and fast data access, and can effectively support application scenarios such as high-speed computing system cache and high-bandwidth network data exchange. At the same time, it has data retention capabilities under low voltage, further improving and ensuring the adaptability and reliability of the chip in complex application scenarios.

[0036] In this embodiment, the reset unit is implemented using a B706 bare chip, which is used to monitor the power supply voltage and the working status of the FPGA unit; when the power supply voltage is monitored to be lower than the specified threshold, a reset signal is generated to ensure that the system does not have abnormalities during unstable power supply or startup; when the rising edge of the DONE signal of the FPGA unit is monitored, a high level is provided as the initial reset signal of the FPGA unit after the DONE signal is pulled high, thereby resetting the FPGA unit.

[0037] In this embodiment, the reconfigurable miniaturized, low-cost, highly integrated SiP chip module is realized through the following reliability design and process: the present invention uses wire bonding to place and connect 9 bare cores (i.e., the bare cores corresponding to the above-mentioned 9 functional units) on a substrate (the substrate serves as a bridge between the bare core and the external PCB circuit board, and is not easily affected by temperature differences and humidity. At the same time, its thermal expansion coefficient is more matched with the bare core, which can effectively reduce the mechanical damage caused by thermal stress). The wire bonding adopts a gold wire bonding process (the gold wire bonding process is a key electrical interconnection technology and is widely used in the field of microelectronics packaging. This process uses fine metal wires (mainly gold wires) to connect the solder joints on the chip to the corresponding solder joints on the packaging substrate or another chip through various methods such as heat, pressure, and ultrasonic energy to form a firm connection and realize the transmission of electrical signals. The gold wire bonding process has the advantages of high precision, reliable connection, and long-term stability. At the same time, the gold wire bonding process has the characteristics of strong adaptability and can adapt to the connection requirements of various different materials). The substrate is connected to the PCB circuit board through solder balls. The external input / output signals of the 9 bare core SiP chip modules are transmitted to the PCB circuit board through the substrate solder ball points, and the PCB circuit board leads the signal lines to the input / output pins of the SiP chip.

[0038] Furthermore, reliability design is carried out in advance, and reliability analysis of the design scheme is performed through simulations such as substrate warpage simulation and thermal simulation to ensure the reliability of the SiP chip module. The details are as follows:

[0039] (1) Conduct reliability design for thermal stress. With a high-logic-density FPGA unit as the core unit, other functional units are built around it (the layout follows the principle of placing devices with high heat generation close to the chip edge). Highly thermally conductive molding compound is used for integrated packaging to reduce junction-to-case thermal resistance. The overall high level of integration effectively reduces product power consumption.

[0040] (2) Conduct reliability design for mechanical stress. A silicon substrate is used as a bridge between the bare die and the external PCB circuit board. It is not easily affected by temperature differences and humidity. At the same time, its thermal expansion coefficient is more closely matched to that of the bare die, which can effectively reduce mechanical damage caused by thermal stress. Through mechanical analysis and simulation of the package pins, the SiP chip module selects the BGA676 package size. Overall, the volume is greatly reduced, reducing failures caused by mechanical stress.

[0041] (3) Conduct reliability design for electrical performance. The bare die is connected to the PCB circuit board using bare die stacking, bonding connection and flip-chip soldering processes, ensuring high process stability and assembly accuracy while effectively shortening the signal line length, reducing interference and improving circuit reliability. The substrate optimizes signal routing, reduces signal crosstalk and reflection through a precise multi-layer structure, and ensures good signal integrity. In addition, the substrate adopts an isolated power ground design. The power supply and ground between units are completely independent and all are powered through external pins, effectively reducing the power bounce or ground bounce caused by power fluctuations, and reducing the impact of the power supply and ground plane noise inside the SiP chip module on other external chips. The gold wire diameter is 20 / 25μm, and the lead end uses 63Sn37Pb solder balls to ensure the reliability of electrical connections.

[0042] In this embodiment, the FPGA software reconfiguration design of this reconfigurable, miniaturized, low-cost, highly integrated SiP chip module is as follows: The productized functional module uses a standard 3U VPX architecture as the main body, and is assembled into a complete product through a standard 3U backplane and chassis plug-in method. Traditional FPGA download methods reserve a JTAG physical socket at the board level and burn the configuration file through the JTAG port. Whether the module is sealed or assembled into a complete machine, any program modification and re-download requires opening the module cover, resulting in a waste of time and labor costs, and also the risk of introducing unnecessary items. If the JTAG burning node is extended to a point in the module's external connector, while the product does not need to be opened for program download, this method of extending the node introduces the potential risk of program loading interference during power-on. Furthermore, the external connector nodes of each module are limited and precious, so this method also poses significant reliability risks. To address the above issues, the present invention uses an ASIC chip that supports remote upgrades to achieve convenient one-click software upgrades. Combined with an RS-485 communication unit, it can effectively reduce the number of download contact points. Reconfigurable circuit architecture and data flow relationship Figure 2 shown.

[0043] (1) The data flow of the reconfigurable function is as follows:

[0044] a) The RS-485 communication unit connects to the host computer via a differential signal, enabling half-duplex communication with the host computer's UART. The other end of the RS-485 communication unit communicates with the reconfigurable FPGA functional unit. Using the RS-485 communication unit allows the SiP chip module to support FPGA software reconfiguration by only requiring two points. The main port signals of the RS-485 communication unit are shown in Table 1 below:

[0045] signal name Input / Output Remark A Input or output Data signal differential P end B Input or output Data signal differential N-terminal RE# / DE enter Enable terminal, high and low represent the direction of data transmission RO Output Data output to reconfigurable unit DI enter Data is output from the reconfigurable unit to this port

[0046] Table 1, RS-485 communication unit main port signal table

[0047] b) The reconfigurable FPGA functional unit responds to commands and data from the host computer, implements frame protocol parsing and verification, and uses the JTAG conventional interface to operate the read, write, erase, and verification functions of the PROM configuration storage unit, completing remote online reconfiguration. The main port signals of the reconfigurable FPGA functional unit are shown in Table 2 below:

[0048] signal name Input / Output Remark UART_EN Output Control RS482 unit data transmission direction UART_IN enter Data Input UART_OUT Output Data Output TDI Output Data Output TDO enter Data Input TCK Output Boundary Scan Clock TMS Output Boundary scan mode selection port

[0049] Table 2. Main port signals of reconfigurable FPGA functional units

[0050] c) After the SiP chip module is powered on, the FPGA unit automatically triggers the reading of the configuration file in the PROM configuration storage unit to complete the loading and running of the program. The main port signals of the PROM configuration storage unit are shown in Table 3 below:

[0051] signal name Input / Output Remark TDI enter Data Input TDO Output Data Output TCK enter Boundary Scan Clock TMS enter Boundary scan mode selection port [D7:D0] Input or output In parallel loading mode, the parallel data port CLK enter Clock input CF# Output Data output / output enable CE# enter Control Input OE / RESET# Input or output Input / Output / Output Enable

[0052] Table 3, PROM configuration storage unit main port signal table

[0053] (2) The communication protocol between the reconfigurable FPGA functional unit and the host computer is as follows:

[0054] a) Transmission Format: Instructions and data are typically sent sequentially in bytes. The UART interface of the reconfigurable FPGA functional unit uses an 11-bit transmission mode, consisting of a 1-bit start bit, 8-bit data bits, a 1-bit parity bit, and a 1-bit stop bit. Each byte is transmitted from left to right according to the following format. When transmitting multiple bytes, the most significant byte is transmitted first, followed by the second most significant byte, and finally the least significant byte. Within a byte, the least significant byte is transmitted first, followed by the most significant byte.

[0055] b) Baud Rate: The default baud rate of the UART interface of the reconfigurable FPGA functional unit is 115200 bps. The UART interface baud rate can be switched by sending serial port commands. There are four switchable baud rates: 57600 bps, 115200 bps, 628000 bps, and 1280000 bps. The baud rate resets to 115200 bps after powering on or resetting the reconfigurable FPGA functional unit.

[0056] c) Frame format: The data link layer uses a frame structure with a certain format for transmission. According to the transmission mode of the data link layer, the frame includes two types: command frame and response frame. The two frame formats are shown in Table 4 below:

[0057] Frame header UART ID Length field Command domain Address field Data Domain Verification Field [15:0] [15:0] [15:0] [4:0] [26:0] 2B~1024B [15:0]

[0058] Table 4, command frame format table

[0059] The meaning of each part in the command frame is as follows:

[0060] a) Frame header: occupies 16 bits and is used to identify the start of the command frame. It is fixed at EB90.

[0061] b) UART ID: Occupies 16 bits and is the ID of the reconfigurable FPGA functional unit. It is used to identify multiple modules on the same UART bus. The lower 4 bits are valid and the upper 12 bits default to 0. It can be set to any value between 4'b000-4'b1111 and supports up to 16 IDs. The default value of the UART ID is all zeros and is used for the first reconstruction.

[0062] c) Length field: occupies 16 bits and is used to identify the length of the command frame, indicating the number of bytes in the frame starting from the command field.

[0063] d) Command field: occupies 5 bits and represents the command executed in this operation, as shown in Table 5 below:

[0064] Serial number Command domain meaning 1 0b01100 Baud rate selection command 2 0b01101 JTAG channel selection command 3 0b01110 JTAG direct connection commands 4 0b01111 JTAG link device identification command 5 0b10000 JTAG device select command 6 0b10001 JTAG Write Command 7 0b10010 JTAG Read Command 8 0b10011 JTAG Erase Command 9 0b10100 JTAG_CRC check command 10 0b10101 UART direct connection command 11 0b10110 Device reset command 12 0b10111 Read Status Register Command

[0065] Table 5, Command domain definition table

[0066] e) Address field: occupies 27 bits and represents address signals such as programming address, read address, start address and end address of storage code stream.

[0067] f) Data field: It is the valid data of the UART link layer. The maximum length does not exceed 1024 bytes, and it is agreed to use a length of 2N (Byte), that is, an even number of bytes.

[0068] g) Check Field: Occupies 2 bytes and uses XOR and Sum verification. The verification range is from the frame header to the data field. The XOR and Sum are performed on every two bytes to obtain the final verification result.

[0069] Furthermore, the response frames are divided into two types, as follows:

[0070] a) Response frame representing the check result and timeout signal: 2 bytes in total, as shown in Table 6 below:

[0071] answer illustrate 2D2D Command frame XOR and checksum error CECE Command frame reception timeout (maximum waiting time is 3.2ms) D2D2 Command frame XOR and checksum are correct

[0072] Table 6, Verification result and timeout response frame format

[0073] b) Valid data response frame: The valid data response frame is returned only when the reconfigurable FPGA function unit JTAG read command, JTAG_CRC check command and read register three instructions are executed. The format is shown in Table 7 below:

[0074] Frame header UART ID Command domain Length field Data Domain Verification Field [15:0] [15:0] [15:0] [15:0] 2B~1024B [15:0]

[0075] Table 7, Valid data response frame format

[0076] The meaning of each part is as follows:

[0077] a) Frame header: occupies 2 bytes and is a flag for identifying the start of the command frame. It is fixed at EB90.

[0078] b) UART ID: occupies 16 bits and is the ID of the reconfigurable FPGA functional unit. The lower 4 bits are valid and can be set to any value between 4'b000-4'b1111. A maximum of 16 IDs are supported.

[0079] c) Command field: occupies 2 bytes and represents the command executed in this operation. The lower 5 bits are shown in Table 1, and the upper 11 bits are zero.

[0080] d) Length field: occupies 2 bytes and is used to identify the length of the data field and the check field, indicating the number of bytes.

[0081] e) Data field: occupies N*(2Byte), indicating the read data (N is an even number).

[0082] f) Check field: occupies 2 bytes, uses XOR and check method, and the check range is from the frame header to the data field.

[0083] Furthermore, the response frames corresponding to different command frames are shown in Table 8 below:

[0084]

[0085] Table 8, Response frame meaning table

[0086] In this embodiment, through SiP packaging technology, 9 bare chips (FPGA unit, PROM configuration storage unit, reconfigurable FPGA functional unit, M-LVDS transmitting unit, M-LVDS receiving unit, RS-485 communication unit, level conversion unit, SRAM unit, reset unit) are integrated into a 676-pin chip (SiP chip module), which completely replaces the 17 discrete device chips of the general functional part in the original productized functional module, greatly reducing the number of chips used and realizing the miniaturization and low-cost design of the productized functional module.

[0087] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

[0088] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

Claims

1. A reconfigurable miniaturized, low-cost, highly integrated SiP chip module, characterized in that: include: FPGA unit, PROM configuration storage unit, reconfigurable FPGA function unit, RS-485 communication unit, M-LVDS hardware interface receiving unit, M-LVDS hardware interface transmitting unit, level conversion unit, SRAM unit and reset unit; During the normal operation of the SiP chip module's logical functions: the SiP chip module uses the FPGA unit as the core module of the data flow, the PROM configuration storage unit is responsible for storing the program configuration file of the FPGA unit, and provides configuration data to the FPGA unit when powered on or reset to initialize the FPGA unit, so that the FPGA unit can perform the established functions; the M-LVDS hardware interface receiving unit and the M-LVDS hardware interface sending unit are responsible for the 4-receive and 4-transmit interface communication between the FPGA unit and the outside world, realizing the conversion between the M-LVDS differential signal and the CMOS signal; the level conversion unit is responsible for the 64-channel interface communication between the FPGA unit and the outside world, and is responsible for the conversion between the external signal and the FPGA unit signal; the SRAM unit is responsible for the effective storage of data during the application process of the SiP chip module; the reset unit is responsible for providing a reset signal to the FPGA unit when the SiP chip module works abnormally; When the SiP chip module executes the FPGA software reconfigurable function: one end of the RS-485 communication unit is connected to the host computer through a differential signal to realize half-duplex communication with the host computer UART, and the other end of the RS-485 communication unit communicates with the reconfigurable FPGA functional unit; the reconfigurable FPGA functional unit responds to the commands and data of the host computer, realizes the parsing and verification of the frame protocol, and uses the JTAG conventional interface to operate the read, write, erase and verification functions of the PROM configuration storage unit to complete remote online reconfiguration; after the SiP chip module is powered on, the FPGA unit automatically triggers the reading of the program configuration file in the PROM configuration storage unit to complete the loading and running of the program.

2. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The FPGA unit is implemented using the BQ2V1000 bare core, which contains a programmable logic module CLB, a general-purpose input / output module IOB, and various IP resources. The programmable logic module CLB contains 10,240 logic cells LC, each of which consists of a 4-input lookup table and a user trigger to implement the logic functions required by the user. The general-purpose input / output module IOB supports a variety of single-ended and differential protocols under multi-voltage conditions, with a maximum data transmission speed of 622Mb / s, providing a bidirectional path between external pins and internal signals. The IP resources include a multiplier, a block memory BRAM, and a digital clock manager DCM. The multiplier is an 18-bit by 18-bit signed complement multiplier. The block memory BRAM supports a variable bit width of 1 to 36 bits, with a single block capacity of 18Kbit. The digital clock manager DCM provides clock phase shifting, de-skew, and frequency synthesis functions, with a maximum output frequency of 360MHz.

3. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The PROM configuration storage unit is implemented using the BQ18V04 bare core and is used to store the program configuration file of the FPGA unit; at the same time, it supports serial configuration output mode and 8-bit parallel configuration mode.

4. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The reconfigurable FPGA functional unit is implemented using the BM2166 bare core ASIC chip that supports remote upgrades, and supports remote online upgrades of the reconfigurable FPGA functional unit configuration file through the UART bus.

5. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The RS-485 communication unit is implemented using the B3362 bare core, with a maximum data transmission rate of 20Mbps, completing half-duplex serial communication between the host computer and the reconfigurable FPGA functional unit.

6. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The M-LVDS hardware interface sending unit is implemented using the B91M047 bare core. The B91M047 bare core is responsible for converting the CMOS signal output by the FPGA unit into an M-LVDS differential signal and sending it to other units.

7. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The M-LVDS hardware interface receiving unit is implemented using the BMLVD048 bare core, which is responsible for converting the received M-LVDS differential signal into a CMOS signal and outputting it to the FPGA unit.

8. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The level conversion unit is implemented using the BM2716 bare core and serves as a bridge for communication between the FPGA unit and the outside world. It is used to realize the conversion between signals of different voltage logic levels and supports up to 64 channels of 5V / 3.3V / 1.8V level conversion.

9. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The SRAM unit is implemented using the B8R512K32 bare core with a maximum capacity of 4MB. It uses an asynchronous read method with a maximum data read time of 20ns to 25ns. At the same time, it has data retention capabilities under low voltage.

10. The reconfigurable miniaturized, low-cost, highly integrated SiP chip module according to claim 1, characterized in that: The reset unit is implemented using a B706 bare chip and is used to monitor the power supply voltage and the working status of the FPGA unit. When the power supply voltage is monitored to be lower than the specified threshold, a reset signal is generated to ensure that the system does not have abnormalities during unstable power supply or startup. When the rising edge of the DONE signal of the FPGA unit is monitored, a high level is provided as the initial reset signal of the FPGA unit after the DONE signal is pulled high to reset the FPGA unit.

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