Storage index method, storage index device, electronic equipment and storage medium

Abstract

The invention discloses a storage indexing method, a storage indexing device, electronic equipment and a storage medium. The index storage method comprises the steps that an access request for a storage device is received, the access request comprises an access address, and the storage device comprises a plurality of storage spaces; determining a target storage space corresponding to the access address in the plurality of storage spaces according to a spatial index field belonging to the tag part in the access address; and performing storage access in the target storage space according to the access address. According to the storage indexing method, the flexible adaptability of storage access can be improved, implementation is easy, and the hardware complexity and the area and power consumption of a chip cannot be increased.

Description

Technical Field

[0001] The present disclosure relates to a storage index method, a storage index device, an electronic device and a storage medium. Background Art

[0002] With the advent of the era of big data and artificial intelligence, the demand for high-performance and high-computing chips is increasing, and storage performance has become a crucial link. As the number of processor cores increases, the large capacity and low latency of storage play a significant role in improving performance in multi-core shared hardware design. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a storage indexing method, comprising: receiving an access request to a storage device, the access request including an access address, the storage device including multiple storage spaces; determining a target storage space corresponding to the access address in multiple storage spaces based on a spatial index field belonging to a tag part in the access address; and performing storage access in the target storage space based on the access address.

[0004] For example, in the storage index method provided by at least one embodiment of the present disclosure, the total storage capacity of the storage device is not equal to an integer power of 2, and / or the storage capacity of each storage space of the multiple storage spaces is an integer power of 2.

[0005] For example, in the storage index method provided by at least one embodiment of the present disclosure, a target storage space corresponding to an access address in multiple storage spaces is determined according to a spatial index field belonging to a tag part in the access address, including: determining a storage space access index according to address bits in a spatial index field belonging to a tag part in the access address; determining a target storage space according to the storage space access index.

[0006] For example, in the storage index method provided by at least one embodiment of the present disclosure, the storage space access index is determined according to the address bits in the space index field belonging to the tag part of the access address, including: performing operations on the numerical values ​​of the address bits in the space index field, and determining the storage space access index according to the operation results.

[0007] For example, in the storage index method provided by at least one embodiment of the present disclosure, it also includes: multiple storage spaces correspond to multiple theoretical result values ​​determined according to the calculation results; a first ratio of the number of corresponding theoretical result values ​​of each storage space to the total number of multiple theoretical result values ​​matches a second ratio of the storage capacity of each storage space to the total storage capacity of multiple storage spaces.

[0008] For example, in the storage index method provided by at least one embodiment of the present disclosure, the operation includes a modulus operation or a hash operation.

[0009] For example, in the storage index method provided by at least one embodiment of the present disclosure, the modulo operation includes: using the modulus determined after proportional operation based on multiple storage spaces to obtain the operation result after modulo calculation of the numerical value of the address bit in the space index field.

[0010] For example, in the storage index method provided by at least one embodiment of the present disclosure, multiple storage spaces are divided into multiple storage space groups, each storage space group in the multiple storage space groups includes at least one storage space, and the storage index method also includes: determining the target storage space group corresponding to the access address in the storage device according to the group index field in the space index field.

[0011] For example, in the storage index method provided by at least one embodiment of the present disclosure, it also includes: determining the target storage space corresponding to the access address in the target storage space group according to the space index field.

[0012] For example, in the storage index method provided by at least one embodiment of the present disclosure, each storage space in the plurality of storage spaces is mapped in a direct associative or group associative manner.

[0013] For example, in the storage indexing method provided by at least one embodiment of the present disclosure, the access address includes a tag part and an index part; storage access is performed in the target storage space according to the access address, including: according to the index part, addressing the target storage location in the target storage space, and according to the tag part, comparing with the tag stored in the target storage location to confirm that the target access data corresponding to the access request is stored in the target storage location.

[0014] At least one embodiment of the present disclosure also provides a storage index device for a storage device, comprising: a receiving unit, configured to receive an access request to the storage device, the access request including an access address, and the storage device including multiple storage spaces; an access unit, configured to determine a target storage space corresponding to the access address in the storage device based on a spatial index field belonging to a tag part in the access address, and perform storage access in the target storage space based on the access address.

[0015] At least one embodiment of the present disclosure also provides a storage index device, wherein the access unit includes: a modulo unit, configured to perform a modulo operation on the numerical value of the address bits in the space index field, and determine the storage space access index according to the result of the modulo operation; and a space selection unit, configured to determine the target storage space corresponding to the access address in the storage device according to the index identification bits in the storage space access index and the access address.

[0016] At least one embodiment of the present disclosure also provides a storage index device, wherein the space selection unit includes: a first AND gate and a second AND gate, the first AND gate and the second AND gate are arranged in corresponding branches of different storage spaces, and the output logic relationship of the first AND gate and the second AND gate is opposite.

[0017] At least one embodiment of the present disclosure also provides an electronic device, comprising at least one memory and at least one processor, wherein the at least one memory is configured to store computer-executable instructions; and the at least one processor is configured to execute the computer-executable instructions. When the computer-executable instructions are executed by the at least one processor, the storage index method described in any of the above embodiments is implemented.

[0018] At least one embodiment of the present disclosure further provides a non-temporary storage medium that non-temporarily stores computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the storage index method described in any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0020] Figure 1 A schematic diagram of a usage scenario of a storage index method provided by at least one embodiment of the present disclosure is shown;

[0021] Figure 2 A schematic diagram of a storage index method provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 3 A schematic diagram showing the mapping relationship principle of direct associativity, full associativity and set associativity in the cache is shown;

[0023] Figure 4 A schematic diagram showing a set-associative organization form and addressing mode of a cache provided by at least one embodiment of the present disclosure;

[0024] Figure 5 A block diagram of a memory provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 6 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 7 An exemplary schematic diagram showing the operation logic of a storage index device provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 8 A schematic diagram of a storage indexing process of a last level cache (LLC) provided by at least one embodiment of the present disclosure is provided;

[0028] Fig. 9 A schematic diagram showing an electronic device provided by at least one embodiment of the present disclosure; and

[0029] Fig.10 A schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0032] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0033] The terms used in this disclosure are those general terms currently widely used in the art in consideration of the functions of the technical features in the embodiments of the present disclosure, but these terms may vary according to the intentions of those skilled in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0034] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0035] As the demand for high-performance and high-computing chips increases, storage performance has become a crucial link. For example, cache is performed before accessing the main memory, so that the cache with higher storage speed can be used to solve the problem of high latency when accessing the main memory. Especially as the number of processing cores increases, setting a larger capacity cache in such a multi-core design can significantly improve the access performance of the main memory.

[0036] Therefore, it is very important to make the cache as large as possible within a limited chip size, but maximizing the cache capacity within the chip often results in the cache capacity not being equal to an integer power of 2.

[0037] In view of the above situation, a method for indexing cache whose capacity is not equal to an integer power of 2 is proposed. The method can be implemented by adopting a hash algorithm or increasing the number of ways in the cache.

[0038] The complexity of the hash algorithm is relatively high, and there are hash conflicts in some cases. Therefore, in such a design, not only is it necessary to set up a set of hash mapping relationships for the hash algorithm itself, but it is also necessary to set up an additional set of hardware based on possible hash conflicts. This not only increases the access delay, but also brings further hardware overhead due to the irreversibility of the hash algorithm, which requires indexing by storing full address information.

[0039] Increasing the number of ways in the cache will slow down cache indexing due to the increase in the number of ways, increase access latency, and increase chip area and power consumption.

[0040] To this end, in the design of achieving the largest possible storage capacity (for example, cache capacity) within a limited chip size, the irregularity of the storage capacity (that is, the storage capacity is not equal to an integer power of 2) will lead to complex hardware design, increased access latency, and increased chip area and power consumption.

[0041] In response to the above problems, the present disclosure proposes a storage indexing method, which includes: receiving an access request to a storage device, the access request including an access address, and the storage device including multiple storage spaces; determining a target storage space corresponding to the access address in multiple storage spaces based on a spatial index field belonging to a tag part in the access address; and performing storage access in the target storage space based on the access address.

[0042] In the storage index method of the above-mentioned embodiment of the present disclosure, the target storage space corresponding to the access address in multiple storage spaces is determined according to the spatial index field belonging to the tag part in the access address, so that regardless of regular or irregular storage capacity access, the storage index method can be flexibly adapted to perform index access, and the method is easy to implement without increasing the hardware complexity and the chip area and power consumption.

[0043] Figure 1 A schematic diagram of a usage scenario of a storage index method provided by at least one embodiment of the present disclosure is shown.

[0044] like Figure 1 As shown, the memory provided in the embodiment of the present disclosure is used as a cache in a computer system. Figure 1 As shown, the request end 60 is connected to the storage device 70 for communication, and the cache 70 is connected to the main memory 202 for communication, including the storage index device or memory of at least one embodiment of the present disclosure. The request end 60 may be a storage device of the upper level of the storage device 70, for example, it may be any device that can directly access the storage device 70 using an access address and issue an access request, such as a processor (or processor core), various controllers (such as a direct memory access (DMA) controller, etc.), or an input / output interface (IO), and the present disclosure does not limit this.

[0045] The storage device 70 can be a memory of the previous level of the main memory 202, or a cache. For example, the storage device 70 can be a first-level cache, a second-level cache, or a higher-level cache (such as a last-level cache (LLC)) in a computer system, which is used to improve the response speed of access requests and the overall efficiency of the computer system. The storage device 70 includes a storage array composed of a random access memory (RAM). For example, the random access memory array includes a tag array and a data array, which are respectively used to store information such as tags and data information in the access address of the stored object (such as data or instructions). The random access memory is usually a static random access memory (SRAM). For convenience, the above-mentioned tag array and data array can also be referred to as Tag RAM array and SRAM array, respectively.

[0046] In some embodiments, the storage device 70 includes multiple storage spaces, for example, storage spaces 0 to n (n is greater than or equal to 1). For example, each storage space can be used as an independently accessible cache, for example, each storage space includes a Tag RAM array and an SRAM array.

[0047] In some embodiments, the storage capacity of the storage device 70 may not be equal to an integer power of 2, and the storage capacity of the storage device 70 may be increased by adding an SRAM array during design.

[0048] The main memory 202 is also referred to as a memory, and may be, for example, a random access memory, such as a dynamic random access memory (DRAM).

[0049] During operation, the access request sent by the request end 60 may be responded to and processed in the storage device 70, or further access requests may be sent by the storage device 70 to the main memory 202, which may respond and process the requests. For example, the request end 60 sends an access request, and if the data requested by the access request is found in the storage device 70, the storage device 70 processes and responds to the access request; if the data requested by the access request is not found in the storage device 70, the storage device 70 further sends an access request to the main memory 202, and the main memory 202 processes and responds to the access request.

[0050] Figure 2 A flowchart of a storage index method provided by at least one embodiment of the present disclosure is shown.

[0051] like Figure 2 As shown, in some embodiments of the present disclosure, the storage index method includes steps S30 to S32.

[0052] For step S30, an access request to a storage device is received, wherein the access request includes an access address. Here, the storage device includes a plurality of storage spaces. For example, a storage index device receives an access request to a storage device.

[0053] In some embodiments of the present disclosure, the request end 60 issues an access request to the storage device, and the access request includes an access address (e.g., a physical address), and the access address corresponds to a storage address in the storage device. The storage device includes multiple storage spaces, and the multiple storage spaces can be obtained by dividing the storage device according to the storage capacity. Each storage space can be used as a cache that can be accessed independently. For example, the sum of the storage capacity of the multiple storage spaces is equal to the storage capacity of the storage device.

[0054] For step S31, a target storage space corresponding to the access address among multiple storage spaces is determined according to a space index field belonging to a tag part in the access address.

[0055] In a computer system, the access address of a memory may include three parts from low to high: an offset, an index, and a tag. In an embodiment of the present disclosure, the tag part of the access address further includes a spatial index field, and the spatial index field may include one or more address bits. The spatial index field is used to index the storage space so as to access the corresponding storage space through the spatial index field corresponding to each storage space. Each storage space has one or more values ​​corresponding to the spatial index field. For example, multiple storage spaces include storage space 0 and storage space 1, and the spatial index field includes 2 bits. The corresponding spatial index values ​​include 01, 00, 11, and 10. 01, 00, and 11 can be used as the spatial index values ​​corresponding to storage space 0, and 10 can be used as the spatial index value of storage space 1. It should be noted that the spatial index value corresponding to each storage space is different, and each spatial index value can only index the corresponding storage space. For example, if the spatial index value of the access address is 01, the target storage space to be indexed is storage space 0.

[0056] The spatial index field can be directly extracted from the tag part of the access address. For example, the spatial index field belonging to the tag part in the access address can be a part of the address field in the access address. In an embodiment of the present disclosure, a part of the address field of the tag part in the access address is selected as the spatial index field. The spatial index field is extracted for calculation to index the storage space.

[0057] For step S32, storage access is performed in the target storage space according to the access address.

[0058] After the target storage space is determined, the access address is used to perform storage access in the target storage space. For example, the access address may be parsed, the target storage location in the target storage space may be determined according to the parsed access address, and the access data of the target storage location may be accessed.

[0059] In the above-mentioned embodiment of the present disclosure, by first determining the target storage space of the access address in multiple storage spaces of the storage device, and then accessing according to the access address in the target storage space, such a multi-level indexing method makes the storage access flexibility and adaptability of the storage device higher, and such a storage access method is easy to implement and will not increase the complexity of the hardware and the area and power consumption of the chip.

[0060] In some embodiments of the present disclosure, the total storage capacity of the storage device is not equal to an integer power of 2.

[0061] For example, when the storage device is a cache, it may include multiple SRAM arrays; for example, the capacity of each SRAM array is an integer power of 2.

[0062] In some embodiments of the present disclosure, the storage capacity of each storage space of the plurality of storage spaces is an integer power of 2.

[0063] For example, the total storage capacity of the storage device may be divided into a plurality of storage spaces in the storage device according to the condition of satisfying an integer power of 2, so that the capacity of each storage space in the plurality of storage spaces is an integer power of 2.

[0064] In some embodiments of the present disclosure, the total storage capacity of the storage device is not equal to an integer power of 2, while the storage capacity of each storage space of the plurality of storage spaces is an integer power of 2.

[0065] In order to maximize the capacity of the storage device in a limited space, for example, during the design or configuration of the storage device, the total capacity of the storage device finally obtained is not equal to an integer power of 2. If the access address is used to access the storage device with the maximum capacity, since the total capacity of the storage device is not equal to an integer power of 2, the address bits of all the tag parts of the access address need to be calculated to route the request to the target storage bit, and such calculation will greatly increase the access delay and the complexity of the system hardware.

[0066] A storage device with a maximum capacity whose total capacity is not equal to an integer power of 2 may be divided into a plurality of storage spaces, so that the storage capacity of each storage space is an integer power of 2. For example, the capacity of the storage device is X (MB), where X≠2k and X and k are both positive integers. For example, the capacity X (MB) of the storage device may be divided into a storage space of 2n (MB) and a storage space of 2m (MB) (where n and m are non-negative integers), and the relationship of the storage capacities satisfies X (MB) = 2n (MB) + 2m (MB).

[0067] In this way, the storage device with the largest capacity can be accessed by first accessing the target storage space therein, and then accessing the target storage bit in the target storage space. The above method is suitable for accessing all storage devices whose total capacity is not equal to an integer power of 2. This method greatly improves the flexibility of storage access, and does not require increasing the complexity of hardware or increase access delay.

[0068] In some embodiments of the present disclosure, step S31 of the above storage index method also includes step S310 and step S311.

[0069] For step S310, the storage space access index is determined according to the address bits in the space index field belonging to the tag part in the access address.

[0070] For step S311, a target storage space is determined according to the storage space access index.

[0071] For example, the address bits in the space index field are mapped or calculated to determine the storage space access index. For example, in at least one embodiment, a mapping relationship between the storage space and the space access index (space index value) is provided, such as providing a lookup table recording the mapping relationship, so that the target storage space can be determined through the storage space access index.

[0072] By determining the storage space access index according to the address bit in the space index field belonging to the tag part of the access address, it is possible to prevent access failure due to index conflict when accessing the storage space. That is, a storage space access index will only point to one corresponding storage space, and a storage index will not point to multiple storage spaces.

[0073] In some embodiments of the present disclosure, step S310 of the above storage index method also includes step S320.

[0074] For step S320, the numerical value of the address bit in the space index field is operated, and the storage space access index is determined according to the operation result.

[0075] For example, there is a proportional relationship between the multiple storage capacities corresponding to the multiple storage spaces, where the storage capacities of the multiple storage spaces all satisfy an integer power of 2. For example, the multiple storage spaces include two storage spaces, for example, storage space 0 and storage space 1. The proportional relationship between the capacities of the two storage spaces is storage space 0: storage space 1 = 2n (MB): 2m (MB). For example, when n=2 and m=3, the proportional relationship is storage space 0: storage space 1 = 4 (MB): 8 (MB). It can also be further simplified to obtain the simplest ratio, for example, storage space 0: storage space 1 = 1:2, so the number of spatial index values ​​corresponding to storage space 0 is half of the spatial index value corresponding to the storage space.

[0076] According to the proportional relationship between the multiple storage capacities corresponding to the multiple storage spaces, the numerical value of the address bit in the space index field is calculated. For example, according to the proportional relationship between the multiple storage capacities of storage space 0: storage space 1 = 1:2, it can be known that the total number of storage capacities in all storage spaces is 3, and the correspondence between each storage space and the space index value can be based on the proportional relationship between the multiple storage capacities corresponding to the multiple storage spaces. Perform a modulo operation on the space index field according to the total number of copies, for example, the space index field MOD 3. Determine the storage space access index based on the possible operation results 00, 01 and 10.

[0077] For example, when the capacities of multiple storage spaces all satisfy an integer power of 2, the size of the index field and the number of spatial index values ​​can also be determined based on the relationship between multiple exponents of the storage capacities of the multiple storage spaces when expressed as an integer power of 2. For example, the multiple storage spaces include two storage spaces, for example, storage space 0 = 2n (MB) and storage space 1 = 2m (MB). For example, according to the formula, the value of the spatial index field is subjected to a modulo operation, that is, the spatial index value MOD (2abs (mn) + 1), and the operation result is obtained. For example, when n = 2 and m = 3, the spatial index value MOD (2abs (3-2) + 1) = the spatial index value MOD 3. Based on the possible operation results 00, 01 and 10, the storage space access index is determined.

[0078] For example, the possible operation results 00, 01 and 10 can be divided into storage space 0: storage space 1 = 1:2 according to the ratio of the storage capacity of the above two storage spaces. For example, the value 00 is used as the index of storage space 0, and the values ​​01 and 10 are used as the index of storage space 1, that is, the operation result 00 corresponds to storage space 0, and the operation results 01 and 10 correspond to storage space 1.

[0079] It should be noted that the number of digits of the address bits in the spatial index field will affect the number of numerical values ​​of the address bits in the spatial index field, thereby affecting the index uniformity for multiple storage spaces. The value corresponding to the number of digits of the address bits in the spatial index field is an integer multiple of the modulus in the modulus operation, and the better the index uniformity for multiple storage spaces. For example, if the number of digits of the address bits in the spatial index field is 2, the minimum value of the address bits in the spatial index field is 0 and the maximum is 3. If the total number of copies of the storage capacity is 3, then the spatial index field MOD 3 will have 3 operation results 01, 10 and 00. For example, if 00 is used as the index of storage space 0 according to the proportional relationship of the storage capacity of multiple storage spaces, and 01 and 10 are used as the index of storage space 1, then the ratio of being able to index storage space 0 to being able to index storage space 1 is 1:2, which is equal to the ratio of the capacity of multiple storage spaces, storage space 0: storage space 1 = 1:2. In this way, the index uniformity for multiple storage spaces is better.

[0080] For example, when the value corresponding to the number of address bits in the spatial index field cannot be an integer multiple of the modulus in the modulus operation, the index uniformity for multiple storage spaces can be improved by increasing the number of address bits in the spatial index field.

[0081] It should be noted that, although the above example of multiple storage space indexes is based on two storage spaces, this does not limit the number of multiple storage spaces, and the number of multiple storage spaces can also be 3 or more. For example, the proportional relationship of the storage capacity of the three storage spaces is storage space 0: storage space 1: storage space 2 = 2n (MB): 2m (MB): 2p (MB) = 24 (MB): 22 (MB): 21 (MB) = 8:2:1, so the total number of storage capacities of the three storage spaces is 11. For example, the space index field can include 4 address bits, and the storage space access index can be determined by the calculation result of the corresponding space index value MOD 11. The storage space access index can also be determined by calculating the calculation result of the space index value MOD (2abs (mn) + 2abs (np) + 1) according to the formula.

[0082] It should be noted that although the above examples of storage capacity of multiple storage spaces are described according to the unit of storage capacity being megabytes (MB), this does not limit the storage capacity units of multiple storage spaces and storage devices. In the present disclosure, when describing whether the storage device and the storage space are integer powers of 2, it is based on the same storage capacity unit. The storage capacity units of the storage device and the storage space can be kilobytes (KB), megabytes (MB), gigabytes (GB), terabytes (TB), petabytes (PB) and exabytes (EB), etc., which are not limited in the present disclosure.

[0083] In some embodiments of the present disclosure, in the above-mentioned storage index method, multiple storage spaces correspond to multiple theoretical result values ​​(result value spaces) determined according to the calculation results; a first ratio of the number of corresponding theoretical result values ​​of each storage space to the total number of multiple theoretical result values ​​matches a second ratio of the storage capacity of each storage space to the total storage capacity of multiple storage spaces.

[0084] The multiple theoretical result values ​​of the multiple storage spaces can be determined by the operation results according to the proportional relationship of the multiple storage capacities. For example, the multiple storage spaces include two storage spaces, for example, storage space 0 and storage space 1. The proportional relationship of the storage capacity of the above two storage spaces is storage space 0: storage space 1 = 1:2. For example, according to the above MOD3 operation results, there are 3, and the multiple storage spaces correspond to the multiple theoretical result values ​​determined according to the operation results, 00, 01 and 10, wherein the storage space 0 corresponds to the theoretical result value of 00, and the storage space 1 corresponds to the theoretical result values ​​of 01 and 10, that is, 00 is used as the index of storage space 0, and 01 and 10 are used as the index of storage space 1. For example, the number of theoretical result values ​​corresponding to storage space 0 is 1, and the number of theoretical result values ​​corresponding to storage space 1 is 2, then the number of theoretical result values ​​corresponding to storage space 0 / the total number of multiple theoretical result values ​​(first ratio) = the storage capacity of storage space 0 / the total storage capacity of multiple storage spaces (second ratio); the number of theoretical result values ​​corresponding to storage space 1 / the total number of multiple theoretical result values ​​(first ratio) = the storage capacity of storage space 1 / the total storage capacity of multiple storage spaces (second ratio).

[0085] Another example is storage space 0 and storage space 1. The storage capacity ratio of the above two storage spaces is storage space 0: storage space 1 = 1:3. Then the MOD4 operation can be used. There are 4 operation results. The theoretical result values ​​of multiple operations are 00, 01, 10 and 11. Then the theoretical result value corresponding to storage space 0 is 00, and the theoretical result value corresponding to storage space 1 is 01, 10 and 11. That is, 00 is used as the index of storage space 0, and 01, 10 and 11 are used as the index of storage space 1. In this example, the value of the 2-bit space index field itself can actually be used directly for indexing. For example, 11 is used as the index of storage space 0, and 00, 01, 10 are used as the index of storage space 1.

[0086] In some embodiments of the present disclosure, the numerical value corresponding to the number of bits of the address bits in the spatial index field is not equal to an integer multiple of the modulus in the modulus operation. For example, the proportional relationship between the storage capacity of the above two storage spaces is storage space 0: storage space 1 = 2:3. For example, the storage space access index is determined based on the possible results of the modulus operation on the numerical value of the address bits in the spatial index field according to the above proportional relationship. For example, the operation results 001 and 000 are used as the storage space access index of storage space 0, and the operation results 011, 100 and 010 are used as the storage space access index of storage space 1.

[0087] For example, in the above embodiment, the number of address bits in the spatial index field is 3 bits, then the minimum value of the address bits in the spatial index field is 0 and the maximum value is 7, and the multiple storage spaces have multiple theoretical result values ​​of 001, 010, 011, 100, 000, 001, 010 and 111, a total of 8, and the number of theoretical result values ​​corresponding to storage space 0 can be determined as 3, and the number of theoretical result values ​​corresponding to storage space 1 can be determined as 5. Although the number of theoretical result values ​​corresponding to storage space 0 / the total number of multiple theoretical result values ​​(first ratio) ≠ the storage capacity of storage space 0 / the total storage capacity of multiple storage spaces (second ratio), the number of theoretical result values ​​corresponding to storage space 1 / the total number of multiple theoretical result values ​​(first ratio) ≠ the storage capacity of storage space 1 / the total storage capacity of multiple storage spaces (second ratio), it is also considered that the first ratio and the second ratio are matched. Therefore, the first ratio and the second ratio are matched within a certain reasonable deviation range, and the size of the specific reasonable deviation range is not limited in this disclosure.

[0088] In some embodiments of the present disclosure, the above operation of obtaining the index value may include a modulus operation or a hash operation.

[0089] For example, a hash operation is performed on the numerical value of the address bit in the space index field, a hash index table is established according to the operation result of the hash operation, and the storage space access index is determined according to the hash index table.

[0090] In some embodiments of the present disclosure, the modulo operation includes: using a modulus determined after a proportional operation based on multiple storage spaces to obtain an operation result after performing a modulo calculation on the numerical value of the address bits in the space index field.

[0091] For example, the modulus can be determined according to the proportional relationship of the storage capacity corresponding to the multiple storage spaces. For example, the proportional relationship of the multiple storage capacities is storage space 0: storage space 1 = 1:2, then the total number of 3 copies can be determined as the modulus. For example, the proportional relationship of the storage capacity of the multiple storage spaces is storage space 0: storage space 1: storage space 2 = 2n (MB): 2m (MB): 2p (MB) = 24 (MB): 22 (MB): 21 (MB), then the modulus can be determined according to a preset formula, such as modulus = 2abs (mn) + 2abs (np) + 1 to determine the modulus, or according to modulus = m + n + p to determine the modulus.

[0092] In some embodiments of the present disclosure, a plurality of storage spaces are divided into a plurality of storage space groups, each of the plurality of storage space groups includes at least one storage space, and the storage indexing method further includes the following step S33.

[0093] For step S33, the target storage space group corresponding to the access address in the storage device is determined according to the group index field in the space index field.

[0094] For example, if the number of storage spaces in the multiple storage spaces is greater than two, there will be a situation where the amount of calculation is too large when determining the target storage space. Therefore, the multiple storage spaces can be further divided into multiple storage space groups, wherein each storage space group includes at least one storage space. For example, the multiple storage spaces include storage space 0, storage space 1, and storage space 2, storage space 0 can be divided into storage space group 0, and storage space 1 and storage space 2 can be divided into storage space group 1.

[0095] The target storage space group corresponding to the access address in the storage device can be determined first according to the group index field in the space index field. For example, if the group index field in the space index field is 01, the target storage space group is determined to be storage space group 1 according to the group index field.

[0096] In some embodiments of the present disclosure, the above storage index method also includes step S34.

[0097] For step S34, the target storage space corresponding to the access address in the target storage space group is determined according to the space index field.

[0098] After the target storage space group is determined, the target storage space corresponding to the access address in the target storage space group can be determined according to the space index field. For example, if the target storage space group is storage space group 1 (including storage space 1 and storage space 2), the target storage space can be determined to be storage space 2 according to space index field 10. For example, if the target storage space group includes only one storage space, the storage space in the target storage space group can be directly determined.

[0099] It should be noted that although the storage space is indexed by nesting three storage spaces at two levels in the embodiment of the present disclosure, the number of levels of nested indexing is not limited. For example, four or even more storage spaces can be indexed to the target storage space by nesting three or four levels.

[0100] In some embodiments of the present disclosure, each storage space in the plurality of storage spaces is mapped in a direct associative or group associative manner.

[0101] Figure 3 The figure shows the principle diagram of the mapping relationship among direct associativity, full associativity and set associativity in the cache.

[0102] The storage device may be a cache, wherein multiple storage spaces may be accessed in a cached manner. The basic unit of a cache is a cache block or a cache line. The content stored in the cache is only a subset of the content of the main memory. In order to cache data in the main memory into the cache, a certain function must be applied to locate the access address to the cache, which is called address mapping. After the data in the main memory is mapped to the cache according to this mapping relationship, when the CPU executes the program, the access address in the program will be converted into a cache address. Cache address mapping methods usually include direct mapping, fully associative mapping, and set associative mapping.

[0103] Although the storage capacity of the cache is smaller than that of the main memory, its speed is much faster than that of the main memory. Therefore, the main function of the cache is to store data that the processor may need to access frequently in the near future. In this way, the processor can directly read data from the cache without frequently accessing the slower main memory, thereby increasing the processor's access speed to the main memory.

[0104] For example, similar to the division of a cache into multiple cache blocks, the data stored in the main memory is also divided similarly. The divided data blocks in the main memory are called memory blocks (or memory lines). Generally, the size of a memory block can be 32 bytes, and the size of a cache block can also be 32 bytes. It should be noted that in actual applications, the size of the main memory block and the cache line can also be set to other values, as long as the size of the main memory block is the same as the size of the cache block.

[0105] like Figure 3 As shown in Figure 1, both the main memory and the cache are divided into blocks of the same size. Assume that the main memory has 32 items and the cache has 8 items.

[0106] like Figure 3 As shown in (a), in the direct associative mode, each main memory block can only be placed in one location in the cache. Suppose you want to put the 12th main memory block in the cache. Since the cache has only 8 items, it can only be placed in the (12 mod8 = 4)th item and cannot be placed anywhere else. Therefore, it can be seen that the 4th, 12th, 20th, and 28th main memory blocks all correspond to the 4th item in the cache. If there is a conflict, they can only be replaced. The hardware required for the direct associative mode is simple but inefficient.

[0107] like Figure 3 As shown in (b), in the fully associative mode, each main memory block can be placed in any position of the cache, so that the 4th, 12th, 20th, and 28th main memory blocks can be placed in the cache at the same time. The hardware required for the fully associative mode is complex but efficient.

[0108] like Figure 3 As shown in (c), set associativity is a compromise between direct associativity and full associativity. Taking two-way set associativity as an example, the cache positions 0, 2, 4, and 6 are one way (here called the 0th way), and the positions 3, 5, and 7 are another way (here called the 1st way), with 4 blocks in each way. For block No. 12 of the main memory, because the remainder of 12 divided by 4 is 0, block No. 12 can be placed in the 0th position of the 0th way of the cache (that is, the 0th position of the cache), or in the 0th position of the 1st way (that is, the 1st position of the cache).

[0109] In some embodiments of the present disclosure, the access address includes a tag portion and an index portion, and step S32 of the above-mentioned storage index method further includes step S320.

[0110] For step S320, according to the index part, the target storage location in the target storage space is addressed, and according to the tag part, the tag is compared with the tag stored in the target storage location to confirm that the target access data corresponding to the access request is stored in the target storage location. For example, the tag part of the access address is compared with the tag stored in the target storage location. If they are the same, it is confirmed that the target access data corresponding to the access request is stored in the target storage location. Otherwise, it is confirmed that the target access data corresponding to the access request is not stored in the target storage location.

[0111] Figure 4 A schematic diagram of a cache set associative organization and addressing method provided by at least one embodiment of the present disclosure is shown.

[0112] like Figure 4 As shown in the figure, the cache is organized in the form of a cache line array (Set). A column of cache lines forms a way, and multiple cache lines at the same position in multiple columns of cache lines form a group. The cache includes multiple cache groups. The location of the accessed data or the accessed instruction in the cache is obtained by reading the access address (Set, Way, Byte). Each access address can include:

[0113] (a) The index part (Index) is used to select a set in the cache. All cache lines in the same set are selected by the index.

[0114] (b) The tag part (Tag) is used to select a specific cache line in a set (Set). The tag of the physical address is compared with the tag of each cache line. If they match, it is a cache hit (Cache Hit), thereby selecting this cache line. Otherwise, it is a cache miss (Cache Miss).

[0115] (c) The offset part (Offset) is used to select the corresponding address in the cache line. It indicates that the access address is the first byte (Byte) in the cache line, and the corresponding data or instruction is read from the position of this byte.

[0116] For example, for a cache, the tag portion corresponding to the stored data may be stored in a Tag RAM array.

[0117] For the target storage space, firstly, a target storage location in the target storage space is addressed according to an index portion in the access address, wherein the target storage location may be located in a target cache group in the target cache.

[0118] For example, after determining the target cache group, the tag part of the access address is compared with multiple tags stored in the target cache group to confirm that the target access data corresponding to the access request is stored in a cache line, and the cache line is the target cache line.

[0119] If it is confirmed that the target access data corresponding to the access request is stored in the target cache line, then the corresponding data or instruction is determined to be read from the target byte position in the target cache line according to the offset portion.

[0120] For example, Figure 4 As shown, for a 32-bit access address, the tag part is the high-order part of the access address, one or more address bits adjacent to the lowest address bit of the tag part are the index part, and the offset is the low-order part of the access address.

[0121] At least one embodiment of the present disclosure also provides a storage index device. The storage index device is used for a storage device and includes a receiving unit and an access unit. The storage device includes multiple storage spaces, such as a cache for a computer system, and the multiple storage spaces can be accessed independently in a cache manner.

[0122] The receiving unit is configured to receive an access request to the storage device, wherein the access request includes an access address; the access unit is configured to determine a target storage space corresponding to the access address in the storage device according to a space index field belonging to a tag part in the access address, and perform storage access in the target storage space according to the access address.

[0123] Figure 5 A block diagram of a memory provided by at least one embodiment of the present disclosure is shown.

[0124] like Figure 5 As shown, the storage index device 80 is used in the storage device 70, and the storage index device 80 includes a receiving unit 801 and an access unit 802. The storage device 70 includes a plurality of storage spaces, each of which includes a storage array, and the storage array is, for example, an SRAM storage array.

[0125] The receiving unit 801 is configured to receive an access request to the storage device 70 , where the access request includes an access address.

[0126] The access unit 802 is configured to determine the target storage space corresponding to the access address in the storage device 70 according to the space index field belonging to the tag part in the access address, and perform storage access in the target storage space according to the access address.

[0127] For example, in one example, the access unit 802 may include a modulo unit and a spatial selection unit.

[0128] The modulo unit is configured to perform a modulo operation on the numerical value of the address bit in the space index field, and determine the storage space access index according to the operation result of the modulo operation.

[0129] The space selection unit is configured to determine a target storage space corresponding to the access address in the storage device according to an index identification bit in the storage space access index and the access address.

[0130] For example, in one example, the space selection unit may include a first AND gate and a second AND gate.

[0131] The first AND gate and the second AND gate are arranged in corresponding branches of different storage spaces, and the output logic relationships of the first AND gate and the second AND gate are opposite.

[0132] The description of the storage device, storage space and spatial index field here is the same as above, please refer to the above, so it will not be repeated here.

[0133] The technical effect of the storage index device of the above embodiment of the present disclosure is the same as the technical effect of the above storage index method, so it will not be repeated.

[0134] At least one embodiment of the present disclosure also provides an electronic device, comprising: at least one memory configured to store computer-executable instructions; and at least one processor configured to execute the computer-executable instructions, wherein when the computer-executable instructions are executed by the at least one processor, the storage indexing method as described in any of the above embodiments is implemented.

[0135] Figure 6 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0136] like Figure 6 As shown, the electronic device 600 includes at least one memory 610 and at least one processor 620 .

[0137] The at least one memory 610 is configured to store computer executable instructions.

[0138] At least one processor 620 is configured to execute computer executable instructions. When the computer executable instructions are executed by the at least one processor 620, the storage indexing method as described in any of the above embodiments is implemented.

[0139] Figure 7 FIG. 1 is an exemplary schematic diagram showing the operation logic of a storage index device provided by at least one embodiment of the present disclosure. Figure 7 Taking the storage device being divided into two storage spaces for indexing as an example, this does not mean that the disclosure is limited to the storage space of the index being two storage spaces. Those skilled in the art in the disclosure can Figure 7 The logical designs made based on the logical conception belong to the scope of protection of this disclosure.

[0140] like Figure 7 As shown, the access request can be for a data read operation or a data write operation, for example, for a last level cache (LLC), which includes multiple storage spaces, each of which can be operated using a cache access mode. In the operation logic, firstly, the space index field in the access address (physical address) PA[M:N] is used to perform a modulo operation on the value of the address bit in the space index field through the modulo unit 30, and the storage space access index is determined according to the result of the modulo operation.

[0141] The storage capacity of storage space 0 and storage space 1 are both integer powers of 2. For example, the storage capacity of storage space 0 is 2n (MB), and the storage capacity of storage space 1 is 2m (MB). Both storage space 0 and storage space 1 include an SRAM array and a Tag RAM array.

[0142] like Figure 7 As shown, an index identification signal can be generated according to the storage space access index, so that the index identification signal is used as an enable signal (Enable) to select different storage spaces. For example, when the index identification signal is high, storage space 0 is selected, and when it is low, storage space 1 is selected. For example, the signal output by the modulus unit 30 will be sent to the branch where storage space 0 is located and the branch where storage space 1 is located, wherein an inverter 3 is provided on the branch where storage space 1 is located. Inverter 3 can invert the signal, thereby realizing the selection between storage space 0 and storage space 1.

[0143] The index identification bit in the storage space access index can be input into the space selection unit 400 together with the access address to determine the target storage space corresponding to the access address in the storage device. The space selection unit 400 may include a first AND gate 40 and a second AND gate 41, and the first AND gate 40 and the second AND gate 41 are set in corresponding branches of different storage spaces. The output logic relationship of the first AND gate 40 and the second AND gate 41 is opposite, that is, when the first AND gate 40 outputs a signal, the second AND gate 41 does not output a signal. For example, the output drive selection of the first AND gate 40 and the second AND gate 41 is performed through the index identification bit, so that the access address PA[M:N] can be transmitted to the branch corresponding to the target storage space.

[0144] It should be noted that although this embodiment takes the space selection unit 400 as an example including the first AND gate 40 and the second AND gate 41, the space selection unit 400 is not limited to being implemented by an AND gate. For example, it can also be implemented by selection through a multiplexer, etc., and the present disclosure does not limit this.

[0145] After the first AND gate 40 and the second AND gate 41 , a decoding unit 31 for decoding the access address may be provided. The decoding unit 31 may be used to parse the access address, for example, parse the index part and the tag part in the access address.

[0146] Storage space 0 and storage space 1 are caches. A corresponding target cache group is selected in the SRAM array in the target storage space according to the index part, and a target cache line is searched in the target cache group according to the tag part.

[0147] For example, the access data of the access address may be found by searching from the target cache line.

[0148] In some embodiments of the present disclosure, the decoding unit 31 may also parse the offset portion in the access address, and determine the corresponding data or instruction in the target cache line to be read from the target byte position according to the offset portion.

[0149] Figure 8 A schematic diagram of a storage index process of a last level cache (LLC) provided by at least one embodiment of the present disclosure is shown. For example, when the storage device 70 is a last level cache (LLC), the last level cache includes multiple storage spaces, such as storage space 0 and storage space 1 (refer to Figure 7 described above).

[0150] Receive the access address in the access request for the LLC, and perform an operation on the value of the spatial index field belonging to the tag part of the access address, for example, perform a modulus operation on the value of the spatial index field. Figure 7 , a modulo operation is performed by the modulo unit 30.

[0151] Determine whether to map to a certain storage space of LLC according to the operation result. For example, an index identification signal can be generated according to the operation result, and determine whether to map to a certain storage space of LLC according to the index identification signal. Figure 7 , according to the operation result of the modulo unit 30, the inverter 2 is used to generate different index identification signals. Figure 7 , the index identification signal is input to the first AND gate 40 corresponding to storage space 0, and the index identification signal through inverter 3 is input to the second AND gate 41 corresponding to storage space 1. For example, storage space 0 is selected when the index identification signal is high, and storage space 1 is selected when it is low.

[0152] Determine whether the result of the modulo operation is mapped to the LLC storage space 0. For example, refer to Figure 7 , determine whether to map to storage space 0 of LLC based on the outputs of the first AND gate 40 and the second AND gate 41. If the first AND gate 40 can output the access address, it is mapped to storage space 0, otherwise, it is mapped to storage space 1.

[0153] For example, if the judgment result is yes, then the target storage space accessed by the access address is storage space 0, and through the decoding unit corresponding to storage space 0 (for example Figure 7 The decoding unit 31 performs decoding to determine the tag part and the index part in the access address.

[0154] For example, if the judgment result is no, then the target storage space accessed by the access address is storage space 1, and through the decoding unit corresponding to storage space 1 (for example Figure 7 The decoding unit 31 performs decoding to determine the tag part and the index part in the access address.

[0155] In the target storage space, the target storage location can be found according to the index part in the access address. For example, if the storage space 0 is accessed, the target cache group (Set) is found according to the index part in the storage space 0. For example, if the storage space 1 is accessed, the target cache group (Set) is found according to the index part in the storage space 1. It should be noted that each storage space may include at least one cache group. If there is only one cache group in the target storage space, it can be determined that the cache group is the target cache group.

[0156] In the target cache group, the Tag RAM array of the corresponding storage space can be searched according to the tag part in the access address to determine whether it matches the tag part. By determining the match with the tag part, it is possible to determine whether the target cache line exists. For example, if the storage space 0 is accessed, the Tag RAM array of storage space 0 is searched to determine whether it matches the tag part. For example, if the storage space 1 is accessed, the Tag RAM array of storage space 1 is searched to determine whether it matches the tag part.

[0157] If the tag part matches successfully, the cache hits (Cache Hit). The access data of the corresponding storage space can be accessed according to the index part of the access address. For example, the tag part in the access address matches the tag stored in the Tag RAM array of the target storage space (storage space 0), the cache line of the cache hit (Cache Hit) is determined, and the access data in the cache line is accessed.

[0158] If the tag part fails to match, it is a cache miss (Cache Miss), indicating that the access data of the access address is not stored in the target storage space, and an access request needs to be sent to the main memory or other cache to continue searching. For example, if the tag part in the access address does not match the tag stored in the Tag RAM array of the target storage space (storage space 1), an access request is sent to the main memory or other cache to continue searching.

[0159] At least one embodiment of the present disclosure further provides a memory, referring to Figure 5 As shown, the memory 800 includes the storage index device 80 and the storage device 70 described in at least one of the above embodiments. For example, the memory 800 can be used as a cache in a computer system.

[0160] The description of the corresponding storage index device and storage device is the same as above, please refer to the above, and will not be repeated here.

[0161] The technical effect of the memory of the above embodiment of the present disclosure is the same as the technical effect of the above storage index method, so it will not be repeated here.

[0162] At least one embodiment of the present disclosure further provides an electronic device, which includes the storage index device or memory described in at least one of the above embodiments.

[0163] Fig. 9 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0164] The electronic device 1000 in the embodiment of the present disclosure may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. The electronic device 1000 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiment of the present disclosure.

[0165] For example, refer to Fig. 9 In some examples, the electronic device 1000 includes at least one processing device (such as a central processing unit, a graphics processing unit, etc.) 1001, and a cache is provided for the processing device. The cache is a memory (including a storage index device and a storage device) according to any embodiment of the present disclosure, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage device 1008 to the random access memory (RAM) 1003. For example, the ROM 1002 can be used as the main memory 202, and various programs and data required for the operation of the computer system are also stored in the RAM 1003. The processing device 1001, the input / output (I / O) interface 1005, the ROM 1002, and the RAM 1003 are connected to each other through the Internet 1004.

[0166] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; the input device 1006 may be used as the request end 60 in the embodiment of the present disclosure, including an output device 1007 such as a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; a communication device 1009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or wired to exchange data, and perform communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that the computer program read therefrom is installed into the storage device 1008 as needed. Although the electronic device 1000 including various devices is shown, it should be understood that it is not required to implement or include all the devices shown. Greater or fewer devices may alternatively be implemented or included.

[0167] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0168] For example, the electronic device 1000 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0169] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer executable instructions. For example, when the computer executable instructions are executed by a processor, the storage index method provided by at least one embodiment of the present disclosure is implemented. The processor includes at least one processing unit.

[0170] Fig.10 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. Fig.10 As shown, the non-transitory storage medium 900 can non-transitorily store computer executable instructions 910, and the computer executable instructions 910 implement the storage index method provided by any embodiment of the present disclosure when executed by a computer.

[0171] The technical effect of the above-mentioned non-temporary storage medium is the same as the technical effect of the above-mentioned storage index method, which will not be repeated here.

[0172] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of the code contains at least one executable instruction for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0173] In general, various example embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, firmware, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device. When various aspects of the embodiments of the present disclosure are illustrated or described as block diagrams, flow charts, or using some other graphical representation, it will be understood that the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, firmware, dedicated circuits or logic, general hardware or controllers or other computing devices, or some combination thereof as non-limiting examples.

[0174] There are a few points to note about this disclosure:

[0175] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0176] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0177] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A storage index method, comprising: Receiving an access request to a storage device, wherein the access request includes an access address, and the storage device includes a plurality of storage spaces; Determine, according to a space index field belonging to a tag part in the access address, a target storage space corresponding to the access address in the plurality of storage spaces; A storage access is performed in the target storage space according to the access address.

2. The storage index method according to claim 1, wherein: The total storage capacity of the storage device is not equal to an integer power of 2, and / or the storage capacity of each storage space of the multiple storage spaces is an integer power of 2.

3. The storage index method according to claim 1, wherein: The step of determining, according to a spatial index field belonging to a tag part in the access address, a target storage space corresponding to the access address in the plurality of storage spaces comprises: Determine a storage space access index according to the address bits in the space index field in the access address; The target storage space is determined according to the storage space access index.

4. The storage index method according to claim 3, wherein: The step of determining the storage space access index according to the address bits in the space index field in the access address comprises: An operation is performed on the numerical value of the address bit in the space index field, and the storage space access index is determined according to the operation result of the operation.

5. The storage index method according to claim 4, wherein: The plurality of storage spaces correspond to a plurality of theoretical result values ​​determined according to the operation results; A first ratio of the number of corresponding theoretical result values ​​of each storage space to the total number of the plurality of theoretical result values ​​matches a second ratio of the storage capacity of each storage space to the total storage capacity of the plurality of storage spaces.

6. The storage index method according to claim 4, wherein: The operation includes a modulo operation or a hash operation.

7. The storage index method according to claim 6, wherein: The modulo operation includes: The modulus determined after performing proportional operation based on the multiple storage spaces is used to obtain the operation result after performing modulus calculation on the numerical value of the address bit in the space index field.

8. The storage index method according to claim 1, wherein: The plurality of storage spaces are divided into a plurality of storage space groups, each of the plurality of storage space groups includes at least one storage space, and the storage index method further includes: The target storage space group corresponding to the access address in the storage device is determined according to the group index field in the space index field.

9. The storage index method according to claim 8, further comprising: The target storage space corresponding to the access address in the target storage space group is determined according to the space index field.

10. The storage index method according to any one of claims 1 to 9, wherein: Each storage space in the plurality of storage spaces is mapped in a direct associative or group associative manner.

11. The storage index method according to any one of claims 1 to 9, wherein: The access address includes a tag part and an index part; The performing storage access in the target storage space according to the access address includes: addressing a target storage location in the target storage space according to the index portion, and According to the tag part, a comparison is made with the tag stored in the target storage location to confirm that the target access data corresponding to the access request is stored in the target storage location.

12. A storage index device, used in a storage device, comprising: A receiving unit, configured to receive an access request to the storage device, wherein the access request includes an access address, and the storage device includes a plurality of storage spaces; The access unit is configured to determine the target storage space corresponding to the access address in the storage device according to the space index field belonging to the tag part in the access address, and perform storage access in the target storage space according to the access address.

13. The storage index device according to claim 12, wherein: The access unit comprises: A modulo unit configured to perform a modulo operation on the numerical value of the address bit in the space index field, and determine the storage space access index according to the operation result of the modulo operation; The space selection unit is configured to determine a target storage space corresponding to the access address in the storage device according to an index identification bit in the storage space access index and the access address.

14. The storage index device according to claim 13, wherein: The space selection unit includes: a first AND gate and a second AND gate, The first AND gate and the second AND gate are arranged in corresponding branches of different storage spaces, and the output logic relationships of the first AND gate and the second AND gate are opposite.

15. An electronic device, comprising: at least one memory configured to store computer-executable instructions; as well as at least one processor configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the at least one processor, the storage indexing method according to any one of claims 1-11 is implemented.

16. A non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein: When at least one processor executes the computer executable instructions, the storage indexing method according to any one of claims 1 to 11 is implemented.

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