Authentication chip and self-detection circuit

Abstract

The invention provides an authentication chip and a self-detection circuit, the authentication chip is used for being installed on a replaceable accessory, the replaceable accessory is used for being installed in a host, the self-detection circuit is characterized in that a self-detection trigger signal is received, physical parameters of the authentication chip are detected, first detection data are generated, and the physical parameters are inherent attribute parameters of the authentication chip; generating first ID bit data of the authentication chip according to the first detection data; adjusting data on an ID bit of the storage module according to the first ID bit data; receiving an authentication request sent by the host, and responding to the identity authentication of the host by using the data on the ID bit adjusted according to the first ID bit data; the authentication chip can respond to the self-detection trigger signal, automatically detect the physical parameters of the authentication chip, generate the first ID bit data in a use environment, and further adjust the information on the ID bit of the storage module, so that the data currently stored on the ID bit of the authentication chip better conforms to the actual use environment.

Description

Technical Field

[0001] The present application relates to the technical field of authentication chips, and in particular to an authentication chip and a self-detection circuit. Background Art

[0002] Printers are commonly used office equipment. Printers are provided with replaceable print cartridges, such as ink cartridges, developer cartridges and other consumables. The replaceable print cartridge is provided with a data storage chip (authentication chip). In order to improve the security of the replaceable print cartridge data storage chip and the accuracy of identity recognition, PUF (abbreviation of physical unclonable technology, an important hardware security technology that uses the inherent properties of semiconductors to randomly extract unclonable physical properties) is used to generate the chip's identity identifier (ID bit data). The existing method is to measure the physical parameters of the data storage chip during manufacturing and store them in some units of the ID bit to generate ID bit data. When the data storage chip is installed in the printing device, the printing device will measure the value of the physical parameter of the chip on site and compare it with the value of the physical parameter in the ID bit of the data storage chip. If it does not match (that is, it is not within a given tolerance), the printing device prompts that the replaceable print cartridge is untrustworthy. However, due to the influence of on-site environments such as temperature and humidity, high pressure, and electromagnetic, the physical parameters of the trustworthy replaceable print cartridge data storage chip may also be out of the given tolerance. At this time, the printing device will have an error prompt phenomenon, resulting in the replaceable print cartridge data storage chip not being authenticated and cannot be used. Summary of the invention

[0003] The present application provides an authentication chip, which is used to reduce the impact of the on-site environment when the authentication chip performs authentication on a host.

[0004] In order to achieve the above-mentioned purpose, on the one hand, the present application provides an authentication chip, the authentication chip is used to be installed on a replaceable accessory, the replaceable accessory is used to be installed in a host, receive a self-detection trigger signal, detect the physical parameters of the authentication chip, generate first detection data, the physical parameters are the inherent attribute parameters of the authentication chip; generate first ID bit data of the authentication chip according to the first detection data; adjust the data on the ID bit of the storage module of the authentication chip according to the first ID bit data; receive the authentication request sent by the host, and respond to the identity authentication of the host with the data on the ID bit adjusted according to the first ID bit data. In a possible design, the data on the ID bit of the storage module is adjusted according to the first ID bit data; including: if the ID bit of the storage module of the authentication chip does not have the second ID bit data, then write the first ID bit data into the ID bit; if the ID bit of the storage module of the authentication chip has the second ID bit data, then determine whether to update the data on the ID bit according to the comparison result of the first detection data and the physical parameter data of the storage module of the authentication chip.

[0005] In one possible design, the receiving of the self-detection trigger signal includes receiving a power-on signal of the authentication chip, or receiving a signal from a printing device detecting a physical parameter of the authentication chip, as the self-detection trigger signal.

[0006] In a possible design, generating the first ID bit data of the authentication chip according to the first detection data includes generating the first ID bit data according to the first detection data and reference data stored in the storage module.

[0007] In one possible design, the determination of whether to update the data on the ID position is made based on a comparison result between the first detection data and the physical parameter data of the authentication chip storage module; including: if the comparison result is within a first tolerance range stored in the storage module, then the data on the ID position is not updated; if the comparison result is not within the first tolerance range stored in the storage module, then the data on the ID position is updated, or the reference data is updated, or the physical parameters of the authentication chip are detected again.

[0008] In one possible design, if the comparison result is not within the first tolerance range stored in the storage module, the data on the ID bit is updated, or the reference data is updated, or the physical parameters of the authentication chip are detected again; including, if the comparison result is within the second tolerance range stored in the storage module, then obtaining the number of detections N under the current self-detection trigger signal, if N≤1, then detecting the physical parameters of the authentication chip again, if N>1, adjusting the second ID bit data on the ID bit to the first ID bit data, or adjusting the reference data; if the comparison result is not within the second tolerance range stored in the storage module, adjusting the second ID bit data on the ID bit to the first ID bit data, or adjusting the reference data; wherein, the first tolerance range is smaller than the second tolerance range.

[0009] In one possible design, if the comparison result is not within the first tolerance range stored in the storage module, the data on the ID bit is updated, or the reference data is updated, or the physical parameters of the authentication chip are detected again; including locating the corresponding data segment to be adjusted according to the address pointer data in the storage module to update and write the data on the ID bit or the reference data.

[0010] In one possible design, the first ID bit data of the authentication chip is generated according to the first detection data; it also includes recording the first environmental information of the first environment, and the first ID bit data corresponding to the first environment, for autonomously updating and adjusting the data on the ID bit in the first environment that occurs subsequently.

[0011] On the other hand, the present application also provides a self-detection circuit, which is applied to an authentication chip. The self-detection circuit includes a physical information module, a self-detection module, an ID bit generation module and a storage module. The self-detection module is connected to the physical information module and the ID bit generation module respectively, and the ID bit generation module is also connected to the storage module; the physical information module is used to provide physical parameters of the authentication chip, and the physical parameters are inherent attribute parameters of the authentication chip; the self-detection module includes a clock circuit, an acquisition circuit and a detection circuit, the clock circuit is used to trigger a self-detection function in response to a self-detection trigger signal, the acquisition circuit is used to acquire the physical parameters of the physical information module, and the detection circuit is used to generate detection information according to the physical parameters; the ID bit generation module includes an algorithm circuit, and the algorithm circuit is used to generate first ID bit data according to the detection information; the storage module includes an ID bit module, and the ID bit module is used to store the first ID bit data generated by the ID bit generation module; the first ID bit data is used to respond to an authentication request sent by a subsequent host.

[0012] In one possible design, the storage module also includes a deviation data module, a reference data module, a physical parameter data module and an address pointer module, the deviation data module is used to store deviation data, the reference data module is used to store reference data, the physical parameter data module is used to store physical parameter data, the physical parameter data is data corresponding to the ID bit data, and the address pointer module is used to store address pointer data, the address pointer data points to the address information of the data on the ID bit, the physical parameter data, the reference data and the deviation data in the storage module.

[0013] The present application provides an authentication chip and a self-detection circuit, which can respond to a self-detection trigger signal and the physical parameters of the authentication chip to generate a first ID bit data under a usage environment, and adjust the information on the ID bit of the storage module according to the first ID bit data, so that the data currently stored on the ID bit of the authentication chip is more in line with the actual usage environment, reducing the influence of on-site environments such as temperature and humidity, high voltage, and electromagnetic, which may cause the authentication chip to erroneously fail to recognize the machine.

[0014] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by a chip upgrade device provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic diagram of the main self-test process of the authentication chip provided in one embodiment of the present application; Figure 2 A schematic diagram of a self-detection process of an authentication chip according to whether the second ID bit data exists in a storage module provided by an embodiment of the present application; Figure 3 A schematic diagram of a self-detection process of an authentication chip according to an embodiment of the present application, based on whether the detected first ID bit data and the existing second ID bit data are within a tolerance range; Figure 4A schematic diagram of a flow chart of an authentication chip according to an embodiment of the present application performing precise self-detection according to a first tolerance range and a second tolerance range; Figure 5 A schematic diagram of a module of a self-detection circuit provided in an embodiment of the present application; Figure 6 A schematic diagram of a self-detection module provided in an embodiment of the present application; Figure 7 A schematic diagram of an ID bit generation module provided in an embodiment of the present application; Figure 8 A schematic diagram of a storage module provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] The technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. The drawing numbers in the present application are only used to distinguish the steps in the scheme and are not used to limit the execution order of the steps. The specific execution order is subject to the description in the specification.

[0019] In order to solve the problems existing in the prior art, the present application embodiment provides an authentication chip, such as Figure 1 As shown, the self-test process of the authentication chip at least includes the following steps S1 to S3.

[0020] Step S1, receiving a self-detection trigger signal, detecting physical parameters of the authentication chip, and generating first detection data.

[0021] The authentication chip is a slave device, and the host is a master device. They are in a master-slave relationship, and the slave device is controlled by the master device.

[0022] In the embodiments of the present application, the authentication chip may be a consumable chip, the replaceable accessory may be a consumable box, and the host may be a printer; the authentication chip may also be a toy card, a phone card, and the host may also be a toy or a telephone and other devices, without limitation.

[0023] In an embodiment of the present application, the ID bit data is an identity identifier of an authentication chip. For example, in a printing system, the consumables can contain an authentication chip with an identification (ID bit) bit pre-programmed with a digital value of logic "1" (high) or logic "0" (low). When the consumable box is inserted into the printer system, the printer controller determines whether the box is authentic by reading (i.e., measuring) the high and low logic values ​​of the ID bit data to see if they match the preset logic values.

[0024] In the embodiment of the present application, after the authentication chip is installed in the host, it is electrically connected to the power supply interface of the host and begins to enter the self-test process S00. Figure 2 As shown, the following steps are also included: S11: The authentication chip is powered on or the printing device detects the physical parameters of the authentication chip (the clock module of the authentication chip monitors that the authentication chip is powered on or the printing device detects the physical parameters of the authentication chip, and uses the detection signal as the self-detection trigger signal in step S1).

[0025] S12: Start detecting the physical parameters of the authentication chip and generate first detection data according to the results; in the embodiment of the present application, the physical parameters are inherent attribute parameters of the authentication chip such as electrical characteristics.

[0026] S13: Transmit the first detection data to the algorithm circuit inside the chip.

[0027] Step S2: Generate first ID bit data of the authentication chip according to the first detection data.

[0028] In the embodiment of the present application, since the first detection data is an analog quantity, it needs to be calculated and converted by the algorithm circuit to generate the ID bit data required by the chip. Therefore, the following steps are required: Step S21: the algorithm circuit operates on the received first detection data to generate first ID bit data.

[0029] In an embodiment of the present application, the storage module stores one or more of address pointer data, configuration data, reference data, and ID bit data; wherein the configuration data includes ink color information, ink cartridge capacity information, etc., and the reference data represents the reference value of the conversion of the physical parameter of the current to be measured. The ID bit data is the identification of the chip, and the address pointer data points to the address information of the configuration data, reference data, and ID bit data in the storage module; the algorithm circuit performs calculations based on the physical quantity of the first detection data provided in the previous step, combined with the reference data and the algorithm, etc., to generate the first ID bit data, and the first ID bit data is digital information that can be stored in the ID bit.

[0030] In the embodiment of the present application, in addition to storing the generated first ID bit data on the storage module, the detected first detection data is also stored on the storage module as the physical parameter data of the chip.

[0031] In the embodiments of the present application, the algorithm used may be a simple data arrangement, data addition and subtraction operation, or a symmetric / asymmetric encryption algorithm.

[0032] Specifically, the comparison and analysis circuit 1032 divides (searches) the reference data blocks in the storage module according to the address pointer data.

[0033] In an embodiment of the present application, step S3 is also included: adjusting the data on the ID bit of the storage module according to the first ID bit data.

[0034] In one embodiment of the present application, the ID bit of the storage module of the authentication chip does not pre-store data such as electrical characteristics detected and written during manufacturing, that is, pre-detected physical parameter data and generated second ID bit data. After the authentication chip generates the first ID bit data according to step S21, it does not make any judgment, but directly writes the first ID bit data into the ID bit of the storage module, and writes the physical parameter data obtained by on-site detection. This arrangement not only omits the process steps of detection and writing during manufacturing, but also makes the generation environment of the data on the current generated ID bit consistent with the host detection environment, thereby reducing the impact of the environment on the authentication chip authentication.

[0035] like Figure 2 As shown, it is a flowchart of performing chip self-detection and generating data on the ID bit according to whether the storage module has the second ID bit data provided by an embodiment of the present application; a proofreading analysis step is added to the process: Step S311: Determine whether the storage module has the second ID bit data; In one embodiment of the present application, the storage module itself has second ID bit data, which may be written during the factory test phase, or may be generated by the authentication chip in the previous self-test process. Due to the difference between the factory test environment and the current usage environment of the host, or the difference between the host in different working process environments, such as the large difference in working temperature when the machine is on and when printing continuously, these differences will affect the authentication of the data on the ID bit of the authentication chip.

[0036] The detection steps of the authentication chip are as follows: if the second ID bit data is not stored in the ID bit of the storage module, then enter step S32: locate the ID bit data address according to the address pointer data in the storage module and write the corresponding data (first ID bit data); in this step, since there is no ID bit data in the ID bit of the storage module, the first ID bit data can be directly written into the ID bit as the final ID bit data generated by the self-detection.

[0037] If the ID bit of the authentication chip storage module has second ID bit data, it is determined whether to update the data on the ID bit according to the comparison result between the first detection data and the physical parameter data of the authentication chip storage module.

[0038] In an embodiment of the present application, step S21 may also be placed after the tolerance determination step of S311, and the first ID bit data is generated after determining that the comparison result is within the tolerance range.

[0039] In an embodiment of the present application, the physical parameter data is data such as electrical characteristics that are detected and encoded during manufacturing, and may also be electrical characteristic data corresponding to the stored ID bit data stored in the authentication chip storage module during the previous self-test process, that is, at least some data bits of the ID bit data correspond to the physical parameter data.

[0040] In an embodiment of the present application, after the authentication chip is manufactured, during typical operation in the field, in addition to comparing the logic high and low of the authentication identifier of the ID bit data of the authentication chip, the host (printer) also measures the value of the physical parameter of the specific memory unit of the authentication chip. The system compares the value of the physical parameter measured in the field with the value (physical parameter data) measured and encoded into the storage module during manufacturing. If the value measured in the field matches the value encoded during manufacturing (i.e., within a given tolerance), then the authentication system recognizes the replaceable supply device.

[0041] In the embodiment of the present application, the comparison and analysis circuit 1032 is used to compare the first detection data with the physical parameter data (analog information data) in the storage unit in combination with the tolerance range and the reference data.

[0042] In one embodiment of the present application, it is also possible to detect whether there is physical parameter data in the storage module to start the above-mentioned detection and data writing steps. The judgment method is the same as the judgment method of the second ID bit data and will not be repeated.

[0043] In the embodiments of the present application, Figure 3 As shown, the storage module also stores a tolerance range, which represents an allowable range of deviation data generated by the comparison result of the first detection data and the physical parameter data of the authentication chip storage module.

[0044] In an embodiment of the present application, the tolerance range may be given to one or more, for example, a first tolerance range and a second tolerance range may be set according to the range size, wherein the first tolerance range is smaller than the second tolerance range.

[0045] In an embodiment of the present application, the first tolerance range is a standard tolerance range, which is a pre-set tolerance range that allows the authentication chip to pass authentication, and the second tolerance range is an extreme tolerance range, which takes into account the allowable extreme deviation value generated by the comparison result of the first detection data detected and the physical parameter data of the authentication chip storage module caused by temporary environmental mutations.

[0046] The judgment steps are as follows: Step S311, determining whether the deviation data generated by the comparison result is within a tolerance range (one of the tolerance ranges stored in the storage module, preferably, determining the segment with a smaller tolerance range first).

[0047] Specifically, the following steps are also included: the comparison and analysis circuit 1032 divides the tolerance data blocks in the storage module according to the address pointer data.

[0048] If the judgment result is yes, the data on the storage module ID bit is not updated, and the process goes directly to step S01 to end the self-test process.

[0049] If the judgment result is no, then proceed to step 312: locate the corresponding data segment to be adjusted according to the address pointer data in the storage module and update and write. The following will describe in detail how to select the data segment to be adjusted.

[0050] In the embodiments of the present application, since the deviation between the first detection data of the on-site detection and the physical parameter data of the authentication chip storage module is large, the reason may be that the pre-written reference data is inappropriate (the reference value converted from the pre-stored physical parameter data is inappropriate, so there is a comparison deviation), or the second ID bit data pre-stored in the chip and its corresponding physical parameter data may be affected by the environment and are no longer applicable to the current environment.

[0051] In one embodiment of the present application, the authentication chip may restart the self-detection process to determine the cause of the large deviation and select the data type that needs to be adjusted.

[0052] If the second detection data generated by the secondary self-detection and the first detection data generated by the previous self-detection (similar environment) are within the first tolerance range, it is determined that the self-detection result is caused by environmental influence, and the data on the ID position is directly updated.

[0053] Otherwise, update the reference data so that the ID bit data subsequently generated based on the new reference data is more accurate.

[0054] In another embodiment of the present application, a third tolerance range can also be set to determine whether the deviation data generated by the comparison result is within the third tolerance range (the third tolerance range is larger than the first tolerance range, and if there is a second tolerance range, the third tolerance range is also larger than the second tolerance range); if the judgment result is yes, it may be that the original reference data does not match, so the reference data is adjusted; if the result is no, it means that the deviation is large and the possibility of environmental impact is large, by adjusting the ID bit data and physical parameter data, such as adjusting to the first ID bit data and the first detection data obtained by self-detection.

[0055] In an embodiment of the present application, multiple tolerance ranges can be set in steps, which can be reference ratio values ​​or specific values, for example, the first tolerance range is ±5% (refer to the original ID bit data), the second tolerance range is ±8%, and the third tolerance range is ±10%, or the first tolerance range is ±5 (refer to the original ID bit data), the second tolerance range is ±8, and the third tolerance range is ±10.

[0056] In one embodiment of the present application, the data on the ID bit may include physical parameter data, so some data segments of the generated first ID bit data will include the encoded values ​​of the physical parameter data. Therefore, when the data needs to be updated, it only needs to be written or replaced with the first ID bit data in the storage module.

[0057] In another embodiment of the present application, the data on the ID bit may be stored separately from the physical parameter data. Therefore, when data update is required, the first ID bit data and the first detection data need to be written or replaced in the storage module at the same time.

[0058] In the embodiment of the present application, after adjusting and optimizing the reference data or the data on the ID bit, the self-detection process can be restarted.

[0059] In one embodiment of the present application, the self-detection process can be restarted after adjusting and optimizing the reference data, and the self-detection process can be directly ended after adjusting the data on the ID position, because the data on the ID position has been adjusted to the data for self-detection in the current environment, which is generally considered to be more accurate.

[0060] In the embodiment of the present application, if the authentication chip has multiple tolerance ranges, such as Figure 4 As shown, after step 312, it is possible to further compare whether the deviation data is within the second tolerance range (the second tolerance range is greater than the first tolerance range) to perform precise matching or adjustment, and the specific steps include the following aspects: If the deviation data generated by the comparison result is within the second tolerance range stored in the storage module, the number of detections N (N is an integer) under the current self-detection trigger signal is obtained again. If N≤1 (that is, it is the first detection in the current environment), the self-detection process is started again to detect the physical parameters of the authentication chip, and the fifth ID bit data is generated. The fifth ID bit data is compared to see if it is within the first tolerance range. If so, the self-detection process is terminated. If not, the adjustment of step S312 is performed.

[0061] In this process, if the second self-test result meets the first tolerance range requirement, it can be determined that the previous self-test did not meet the tolerance range due to a temporary environmental mutation, and the mutated environment has been restored in the next self-test.

[0062] If N>1 (that is, it is not the first detection in the current environment), the second ID bit data on the ID bit is adjusted to the ID bit data generated by the last detection, or the reference data is adjusted; the specific adjustment method is as described above.

[0063] In this process, it can be determined that the failure of the last self-test to meet the tolerance range is not caused by a temporary environmental mutation, or the mutated environment is not restored in the next self-test.

[0064] If the comparison result is not within the second tolerance range stored in the storage module, the second ID bit data on the ID bit is adjusted to the first ID bit data, or the reference data is adjusted. The specific adjustment method is as described above.

[0065] In this way, a characteristic identifier is generated for the analog value of the physical parameter of the authentication chip measured by the authentication chip in the on-site environment, or a characteristic identifier that conforms to the tolerance range of the analog value measured on-site is used as a unique identifier to supply the analog serial number of the authentication chip to the device, so as to identify the authentication chip on the host; this not only meets the host's requirements for identity authentication of the authentication chip, but also reduces the impact of the environment on the characteristic identifier.

[0066] The authentication chip provided in the present application also has the ability of autonomous learning and autonomous updating and adjustment (equipped with an AI module). After self-detection generates the first ID bit data of the authentication chip, it records the first environment information and the corresponding first ID bit data under the first environment, which is used to autonomously update and adjust the data on the ID bit in the subsequent first environment. It can skip the self-detection process and quickly respond to the host.

[0067] In an embodiment of the present application, the first environment information and the first ID bit data corresponding to the first environment are recorded for discrete data statistics, and the discrete data is fitted and analyzed to obtain a function model.

[0068] In the embodiments of the present application, the first environment is such as when the printing device has just been started or is in continuous printing operation, and therefore, in subsequent identical first environments, the previous detection data can be directly used.

[0069] In the embodiments of the present application, the ID bit described is an ID bit in a narrow sense, which is used to store ID bit data. In fact, the ID bit may also store physical parameter data, serial number data, scrambled data, etc.; wherein the physical parameter data is data such as electrical characteristics detected and written during manufacturing, and at least some data bits of the ID bit data correspond to the physical parameter data.

[0070] The present application also provides a self-detection circuit 100, such as Figure 5 As shown, the self-detection circuit 100 includes a physical information module 101 , a self-detection module 102 , an ID bit generation module 103 and a storage module 104 . The self-detection module 102 is connected to the physical information module 101 and the ID bit generation module 103 respectively, and the ID bit generation module 103 is also connected to the storage module 104 .

[0071] In the embodiment of the present application, the physical information module 101 is used to provide the physical parameters of the authentication chip, and the self-detection module 102 obtains the physical parameters of the physical information module 101 for detection.

[0072] In the embodiments of the present application, Figure 6 As shown, the self-detection module 102 includes a clock circuit 1021, an acquisition circuit 1022 and a detection circuit 1023. The clock circuit 1021 is used to trigger the self-detection function in response to a self-detection trigger signal. The clock circuit 1021 can trigger the self-detection function when it detects that the physical information module 101 is acquired by an external signal (host acquisition), and can also trigger the self-detection function when it detects that the authentication chip is powered on. The acquisition circuit 1022 is used to acquire physical parameters of the physical information module 101, and the detection circuit 1023 is used to generate detection information based on the physical parameters.

[0073] like Figure 7 As shown, the ID bit generation module 103 includes an algorithm circuit 1031 and a calibration circuit 1033. The algorithm circuit 1031 is used to generate the first ID bit data according to the detection information; the calibration circuit 1033 is used to confirm the calibration method according to the exceeded tolerance range.

[0074] like Figure 8 As shown, the storage module 104 includes an ID bit module 1043, which is used to store original second ID bit data (generated in the factory stage or generated and written in the previous process) or store first ID bit data generated by the ID bit generation module 103.

[0075] like Figure 8As shown, the storage module 104 further includes a configuration data module 1042 for storing configuration data.

[0076] In an embodiment of the present application, the storage module 104 also includes a deviation data module 1044, a reference data module 1045, a physical parameter data module (not shown) and an address pointer module 1041. The deviation data module 1044 is used to store deviation data, the reference data module 1045 is used to store reference data, the physical parameter data module is used to store physical parameter data, and the address pointer module 1041 is used to store address pointer data. The address pointer data points to the address information of the data on the ID bit module 1043, the physical parameter data, the reference data and the deviation data in the storage module, so as to facilitate the extraction and writing of the corresponding data of the storage module 104.

[0077] In the embodiment of the present application, the deviation data represents the tolerance range of the deviation between the detection data and the physical parameter data.

[0078] In one embodiment of the present application, the ID bit module 1043 includes a physical parameter data module, and some data bits of the ID bit data correspond to the physical parameter data.

[0079] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0080] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, so that the internal connection of two elements or the interaction relationship between two elements can be achieved. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0081] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An authentication chip, the authentication chip is used to be installed on a box body of a replaceable accessory, the replaceable accessory is used to be installed in a host, characterized in that: receiving a self-detection trigger signal, detecting a physical parameter of the authentication chip, and generating first detection data, wherein the physical parameter is an inherent attribute parameter of the authentication chip; Generate first ID bit data of the authentication chip according to the first detection data; Adjust the data on the storage module ID bit of the authentication chip according to the first ID bit data; Receive an authentication request sent by the host, and respond to the identity authentication of the host using the data on the ID bit adjusted according to the first ID bit data.

2. The authentication chip according to claim 1, characterized in that: Adjust the data on the storage module ID bit of the authentication chip according to the first ID bit data; include, If the ID bit of the storage module of the authentication chip does not contain the second ID bit data, writing the first ID bit data into the ID bit; If the ID bit of the authentication chip storage module contains the second ID bit data, it is determined whether to update the data on the ID bit according to a comparison result between the first detection data and the physical parameter data of the authentication chip storage module.

3. The authentication chip according to claim 2, characterized in that: The receiving self-detection trigger signal; include, A power-on signal of the authentication chip is received, or a signal of a printing device detecting the physical parameter of the authentication chip is received as the self-detection trigger signal.

4. The authentication chip according to claim 2 or 3, characterized in that: The step of generating the first ID bit data of the authentication chip according to the first detection data includes: The first ID bit data is generated according to the first detection data and the reference data stored in the storage module.

5. The authentication chip according to claim 4, characterized in that: The step of determining whether to update the data on the ID bit according to a comparison result between the first detection data and the physical parameter data of the authentication chip storage module; include, If the comparison result is within the first tolerance range stored in the storage module, the data on the ID bit is not updated; If the comparison result is not within the first tolerance range stored in the storage module, the data on the ID bit is updated, or the reference data is updated, or the physical parameters of the authentication chip are detected again.

6. The authentication chip according to claim 5, characterized in that: If the comparison result is not within the first tolerance range stored in the storage module, the data on the ID bit is updated, or the reference data is updated, or the physical parameters of the authentication chip are detected again; include, If the comparison result is within the second tolerance range stored in the storage module, then obtaining the number of detections N under the current self-detection trigger signal, and if N≤1, then detecting the physical parameters of the authentication chip again, and if N>1, adjusting the second ID bit data on the ID bit to the first ID bit data, or adjusting the reference data; If the comparison result is not within the second tolerance range stored in the storage module, adjusting the second ID bit data on the ID bit to the first ID bit data, or adjusting the reference data; Wherein, the first tolerance range is smaller than the second tolerance range.

7. The authentication chip according to claim 5, characterized in that: If the comparison result is not within the first tolerance range stored in the storage module, the data on the ID bit is updated, or the reference data is updated, or the physical parameters of the authentication chip are detected again; include, The corresponding data segment to be adjusted is located according to the address pointer data in the storage module to update and write the data on the ID bit or the reference data.

8. The authentication chip according to claim 7, characterized in that: generating the first ID bit data of the authentication chip according to the first detection data; and include, The first environment information of the first environment and the first ID bit data corresponding to the first environment are recorded, so as to autonomously update and adjust the data on the ID bit in the first environment that occurs subsequently.

9. A self-detection circuit, applied to an authentication chip, characterized in that: The self-detection circuit comprises a physical information module, a self-detection module, an ID bit generation module and a storage module, wherein the self-detection module is connected to the physical information module and the ID bit generation module respectively, and the ID bit generation module is also connected to the storage module; The physical information module is used to provide physical parameters of the authentication chip, where the physical parameters are inherent attribute parameters of the authentication chip; The self-detection module includes a clock circuit, an acquisition circuit and a detection circuit, wherein the clock circuit is used to trigger a self-detection function in response to a self-detection trigger signal, the acquisition circuit is used to acquire the physical parameters of the physical information module, and the detection circuit is used to generate detection information according to the physical parameters; The ID bit generation module includes an algorithm circuit, and the algorithm circuit is used to generate first ID bit data according to the detection information; The storage module includes an ID bit module, and the ID bit module is used to store the first ID bit data generated by the ID bit generation module; the first ID bit data is used to respond to the authentication request sent by the subsequent host.

10. The self-detection circuit according to claim 9, characterized in that: The storage module also includes a deviation data module, a reference data module, a physical parameter data module and an address pointer module. The deviation data module is used to store deviation data, the reference data module is used to store reference data, the physical parameter data module is used to store physical parameter data, and the physical parameter data is data corresponding to the ID bit data. The address pointer module is used to store address pointer data, and the address pointer data points to the address information of the data on the ID bit, the physical parameter data, the reference data and the deviation data in the storage module.

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