A method, device, electronic device and storage medium for emulating network on chip

Abstract

The embodiment of the present invention provides a simulation method, device, electronic device and storage medium of a network on chip, which relates to the field of network on chip technology. The method includes: obtaining network simulation structure parameters, task simulation allocation parameters and performance optimization conditions; obtaining the simulation task of the network on chip; obtaining the simulation scale of the network on chip; based on the solver of the satisfiability modulo theory model, obtaining the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, task simulation allocation parameters and performance optimization conditions are satisfied. On the one hand, the design difficulty of the network on chip can be reduced; on the other hand, the optimal node physical topology simulation result obtained by the solver of the satisfiability modulo theory model has high accuracy, has a strong reference significance for the design of the network on chip, is conducive to improving the design efficiency of the network on chip, and improves the design accuracy of the network on chip.

Description

Technical Field

[0001] The present invention relates to the technical field of network on chip, and in particular to a simulation method of a network on chip, a simulation device of a network on chip, an electronic device and a storage medium. Background Art

[0002] Network-on-Chip (NoC) is an interconnection architecture of System-on-Chip (SoC). It has broad application prospects due to its advantages such as higher bandwidth.

[0003] In the design of on-chip networks, a design method is usually provided first and then tested. The test is mainly used to verify what problems exist in the design method provided first, which is a post-hoc method.

[0004] However, the above-mentioned a posteriori method requires providing a design method in advance, which is not conducive to the design of the on-chip network, especially for the design of large-scale on-chip networks. Summary of the invention

[0005] In view of the above problems, an embodiment of the present invention is proposed to provide a method for simulating a network on chip that overcomes the above problems or at least partially solves the above problems, so as to reduce the difficulty of designing the network on chip.

[0006] In a first aspect, the present invention provides a method for simulating a network on chip, comprising:

[0007] Obtain network simulation structure parameters, task simulation allocation parameters and performance optimization conditions;

[0008] Acquire the simulation task of the network on chip and the simulation scale of the network on chip;

[0009] Based on the solver of the satisfiability modulo theory model, the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale is obtained when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied.

[0010] In a second aspect, the present invention provides a simulation device for a network on chip, comprising:

[0011] The first acquisition module is used to obtain network simulation structure parameters, task simulation allocation parameters and performance optimization conditions;

[0012] A second acquisition module, used to acquire the simulation task of the network on chip and the simulation scale of the network on chip;

[0013] The simulation module is used to obtain the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, which satisfies the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions based on the solver of the satisfiability module theory model.

[0014] In a third aspect, the present invention provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned on-chip network simulation method when executing the program.

[0015] In a fourth aspect, the present invention provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute the above-mentioned on-chip network simulation method.

[0016] In a fifth aspect, the present invention provides a computer program product, comprising instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute any one of the aforementioned on-chip network simulation methods.

[0017] The present invention includes the following advantages:

[0018] In the present application, a solver based on a satisfiability modulo theory model is used to obtain an optimal node physical topology simulation result corresponding to a simulation task under a simulation scale that satisfies network simulation structure parameters, task simulation allocation parameters and performance optimization conditions. The above-mentioned simulation scale, network simulation structure parameters, task simulation allocation parameters and performance optimization conditions are all basic restriction conditions for on-chip network design. On the one hand, the simulation result can be used as a reference for on-chip network design, and the prior information before on-chip network design is obtained, which can reduce the difficulty of on-chip network design; on the other hand, the optimal node physical topology simulation result obtained by the solver of the satisfiability modulo theory model has high accuracy, has a strong reference significance for the design of on-chip network, is conducive to improving the design efficiency of on-chip network, and improves the design accuracy of on-chip network. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0020] Figures 1 to 3 It is a flowchart of the steps of three on-chip network simulation method embodiments provided by the embodiments of the present invention;

[0021] Figure 4A structural block diagram showing an embodiment of a simulation device for a network on chip of the present invention is shown;

[0022] Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] One of the core concepts of the embodiments of the present invention is that, based on the solver of the satisfiability modulo theoretical model, the application obtains the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, which satisfies the network simulation structure parameters, task simulation allocation parameters and performance optimization conditions. The above-mentioned simulation scale, network simulation structure parameters, task simulation allocation parameters and performance optimization conditions are all basic restriction conditions for on-chip network design. On the one hand, the simulation result can be used as a reference for on-chip network design, and the prior before on-chip network design is obtained, which can reduce the difficulty of on-chip network design; on the other hand, the optimal node physical topology simulation result obtained by the solver of the satisfiability modulo theoretical model has high accuracy, has a strong reference significance for the design of the on-chip network, is conducive to improving the design efficiency of the on-chip network, and improves the design accuracy of the on-chip network.

[0025] The present application provides a method for simulating a network on a chip, referring to Figure 1 The simulation method of the network on chip may specifically include the following steps.

[0026] Step 101: Obtain network simulation structure parameters, task simulation allocation parameters and performance optimization conditions.

[0027] The network simulation structure parameters refer to the basic configuration parameters of the network on chip to be simulated, and the network simulation structure parameters are related to the structure of the network on chip to be simulated. For example, when the structure of the network on chip to be simulated is a mesh structure or a mesh network on chip, the network simulation structure parameters may include but are not limited to: the encoding of each direction, that is, the replacement method when replacing the direction with a number; the time delay of the data fragment (Flit) waiting in the input buffer; the time delay of the router (Router) in the input buffer; the required maximum task completion delay; the number of directions supported by the router; the number of input buffers in each direction of the router; the number of data fragments that can be in the output multiplexer (Output MUX) and arbiter (Arbiter) state at the same time in each direction of the router, that is, the depth of the output multiplexer and arbiter; the number of data fragments that can be output simultaneously in each direction of the router; the number of ports (Port) supported by a router; routing strategy, the routing strategy includes XY routing strategy and XY&YX routing strategy. The XY routing strategy is a deterministic routing strategy in which data packets move in a network in a certain dimensional order. Specifically, the data packet first moves along the X dimension (horizontal direction) until it reaches the same X coordinate position as the destination node; then, the data packet moves along the Y dimension (vertical direction) until it reaches the destination node. The XY&YX routing strategy is that the order in which the data packet moves in the X and Y dimensions is not fixed, but can be selected according to actual conditions. Specifically, the data packet can choose to move along the X dimension first and then along the Y dimension (XY routing), or it can choose to move along the Y dimension first and then along the X dimension (YX routing).

[0028] The task simulation allocation parameters are used to specify the allocation method of the simulation tasks on the on-chip network, etc. For example, the task simulation allocation parameters may include: setting whether to use random tasks and random subtasks. If it is true, the subtask or task is placed at the physical location of the on-chip network to add to the target to be solved. If it is false, the subtask or task set manually is read and placed at the physical location of the on-chip network.

[0029] The performance optimization condition refers to the degree to which the simulation can be terminated, which can be considered as the end condition of the simulation. For example, the performance optimization condition can mean optimizing only the critical path, which is a kind of local performance optimization condition, meaning that the optimal total delay (the sum of the time that all data fragments stay in this on-chip network, which is a kind of global optimality) is not adopted, but the optimal each delay (the optimal time for each data fragment on the chip) is adopted.

[0030] The network simulation structure parameters, task simulation allocation parameters and performance optimization conditions can be set in a configuration file, and the network simulation structure parameters, task simulation allocation parameters and performance optimization conditions can be obtained from the configuration file.

[0031] Step 102: Acquire the simulation task of the network on chip and the simulation scale of the network on chip.

[0032] The simulation task of the network on chip refers to the task that needs to be simulated. The number of the simulation tasks can be one or more, and there is no specific limitation on this.

[0033] The simulation scale of the NOC is used to characterize the scale of the NOC to be simulated, and there is no limitation on the scale of the simulation scale of the NOC. For example, when the structure of the NOC to be simulated is a grid structure, the simulation scale of the NOC may be 2×2.

[0034] It should be noted that the above steps 101 to 102 can be combined into one step, and there is no specific limitation on this. At the same time, the execution order of the above steps 101 to 102 is also not specifically limited. For example, step 102 can be executed first and then step 101, or step 101 and step 102 can be executed at the same time.

[0035] Step 103, based on the solver of the satisfiability modulo theory model, obtain the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied.

[0036] It can be a language corresponding to the solver of the above-mentioned simulation task, simulation scale, network simulation structure parameters, task simulation allocation parameters and performance optimization conditions translated into the model of satisfiability modulo theory. Satisfiability modulo theory is to determine the satisfiability problem of first-order logic formulas under the combinatorial background theory. It can logically prove the appropriate on-chip network design method before encountering the problem, by helping to find the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions, and taking into account the delay of the router and the functional node time in the modeling, and then giving certain opinions or suggestions on the design of the on-chip network. Compared with the current single-step simulation, the simulation method provided by the present application can give the optimal node physical topology simulation result from a more comprehensive perspective, and the auxiliary effect on the design of the on-chip network is stronger and more accurate. In addition, compared with the existing simulation that can only perform specific scenarios, the simulation method provided by the present application is for the optimization of the lack of conditions and the optimization of logical expression, and has stronger applicability or versatility.

[0037] This application provides another on-chip network simulation method, referring to Figure 2The simulation method of the network on chip may specifically include the following steps.

[0038] Step 201: Obtain network simulation structure parameters, task simulation allocation parameters and performance optimization conditions.

[0039] Step 202: obtaining a simulation task of the network on chip and a simulation scale of the network on chip;

[0040] Here, steps 201 to 202 may refer to the related records of the aforementioned steps 101 to 102, and will not be described again here to avoid repetition.

[0041] Step 203, under the principle of prohibiting message overlap and back pressure, based on the solver of the satisfiability modulus theory model, obtains the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

[0042] Message overlap refers to the situation in which two or more messages overlap on the transmission path, processing node or storage resource in the on-chip network, resulting in data conflict or resource contention. Message overlap usually leads to data errors, transmission delays or resource conflicts. Message overlap can include: time overlap and space overlap. Time overlap refers to multiple messages trying to access the same resource (such as processing node, cache or bus) in the same time period. Space overlap refers to the overlap of multiple messages on the transmission path, such as using the same physical link or channel. Prohibiting message overlap means that only one message can be sent on the node with the same coordinate at the same time, and other messages need to wait. By prohibiting message overlap, problems such as time delay and resource conflict caused by message overlap can be avoided, thereby improving the accuracy of the obtained simulation results.

[0043] Back pressure is a dynamic feedback mechanism that allows the receiver to send a signal to the sender to inform it of its current processing capacity and buffer status, thereby adjusting the sending rate to avoid message overlap and data loss. In this application, back pressure is used to avoid message overlap and data loss, which can also improve the accuracy of the simulation results.

[0044] In this application, by prohibiting message overlap and back pressure, a formal model for on-chip network systems of any scale under any specific task is constructed, and the optimization solution of the physical topology (node ​​placement) can be achieved, and finally the theoretical performance limit under the current limitations can be calculated.

[0045] The present application provides another method for simulating a network on a chip, referring to Figure 3 The simulation method of the network on chip may specifically include the following steps.

[0046] Step 301: Obtain network simulation structure parameters, task simulation allocation parameters and performance optimization conditions.

[0047] Step 302: obtaining a simulation task of the network on chip and a simulation scale of the network on chip;

[0048] Here, steps 301 to 302 may refer to the related records of the aforementioned steps 101 to 102, and will not be described again here to avoid repetition.

[0049] Step 303, the simulation task includes: a number of simulation subtasks, and dependencies between the simulation subtasks; the solver of the satisfiability module theory model constructs all possible node physical topologies corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions, according to the dependencies between the simulation subtasks.

[0050] A simulation subtask refers to multiple subtasks obtained by decomposing a simulation task. There is usually a dependency relationship between simulation subtasks. The dependency relationship here means that the execution of a simulation subtask depends on the execution results of one or more other simulation subtasks. For example, taking the non-listening direct memory transfer read transaction in the CHI (Coherent Hub Interface) protocol as an example, it takes a certain amount of time for RN-F (Full-Function Request Node) to be static and send out a Read request. This operation is named task0. After HN-F (Home Node-Full) receives a ReadShared request, it takes a certain amount of processing time to send a request to SN-F (Slave). Node-Full, full-function slave node) sends ReadNoSnp (read without listening), and this operation is named task1. After receiving the ReadNoSnp request, SN-F needs a certain amount of processing time to send out CompData_UC (completion data_uncached), and this operation is named task2. Similarly, RN-F performs task3 after receiving CompData_UC, and then returns CompAck (completion confirmation) to HN-F, and then executes the final task4 on HN-F, ending the entire transaction flow. From the above process, it can be deduced that the execution of task1 depends on the execution result of task0, the execution of task2 depends on the execution result of task1, the execution of task3 depends on the execution result of task2, and the execution of task4 depends on the execution result of task3. In addition, these dependent tasks need to be started after the dependent tasks are completed. That is, for a task, its start execution time needs to be greater than or equal to the completion time of the task it depends on. A simulation logic in this application can be a task whose start execution time is equal to the completion time of the task it depends on. In a more complex transaction, for example, Read transaction with snoop response with partial data and nomemory update (partial data read transaction with snoop response and no memory update), Mergedata occurs on HN-F, which is a task that depends on two predecessor tasks at the same time.

[0051] By simulating the dependencies between subtasks, the relative physical positions of the nodes that execute the above simulation subtasks can be roughly determined. Then, under the simulation scale, all possible node physical topologies corresponding to the simulation task that meet the relative physical positions of the nodes of the above simulation subtasks are created, and the above network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are met. The physical topologies of all possible nodes are the subsequent traversal space. That is to say, the satisfiability modulo theory model can support any number of dependent tasks and any depth of task dependency, and can perfectly simulate more complex situations. By simulating the dependencies between subtasks, the satisfiability modulo theory model simulates the time delay caused by the devices mounted on the NoC when executing tasks or subtasks and the mutual dependencies between different tasks or subtasks in different devices / on the same device.

[0052] Optionally, the simulation task in the aforementioned step 303 also includes: edges, where the edges represent the connection between nodes, and each edge has a unique index, which is used to identify its position and direction (horizontal or vertical) in the mesh-type on-chip network. Before the aforementioned step 303, the method may also include: for each edge, determining the number of routers corresponding to the edge according to the physical distance of the edge, and determining the position order of each router corresponding to the edge; using the edge and the position order of each router corresponding to the edge as an index, writing constraints. The router is located at the intersection of each node and is responsible for forwarding data packets. Each router also has a unique index, usually based on its position in the grid. For each edge, determining the position order of each router corresponding to the edge is mainly based on the aforementioned routing strategy, and the horizontal and vertical coordinates of the intermediate node router, the time when the data packet enters the intermediate node router, and the time when the data packet is sent out from the intermediate node router, and the forward direction of the data packet after being sent out from the intermediate node router can also be calculated according to the routing strategy. The aforementioned constraints may include: each edge must connect two routers, router location uniqueness, etc. Here, for the mesh-type on-chip network, a set of state machines is created independently for each data packet with the transmitted data packet as the index. The solver then calculates the delay and other parameters of the data packet in the router based on the time overlap between the data packet and other data packets in the same router or input buffer. This constraint helps to ensure the optimization of network performance, reliability and resource utilization.

[0053] The aforementioned step 303 may include: the solver of the satisfiability modulo theory model, under the constraints of the aforementioned constraints, based on the dependencies between the simulation subtasks, constructs all possible node physical topologies corresponding to the simulation task under the simulation scale, under the condition that the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied. Due to the addition of the constraint, all possible node physical topologies obtained help to ensure further optimization of the performance, reliability and resource utilization of the network, and the subsequent simulation results may be more optimized and more accurate. Moreover, compared to establishing a complete set of router grids for each cycle, the method of the present application can greatly optimize the solution space and the difficulty of solution.

[0054] Step 304, the solver of the satisfiability modulo theory model traverses all the possible node physical topologies, and determines the possible physical topology with the shortest time among all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale that satisfies the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

[0055] The time consumption here may include: the time consumption for transmission on the line, and the time consumption for executing the simulation task or simulation subtask in the node. The solver of the satisfiability modulo theory model will traverse all the possible node physical topologies mentioned above, and determine the possible physical topology with the shortest time consumption among all node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions. The optimal node physical topology simulation result matches the simulation scale, the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions as well as the simulation task, and the simulation result achieves the optimal time consumption, which has a strong reference and guiding significance for designing similar on-chip networks.

[0056] Optionally, the aforementioned performance optimization conditions include: global performance optimization conditions or local performance optimization conditions. The global performance optimization conditions may refer to: the shortest time required to complete all simulation tasks and all simulation subtasks. The local performance optimization conditions may refer to: the shortest time required to complete some simulation tasks or some simulation subtasks. Here, some simulation tasks or some simulation subtasks may represent critical paths and have high representativeness. In the case of the aforementioned optimization conditions, the aforementioned step 304 may include: step 3041 and step 3042.

[0057] Step 3041, when the performance optimization condition includes: a global performance optimization condition, the solver of the satisfiability modulo theory model traverses all the possible node physical topologies, and determines the possible physical topology that takes the shortest time to complete the simulation task in all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the simulation task satisfies the network simulation structure parameters, the task simulation allocation parameters and the performance optimization condition. Specifically, since the performance optimization condition includes the global performance optimization condition, it is to find the possible physical topology that takes the shortest time to complete all simulation tasks in all possible node physical topologies. The simulation result is the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization condition are satisfied. The simulation result has a strong reference and auxiliary role in the global optimization of on-chip network design.

[0058] Step 3042: When the performance optimization condition includes the local performance optimization condition, the solver of the satisfiability modulo theory model traverses all the possible node physical topologies, and determines the possible physical topology with the shortest execution time of the key path in the local performance optimization condition in all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization condition are satisfied. The key path in the local performance optimization condition refers to the transmission path in part of the simulation task or part of the simulation subtask. Since the performance optimization condition includes the local performance optimization condition, it is to find the possible physical topology with the shortest execution time of the key path in all possible node physical topologies. The simulation result is the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization condition are satisfied. The simulation result has a strong reference and auxiliary role for the on-chip network design of local optimization.

[0059] Optionally, the aforementioned task simulation allocation parameters are used to specify the distribution method of simulation tasks on the on-chip network, etc. For example, the task simulation allocation parameters may include: allocating a target node at a fixed physical position for part of the simulation tasks and / or part of the simulation subtasks, placing the remaining simulation tasks and remaining simulation subtasks in the physical position of the on-chip network to add to the target to be solved, and allocating the set part of the simulation tasks and / or part of the simulation subtasks to the target node at a fixed physical position. Then, each possible node physical topology corresponding to the simulation task in the aforementioned steps contains the target node at a fixed physical position corresponding to the set part of the simulation tasks and / or part of the simulation subtasks. The flexibility of the simulation is increased here, and the applicability of the present application is broadened.

[0060] More specifically, in the actual NoC implementation, the port on which the device is mounted on which router may have a very large impact on the overall NoC transmission time delay, so the present application can calculate the overall time delay of the task or transaction on any given spatial planning. Task simulation allocation parameters may include: in the case of allocating a target node with a fixed physical position for some simulation tasks and / or some simulation subtasks, it is not only necessary to give a simulation task and the dependencies between the various simulation subtasks in the simulation task, but also to allocate three parameters for some simulation tasks and / or some simulation subtasks: 1. The horizontal coordinate of the mounted router. 2. The vertical coordinate of the mounted router. 3. On which port of the router it is mounted, the above three parameters can characterize the target node with a fixed physical position. In this case, it is to optimize the physical position of the node corresponding to the remaining simulation tasks and simulation subtasks under the known conditions. Task simulation allocation parameters may include: random allocation. In this case, it is not necessary to set the horizontal and vertical coordinates of the mounted router and the number of the mounted port for any simulation task or any simulation subtask.

[0061] Optionally, the solver of the satisfiability modulo theory model mentioned in the present application may include: a Z3 solver of the satisfiability modulo theory model, where Z3 is a solver serving the SMT theory, which has fast and accurate effects and can improve the accuracy and efficiency of simulation.

[0062] Normally, the solver of the satisfiability modulo theory model can be used to call the central processing unit (CPU) to obtain simulation results. Optionally, the solver of the satisfiability modulo theory model can call an accelerator for simulation. The accelerator here is good at parallel computing, faster calculation speed, faster solution speed or faster simulation speed. There is no limitation on the type of the accelerator. For example, the accelerator can be a GPU (Graphics Processing Unit).

[0063] Optionally, the accelerator has a built-in memory; the solver of the satisfiability modulo theory model can call the accelerator and the memory of the accelerator for simulation to obtain the true result. Specifically, usually, both the accelerator and the CPU perform simulation by interacting with the memory. When the accelerator has a built-in memory, the simulation speed is faster by interacting with the accelerator's own memory. For example, the GPU usually has a built-in memory, and the solver of the satisfiability modulo theory model can call the GPU and the built-in memory of the accelerator for simulation to speed up the simulation speed.

[0064] Optionally, the simulation method of the on-chip network may also include: converting the execution process of the aforementioned solver into an image file, which may be in a picture format or a video, animation format, etc., without specific limitation, thereby realizing visualization of the execution process or the solution process, and having a good auxiliary effect on interpreting or applying the simulation results.

[0065] Specifically, the configuration file can be configured to configure the file name of the output image file, which can be used to store detailed data during the simulation process, such as the delay and path information of each simulation task or simulation subtask; the resolution or image quality of the image file can also be configured in the configuration file; the drawing time of the image file can also be configured in the configuration file, for example, drawing the image file before the end of the simulation or drawing the image file after the end of the simulation; when the image file contains animation or video, the playback time of the video or animation can also be configured in the configuration file to control the playback speed or duration of the video or animation. More specifically, the solver can output a text file, and the required information can be extracted from the text file, and then the text information can be converted into a picture. For videos or animations, multiple pictures can be combined into a video or animation.

[0066] Optionally, the simulation method of the network on chip may further include: outputting the time consumption of the optimal node physical topology simulation result, etc., so as to facilitate the time consumption reference of the network on chip designer. The output may be directly in text form or in the aforementioned image file, etc., and there is no specific limitation on this.

[0067] To sum up, the on-chip network simulation method provided by the present application can support any number of dependent tasks, subtasks and any depth of task and subtask dependencies, and can perform simulations for situations of any scale and complexity. It has a wide range of applications, fast simulation speed, more accurate simulation results, and greater contribution or assistance to the design of on-chip networks.

[0068] The present application also provides a training method for a satisfiability modulo theory model and its solver, which may include: obtaining training samples, which may include: network simulation structure parameter samples, task simulation allocation parameter samples, performance optimization condition samples, simulation task samples, and optimal node physical topology simulation result samples corresponding to the network simulation structure parameter samples, task simulation allocation parameter samples and performance optimization condition samples under the aforementioned simulation scale samples; after labeling multiple of the above training samples, input them into the satisfiability modulo theory model and its solver for learning and training to obtain the satisfiability modulo theory model and its solver in the present application, and no specific limitation is made on the specific training method.

[0069] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0070] Reference Figure 4 , Figure 4 A structural block diagram of an embodiment of a simulation device for a network on chip of the present invention is shown. The simulation device for the network on chip may specifically include the following modules: a first acquisition module 401, used to acquire network simulation structure parameters, task simulation allocation parameters and performance optimization conditions; a second acquisition module 402, used to acquire the simulation task of the network on chip and the simulation scale of the network on chip; a simulation module 403, used to obtain the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied, based on a solver of the satisfiability module theory model.

[0071] Optionally, the simulation module includes: a first simulation sub-module, which is used to obtain the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, while satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions, based on a solver of the satisfiability module theory model under the principle of prohibiting message overlap and back pressure.

[0072] Optionally, the simulation task includes: a number of simulation sub-tasks, and dependencies between the simulation sub-tasks; the simulation module includes: a physical topology establishment sub-module, which is used for the solver of the satisfiability modulo theoretical model to construct all possible node physical topologies corresponding to the simulation task under the simulation scale, according to the dependencies between the simulation sub-tasks, while satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions; a second simulation sub-module, which is used for the solver of the satisfiability modulo theoretical model to traverse all the possible node physical topologies, and determine the possible physical topology with the shortest time among all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, while satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

[0073] Optionally, the performance optimization conditions include: global performance optimization conditions or local performance optimization conditions; the second simulation submodule includes: a first simulation unit, used for, when the performance optimization conditions include: when the performance optimization conditions include: the global performance optimization conditions, the solver of the satisfiability modulo theoretical model traverses all the possible node physical topologies, and determines the possible physical topology with the shortest time to complete the execution of the simulation task among all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale that satisfies the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions; a second simulation unit, used for, when the performance optimization conditions include: the local performance optimization conditions, the solver of the satisfiability modulo theoretical model traverses all the possible node physical topologies, and determines the possible physical topology with the shortest time to complete the execution of the critical path in the local performance optimization conditions among all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale that satisfies the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

[0074] Optionally, the simulation task also includes: edges; the network simulation structure parameters include: a grid-type on-chip network; the simulation device of the on-chip network also includes: a determination module, used to determine, for each of the edges, the number of routers corresponding to the edge according to the physical distance of the edge, and determine the position order of each of the routers corresponding to the edge; a constraint writing module, used to write constraints with the edge and the position order of each of the routers corresponding to the edge as index; the physical topology establishment submodule includes: a physical topology establishment unit, which is used for the solver of the satisfiability module theory model, and under the constraints of the constraints, according to the dependencies between the simulation subtasks, constructs all possible node physical topologies corresponding to the simulation task under the simulation scale, while satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

[0075] Optionally, the task simulation allocation parameters include: allocating target nodes with fixed physical locations to part of the simulation tasks and / or part of the simulation subtasks;

[0076] Each of the possible node physical topologies corresponding to the simulation task includes: the target node corresponding to the part of the task and / or the part of the simulation subtask.

[0077] Optionally, the simulation module includes: a third simulation sub-module, which is a solver for the satisfiability module theory model, calling an accelerator to perform simulation, and obtaining the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

[0078] Optionally, the accelerator has a built-in memory; the third simulation sub-module includes: a third simulation unit, which is a solver for the satisfiability module theory model, calling the accelerator and the memory of the accelerator to perform simulation, and obtaining the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

[0079] Optionally, the on-chip network simulation device further includes: a conversion module, used to convert the execution process of the solver into an image file.

[0080] Optionally, the solver of the satisfiability modulo theory model includes: a Z3 solver of the satisfiability modulo theory model.

[0081] It should be noted that the relevant parts of the on-chip network simulation method and the on-chip network simulation device in the present application can be referenced to each other and have the same or similar beneficial effects. In order to avoid repetition, the relevant parts are abbreviated.

[0082] Figure 5 is a structural diagram of an electronic device provided by an embodiment of the present invention. Figure 5 The present invention also provides an electronic device, see Figure 5 , including: a processor 501, a memory 502, and a computer program 5021 stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of each embodiment of the above-mentioned on-chip network simulation method are implemented.

[0083] The present invention also provides a readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the steps of each embodiment of the above-mentioned on-chip network simulation method.

[0084] The present invention also provides a computer program product, comprising instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute the steps of any one of the aforementioned embodiments of the on-chip network simulation method.

[0085] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0086] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0087] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data transmission terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data transmission terminal device generate instructions for implementing the process in the flowchart. Figure 1A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0088] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data transmission terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0089] These computer program instructions can also be loaded onto a computer or other programmable data transmission terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0090] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0091] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0092] The above is a detailed introduction to a simulation method and device for an on-chip network, an electronic device and a storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a general technician in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for simulating a network on chip, characterized in that: include: Obtain network simulation structure parameters, task simulation allocation parameters and performance optimization conditions; The network simulation structure parameters refer to basic configuration parameters of the on-chip network to be simulated, and the network simulation structure parameters are related to the structure of the on-chip network to be simulated; The task simulation allocation parameter is used to specify the allocation method of the simulation task on the chip network, including: setting whether to use random tasks, if true, the simulation task is placed at the physical location of the chip network to add to the target to be solved, if false, the artificially set simulation task is read and placed at the physical location of the chip network; Acquire the simulation task of the network on chip and the simulation scale of the network on chip; Based on the solver of the satisfiability modulo theory model, the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale is obtained when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied.

2. The method for simulating a network on chip according to claim 1, characterized in that: The solver based on the satisfiability modulo theory model obtains the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied, including: Under the principle of prohibiting message overlap and back pressure, a solver based on the satisfiability modulus theory model is used to obtain the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

3. The method for simulating a network on chip according to claim 1 or 2, characterized in that: The simulation task includes: a plurality of simulation subtasks, and dependencies between the simulation subtasks; the solver based on the satisfiability modulus theory model obtains the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied, including: The solver of the satisfiability modulo theory model is constructed according to the dependency relationship between the simulation subtasks, under the simulation scale, and under the condition that the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied, and all possible node physical topologies corresponding to the simulation tasks are obtained; The solver of the satisfiability modulo theory model traverses all the possible node physical topologies, and determines the possible physical topology with the shortest time among all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, which satisfies the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

4. The method for simulating a network on chip according to claim 3, characterized in that: The performance optimization condition includes: a global performance optimization condition or a local performance optimization condition; the solver of the satisfiability modulus theory model traverses all the possible node physical topologies, and determines the possible physical topology with the shortest time consumption among all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization condition are satisfied, including: In the case where the performance optimization condition includes: the global performance optimization condition, the solver of the satisfiability modulo theory model traverses all the possible node physical topologies, and determines the possible physical topology that takes the shortest time to complete the simulation task among all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization condition are satisfied; When the performance optimization condition includes: the local performance optimization condition, the solver of the satisfiability modulo theory model traverses all the possible node physical topologies, and determines the possible physical topology with the shortest time to complete the execution of the critical path in the local performance optimization condition among all the possible node physical topologies as the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale that satisfies the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

5. The method for simulating a network on chip according to claim 3, characterized in that: The simulation task further includes: edges; the network simulation structure parameters include: a mesh-type on-chip network; the solver of the satisfiability module theory model is constructed according to the dependencies between the simulation subtasks, under the simulation scale, under the condition that the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied, before all possible node physical topologies corresponding to the simulation task, the method further includes: For each of the edges, determine the number of routers corresponding to the edge according to the physical distance of the edge, and determine the position order of each of the routers corresponding to the edge; Using the edge and the position order of each router corresponding to the edge as an index, compile a constraint condition; The solver of the satisfiability modulo theory model is constructed according to the dependencies between the simulation subtasks, under the simulation scale, and under the condition that the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied, and all possible node physical topologies corresponding to the simulation tasks include: The solver of the satisfiability modulo theory model, under the constraints of the constraints, constructs all possible node physical topologies corresponding to the simulation tasks under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions according to the dependencies between the simulation subtasks.

6. The method for simulating a network on chip according to claim 3, characterized in that: The task simulation allocation parameters include: allocating target nodes with fixed physical locations to part of the simulation tasks and / or part of the simulation subtasks; Each of the possible node physical topologies corresponding to the simulation task includes: the target node corresponding to the part of the simulation task and / or the part of the simulation subtask.

7. The method for simulating a network on chip according to claim 1 or 2, characterized in that: The solver based on the satisfiability modulo theory model obtains the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied, including: The solver of the satisfiability modulus theory model calls the accelerator to perform simulation to obtain the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

8. The method for simulating a network on chip according to claim 7, characterized in that: The accelerator has a built-in memory; the solver of the satisfiability modulus theory model calls the accelerator to perform simulation, and obtains the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, when the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions are satisfied, including: The solver of the satisfiability modulus theory model calls the accelerator and the memory of the accelerator to perform simulation, and obtains the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, satisfying the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions.

9. The method for simulating a network on chip according to claim 1 or 2, characterized in that: Also includes: The execution process of the solver is converted into an image file.

10. The method for simulating a network on chip according to claim 1 or 2, characterized in that: The solver of the satisfiability modulo theoretical model includes: a Z3 solver of the satisfiability modulo theoretical model.

11. A simulation device for a network on chip, characterized in that: include: The first acquisition module is used to obtain network simulation structure parameters, task simulation allocation parameters and performance optimization conditions; The network simulation structure parameters refer to basic configuration parameters of the on-chip network to be simulated, and the network simulation structure parameters are related to the structure of the on-chip network to be simulated; The task simulation allocation parameter is used to specify the allocation method of the simulation task on the chip network, including: setting whether to use random tasks, if true, the simulation task is placed at the physical location of the chip network to add to the target to be solved, if false, the artificially set simulation task is read and placed at the physical location of the chip network; A second acquisition module, used to acquire the simulation task of the network on chip and the simulation scale of the network on chip; The simulation module is used to obtain the optimal node physical topology simulation result corresponding to the simulation task under the simulation scale, which satisfies the network simulation structure parameters, the task simulation allocation parameters and the performance optimization conditions based on the solver of the satisfiability module theory model.

12. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the simulation method of the network on chip as claimed in any one of claims 1 to 10 when executing the program.

13. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the on-chip network simulation method according to any one of claims 1 to 10.

14. A computer program product, characterized in that The invention comprises instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute the on-chip network simulation method according to any one of claims 1 to 10.

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