Pixel control circuit, method and display panel

Abstract

This application belongs to the field of display panel technology, and provides a pixel control circuit, method, and display panel. The display panel includes multiple pixel units, each pixel unit including a first sub-pixel unit and a second sub-pixel unit. The pixel control circuit includes a first control module, a second control module, and a third control module. The third control module is used to connect the corresponding second sub-pixel unit to the circuit under a specified state, so that the second sub-pixel unit is controlled by a line scan signal and / or a data signal to be in an active state. The specified state includes at least one of a first sub-pixel unit malfunction and jagged edges appearing on the display screen. This application can connect the second sub-pixel unit when the first sub-pixel unit malfunctions, eliminating the bright cross-shaped line phenomenon. Furthermore, when jagged edges appear on the display screen, connecting the second sub-pixel unit can also provide a smooth transition to the jagged state, reducing the jaggedness.

Description

Technical Field

[0001] This application belongs to the field of display panel technology, and particularly relates to a pixel control circuit, method and display panel. Background Technology

[0002] Miniature Light Emitting Diode (Mini LED) backlighting uses Mini LEDs as the backlight source for Liquid Crystal Display (LCD) panels, giving them advantages such as ultra-high contrast, wide color gamut, and high-dynamic range (HDR), thus significantly improving display performance. Compared to traditional backlighting, Mini LED backlighting achieves better brightness uniformity within a smaller mixing distance, and due to its local dimming design, it has more refined HDR zones and significantly improves the contrast of LCD displays. However, due to the characteristics of Mini LEDs, when a Mini LED chip experiences an open circuit, a cross-shaped bright line phenomenon will appear, affecting the product's display effect. Summary of the Invention

[0003] In view of this, embodiments of this application provide a pixel control circuit, method, and display panel to solve the problem that when MiniLED lamp beads have an open circuit, a cross-shaped bright line phenomenon will appear, affecting the product display effect.

[0004] The first aspect of this application provides a pixel control circuit for a display panel. The display panel includes a plurality of pixel units, which are arranged in an array in the form of n rows and m columns. Each pixel unit includes a first sub-pixel unit and a second sub-pixel unit. The pixel control circuit includes a first control module, a second control module, a third control module, n row signal lines, and m column signal lines.

[0005] The first control module is connected to the row signal line, the second control module is connected to the column signal line, and the pixel unit in the i-th row and j-th column is connected to the i-th row signal line and the j-th column signal line respectively.

[0006] The first control module is used to output a row scan signal to the row signal line;

[0007] The second control module is used to output data signals to the column signal lines;

[0008] The first sub-pixel unit is controlled by the row scan signal and / or the data signal to be in an active or inactive state;

[0009] The third control module is used to connect the corresponding second sub-pixel unit to the circuit under a specified state, so that the second sub-pixel unit is controlled by the row scanning signal and / or the data signal to be in an active state;

[0010] The specified state includes at least one of the following: a first sub-pixel unit failure and a jagged edge on the display screen; i is an integer, and i∈[1,n]; j is an integer, and j∈[1,m].

[0011] A second aspect of this application provides a pixel control method, applied to the pixel control circuit of the display panel provided in the first aspect of this application, comprising:

[0012] Determine the working status of the display panel;

[0013] If the working state is a specified state, the corresponding second sub-pixel unit is connected to the circuit so that the second sub-pixel unit is controlled by the row scan signal and / or the data signal and is in an active state.

[0014] A third aspect of this application provides a display panel including a pixel control circuit of the display panel provided in the first aspect of this application. The pixel control circuit includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the pixel control method provided in the second aspect of this application.

[0015] A first aspect of this application provides a pixel control circuit for a display panel. The display panel includes multiple pixel units arranged in an array of n rows and m columns. Each pixel unit includes a first sub-pixel unit and a second sub-pixel unit. The pixel control circuit includes a first control module, a second control module, a third control module, n row signal lines, and m column signal lines. The first control module is connected to the row signal lines, and the second control module is connected to the column signal lines. The pixel unit in the i-th row and j-th column is connected to the i-th row signal line and the j-th column signal line, respectively. The first control module is used to control the row signal lines and the column signal lines. The signal line outputs a row scan signal; the second control module outputs a data signal to the column signal line; the first sub-pixel unit is controlled by the row scan signal and / or the data signal to be in an active or inactive state; the third control module is used to connect the corresponding second sub-pixel unit to the circuit under a specified state, so that the second sub-pixel unit is controlled by the row scan signal and / or the data signal to be in an active state; wherein, the specified state includes at least one of the first sub-pixel unit failure and the appearance of jagged edges on the display screen; i is an integer, and i∈[1,n]; j is an integer, and j∈[1,m]. This application can connect the second sub-pixel unit when the first sub-pixel unit fails, eliminating the bright cross line phenomenon. In addition, when jagged edges appear on the display screen, connecting the second sub-pixel unit can also provide a smooth transition to the jagged state and reduce the jagged edge phenomenon.

[0016] It is understandable that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect above, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a pixel control circuit provided in one embodiment of this application;

[0019] Figure 2 This is a schematic diagram of a pixel control circuit provided in another embodiment of this application;

[0020] Figure 3 This is a schematic diagram of a pixel control circuit provided in another embodiment of this application;

[0021] Figure 4This is a schematic diagram of a pixel control circuit provided in another embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the pixel unit distribution of a pixel control circuit provided in an embodiment of this application;

[0023] Figure 6 This is a schematic flowchart of a pixel control method provided in an embodiment of this application;

[0024] Figure 7 This is a schematic flowchart of a pixel control method provided in another embodiment of this application;

[0025] Figure 8 This is a schematic diagram of a jagged screen provided in an embodiment of this application;

[0026] Figure 9 This is a schematic diagram of the pixel control circuit provided in one embodiment of this application.

[0027] In the picture:

[0028] 1 - Pixel unit, 11 - First sub-pixel unit, 12 - Second sub-pixel unit,

[0029] 2-Pixel control circuit, 21-First control module, 22-Second control module, 221-Second feedback signal processing module, 23-Third control module, 24-Column signal line, 25-Row signal line, 26-Switch module, 27-First feedback signal processing module. Detailed Implementation

[0030] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0031] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0032] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0033] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0034] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0036] Example 1

[0037] The pixel control circuit of the display panel provided in this application embodiment includes a display panel comprising multiple pixel units 1, which are arranged in an array of n rows and m columns. Each pixel unit 1 includes a first sub-pixel unit 11 and a second sub-pixel unit 12. The pixel control circuit includes a first control module 21, a second control module 22, a third control module 23, n row signal lines 25, and m column signal lines 24. The first control module 21 is connected to the row signal lines 25, and the second control module 22 is connected to the column signal lines 24. The pixel unit 1 in the i-th row and j-th column is connected to the i-th row signal line 25 and the j-th column signal line 24, respectively. The first control module 21... A first control module 1 is used to output a row scan signal to the row signal line 25; a second control module 22 is used to output a data signal to the column signal line 24; a first sub-pixel unit 11 is controlled by the row scan signal and / or the data signal to be in an active or inactive state; a third control module 23 is used to connect the corresponding second sub-pixel unit 12 to the circuit under a specified state, so that the second sub-pixel unit 12 is controlled by the row scan signal and / or the data signal to be in an active state; wherein, the specified state includes at least one of the first sub-pixel unit 11 malfunction and the appearance of jagged edges on the display screen; i is an integer, and i∈[1,n]; j is an integer, and j∈[1,m]. This application can connect the second sub-pixel unit 12 when the first sub-pixel unit 11 malfunctions, eliminating the bright cross line phenomenon. In addition, when jagged edges appear on the display screen, connecting the second sub-pixel unit 12 can also smooth the jagged state and reduce the jagged edge phenomenon.

[0038] In applications, the pixels of the display panel are designed with a special grid-like "island" structure. Pixel unit 1 is used in multi-color display panels and refers to any portion of the pixel that can be independently addressed to emit a specific color. For example, blue pixel unit 1 is the portion of the pixel that can be addressed to emit blue light. In full-color displays, pixels typically include three primary color pixel units 1, namely blue, green, and red. Alternatively, pixel unit 1 refers to an individual light-emitting element.

[0039] In the application, the row scan signal is used to select a row of pixels on the display panel, enabling it to receive data signals from column signal lines 24. When the row scan signal is activated, it turns on all pixels in a specific row, allowing these pixels to receive data voltages transmitted on the data lines. When the row scan signal is low, the corresponding pixel row is turned off and does not receive data voltages. The row scan signal is activated row by row in a certain periodic order, ensuring that each row of pixels has the opportunity to receive data voltages. For example, if the display panel has 10 rows of pixels, the row scan signal will activate row 1, row 2, ..., row 10 in sequence, and then cycle back to row 1.

[0040] In the application, the data signals output by column signal line 24 are used to control the brightness or color of each pixel. The data signals carry the brightness or color information that each pixel needs to display. When a pixel in a column is selected by the row scan signal, the data signal for that column will be loaded onto the pixel.

[0041] like Figure 1 and 2 As shown, the pixel control circuit of the display panel provided in this application embodiment includes a first control module 21, a second control module 22, a third control module 23, n row signal lines 25 and m column signal lines 24; the first control module 21 is connected to the row signal lines 25, the second control module 22 is connected to the column signal lines 24, and the pixel unit 1 in the i-th row and j-th column is connected to the i-th row signal line 25 and the j-th column signal line 24 respectively; the display panel includes a plurality of pixel units 1, the pixel units 1 are arranged in an array in the form of n rows and m columns, and the pixel unit 1 includes a first sub-pixel unit 11 and a second sub-pixel unit 12;

[0042] The first control module 21 is used to output a row scanning signal to the row signal line 25;

[0043] The second control module 22 is used to output data signals to the column signal line 24;

[0044] The first sub-pixel unit 11 is controlled by the row scan signal and / or data signal to be in an active or inactive state;

[0045] The third control module 23 is used to connect the corresponding second sub-pixel unit 12 to the circuit under a specified state, so that the second sub-pixel unit 12 is controlled by the row scanning signal and / or data signal to be in an active state.

[0046] The specified states include at least one of the following: a fault in the first sub-pixel unit 11 and a jagged edge in the displayed image; i is an integer and i∈[1,n]; j is an integer and j∈[1,m].

[0047] In application, the first control module 21 and the third control module 23 can be hardware modules that implement the above functions, or they can be virtual modules within an integrated circuit. The first control module 21 and the third control module 23 can be integrated into a scanning integrated circuit (Scan IC), and their functions are directly implemented by the scanning IC. Alternatively, the control lines of the first control module 21 and the third control module 23 can be routed along the left and right edges of the display panel. Simultaneously, the control signals are generated by other ICs such as the timing controller IC (Tcon IC) on the PCBA board, and connected to the in-plane gate drive line (GDL) area via the bypass pin of the driver IC, thus controlling the on / off state of the switch module 26. This application does not limit the specific form of the first control module 21 and the third control module 23; any hardware or software module that can implement the above functions can be applied to the embodiments of this application.

[0048] In this application, a 3x3 pixel unit 1 is used as an example to illustrate the scheme of this embodiment. The first control module 21 scans each row of pixel units 1 in the pixel array via row signal lines 25. Specifically, the first row signal line 25 is connected to all pixel units 1 in the first row, and outputs a row scan signal to all pixel units 1 in the first row. Similarly, the second row signal line 25 is connected to all pixel units 1 in the second row, and outputs a row scan signal to all pixel units 1 in the second row. The third row signal line 25 is connected to all pixel units 1 in the third row, and outputs a row scan signal to all pixel units 1 in the third row.

[0049] In the application, a second sub-pixel unit 12 is provided at each first sub-pixel unit 11. The cathodes of the first sub-pixel unit 11 and the second sub-pixel unit 12 are connected to the same column signal line 24, while the anode of the first sub-pixel unit 11 is connected to the row signal line 25 of the corresponding row. The anode of the second sub-pixel unit 12 is connected to the same row signal line 25 as the first sub-pixel unit 11, or connected to a third control module 23 via a switch module 26. The third control module 23 controls the switching module 26 to enable or disable the second sub-pixel unit 12.

[0050] In application, a fault in the first sub-pixel unit 11 includes an open circuit. Taking a row scan on-state voltage of 5V and an off-state voltage of 3V as an example, when the row scan signal is high, the data signal adjusts the display grayscale by controlling the low pulse duty cycle; the data signal is active low and at 0V. When the first sub-pixel unit 11 is on, the scan voltage of the row data lines is transmitted to the column data lines, making the low level of the data signal approximately 1V. If a first sub-pixel unit 11 is open, the low level of the data signal cannot be pulled high from 0V to approximately 1V through the open-circuited first sub-pixel unit 11, resulting in a slight conduction in the column containing the open-circuited first sub-pixel unit 11, thus causing a bright cross-shaped line phenomenon. When the first sub-pixel unit 11 is open, the third control module 23 connects the second sub-pixel unit 12 located at the open-circuited first sub-pixel unit 11 to the circuit. The low level of the data signal can then be pulled high from 0V to approximately 1V through the second sub-pixel unit 12, thus avoiding the bright cross-shaped line phenomenon.

[0051] In one embodiment, such as Figure 3 As shown, it also includes a first feedback signal processing module 27;

[0052] The j-th input terminal of the second control module 22 is connected to the j-th column signal line 24, the j-th output terminal of the second control module 22 is connected to the j-th input terminal of the first feedback signal processing module 27, and the j-th output terminal of the first feedback signal processing module 27 is connected to the j-th input terminal of the third control module 23.

[0053] The first feedback signal processing module 27 is used to determine the fault state of the first sub-pixel unit 11 based on the voltage of the acquired column signal line 24, locate the column coordinates of the faulty pixel unit 1, and send them to the third control module 23.

[0054] The third control module 23 is also used to connect the corresponding second sub-pixel unit 12 to the circuit according to the row and column coordinates of the faulty pixel unit 1.

[0055] In the application, a feedback line can be set up in the second module to collect the feedback voltage of each column signal line 24 and transmit it to the first feedback signal processing module 27. The first feedback signal processing module 27 can be an independently set physical module, such as a hardware circuit, or it can be a physical module or virtual module set inside a physical module (such as a scanning integrated circuit). Each column signal line 24 has a unique number. Therefore, in addition to receiving the voltage value of the column signal line 24, the first feedback signal processing module 27 can also identify the correspondence between the column signal line 24 and the voltage value according to the number of the column signal line 24, and thus determine the relevant status of the column corresponding to the column signal line 24 based on the magnitude of the voltage value. For example, if the first sub-pixel unit 11 of the first row and first column is open, and the first sub-pixel unit 11 of the first row and second column is normal, then the feedback voltage value of the first column signal line 24 is 0V, while the feedback voltage value of the second column signal line 24 is 1V. After receiving the voltage value data, the first feedback signal processing module 27 determines that the column signal line 24 corresponding to 0V is in column 1, meaning the first sub-pixel unit 11 in column 1 is open. The first feedback signal processing module 27 then sends the column coordinates of this open first sub-pixel unit 11 to the third control module 23. Since the current row scan signal is row 1, the coordinate position of the open first sub-pixel unit 11 is determined to be row 1, column 2. Based on the row and column coordinates of the open first sub-pixel unit 11, the third control module 23 turns on the switch module 26 in row 1, column 1. At this time, the second sub-pixel unit 12 in the same row and column is connected to the circuit and can be displayed at a specified brightness under the action of the row scan signal and the data signal.

[0056] In one embodiment, a switching module 26 corresponding to each second sub-pixel unit 12 is also included;

[0057] The controlled end of the switch module 26 in the i-th row and j-th column is connected to the third control module 23, the input end is connected to the first control module 21, and the output end is connected to one end of the second sub-pixel unit 12 in the i-th row and j-th column. One end of the first sub-pixel unit 11 in the i-th row and j-th column is connected to the i-th row signal line 25, and the other ends of the first sub-pixel unit 11 in the i-th row and j-th column and the second sub-pixel unit 12 in the i-th row and j-th column are connected to the j-th column signal line 24. The third control module 23 is also used to turn on the corresponding switch module 26 in a specified state so that the corresponding second sub-pixel unit 12 is connected to the circuit.

[0058] In application, the switch module 26 can be a single switching transistor or a switch unit including the switching transistor and other components. When the switch module 26 includes a switching transistor, the controlled terminal of the switching transistor is connected to the third control module 23, which controls the switching module 26. This allows the third control module 23 to control the on / off state of the switch module 26, thereby enabling the second sub-pixel unit 12 to be connected when necessary. For example, it can be connected when the first sub-pixel unit 11 is open, or when jagged edges appear on the screen. The input terminal of the switch module 26 in the i-th row and j-th column is connected to the first control module 21. This connection can be direct or indirect.

[0059] In one embodiment, the input terminal of the switch module 26 in the i-th row and j-th column is connected to the first control module 21 through the i-th row signal line 25, or the input terminal of the switch module 26 in the i-th row and j-th column is directly connected to the first control module 21. The first control module 21 is used to send a row scanning signal to the corresponding second sub-pixel unit 12 through the switch module 26 in the i-th row and j-th column.

[0060] In applications, such as Figure 1 As shown, the input terminal of the switch module 26 in the i-th row and j-th column is connected to the first control module 21 via the i-th row signal line 25. When the third control module 23 controls the switch module 26 to be turned on, the i-th row signal line 25 can output a row scan signal to the first sub-pixel unit 11 and also output a row scan signal to the second sub-pixel unit 12. For example, when the first sub-pixel unit 11 in the first row and first column is open, the third control module 23 controls the switch module 26 in the first row and first column to be turned on. Then, when the first control module 21 outputs a row scan signal to the first row signal line 25, this signal can act on the second sub-pixel unit 12. Since the second sub-pixel unit 12 can be used as compensation for the first sub-pixel unit 11, the problem of the bright cross line can be solved.

[0061] In applications, such as Figure 2 As shown, the input terminal of the switch module 26 in the i-th row and j-th column is directly connected to the first control module 21, instead of being connected to the row signal line 25 of the corresponding row. This is used to realize the time-division driving of the first sub-pixel unit 11 and the second sub-pixel unit 12, which is especially suitable for situations where the sizes of the first sub-pixel unit 11 and the second sub-pixel unit 12 are different.

[0062] In one embodiment, the size of the second sub-pixel unit 12 is smaller than that of the first sub-pixel unit 11, and the first sub-pixel unit 11 and the second sub-pixel unit 12 are misaligned.

[0063] The third control module 23 is also used for:

[0064] When the first sub-pixel unit 11 in the i-th row and j-th column is in an active state, a first data signal is sent to the first sub-pixel unit 11 in the i-th row and j-th column.

[0065] When the second sub-pixel unit 12 in the i-th row and j-th column is in an active state, a second data signal is sent to the second sub-pixel unit 12 in the i-th row and j-th column.

[0066] The duty cycle of the first data signal is greater than that of the first data signal.

[0067] In applications, the size of the second sub-pixel unit 12 can be smaller than that of the first sub-pixel unit 11 to eliminate jagged edges. For example, if the area of ​​a normal pixel unit 1 is 1, the area of ​​the first sub-pixel unit 11 can be 2 / 3, the area of ​​the second sub-pixel unit 12 can be 1 / 3, and the first sub-pixel unit 11 and the second sub-pixel unit 12 can be misaligned. When jagged edges appear, the second sub-pixel unit 12 can smoothly transition the jagged edges of the entire image, reducing the jaggedness.

[0068] In applications, since the size of the second sub-pixel unit 12 is smaller than that of the first sub-pixel unit 11, if the data signal inputs the same duty cycle to both the first and second sub-pixel units 11, the brightness of the second sub-pixel unit 12 will be lower than that of the first sub-pixel unit 11. Therefore, to ensure that the brightness of the second sub-pixel unit 12 is consistent with that of the first sub-pixel unit 11 when enabled, the duty cycle of the data signal output to the second sub-pixel unit 12 can be adjusted. For example, assuming the duty cycle of the data signal for the first sub-pixel unit 11 is set to 40%, the duty cycle of the data signal for the second sub-pixel unit 12 can be set to 60%. This means that within a complete pulse cycle, the second sub-pixel unit 12 emits light for 60% of the time, while the first sub-pixel unit 11 emits light for 40% of the time. Since the input terminal of the switch module 26 is directly connected to the first control module 21, rather than to the corresponding row signal line 25, time-division driving of the first sub-pixel unit 11 and the second sub-pixel unit 12 can be achieved. When the row scan signal points to the first sub-pixel unit 11, the duty cycle of the data signal is set to 40%. At this duty cycle, the first sub-pixel unit 11 will be in a high-level state for 40% of a complete cycle. When the line scan signal points to the second sub-pixel unit 12, the duty cycle of the data signal is set to 60%. At this duty cycle, the second sub-pixel unit 12 will be in a high-level state for 60% of a complete cycle, so that even if the size of the second sub-pixel unit 12 is smaller than that of the first sub-pixel unit 11, it can emit light with the same brightness as the first sub-pixel unit 11.

[0069] In one embodiment, the third control module 23 further includes a second feedback signal processing module 221, and the third control module 23 is further configured to:

[0070] Obtain the row scan feedback signal;

[0071] Obtain the grayscale data of the corresponding row based on the row scan feedback signal;

[0072] Obtain the preset compensation duty cycle based on the grayscale data of the corresponding row;

[0073] The data signal of the corresponding second sub-pixel unit 12 is compensated for the duty cycle according to the preset compensation duty cycle, so that the gray level of the corresponding second sub-pixel unit 12 in the active state is consistent with the gray level of the corresponding row obtained.

[0074] In application, the area of ​​the first sub-pixel unit 11 can be 2 / 3, and the area of ​​the second sub-pixel unit 12 can be 1 / 3, with output grayscale brightness set to 0, 5, 10, 15...255. The actual output brightness of the first sub-pixel unit 11 and the second sub-pixel unit 12 can be measured to confirm the brightness difference and record their respective brightness values. For example, a brightness measuring instrument can be used for measurement. Then, the data signal is adjusted to increase the output duty cycle of the data signal of the second sub-pixel unit 12, and the initial duty cycle and the final duty cycle are recorded until it is confirmed that the actual output brightness value of the second sub-pixel unit 12 is consistent with the grayscale (i.e., the set grayscale) of the first sub-pixel unit 11. The duty cycles (i.e., the final duty cycles) corresponding to the set gray levels 0, 5, 10...255 can be obtained as D0', D5', D10'...D255'. Then the compensated duty cycles for different gray levels are ΔD0, ΔD5...ΔD255. The compensated duty cycle is the difference between the final duty cycle and the initial duty cycle. When a feedback voltage of 0V is received, confirming that an LED (i.e., the first sub-pixel unit 11) is open, the row scanning signal of the row where the open LED is located is also synchronously fed back to the second feedback signal processing module 221 in the third control module 23 through the first control module 21. Whenever the line is output, the third control module 23 will automatically read the gray level of the current line output through the timing control integrated circuit (Tcon IC), and then call the compensation duty cycle of the current gray level to compensate the initial duty cycle to obtain the final duty cycle to be output. The compensation duty cycle is used to perform brightness compensation on the second sub-pixel unit 12 so that the second sub-pixel unit 12 outputs the same brightness as the first sub-pixel unit 11.

[0075] In applications, after the column signal line 24 corresponding to the third control module 23 feeds back to the scan ic, the row scanning voltage output by the scan ic is increased to compensate for the brightness.

[0076] In one embodiment, the LED of the second sub-pixel unit 12 can be designed to have the same appearance as the LED of the first sub-pixel unit 11, with only a size difference. Alternatively, depending on the application scenario, the appearance of the LED of the second sub-pixel unit 12 can be designed to be different from that of the first sub-pixel unit 11.

[0077] In applications, such as Figure 5 As shown, the second sub-pixel unit 12 is located at the lower right of the first sub-pixel unit 11. Alternatively, the second sub-pixel unit 12 can be located at any position, such as the lower left, middle left, middle right, upper left, or upper right of the first sub-pixel unit 11. The appearance of the second sub-pixel unit 12 is designed to ensure the PPI of the display screen and reduce the pitch between the first sub-pixel unit 11 and the second sub-pixel unit 12, without limiting its specific form.

[0078] Example 2

[0079] The pixel control method provided in this application embodiment can be executed by the processor 201 of the pixel control circuit when running a computer program 203 with corresponding functions. It determines the working state of the display panel; if the working state is a specified state, the corresponding second sub-pixel unit 12 is connected to the circuit so that the second sub-pixel unit 12 is controlled by the line scan signal and / or data signal and is in an active state. The second sub-pixel unit 12 can be connected when the first sub-pixel unit 11 fails, eliminating the bright cross-shaped phenomenon. Furthermore, when jagged edges appear on the display screen, connecting the second sub-pixel unit 12 can also smooth the jagged transition and reduce the jagged effect.

[0080] like Figure 6 As shown, the pixel control method provided in this application embodiment includes the following steps S101 and S102:

[0081] Step S101: Determine the working status of the display panel.

[0082] In one embodiment, determining the operating state of the display panel includes:

[0083] The voltage of column signal line 24 is acquired. If the voltage is the first voltage, the operating state is determined to be that the first sub-pixel unit 11 of the corresponding column is normal; if the voltage is the second voltage, the operating state is determined to be that the first sub-pixel unit 11 of the corresponding column is faulty; and / or

[0084] Based on the analysis of the received display screen, it was determined that the display screen exhibited a jagged edge effect.

[0085] In application, the first voltage is the output voltage of the column signal line 24 when the first sub-pixel unit 11 is normal, such as 1V. The second voltage is the output voltage of the column signal line 24 when the first sub-pixel unit 11 is open, such as 0V. By observing the voltage value output by the column signal line 24, it can be determined whether the first sub-pixel unit 11 is in a normal or open-circuit state. Furthermore, if the first sub-pixel unit 11 experiences a short circuit or other faults, this can also be reflected by the output voltage of the column signal line 24.

[0086] In applications, display analysis results can be obtained by the Graphics Processing Unit (GPU) capturing the display screen, performing image analysis using built-in algorithms, and then outputting the analysis results to the pixel control circuit. For example, when the GPU's image analysis module detects jagged edges in the image, this jagged edge phenomenon can be reflected in the display analysis results and detected by the pixel control circuit.

[0087] In applications, graphics processors (GPUs) can perform jagged edge detection based on the Sobel operator or the Canny edge detection algorithm. GPUs utilize convolutional kernels to detect locations in an image where grayscale values ​​change abruptly, i.e., edges. For jagged edges, because the grayscale values ​​change significantly within their local areas, the gradient intensity at these locations increases significantly after applying the Sobel operator, thus enabling their identification. GPUs can apply one or more predefined convolutional kernels (such as the horizontal and vertical templates in the Sobel operator) to each pixel of the image, calculating the gradient intensity by differing the grayscale values ​​of adjacent pixels. If the gradient intensity of a pixel and its neighborhood exceeds a certain threshold, an edge is considered to exist at that location. The analysis results can then be displayed to indicate the presence of jagged edges in the image, and the corresponding region of the jagged edge can also be identified.

[0088] Step S102: If the working state is a specified state, the corresponding second sub-pixel unit 12 is connected to the circuit so that the second sub-pixel unit 12 is controlled by the row scan signal and / or data signal and is in an active state.

[0089] In one embodiment, such as Figure 7 As shown, step S102 includes the following steps S201 and S202:

[0090] Step S201: If the first sub-pixel unit 11 is in a faulty state, the second sub-pixel unit 12, which is in the same row and column as the faulty pixel unit 1, is connected to the circuit.

[0091] In the application, if the first sub-pixel unit 11 is open, the row and column coordinates of the open first sub-pixel unit 11 will drive the switch module 26 in the same row and column to be turned on, so that the second sub-pixel unit 12 can be connected to the circuit.

[0092] Step S202: If the display screen shows jagged edges, connect all second sub-pixel units 12 to the circuit, or connect the second sub-pixel units 12 in the area corresponding to the jagged edges to the circuit.

[0093] In applications, such as Figure 8 As shown, when the display analysis results indicate that the image exhibits jagged edges, all second sub-pixel units 12 of the entire display panel can be connected to the circuit to reduce the jagged edges of the entire image. Alternatively, based on the jagged area indicated in the display analysis results, the second sub-pixel units 12 within the jagged area can be connected to the circuit to reduce the jagged edges in that area.

[0094] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0095] Example 3

[0096] like Figure 9 As shown, this application embodiment also provides a display panel, including the pixel control circuit 2 of the display panel provided in embodiment one of this application. The pixel control circuit 2 includes a memory 202, a processor 201, and a computer program 203 stored in the memory 202 and executable on the processor 201. When the processor 201 executes the computer program 203, it implements the steps of the pixel control method provided in embodiment two of this application.

[0097] In applications, the display panel may include, but is not limited to, a processor and memory. Those skilled in the art will understand that... Figure 9 This is merely an example of a display panel and does not constitute a limitation on the display panel. It may include more or fewer components than shown, or combine certain components, or use different components.

[0098] In applications, the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0099] In applications, the memory may be an internal storage unit of the display panel in some embodiments, such as the display panel's hard drive or RAM. In other embodiments, the memory may be an external storage device of the display panel, such as an on-display panel plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. Furthermore, the memory may include both internal and external storage units of the display panel. The memory is used to store operating systems, applications, bootloaders, data, and other programs, such as program code for computer programs. The memory can also be used to temporarily store data that has been output or will be output.

[0100] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0101] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0102] This application also provides a computer-readable storage medium storing a computer program 203, which, when executed by a processor 201, implements the steps described in the above-described method embodiments.

[0103] This application provides a computer program 203 product that, when run on a display panel, enables the display panel to perform the steps described in the above-described method embodiments.

[0104] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / display panel, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, a computer-readable medium cannot be an electrical carrier signal or a telecommunication signal.

[0105] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0106] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0107] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0108] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of this embodiment.

[0109] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A pixel control circuit of a display panel, characterized by, The display panel comprises a plurality of pixel units arranged in an array in the form of n rows and m columns, the pixel units comprising first sub-pixel units and second sub-pixel units, and the pixel control circuit comprises a first control module, a second control module, a third control module, n row signal lines and m column signal lines; The first control module is connected with the row signal lines, the second control module is connected with the column signal lines, and the pixel units in the i-th row and the j-th column are connected with the i-th row signal line and the j-th column signal line, respectively; The first control module is configured to output a row scanning signal to the row signal lines; The second control module is configured to output a data signal to the column signal lines; The first sub-pixel units are configured to be controlled by the row scanning signal and / or the data signal to be in an activated or inactivated state; The third control module is configured to, in a specified state, connect the corresponding second sub-pixel units to the circuit, so that the second sub-pixel units are controlled by the row scanning signal and / or the data signal to be in an activated state; The specified state comprises at least one of a first sub-pixel unit failure and a display image appearing a jagged phenomenon; i is an integer, and i∈[1, n]; j is an integer, and j∈[1, m]; The first sub-pixel unit failure comprises an open circuit of the first sub-pixel unit, the second sub-pixel unit arranged at the open circuit of the first sub-pixel unit is connected to the circuit, and the voltage of the data signal of the column in which the open circuit of the first sub-pixel unit is located is pulled up; The size of the second sub-pixel unit is smaller than that of the first sub-pixel unit, and the first sub-pixel unit and the second sub-pixel unit are arranged in a staggered manner; if in a state in which the display image appears a jagged phenomenon, all the second sub-pixel units are connected to the circuit, or the second sub-pixel units in the region corresponding to the jagged phenomenon are connected to the circuit.

2. The pixel control circuit of claim 1, wherein, Further comprising a switch module corresponding to each second sub-pixel unit; The control end of the switch module in the i-th row and the j-th column is connected with the third control module, the input end is connected with the first control module, and one end of the second sub-pixel unit in the i-th row and the j-th column is connected with the output end; one end of the first sub-pixel unit in the i-th row and the j-th column is connected with the i-th row signal line, and the other end of the first sub-pixel unit in the i-th row and the j-th column and the second sub-pixel unit in the i-th row and the j-th column is connected with the j-th column signal line; The third control module is further configured to, in the specified state, make the corresponding switch module conductive to connect the corresponding second sub-pixel units to the circuit.

3. The pixel control circuit of claim 2, wherein, The input end of the switch module in the i-th row and the j-th column is connected with the first control module through the i-th row signal line, or The input end of the switch module in the i-th row and the j-th column is directly connected with the first control module, and the first control module is configured to send a row scanning signal to the corresponding second sub-pixel unit through the switch module in the i-th row and the j-th column.

4. The pixel control circuit of claim 1, wherein, Further comprising a first feedback signal processing module; The jth input end of the second control module is connected with the jth column signal line, the jth output end of the second control module is connected with the jth input end of the first feedback signal processing module, and the jth output end of the first feedback signal processing module is connected with the jth input end of the third control module. The first feedback signal processing module is configured to determine a state of the first sub-pixel unit fault according to the voltage of the column signal line, locate the column coordinate of the fault pixel unit, and send the column coordinate to the third control module. The third control module is further configured to connect the corresponding second sub-pixel unit to the circuit according to the row and column coordinates of the fault pixel unit.

5. The pixel control circuit of claim 1, wherein, The size of the second sub-pixel unit is smaller than that of the first sub-pixel unit, and the first sub-pixel unit and the second sub-pixel unit are arranged in a staggered manner. The third control module is further configured to: when the first sub-pixel unit in the ith row and the jth column is in an active state, send a first data signal to the first sub-pixel unit in the ith row and the jth column; when the second sub-pixel unit in the ith row and the jth column is in an active state, send a second data signal to the second sub-pixel unit in the ith row and the jth column; The duty cycle of the first data signal is greater than that of the first data signal.

6. The pixel control circuit according to any one of claims 1 to 5, wherein The third control module is further configured to: acquire a row scanning feedback signal; acquire gray scale data of a corresponding row according to the row scanning feedback signal; acquire a preset compensation duty cycle according to the gray scale data of the corresponding row; compensate the duty cycle of the data signal of the corresponding second sub-pixel unit according to the preset compensation duty cycle, so that the gray scale of the corresponding second sub-pixel unit in the active state is consistent with the gray scale of the corresponding row obtained.

7. A pixel control method applied to the pixel control circuit according to any one of claims 1 to 6, characterized by, It includes: determining the working state of the display panel; if the working state is a specified state, connecting the corresponding second sub-pixel unit to the circuit, so that the second sub-pixel unit is controlled by the row scanning signal and / or the data signal and is in an active state.

8. The pixel control method of claim 7, wherein, The determination of the working state of the display panel includes: acquiring the voltage of the column signal line, if the voltage is a first voltage, determining that the working state of the corresponding column is normal, if the voltage is a second voltage, determining that the working state of the corresponding column is a first sub-pixel unit fault; and / or based on the received display picture analysis result, determining that the display picture appears a jagged phenomenon.

9. The pixel control method of claim 7, wherein, If the working state is a specified state, connecting the corresponding second sub-pixel unit to the circuit, so that the second sub-pixel unit is controlled by the row scanning signal and / or the data signal and is in an active state, including: if the state is the first sub-pixel unit fault, connecting the second sub-pixel unit in the same row and column with the fault pixel unit to the circuit; if the state is the display picture appearing a jagged phenomenon, connecting all second sub-pixel units to the circuit, or connecting the second sub-pixel units in the region corresponding to the jagged phenomenon to the circuit.

10. A display panel, characterized by, The pixel control circuit according to any one of claims 1 to 6, the pixel control circuit comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the pixel control method according to any one of claims 7 to 9 when executing the computer program.

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