Transformer area arc-free alternating current circuit breaker with synchronous compensation capability and control method

Abstract

The invention discloses a transformer area arc-free alternating current circuit breaker with synchronous compensation capability and a control method. The transformer area arc-free alternating current circuit breaker is connected with a voltage sensor, a current sensor, a mechanical circuit breaker, a GPS module, a wireless communication module, a thyristor driving circuit and an electric energy quality adjusting module through a microprocessor. The microprocessor receives sensing signals of the voltage sensor and the current sensor, clock signals of the GPS module and control information of the wireless communication module. According to induction signals of the voltage sensor and the current sensor, clock signals of the GPS module and control information of the wireless communication module, the operation state of the transformer area is calculated, and the mechanical circuit breaker, the thyristor driving circuit and the electric energy quality adjusting module are controlled according to calculation and analysis results. The problem that a traditional circuit breaker cannot meet the new energy requirements of more and more photovoltaic, charging piles and the like in a transformer area is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit breakers, and in particular relates to an arc-free AC circuit breaker with synchronous compensation capability and a control method thereof. Background Art

[0002] Current inventions or utility models have proposed arc-free AC circuit breaker design solutions, such as an intelligent arc-free circuit breaker with patent number ZL200520096776.4, a three-phase arc-free circuit breaker with application number 201020652885.0, and a high-breakage arc-free circuit breaker with application number CN201710544678.X, but they all have certain defects. Due to the use of new energy, there are more and more charging piles and rooftop photovoltaics in the substation area, and the power quality in the substation area is getting worse and worse. The traditional circuit breaker breaking decision can no longer meet the increasing demand for new energy in the substation area. The access to new energy has also put forward new demands for arc-free AC circuit breakers. The present invention designs an arc-free AC circuit breaker based on the increasing demand for the access of existing substations to new energy. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present invention provides an arc-free AC circuit breaker with synchronous compensation capability and a control method for a transformer substation, which solves the problem that traditional circuit breakers can no longer meet the needs of an increasing number of new energy sources such as photovoltaics and charging piles in transformer substations.

[0004] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: an arc-free AC circuit breaker with synchronous compensation capability in a transformer area, comprising a voltage sensor, a current sensor, a mechanical circuit breaker, a power quality adjustment module, a GPS module, a wireless communication module, a thyristor drive circuit, a thyristor and a microprocessor;

[0005] The microprocessor is connected to a voltage sensor, a current sensor, a mechanical circuit breaker, a power quality regulation module, a GPS module, a wireless communication module and a thyristor drive circuit, and the thyristor drive circuit is connected to the thyristor;

[0006] The voltage sensor is used to collect the three-phase voltage value output by the substation transformer, the current sensor is used to collect the three-phase current value output by the substation transformer, the GPS module is used to provide a clock signal for the microprocessor, and the wireless communication module is used to provide control information for the microprocessor. The microprocessor is used to calculate the substation operating status according to the three-phase voltage and current values, clock signals and control information output by the substation transformer, and control the mechanical circuit breaker, thyristor drive circuit and power quality regulation module according to the calculation results. The thyristor is used to control the current.

[0007] Further: the power quality regulation module includes power quality regulation submodules arranged on three phases, and the power quality regulation submodules arranged on each phase have the same structure, and all include a grid-side inductor, a load-side inductor, an inverter inductor, a filter inductor, an inverter and a filter capacitor;

[0008] Among them, one end of the grid-side inductor is connected to the mechanical circuit breaker, and the other end of the grid-side inductor is respectively connected to one end of the load-side inductor, one end of the inverter inductor and one end of the filter inductor. The other end of the inverter inductor is connected to the inverter, the other end of the filter inductor is grounded through the filter capacitor, and the other end of the load-side inductor is connected to the substation load.

[0009] Further: the power quality regulation module is also provided with a three-phase inverter, including an energy storage capacitor A, an energy storage capacitor B, a neutral line inverter, an A-phase inverter, a B-phase inverter and a C-phase inverter;

[0010] Wherein, one end of the energy storage capacitor A is respectively connected to the No. 2 connection terminal of the neutral line inverter, the No. 2 connection terminal of the A phase inverter, the No. 2 connection terminal of the B phase inverter and the No. 2 connection terminal of the C phase inverter, and the other end of the energy storage capacitor A is respectively connected to one end of the energy storage capacitor B, the No. 1 connection terminal of the neutral line inverter, the No. 1 connection terminal of the A phase inverter, the No. 1 connection terminal of the B phase inverter and the No. 1 connection terminal of the C phase inverter;

[0011] The other end of the energy storage capacitor B is respectively connected to the No. 3 connection terminal of the neutral line inverter, the No. 3 connection terminal of the A phase inverter, the No. 3 connection terminal of the B phase inverter and the No. 3 connection terminal of the C phase inverter. The No. 3 connection terminal of the neutral line inverter is connected to the neutral line, the No. 3 connection terminal of the A phase inverter is connected to the inverter inductor on the A phase, the No. 3 connection terminal of the B phase inverter is connected to the inverter inductor on the B phase, and the No. 3 connection terminal of the C phase inverter is connected to the inverter inductor on the C phase.

[0012] Further: the neutral line inverter, A-phase inverter, B-phase inverter and C-phase inverter have the same structure, and all include an upper arm diode, a lower arm diode, a first IGBT module, a second IGBT module, a third IGBT module, a fourth IGBT module, a first IGBT drive module, a second IGBT drive module, a third IGBT drive module, a fourth IGBT drive module, a connection port Q1, a connection port Q2, a connection port Q3, a connection port Q4, a No. 1 connection terminal, a No. 2 connection terminal, a No. 3 connection terminal and a No. 4 connection terminal;

[0013] The gate of the first IGBT module is connected to the connection port Q1 through the first IGBT driving module, the collector of the first IGBT module is connected to the No. 2 connection terminal, and the emitter of the first IGBT module is connected to the collector of the second IGBT module and the cathode of the upper arm diode respectively;

[0014] The gate of the second IGBT module is connected to the connection port Q2 through the second IGBT driving module, and the emitter of the second IGBT module is connected to the collector of the third IGBT module and the No. 4 connection terminal respectively;

[0015] The gate of the third IGBT module is connected to the connection port Q3 through the third IGBT driving module, the emitter of the third IGBT module is respectively connected to the anode of the lower arm diode and the collector of the fourth IGBT module, and the cathode of the lower arm diode is respectively connected to the anode of the upper arm diode and the No. 1 connection terminal;

[0016] The gate of the fourth IGBT module is connected to the connection port Q4 through the fourth IGBT driving module, and the emitter of the fourth IGBT module is connected to the No. 3 connection terminal.

[0017] The control method is applied to a non-arcing AC circuit breaker in a transformer area with synchronous compensation capability, and comprises the following steps:

[0018] S1, perform initialization operation through the initialization subroutine;

[0019] S2, calculating the trip criterion through the trip criterion calculation subroutine;

[0020] S3, determine whether the tripping criterion is equal to 1, if so, enter S4, if not, enter S5;

[0021] S4, perform tripping action through the tripping action subroutine and enter S5;

[0022] S5, calculating the compensation criterion through the compensation criterion calculation subroutine;

[0023] S6. In response to the compensation criterion being equal to 1, a compensation action is performed through a compensation action subroutine.

[0024] Further: S1 comprises the following sub-steps:

[0025] S11, set the low frequency interrupt clock to 100 milliseconds, set the high frequency interrupt clock to 100 microseconds, set the compensation clock to 50 microseconds, set the wireless communication module reading interface, and set the GPS module reading interface;

[0026] S12, setting a low-frequency interrupt condition, and setting a low-frequency interrupt subroutine to be called when the interrupt occurs, setting a high-frequency interrupt condition, and setting a high-frequency interrupt subroutine to be called when the interrupt occurs, setting a compensation interrupt condition, and setting a compensation interrupt subroutine to be called when the interrupt occurs;

[0027] S13. Set variables, including:

[0028] MA is used to represent the current time in seconds, with a value range of 0-59. HA is used to represent the current time in milliseconds, with a value range of 0-999. UA is used to represent the current time in microseconds, with a value range of 0-999. A0 is used to represent the moment when the voltage phase of phase A is zero, in milliseconds. CH is used to represent the high-frequency interruption counter, with a value range of 0-999. XY is used to represent the trip phase threshold, ZY is used to represent the trip impedance threshold, BY is used to represent the compensation threshold, TZ is used to represent the trip mark, and CVA is used to represent the sensor reading counter, with a value range of 0. ~999, CZQ is used to represent the cycle counter, the value range is 0~199, SUMV is used to represent the voltage summation, SUMI is used to represent the current summation, ZSUM is used to represent the impedance, the array VIN

[1000] is used to represent the current sensor reading value, the array FV

[1000] is used to represent the voltage floating point value, the array IIN

[1000] is used to represent the voltage sensor reading value, the array FI

[1000] is used to represent the current floating point value, PT is used to represent the time update data position, FTZ is used to represent the trip calculation variable, and FBZ is used to represent the compensation calculation variable;

[0029] S14, initialize variables, the initialized variables are specifically:

[0030] MA=0,HA=0,UA=0,A0=0,CH=0,PT=0,FTZ=0,FBZ=0,TZ=0,XY=0,ZY=0,BY=0,CVA=0,CZQ=0,SUMV=0,SUMI=0,ZSUM=0,VIN

[1000] is initialized to all zeros, and IIN

[1000] is initialized to all zeros;

[0031] S15, setting a first parameter M1data, a second parameter M2data, a third parameter M3data, a fourth parameter M4data, a fifth parameter M5data and a comparison variable BiJiao;

[0032] In S12, the method of calling the low-frequency interrupt subroutine is specifically as follows:

[0033] SA1, read the data of the wireless communication module, parse the read data according to the wireless communication protocol, and update the A0, XY, ZY and BY variables;

[0034] The wireless communication protocol is arranged by bytes, in the following order: 55, AA, A0 high eight bits, A0 low eight bits, XY high eight bits, XY low eight bits, ZY high eight bits, ZY low eight bits, BY high eight bits, BY low eight bits, check bit, 33, CC;

[0035] Among them, 55, AA indicate the start of the communication packet, 33, CC indicate the end of the communication packet, and the check bits are A0 high eight bits, A0 low eight bits, XY high eight bits, XY low eight bits, ZY high eight bits, ZY low eight bits, BY high eight bits, BY low eight bits, which are bit-wise XORed;

[0036] SA2, read the GPS module data, parse the read data according to the GPS communication protocol, and update the MA, HA and UA variables;

[0037] The GPS communication protocol is arranged by bytes, in the following order: 55, AA, MA, HA high eight bits, HA low eight bits, check bit, 33, CC;

[0038] Among them, 55, AA indicates the beginning of the communication packet, 33, CC indicates the end of the communication packet; the check bit is MA, HA high eight bits, HA low eight bits bit by bit XOR;

[0039] SA3, assign the value of CVA to PT;

[0040] In S12, the method of calling the high-frequency interrupt subroutine is specifically as follows:

[0041] SB1. Assign the storage value of the memory corresponding to the voltage sensor to VIN[CVA], assign the storage value of the memory corresponding to the current sensor to IIN[CVA], and add 1 to CVA;

[0042] SB2. In response to CVA being equal to 1000, set CVA=0, FBZ=1;

[0043] The specific method of calling the compensation interrupt subroutine is:

[0044] Set the compensation action judgment parameter CBuchang=0, and judge whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang];

[0045] If so, the compensation action is: control the IGBT module (103-2) to be turned on, and control the IGBT module (103-3) to be turned off;

[0046] If not, the compensation action is: control the IGBT module (103-2) to be turned off, and control the IGBT module (103-3) to be turned on.

[0047] Further: S2 comprises the following sub-steps:

[0048] S21, let CZQ equal the remainder of CVA with respect to 200,

[0049] S22, in response to CZQ being less than 50, setting FTZ=1;

[0050] S23, determine whether CZQ is greater than 197, if so, and FTZ is equal to 1, then go to step S24; if not, then go to step S3;

[0051] S24, set FTZ=0;

[0052] S25. For i=0-199, calculate:

[0053] FV[i]=(VIN[CVA-197+i]–32768) / 32768;

[0054] FI[i]=(IIN[CVA-197+i]–32768) / 32768;

[0055] S26. Calculate ZSUM, specifically:

[0056] ZSUM=SUMV / SUMI

[0057] in,

[0058] S27. Determine whether ZSUM is less than ZY. If so, set the tripping criterion TZ=1; if not, set the tripping criterion TZ=0.

[0059] Further: S4 includes the following sub-steps:

[0060] S41, control thyristor conduction;

[0061] S42, control the mechanical circuit breaker to disconnect;

[0062] S43, control the thyristor to disconnect.

[0063] Further: S5 comprises the following sub-steps:

[0064] S51, take 300 sample points before the current IIN sampling data through INDATA

[300] , the sampling method is as follows:

[0065] Determine whether CAV is greater than or equal to 300; if so, let INDATA data take IIN[CAV-300]~IIN[CAV]; if not, let INDATA

[300] data take the concatenation of IIN[1000-CAV]~IIN

[1000] and IIN[0]~IIN[CAV];

[0066] S52. In the range of i = 0 to 100, find the first i that simultaneously satisfies INDATA[i] * INDATA[i + 4] < 0 and INDATA[i] < INDATA[i + 4], and let j = i;

[0067] S53. Calculate the first summation parameter SUMF1, specifically:

[0068]

[0069] In the formula, M1data[i] is a preset first parameter;

[0070] S54. Take k = 1 to 25, search for the maximum value MaxSumF2 in the second summation parameter SUMF2[k], where the expression for calculating the second summation parameter SUMF2[k] is specifically:

[0071]

[0072] In the formula, M2data[i] is a preset second parameter;

[0073] Calculate the second compensation sub-criterion BiF2, BiF2 = MaxSumF2 / SUMF1, and determine whether the second compensation sub-criterion BiF2 is greater than 0.03. If so, let the second compensation parameter BuChangF2 = 1; if not, let the second compensation parameter BuChangF2 = 0;

[0074] S55. Take k = 1 to 15, search for the maximum value MaxSumF3 in the third summation parameter SUMF3[k], where the expression for calculating the third summation parameter SUMF3[k] is specifically:

[0075]

[0076] In the formula, M3data[i] is a preset third parameter, and m is the remainder obtained by dividing i by 66;

[0077] Calculate the third compensation sub-criterion BiF3, BiF3 = MaxSumF3 / SUMF1, and determine whether the third compensation sub-criterion BiF3 is greater than 0.03. If so, let the third compensation parameter BuChangF3 = 1; if not, let the third compensation parameter BuChangF3 = 0;

[0078] S56. Take k = 1 to 12, search for the maximum value MaxSumF4 in the fourth summation parameter SUMF4[k], where the expression for calculating the fourth summation parameter SUMF4[k] is specifically:

[0079]

[0080] Wherein, M4data[i] is the preset fourth parameter, and m is the remainder obtained by dividing i by 50;

[0081] Calculate the fourth compensation sub-criterion BiF4, BiF4 = MaxSumF4 / SUMF1, and determine whether the fourth compensation sub-criterion BiF4 is greater than 0.03. If so, set the fourth compensation parameter BuChangF4 = 1; if not, set the fourth compensation parameter BuChangF4 = 0;

[0082] S57, taking k=1-10, searching for the maximum value MaxSumF5 in the fifth sum parameter SUMF5[k], wherein the expression for calculating the fifth sum parameter SUMF5[k] is specifically:

[0083]

[0084] Wherein, M5data[i] is the preset fifth parameter, and m is the remainder obtained by dividing i by 40;

[0085] Calculate the fifth compensation sub-criterion BiF5, BiF5=MaxSumF5 / SUMF1, and determine whether the fifth compensation sub-criterion BiF5 is greater than 0.03. If so, set the fifth compensation parameter BuChangF5=1; if not, set the fifth compensation parameter BuChangF5=0;

[0086] S58, calculating the first compensation parameter BuChang by the following formula;

[0087] BuChang=BuChangF2+BuChangF3+BuChangF4+BuChangF5

[0088] It is determined whether the first compensation parameter BuChang is greater than 1. If so, the compensation criterion BZ=1; if not, the compensation criterion BZ=0.

[0089] Further: In said S6, the method of performing the compensation action through the compensation action subroutine is specifically as follows:

[0090] S61, determine whether the second compensation parameter BuChangF2 is equal to 1, if not, set the second compensation action parameter bcDataF2[i]=0, where i is 0-399;

[0091] If yes, the second compensation action parameters bcDataF2[2*i], bcDataF2[2*i+1], bcDataF2

[199] and bcDataF2[i+200] are calculated by the following formula;

[0092] bcDataF2[2*i]=-1*BiF2*M2data[i], where i is 0 to 99;

[0093] bcDataF2[2*i+1]=(bcDataF2[2*i]+bcDataF2[2*i+2]) / 2, where i is 0 to 98;

[0094] bcDataF2

[199] =(bcDataF2[0]+bcDataF2

[198] ) / 2;

[0095] bcDataF2[i+200]=bcDataF2[i], where i is 0 to 199;

[0096] S62, determine whether the third compensation parameter BuChangF3 is equal to 1, if not, set the third compensation action parameter bcDataF3[i]=0, where i is 0-399;

[0097] If so, the third compensation action parameters bcDataF3[2*i], bcDataF3[2*i+1], bcDataF3

[131] , bcDataF3

[132] , bcDataF3[i+133], bcDataF3

[266] and bcDataF3[i+267] are calculated by the following formula;

[0098] bcDataF3[2*i]=-1*BiF3*M3data[i], where i is 0 to 65;

[0099] bcDataF3[2*i+1]=(bcDataF3[2*i]+bcDataF3[2*i+2]) / 2, where i ranges from 0 to 64;

[0100] bcDataF3

[131] =(bcDataF3[0]+bcDataF3

[130] ) / 2;

[0101] bcDataF3

[132] =bcDataF3

[131] ;

[0102] bcDataF3[i+133]=bcDataF3[i], where i is 0 to 132;

[0103] bcDataF3

[266] =bcDataF3

[265] ;

[0104] bcDataF3[i+267]=bcDataF3[i], where i is 0 to 132;

[0105] S63, determine whether the fourth compensation parameter BuChangF4 is equal to 1, if not, set the fourth compensation action parameter bcDataF4[i]=0, where i is 0-399;

[0106] If yes, the fourth compensation action parameters bcDataF4[2*i], bcDataF4[2*i+1], bcDataF4

[99] , bcDataF4[i+100] and bcDataF4[i+200] are calculated by the following formula;

[0107] bcDataF4[2*i]=-1*BiF4*M4data[i], where i is 0 to 49;

[0108] bcDataF4[2*i+1]=(bcDataF4[2*i]+bcDataF4[2*i+2]) / 2, where i ranges from 0 to 48;

[0109] bcDataF4

[99] =(bcDataF4[0]+bcDataF4

[98] ) / 2;

[0110] bcDataF4[i+100]=bcDataF4[i], where i is 0 to 99;

[0111] bcDataF4[i+200]=bcDataF4[i], where i is 0 to 199;

[0112] S64, determine whether the fifth compensation parameter BuChangF5 is equal to 1, if not, set the fifth compensation action parameter bcDataF5[i]=0, where i is 0-399;

[0113] If yes, the fifth compensation action parameters bcDataF5[2*i], bcDataF5[2*i+1], bcDataF5

[79] , bcDataF5[i+80], bcDataF5[i+160] and bcDataF5[i+320] are calculated by the following formula;

[0114] bcDataF5[2*i]=-1*BiF5*M5data[i], where i ranges from 0 to 39;

[0115] bcDataF5[2*i+1]=(bcDataF5[2*i]+bcDataF5[2*i+2]) / 2, where i ranges from 0 to 38;

[0116] bcDataF5

[79] =(bcDataF5[0]+bcDataF5

[78] ) / 2;

[0117] bcDataF5[i+80]=bcDataF5[i], where i is 0 to 79;

[0118] bcDataF5[i+160]=bcDataF6[i], where i is 0 to 159;

[0119] bcDataF5[i+320]=bcDataF6[i], where i is 0 to 79;

[0120] S65, calculating a first compensation action parameter BuChangV by the following formula, and performing a compensation action according to the first compensation action parameter BuChangV;

[0121] BuChangV=bcDataF2[i]+bcDataF3[i]+bcDataF4[i]+bcDataF5[i], where i ranges from 0 to 399.

[0122] The beneficial effects of the present invention are as follows: the present invention is connected with a voltage sensor, a current sensor, a mechanical circuit breaker, a GPS module, a wireless communication module, a thyristor drive circuit, and a power quality regulation module through a microprocessor. The microprocessor receives the sensing signals of the voltage sensor and the current sensor, the clock signal of the GPS module, and the control information of the wireless communication module; the operation status of the substation is calculated according to the sensing signals of the voltage sensor and the current sensor, the clock signal of the GPS module, and the control information of the wireless communication module, and the mechanical circuit breaker, the thyristor drive circuit, and the power quality regulation module are controlled according to the calculation and analysis results, which solves the problem that traditional circuit breakers can no longer meet the needs of more and more new energy sources such as photovoltaics and charging piles in the substation. BRIEF DESCRIPTION OF THE DRAWINGS

[0123] Figure 1 It is a schematic diagram of an arc-free AC circuit breaker in a transformer area with synchronous compensation capability.

[0124] Figure 2 Schematic diagram of the power quality regulation module.

[0125] Figure 3 A schematic diagram of a three-phase inverter.

[0126] Figure 4 Schematic diagram of a single-phase inverter.

[0127] Figure 5 This is the schematic diagram of the driving circuit of the voltage sensor and current sensor.

[0128] Figure 6 This is the schematic diagram of the thyristor drive circuit.

[0129] Figure 7 is a schematic diagram of the first optical signal transceiver A.

[0130] Figure 8 is a schematic diagram of the first optical signal transceiver B.

[0131] Fig. 9 This is the schematic diagram of the first trigger circuit.

[0132] Fig.10 This is the schematic diagram of the thyristor.

[0133] Fig.11 This is the driving circuit schematic of the IGBT module.

[0134] Fig.12 is a schematic diagram of the second optical signal transceiver A.

[0135] Fig.13 is a schematic diagram of a second optical signal transceiver B.

[0136] Fig.14 This is the schematic diagram of the second trigger circuit.

[0137] Fig.15 Flow chart of the control method.

[0138] Wherein: 1, voltage sensor; 101, upper arm diode; 102, lower arm diode; 103-1, first IGBT module; 103-2, second IGBT module; 103-3, third IGBT module; 103-4, fourth IGBT module; 104-1, first IGBT driver module; 104-2, second IGBT driver module; 104-3, third IGBT driver module; 104-4, fourth IGBT driver module; 105-1, connection port Q1; 105-2, connection port Q2; 105-3, connection port Q3; 105-4, connection port Q4; 106, No. 1 connection terminal; 107, No. 2 connection terminal; 108, No. 3 connection terminal; 109, No. 4 connection terminal; 133, No. 1. Optical signal transceiver A; 134. first optical fiber; 135. first optical signal transceiver B; 136. first trigger circuit; 143. second optical signal transceiver A; 144. second optical fiber; 145. second optical signal transceiver B; 146. second trigger circuit; 2. current sensor; 21. grid-side inductor; 22. load-side inductor; 23. inverter inductor; 24. filter inductor; 25. inverter; 26. filter capacitor; 3. mechanical circuit breaker; 4. power quality regulation module; 5. GPS module; 51. energy storage capacitor A; 52. energy storage capacitor B; 53. neutral line inverter; 54. A-phase inverter; 55. B-phase inverter; 56. C-phase inverter; 6. wireless communication module; 7. thyristor drive circuit; 8. thyristor; 9. microprocessor. DETAILED DESCRIPTION

[0139] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0140] like Figure 1 As shown, in one embodiment of the present invention, an arc-free AC circuit breaker with synchronous compensation capability in a transformer area includes a voltage sensor 1, a current sensor 2, a mechanical circuit breaker 3, a power quality adjustment module 4, a GPS module 5, a wireless communication module 6, a thyristor drive circuit 7, a thyristor 8 and a microprocessor 9;

[0141] Wherein, the microprocessor 9 is connected with the voltage sensor 1, the current sensor 2, the mechanical circuit breaker 3, the power quality regulation module 4, the GPS module 5, the wireless communication module 6 and the thyristor drive circuit 7, and the thyristor drive circuit 7 is connected with the thyristor 8;

[0142] The voltage sensor 1 is used to collect the three-phase voltage value output by the substation transformer, the current sensor 2 is used to collect the three-phase current value output by the substation transformer, the GPS module 5 is used to provide a clock signal for the microprocessor 9, and the wireless communication module 6 is used to provide control information for the microprocessor 9. The microprocessor 9 is used to calculate the substation operation status according to the three-phase voltage and current values, clock signals and control information output by the substation transformer, and control the mechanical circuit breaker 3, the thyristor drive circuit 7, and the power quality regulation module 4 according to the calculation results. The thyristor 8 is used to control the current.

[0143] In this embodiment, Figure 1 Only one-phase structure is shown. In the three-phase structure, there is only one microprocessor 9, wireless communication module 6, and GPS module 5, and the mechanical circuit breaker 3 is a three-phase circuit breaker; other components, such as voltage sensor 1, current sensor 2, power quality regulation module 4, thyristor 8, and thyristor drive circuit 7, need to be used one for each phase, and three for each phase, and the connection method between each phase is the same.

[0144] The output of the substation transformer is a three-phase conductor, which passes through the voltage sensor 1 and the current sensor 2, and is connected to the input end of the mechanical circuit breaker 3. The output end of the mechanical circuit breaker 3 is connected to the input end of the power quality regulation module 4. The output end of the power quality regulation module 4 is connected to the substation load to supply power to the substation load.

[0145] like Figure 2As shown, the power quality regulation module 4 includes power quality regulation submodules arranged on three phases, and the power quality regulation submodules arranged on each phase have the same structure, and all include a grid-side inductor 21, a load-side inductor 22, an inverter inductor 23, a filter inductor 24, an inverter 25 and a filter capacitor 26;

[0146] Among them, one end of the grid-side inductor 21 is connected to the mechanical circuit breaker 3, and the other end of the grid-side inductor 21 is respectively connected to one end of the load-side inductor 22, one end of the inverter inductor 23 and one end of the filter inductor 24, the other end of the inverter inductor 23 is connected to the inverter 25, the other end of the filter inductor 24 is grounded through the filter capacitor 26, and the other end of the load-side inductor 22 is connected to the substation load.

[0147] like Figure 3 As shown, the power quality regulation module 4 is also provided with a three-phase inverter, including an energy storage capacitor A51, an energy storage capacitor B52, a neutral line inverter 53, an A-phase inverter 54, a B-phase inverter 55 and a C-phase inverter 56;

[0148] Among them, one end of the energy storage capacitor A51 is respectively connected to the No. 2 connection terminal of the neutral line inverter 53, the No. 2 connection terminal of the A phase inverter 54, the No. 2 connection terminal of the B phase inverter 55 and the No. 2 connection terminal of the C phase inverter 56, and the other end of the energy storage capacitor A51 is respectively connected to one end of the energy storage capacitor B52, the No. 1 connection terminal of the neutral line inverter 53, the No. 1 connection terminal of the A phase inverter 54, the No. 1 connection terminal of the B phase inverter 55 and the No. 1 connection terminal of the C phase inverter 56;

[0149] The other end of the energy storage capacitor B52 is respectively connected to the No. 3 connection terminal of the neutral line inverter 53, the No. 3 connection terminal of the A phase inverter 54, the No. 3 connection terminal of the B phase inverter 55 and the No. 3 connection terminal of the C phase inverter 56. The No. 3 connection terminal of the neutral line inverter 53 is connected to the neutral line, the No. 3 connection terminal of the A phase inverter 54 is connected to the inverter inductor 23 on the A phase, the No. 3 connection terminal of the B phase inverter 55 is connected to the inverter inductor 23 on the B phase, and the No. 3 connection terminal of the C phase inverter 56 is connected to the inverter inductor 23 on the C phase.

[0150] like Figure 4As shown, the neutral line inverter 53, the A-phase inverter 54, the B-phase inverter 55 and the C-phase inverter 56 have the same structure, and all include an upper arm diode 101, a lower arm diode 102, a first IGBT module 103-1, a second IGBT module 103-2, a third IGBT module 103-3, a fourth IGBT module 103-4, a first IGBT driver module 104-1, a second IGBT driver module 104-2, a third IGBT driver module 104-3, a fourth IGBT driver module 104-4, a connection port Q1 105-1, a connection port Q2 105-2, a connection port Q3 105-3, a connection port Q4 105-4, a No. 1 connection terminal 106, a No. 2 connection terminal 107, a No. 3 connection terminal 108 and a No. 4 connection terminal 109;

[0151] The gate of the first IGBT module 103-1 is connected to the connection port Q1105-1 through the first IGBT driving module 104-1, the collector of the first IGBT module 103-1 is connected to the No. 2 connection terminal 107, and the emitter of the first IGBT module 103-1 is connected to the collector of the second IGBT module 103-2 and the cathode of the upper arm diode 101 respectively;

[0152] The gate of the second IGBT module 103 - 2 is connected to the connection port Q2105 - 2 through the second IGBT driving module 104 - 2 , and the emitter of the second IGBT module 103 - 2 is connected to the collector of the third IGBT module 103 - 3 and the No. 4 connection terminal 109 ;

[0153] The gate of the third IGBT module 103-3 is connected to the connection port Q3105-3 through the third IGBT driving module 104-3, the emitter of the third IGBT module 103-3 is connected to the anode of the lower arm diode 102 and the collector of the fourth IGBT module 103-4, and the cathode of the lower arm diode 102 is connected to the anode of the upper arm diode 101 and the No. 1 connection terminal 106.

[0154] The gate of the fourth IGBT module 103 - 4 is connected to the connection port Q4105 - 4 through the fourth IGBT driving module 104 - 4 , and the emitter of the fourth IGBT module 103 - 4 is connected to the third connection terminal 108 .

[0155] In this embodiment, the model of the microprocessor 9 is TMS320F28027.

[0156] The driving circuit of voltage sensor 1 and current sensor 2 is as follows Figure 5 shown.

[0157] Thyristor drive circuit 7 Figure 6As shown, it includes a first optical signal transceiver A133, a first optical fiber 134, a first optical signal transceiver B135 and a first trigger circuit 136 which are connected in sequence.

[0158] The optical signal transceiver module is composed of a first optical signal transceiver A, a first optical signal transceiver B, and two first optical fibers; one first optical fiber is used to connect the optical signal transmitting end of the first optical signal transceiver A and the optical signal receiving end of the first optical signal transceiver B, and the other first optical fiber is used to connect the optical signal receiving end of the first optical signal transceiver A and the optical signal transmitting end of the first optical signal transceiver B. The first optical signal transceiver A is as follows Figure 7 shown.

[0159] In the above circuit, SWITCH2 is connected to the output pin of the microprocessor, and SWITCH3 is connected to the input pin of the microprocessor; U3 is an integrated circuit produced by TEXAS INSTRUMENT, model SN75451, which is used to provide driving current to U1; U1 is connected to the sending port by the first optical fiber, and U2 is connected to the receiving port by the first optical fiber;

[0160] U1 is used to receive a microprocessor control signal and send the microprocessor control signal to the first optical fiber. The sent signal is transmitted to U2 of the first optical signal transceiver B through the first optical fiber; U2 is used to receive a first optical fiber signal, and the received signal comes from U1 of the first optical signal transceiver B; and send the received first optical fiber signal to the microprocessor;

[0161] The schematic diagram of the first optical signal transceiver B is as follows Figure 8 As shown, U2 is connected to the first optical fiber receiving port, and the first optical fiber receiving port of model HFBR2414 produced by AVAGOTECHNOLOGIES is adopted; the received signal comes from U1 of the first optical signal transceiver A; U2 converts the received optical signal into an electrical signal, and the electrical signal network is named REDATA; REDATA is used to connect the first trigger circuit, so that the first trigger circuit generates a switch trigger signal; at the same time, REDATA is connected to the optical transmission circuit composed of U3 and U1, which is used to feed back the signal to the microprocessor; U3 and U1 constitute an optical transmission circuit, which is used to convert the REDATA electrical signal into an optical signal, and the optical signal emitted by U1 is sent to U2 of the first optical signal transceiver A through the first optical fiber; and the REDATA signal is sent to the microprocessor; U3 is an integrated circuit produced by TEXAS INSTRUMENT, model SN75451, and U1 is connected to the first optical fiber sending port, and the first optical fiber sending port of model HFBR1414 produced by AVAGO TECHNOLOGIES is adopted;

[0162] like Fig. 9As shown, the first trigger circuit amplifies the power of REDATA to trigger the thyristor of the switch circuit; the first trigger circuit is mainly composed of an integrated circuit, a transformer, and a rectifier circuit; U1 is an integrated circuit L292 produced by STMicroelectronics GROUP OF COMPANIES. When U1 receives REDATA as a low level, it generates a high-power square wave; T1 is a three-winding transformer; one primary winding and two secondary windings; the primary winding is connected to the high-power square wave output by U1; the two secondary windings are both connected to a rectifier current composed of a full bridge; the positive pole of the rectifier circuit is connected to the two terminals G1 and G2; the negative pole is connected to the two terminals K1 and K2; the rectifier circuit is composed of four diodes to form a full bridge, and a capacitor and resistor are added to form a filter circuit; the other peripheral circuits of U1 are designed according to the data sheet of L292;

[0163] like Fig.10 As shown, the switch circuit is composed of thyristors Q1 and Q2 connected in reverse parallel, and connected in parallel with a mechanical circuit breaker, and at the same time connected in parallel with a resistor, a series circuit of a resistor and a capacitor; the anode of Q1 is short-circuited with the cathode of Q2, and the connection end is called CON2; the anode of Q1 is short-circuited with the cathode of Q2, and the connection end is called CON2; the cathode of Q1 is short-circuited with the anode of Q2, and the connection end is called CON1; CON1 and CON2 are connected to the mechanical circuit breaker; the gate level of Q1 is short-circuited with the first trigger circuit G1; the gate level of Q2 is short-circuited with the first trigger circuit G2; in the embodiment, the thyristors Q1 and Q2 are selected from the thyristors of model 5STP42U6500 produced by ABB.

[0164] like Fig.11 As shown, the driving circuit of the IGBT module includes a second optical signal transceiver A143, a second optical fiber 144, a second optical signal transceiver B145 and a second trigger circuit 146 which are connected in sequence.

[0165] The optical signal transceiver module is composed of a second optical signal transceiver A, a second optical signal transceiver B, and four second optical fibers; two second optical fibers are used, one end of which is connected to two optical signal sending ends of the second optical signal transceiver A, and the other end is connected to two optical signal receiving ends of the second optical signal transceiver B; one end of the other two second optical fibers is connected to two optical signal receiving ends of the second optical signal transceiver A, and the other end is connected to two optical signal sending ends of the second optical signal transceiver B;

[0166] The second optical signal transceiver A is Fig.12As shown, in the above circuit, SWITCH2 and SWITCH3 are connected to two output pins of the microprocessor, and SWITCH4 and SWITCH5 are connected to two input pins of the microprocessor; U5 is an integrated circuit produced by TEXAS INSTRUMENT, model SN75451, which is used to provide driving current to U1 and U3. U1 and U3 are optical fiber connected to the sending port, and U2 and U4 are optical fiber connected to the receiving port;

[0167] U1 and U3 are used to receive microprocessor control signals and send microprocessor control signals to the optical fiber. The sent signals are transmitted to U2 and U4 of the optical signal transceiver B through the optical fiber. U2 and U4 are used to receive optical fiber signals. The received signals come from U1 and U3 of the optical signal transceiver B and send the received optical fiber signals to the microprocessor.

[0168] like Fig.13 As shown, U2 and U4 are optical fiber connection receiving ports, and adopt the optical fiber receiving port model HFBR2414 produced by AVAGO TECHNOLOGIES; the received signal comes from U1 and U3 of the second optical signal transceiver A; U2 and U4 convert the received optical signal into an electrical signal, and the electrical signal network is named REDATA1 and REDATA2; REDATA1 and REDATA2 are used to connect the second trigger circuit, so that the second trigger circuit generates an insulated gate bipolar transistor driving signal; U3 and U1 are optical fiber connection sending ports, which are used to convert the electrical signals OUTPUT1 and OUTPUT2 of the second trigger circuit into optical signals; and send the OUTPUT1 and OUTPUT2 signals to the microprocessor; U3 and U1 adopt the optical fiber sending port model HFBR1414 produced by AVAGO TECHNOLOGIES;

[0169] like Fig.14 As shown, the second trigger circuit is used to provide a driving signal to the insulated gate bipolar transistor; the second trigger circuit is mainly composed of an insulated gate bipolar transistor driving chip, and two driving chips are used; the driving chip of the embodiment adopts M57962L produced by MITSUBISHI ELECTRIC of Japan; the peripheral circuit of M57962L is designed according to the data sheet of M57962L; the power supply of M57962L is provided by a DC / DC circuit according to its data sheet; a resistor is used to connect pin 5 and the gate drive, and the two gates are named BB1 and BB2 respectively; a diode is used to connect pin 1 and the collector drive, and pin 1 is connected to the positive electrode of the diode; the two collector drives are named CC1 and CC2 respectively;

[0170] The common point of the second trigger circuit is connected to the emitter, and the two transmitters are named EE1 and EE2 respectively; pin 14 is connected to the receiving end and connected to the optical receiving output of the second optical signal transceiver B; that is, REDATA1 is short-circuited to INPUT1, and REDATA2 is short-circuited to INPUT2; a diode is connected between pins 13 and 14, and the anode of the diode is connected to pin 14; pin 13 is connected to the common point; pin 8 is named OUTPUT1 and OUTPUT2, and is connected to the optical transmission input of the second optical signal transceiver B; OUTPUT1 and OUTPUT 2 are short-circuited to TXDATA1 and TXDATA2 of the second optical signal transceiver B respectively.

[0171] The IGBT module is a power module containing two insulated gate bipolar transistors, model: FF1800R17IP5.

[0172] A control method for an arc-free AC circuit breaker in a transformer area with synchronous compensation capability comprises the following steps:

[0173] S1, perform initialization operation through the initialization subroutine;

[0174] S2, calculating the trip criterion through the trip criterion calculation subroutine;

[0175] S3, determine whether the tripping criterion is equal to 1, if so, enter S4, if not, enter S5;

[0176] S4, perform tripping action through the tripping action subroutine and enter S5;

[0177] S5, calculating the compensation criterion through the compensation criterion calculation subroutine;

[0178] S6. In response to the compensation criterion being equal to 1, a compensation action is performed through a compensation action subroutine.

[0179] The S1 comprises the following sub-steps:

[0180] S11, set the low frequency interrupt clock to 100 milliseconds, set the high frequency interrupt clock to 100 microseconds, set the compensation clock to 50 microseconds, set the wireless communication module reading interface, and set the GPS module reading interface;

[0181] S12, setting a low-frequency interrupt condition, and setting a low-frequency interrupt subroutine to be called when the interrupt occurs, setting a high-frequency interrupt condition, and setting a high-frequency interrupt subroutine to be called when the interrupt occurs, setting a compensation interrupt condition, and setting a compensation interrupt subroutine to be called when the interrupt occurs;

[0182] S13. Set variables, including:

[0183] MA is used to represent the current time in seconds, with a value range of 0-59. HA is used to represent the current time in milliseconds, with a value range of 0-999. UA is used to represent the current time in microseconds, with a value range of 0-999. A0 is used to represent the moment when the voltage phase of phase A is zero, in milliseconds. CH is used to represent the high-frequency interruption counter, with a value range of 0-999. XY is used to represent the trip phase threshold, ZY is used to represent the trip impedance threshold, BY is used to represent the compensation threshold, TZ is used to represent the trip mark, and CVA is used to represent the sensor reading counter, with a value range of 0. ~999, CZQ is used to represent the cycle counter, the value range is 0~199, SUMV is used to represent the voltage summation, SUMI is used to represent the current summation, ZSUM is used to represent the impedance, the array VIN

[1000] is used to represent the current sensor reading value, the array FV

[1000] is used to represent the voltage floating point value, the array IIN

[1000] is used to represent the voltage sensor reading value, the array FI

[1000] is used to represent the current floating point value, PT is used to represent the time update data position, FTZ is used to represent the trip calculation variable, and FBZ is used to represent the compensation calculation variable;

[0184] S14, initialize variables, the initialized variables are specifically:

[0185] MA=0,HA=0,UA=0,A0=0,CH=0,PT=0,FTZ=0,FBZ=0,TZ=0,XY=0,ZY=0,BY=0,CVA=0,CZQ=0,SUMV=0,SUMI=0,ZSUM=0,VIN

[1000] is initialized to all zeros, and IIN

[1000] is initialized to all zeros;

[0186] In S12, the method of calling the low-frequency interrupt subroutine is specifically as follows:

[0187] SA1, read the data of the wireless communication module 6, parse the read data according to the wireless communication protocol, and update the A0, XY, ZY and BY variables;

[0188] The wireless communication protocol is arranged by bytes, in the following order: 55, AA, A0 high eight bits, A0 low eight bits, XY high eight bits, XY low eight bits, ZY high eight bits, ZY low eight bits, BY high eight bits, BY low eight bits, check bit, 33, CC;

[0189] Among them, 55, AA indicate the start of the communication packet, 33, CC indicate the end of the communication packet, and the check bits are A0 high eight bits, A0 low eight bits, XY high eight bits, XY low eight bits, ZY high eight bits, ZY low eight bits, BY high eight bits, BY low eight bits, which are bit-wise XORed;

[0190] SA2, read the data from GPS module 5, parse the read data according to the GPS communication protocol, and update the MA, HA and UA variables;

[0191] The GPS communication protocol is arranged by bytes, in the following order: 55, AA, MA, HA high eight bits, HA low eight bits, check bit, 33, CC;

[0192] Among them, 55, AA indicates the beginning of the communication packet, 33, CC indicates the end of the communication packet; the check bit is MA, HA high eight bits, HA low eight bits bit by bit XOR;

[0193] SA3, assign the value of CVA to PT;

[0194] In S12, the method of calling the high-frequency interrupt subroutine is specifically as follows:

[0195] SB1, assign the storage value of the memory corresponding to voltage sensor 1 to VIN[CVA], assign the storage value of the memory corresponding to current sensor 2 to IIN[CVA], and add 1 to CVA;

[0196] SB2. In response to CVA being equal to 1000, set CVA=0, FBZ=1;

[0197] The specific method of calling the compensation interrupt subroutine is:

[0198] Set the compensation action judgment parameter CBuchang=0, and judge whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang];

[0199] If so, the compensation action is: control the IGBT module (103-2) to be turned on, and control the IGBT module (103-3) to be turned off;

[0200] If not, the compensation action is: control the IGBT module (103-2) to be turned off, and control the IGBT module (103-3) to be turned on.

[0201] The S2 comprises the following sub-steps:

[0202] S21, let CZQ equal the remainder of CVA with respect to 200,

[0203] S22, in response to CZQ being less than 50, setting FTZ=1;

[0204] S23, determine whether CZQ is greater than 197, if so, and FTZ is equal to 1, then go to step S24; if not, then go to step S3;

[0205] S24, set FTZ=0;

[0206] S25. For i = 0 to 199, calculate:

[0207] FV[i] = (VIN[CVA - 197 + i] – 32768) / 32768;

[0208] FI[i] = (IIN[CVA - 197 + i] – 32768) / 32768;

[0209] S26. Calculate ZSUM, specifically:

[0210] ZSUM = SUMV / SUMI

[0211] Where,

[0212] S27. Determine whether ZSUM is less than ZY. If so, set the tripping criterion TZ = 1; if not, set the tripping criterion TZ = 0.

[0213] The said S4 includes the following sub - steps:

[0214] S41. Control the thyristor 8 to conduct;

[0215] S42. Control the mechanical circuit breaker 3 to disconnect;

[0216] S43. Control the thyristor 3 to disconnect.

[0217] The said S5 includes the following sub - steps:

[0218] S51. Take 300 sample points before the current IIN sampling data through INDATA

[300] . The sampling method is specifically:

[0219] Judge whether CAV is greater than or equal to 300. If so, set the INDATA data to IIN[CAV - 300] to IIN[CAV]; if not, set the data of INDATA

[300] to the concatenation of two segments of data, IIN[1000 - CAV] to IIN

[1000] and IIN[0] to IIN[CAV];

[0220] S52. In the range of i = 0 to 100, find the first i that simultaneously satisfies INDATA[i]*INDATA[i + 4] < 0 and INDATA[i] < INDATA[i + 4], and set j = i;

[0221] S53. Calculate the first summation parameter SUMF1, specifically:

[0222]

[0223] In the formula, M1data[i] is a preset first parameter;

[0224] S54, taking k=1-25, searching for the maximum value MaxSumF2 in the second sum parameter SUMF2[k], wherein the expression for calculating the second sum parameter SUMF2[k] is specifically:

[0225]

[0226] Wherein, M2data[i] is the preset second parameter;

[0227] Calculate the second compensation sub-criterion BiF2, BiF2 = MaxSumF2 / SUMF1, and determine whether the second compensation sub-criterion BiF2 is greater than 0.03. If so, set the second compensation parameter BuChangF2 = 1; if not, set the second compensation parameter BuChangF2 = 0;

[0228] S55, taking k=1-15, searching for the maximum value MaxSumF3 in the third sum parameter SUMF3[k], wherein the expression for calculating the third sum parameter SUMF3[k] is specifically:

[0229]

[0230] Wherein, M3data[i] is the preset third parameter, and m is the remainder obtained by dividing i by 66;

[0231] Calculate the third compensation sub-criterion BiF3, BiF3 = MaxSumF3 / SUMF1, and determine whether the third compensation sub-criterion BiF3 is greater than 0.03. If so, set the third compensation parameter BuChangF3 = 1; if not, set the third compensation parameter BuChangF3 = 0;

[0232] S56, taking k=1-12, searching for the maximum value MaxSumF4 in the fourth sum parameter SUMF4[k], wherein the expression for calculating the fourth sum parameter SUMF4[k] is specifically:

[0233]

[0234] Wherein, M4data[i] is the preset fourth parameter, and m is the remainder obtained by dividing i by 50;

[0235] Calculate the fourth compensation sub-criterion BiF4, BiF4 = MaxSumF4 / SUMF1, and determine whether the fourth compensation sub-criterion BiF4 is greater than 0.03. If so, set the fourth compensation parameter BuChangF4 = 1; if not, set the fourth compensation parameter BuChangF4 = 0;

[0236] S57, taking k=1-10, searching for the maximum value MaxSumF5 in the fifth sum parameter SUMF5[k], wherein the expression for calculating the fifth sum parameter SUMF5[k] is specifically:

[0237]

[0238] Wherein, M5data[i] is the preset fifth parameter, and m is the remainder obtained by dividing i by 40;

[0239] Calculate the fifth compensation sub-criterion BiF5, BiF5=MaxSumF5 / SUMF1, and determine whether the fifth compensation sub-criterion BiF5 is greater than 0.03. If so, set the fifth compensation parameter BuChangF5=1; if not, set the fifth compensation parameter BuChangF5=0;

[0240] S58, calculating the first compensation parameter BuChang by the following formula;

[0241] BuChang=BuChangF2+BuChangF3+BuChangF4+BuChangF5

[0242] It is determined whether the first compensation parameter BuChang is greater than 1. If so, the compensation criterion BZ=1; if not, the compensation criterion BZ=0.

[0243] In S5, the first to fifth parameters are adaptively set according to actual circuit breaker control requirements.

[0244] In S6, the method of performing the compensation action through the compensation action subroutine is specifically as follows:

[0245] S61, determine whether the second compensation parameter BuChangF2 is equal to 1, if not, set the second compensation action parameter bcDataF2[i]=0, where i is 0-399;

[0246] If yes, the second compensation action parameters bcDataF2[2*i], bcDataF2[2*i+1], bcDataF2

[199] and bcDataF2[i+200] are calculated by the following formula;

[0247] bcDataF2[2*i]=-1*BiF2*M2data[i], where i is 0 to 99;

[0248] bcDataF2[2*i+1]=(bcDataF2[2*i]+bcDataF2[2*i+2]) / 2, where i is 0 to 98;

[0249] bcDataF2

[199] =(bcDataF2[0]+bcDataF2

[198] ) / 2;

[0250] bcDataF2[i+200]=bcDataF2[i], where i is 0 to 199;

[0251] S62, determine whether the third compensation parameter BuChangF3 is equal to 1, if not, set the third compensation action parameter bcDataF3[i]=0, where i is 0-399;

[0252] If so, the third compensation action parameters bcDataF3[2*i], bcDataF3[2*i+1], bcDataF3

[131] , bcDataF3

[132] , bcDataF3[i+133], bcDataF3

[266] and bcDataF3[i+267] are calculated by the following formula;

[0253] bcDataF3[2*i]=-1*BiF3*M3data[i], where i is 0 to 65;

[0254] bcDataF3[2*i+1]=(bcDataF3[2*i]+bcDataF3[2*i+2]) / 2, where i ranges from 0 to 64;

[0255] bcDataF3

[131] =(bcDataF3[0]+bcDataF3

[130] ) / 2;

[0256] bcDataF3

[132] =bcDataF3

[131] ;

[0257] bcDataF3[i+133]=bcDataF3[i], where i is 0 to 132;

[0258] bcDataF3

[266] =bcDataF3

[265] ;

[0259] bcDataF3[i+267]=bcDataF3[i], where i is 0 to 132;

[0260] S63, determine whether the fourth compensation parameter BuChangF4 is equal to 1, if not, set the fourth compensation action parameter bcDataF4[i]=0, where i is 0-399;

[0261] If yes, the fourth compensation action parameters bcDataF4[2*i], bcDataF4[2*i+1], bcDataF4

[99] , bcDataF4[i+100] and bcDataF4[i+200] are calculated by the following formula;

[0262] bcDataF4[2*i]=-1*BiF4*M4data[i], where i is 0 to 49;

[0263] bcDataF4[2*i+1]=(bcDataF4[2*i]+bcDataF4[2*i+2]) / 2, where i ranges from 0 to 48;

[0264] bcDataF4

[99] =(bcDataF4[0]+bcDataF4

[98] ) / 2;

[0265] bcDataF4[i+100]=bcDataF4[i], where i is 0 to 99;

[0266] bcDataF4[i+200]=bcDataF4[i], where i is 0 to 199;

[0267] S64, determine whether the fifth compensation parameter BuChangF5 is equal to 1, if not, set the fifth compensation action parameter bcDataF5[i]=0, where i is 0-399;

[0268] If yes, the fifth compensation action parameters bcDataF5[2*i], bcDataF5[2*i+1], bcDataF5

[79] , bcDataF5[i+80], bcDataF5[i+160] and bcDataF5[i+320] are calculated by the following formula;

[0269] bcDataF5[2*i]=-1*BiF5*M5data[i], where i ranges from 0 to 39;

[0270] bcDataF5[2*i+1]=(bcDataF5[2*i]+bcDataF5[2*i+2]) / 2, where i ranges from 0 to 38;

[0271] bcDataF5

[79] =(bcDataF5[0]+bcDataF5

[78] ) / 2;

[0272] bcDataF5[i+80]=bcDataF5[i], where i is 0 to 79;

[0273] bcDataF5[i+160]=bcDataF6[i], where i is 0 to 159;

[0274] bcDataF5[i+320]=bcDataF6[i], where i is 0 to 79;

[0275] S65, calculating a first compensation action parameter BuChangV by the following formula, and performing a compensation action according to the first compensation action parameter BuChangV;

[0276] BuChangV=bcDataF2[i]+bcDataF3[i]+bcDataF4[i]+bcDataF5[i], where i ranges from 0 to 399.

[0277] In S6, the comparison variable BiJiao is adaptively set according to the actual circuit breaker control demand. The expression of the preset comparison variable BiJiao in this embodiment is specifically:

[0278] BiJiao

[10] ={-1,-0.6,-0.2,0.2,0.6,1,0.6,0.2,-0.2,-0.6}

[0279] Where i is 0 to 399, m is the remainder of i divided by 10, BiJiaoV[i] = BiJiao[m];

[0280] In the description of the present invention, it is necessary to understand that the orientation or positional relationship indicated by the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used only for descriptive purposes, and cannot be understood as indicating or implying the relative importance or the number of implicitly specified technical features. Therefore, the features defined by "first", "second", and "third" may explicitly or implicitly include one or more of the features.

Claims

1. A non-arcing AC circuit breaker with synchronous compensation capability, characterized in that: It comprises a voltage sensor (1), a current sensor (2), a mechanical circuit breaker (3), a power quality regulation module (4), a GPS module (5), a wireless communication module (6), a thyristor drive circuit (7), a thyristor (8) and a microprocessor (9); The microprocessor (9) is connected to the voltage sensor (1), the current sensor (2), the mechanical circuit breaker (3), the power quality regulation module (4), the GPS module (5), the wireless communication module (6) and the thyristor drive circuit (7), and the thyristor drive circuit (7) is connected to the thyristor (8); The voltage sensor (1) is used to collect the three-phase voltage values ​​output by the transformer in the substation area; the current sensor (2) is used to collect the three-phase current values ​​output by the transformer in the substation area; the GPS module (5) is used to provide a clock signal for the microprocessor (9); the wireless communication module (6) is used to provide control information for the microprocessor (9); the microprocessor (9) is used to calculate the substation area operation state according to the three-phase voltage and current values ​​output by the transformer in the substation area, the clock signal and the control information; and the mechanical circuit breaker (3), the thyristor drive circuit (7) and the power quality adjustment module (4) are controlled according to the calculation result; the thyristor (8) is used to control the current.

2. The arc-free AC circuit breaker with synchronous compensation capability according to claim 1, characterized in that: The power quality regulation module (4) comprises power quality regulation submodules arranged on three phases, and the power quality regulation submodules arranged on each phase have the same structure, and all comprise a grid-side inductor (21), a load-side inductor (22), an inverter inductor (23), a filter inductor (24), an inverter (25) and a filter capacitor (26); One end of the grid-side inductor (21) is connected to the mechanical circuit breaker (3), the other end of the grid-side inductor (21) is respectively connected to one end of the load-side inductor (22), one end of the inverter inductor (23) and one end of the filter inductor (24), the other end of the inverter inductor (23) is connected to the inverter (25), the other end of the filter inductor (24) is grounded via a filter capacitor (26), and the other end of the load-side inductor (22) is connected to the substation load.

3. The arc-free AC circuit breaker with synchronous compensation capability according to claim 2, characterized in that: The power quality regulation module (4) is also provided with a three-phase inverter, including an energy storage capacitor A (51), an energy storage capacitor B (52), a neutral line inverter (53), an A-phase inverter (54), a B-phase inverter (55) and a C-phase inverter (56); One end of the energy storage capacitor A (51) is respectively connected to the No. 2 connection terminal of the neutral line inverter (53), the No. 2 connection terminal of the A phase inverter (54), the No. 2 connection terminal of the B phase inverter (55) and the No. 2 connection terminal of the C phase inverter (56); the other end of the energy storage capacitor A (51) is respectively connected to one end of the energy storage capacitor B (52), the No. 1 connection terminal of the neutral line inverter (53), the No. 1 connection terminal of the A phase inverter (54), the No. 1 connection terminal of the B phase inverter (55) and the No. 1 connection terminal of the C phase inverter (56); The other end of the energy storage capacitor B (52) is respectively connected to the No. 3 connection terminal of the neutral line inverter (53), the No. 3 connection terminal of the A phase inverter (54), the No. 3 connection terminal of the B phase inverter (55) and the No. 3 connection terminal of the C phase inverter (56); the No. 3 connection terminal of the neutral line inverter (53) is connected to the neutral line, the No. 3 connection terminal of the A phase inverter (54) is connected to the inverter inductor (23) on the A phase, the No. 3 connection terminal of the B phase inverter (55) is connected to the inverter inductor (23) on the B phase, and the No. 3 connection terminal of the C phase inverter (56) is connected to the inverter inductor (23) on the C phase.

4. The arc-free AC circuit breaker with synchronous compensation capability according to claim 3, characterized in that: The neutral line inverter (53), the A-phase inverter (54), the B-phase inverter (55) and the C-phase inverter (56) have the same structure, and all include an upper arm diode (101), a lower arm diode (102), a first IGBT module (103-1), a second IGBT module (103-2), a third IGBT module (103-3), a fourth IGBT module (103-4), a first IGBT drive module (104-1), a second IGBT drive module (104-2), a third IGBT drive module (104-3), a fourth IGBT drive module (104-4), a connection port Q1 (105-1), a connection port Q2 (105-2), a connection port Q3 (105-3), a connection port Q4 (105-4), a No. 1 connection terminal (106), a No. 2 connection terminal (107), a No. 3 connection terminal (108) and a No. 4 connection terminal (109); The gate of the first IGBT module (103-1) is connected to the connection port Q1 (105-1) through the first IGBT driving module (104-1), the collector of the first IGBT module (103-1) is connected to the No. 2 connection terminal (107), and the emitter of the first IGBT module (103-1) is respectively connected to the collector of the second IGBT module (103-2) and the cathode of the upper arm diode (101); The gate of the second IGBT module (103-2) is connected to the connection port Q2 (105-2) through the second IGBT driving module (104-2), and the emitter of the second IGBT module (103-2) is respectively connected to the collector of the third IGBT module (103-3) and the No. 4 connection terminal (109); The gate of the third IGBT module (103-3) is connected to the connection port Q3 (105-3) through the third IGBT driving module (104-3), the emitter of the third IGBT module (103-3) is respectively connected to the anode of the lower arm diode (102) and the collector of the fourth IGBT module (103-4), and the cathode of the lower arm diode (102) is respectively connected to the anode of the upper arm diode (101) and the No. 1 connection terminal (106); The gate of the fourth IGBT module (103-4) is connected to the connection port Q4 (105-4) through the fourth IGBT driving module (104-4), and the emitter of the fourth IGBT module (103-4) is connected to the No. 3 connection terminal (108).

5. The control method according to any one of claims 1 to 4 is applied to a non-arcing AC circuit breaker in a transformer area with synchronous compensation capability, characterized in that: The following steps are involved: S1, perform initialization operation through the initialization subroutine; S2, calculating the trip criterion through the trip criterion calculation subroutine; S3, determine whether the tripping criterion is equal to 1, if so, enter S4, if not, enter S5; S4, perform tripping action through the tripping action subroutine and enter S5; S5, calculating the compensation criterion through the compensation criterion calculation subroutine; S6. In response to the compensation criterion being equal to 1, a compensation action is performed through a compensation action subroutine.

6. The control method according to claim 5, characterized in that: The S1 comprises the following sub-steps: S11, setting the low frequency interrupt clock to 100 milliseconds, setting the high frequency interrupt clock to 100 microseconds, setting the compensation clock to 50 microseconds, setting the wireless communication module (6) reading interface, and setting the GPS module (5) reading interface; S12, setting a low-frequency interrupt condition, and setting a low-frequency interrupt subroutine to be called when the interrupt occurs, setting a high-frequency interrupt condition, and setting a high-frequency interrupt subroutine to be called when the interrupt occurs, setting a compensation interrupt condition, and setting a compensation interrupt subroutine to be called when the interrupt occurs; S13. Set variables, including: MA is used to represent the current time in seconds, with a value range of 0-59. HA is used to represent the current time in milliseconds, with a value range of 0-999. UA is used to represent the current time in microseconds, with a value range of 0-999. A0 is used to represent the moment when the voltage phase of phase A is zero, in milliseconds. CH is used to represent the high-frequency interruption counter, with a value range of 0-999. XY is used to represent the trip phase threshold, ZY is used to represent the trip impedance threshold, BY is used to represent the compensation threshold, TZ is used to represent the trip mark, and CVA is used to represent the sensor reading counter, with a value range of 0. ~999, CZQ is used to represent the cycle counter, the value range is 0~199, SUMV is used to represent the voltage summation, SUMI is used to represent the current summation, ZSUM is used to represent the impedance, the array VIN[1000] is used to represent the current sensor reading value, the array FV[1000] is used to represent the voltage floating point value, the array IIN[1000] is used to represent the voltage sensor reading value, the array FI[1000] is used to represent the current floating point value, PT is used to represent the time update data position, FTZ is used to represent the trip calculation variable, and FBZ is used to represent the compensation calculation variable; S14, initialize variables, the initialized variables are specifically: MA=0,HA=0,UA=0,A0=0,CH=0,PT=0,FTZ=0,FBZ=0,TZ=0,XY=0,ZY=0,BY=0,CVA=0,CZQ=0,SUMV=0,SUMI=0,ZSUM=0,VIN[1000] is initialized to all zeros, and IIN[1000] is initialized to all zeros; S15, setting a first parameter M1data, a second parameter M2data, a third parameter M3data, a fourth parameter M4data, a fifth parameter M5data and a comparison variable BiJiao; In S12, the method of calling the low-frequency interrupt subroutine is specifically as follows: SA1, read the data from the wireless communication module (6), parse the read data according to the wireless communication protocol, and update the A0, XY, ZY and BY variables; The wireless communication protocol is arranged by bytes, in the following order: 55, AA, A0 high eight bits, A0 low eight bits, XY high eight bits, XY low eight bits, ZY high eight bits, ZY low eight bits, BY high eight bits, BY low eight bits, check bit, 33, CC; Among them, 55, AA indicate the start of the communication packet, 33, CC indicate the end of the communication packet, and the check bits are A0 high eight bits, A0 low eight bits, XY high eight bits, XY low eight bits, ZY high eight bits, ZY low eight bits, BY high eight bits, BY low eight bits, which are bit-wise XORed; SA2, read the data from the GPS module (5), parse the read data according to the GPS communication protocol, and update the MA, HA and UA variables; The GPS communication protocol is arranged by bytes, in the following order: 55, AA, MA, HA high eight bits, HA low eight bits, check bit, 33, CC; Among them, 55, AA indicates the beginning of the communication packet, 33, CC indicates the end of the communication packet; the check bit is MA, HA high eight bits, HA low eight bits bit by bit XOR; SA3, assign the value of CVA to PT; In S12, the method of calling the high-frequency interrupt subroutine is specifically as follows: SB1, assign the storage value of the memory corresponding to the voltage sensor (1) to VIN[CVA], assign the storage value of the memory corresponding to the current sensor (2) to IIN[CVA], and add 1 to CVA; SB2. In response to CVA being equal to 1000, set CVA=0, FBZ=1; The specific method of calling the compensation interrupt subroutine is: Set the compensation action judgment parameter CBuchang=0, and judge whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang]; If so, the compensation action is: control the IGBT module (103-2) to be turned on, and control the IGBT module (103-3) to be turned off; If not, the compensation action is: control the IGBT module (103-2) to be turned off, and control the IGBT module (103-3) to be turned on.

7. The control method according to claim 6, characterized in that: The S2 comprises the following sub-steps: S21, let CZQ equal the remainder of CVA with respect to 200, S22, in response to CZQ being less than 50, setting FTZ=1; S23, determine whether CZQ is greater than 197, if so, and FTZ is equal to 1, then go to step S24; if not, then go to step S3; S24, set FTZ=0; S25. For i=0-199, calculate: FV[i]=(VIN[CVA-197+i]–32768) / 32768; FI[i]=(IIN[CVA-197+i]–32768) / 32768; S26. Calculate ZSUM, specifically: ZSUM = SUMV / SUMI in, S27. Determine whether ZSUM is less than ZY. If so, set the tripping criterion TZ = 1; if not, set the tripping criterion TZ = 0.

8. The control method according to claim 7, characterized in that: The said S4 includes the following sub-steps: S41. Control the thyristor (8) to conduct; S42. Control the mechanical circuit breaker (3) to disconnect; S43. Control the thyristor (3) to disconnect.

9. The control method according to claim 8, characterized in that: The said S5 includes the following sub-steps: S51. Take 300 sample points before the current IIN sampling data through INDATA[300]. The sampling method is specifically as follows: Judge whether CAV is greater than or equal to 300. If so, let the INDATA data take IIN[CAV - 300] to IIN[CAV]; if not, let the data of INDATA[300] take the concatenation of two segments of data, namely IIN[1000 - CAV] to IIN[1000] and IIN[0] to IIN[CAV]; S52. In the range of i = 0 to 100, find the first i that simultaneously satisfies INDATA[i] * INDATA[i + 4] < 0 and INDATA[i] < INDATA[i + 4], and let j = i; S53. Calculate the first summation parameter SUMF1, specifically as follows: In the formula, M1data[i] is a preset first parameter; S54. Take k = 1 to 25, and search for the maximum value MaxSumF2 in the second summation parameter SUMF2[k]. Among them, the expression for calculating the second summation parameter SUMF2[k] is specifically as follows: In the formula, M2data[i] is a preset second parameter; Calculate the second compensation sub-criterion BiF2, BiF2 = MaxSumF2 / SUMF1. Determine whether the second compensation sub-criterion BiF2 is greater than 0.

03. If so, set the second compensation parameter BuChangF2 = 1; if not, set the second compensation parameter BuChangF2 = 0; S55. Take k = 1 to 15, and search for the maximum value MaxSumF3 in the third summation parameter SUMF3[k]. Among them, the expression for calculating the third summation parameter SUMF3[k] is specifically as follows: In the formula, M3data[i] is a preset third parameter, and m is the remainder obtained by dividing i by 66; Calculate the third compensation sub-criterion BiF3, BiF3 = MaxSumF3 / SUMF1. Determine whether the third compensation sub-criterion BiF3 is greater than 0.

03. If so, set the third compensation parameter BuChangF3 = 1; if not, set the third compensation parameter BuChangF3 = 0; S56. Take k = 1 to 12, and search for the maximum value MaxSumF4 in the fourth summation parameter SUMF4[k]. Among them, the expression for calculating the fourth summation parameter SUMF4[k] is specifically as follows: In the formula, M4data[i] is a preset fourth parameter, and m is the remainder obtained by dividing i by 50; Calculate the fourth compensation sub-criterion BiF4, BiF4 = MaxSumF4 / SUMF1, and determine whether the fourth compensation sub-criterion BiF4 is greater than 0.

03. If so, set the fourth compensation parameter BuChangF4 = 1; if not, set the fourth compensation parameter BuChangF4 = 0; S57, taking k=1-10, searching for the maximum value MaxSumF5 in the fifth sum parameter SUMF5[k], wherein the expression for calculating the fifth sum parameter SUMF5[k] is specifically: Wherein, M5data[i] is the preset fifth parameter, and m is the remainder obtained by dividing i by 40; Calculate the fifth compensation sub-criterion BiF5, BiF5=MaxSumF5 / SUMF1, and determine whether the fifth compensation sub-criterion BiF5 is greater than 0.

03. If so, set the fifth compensation parameter BuChangF5=1; if not, set the fifth compensation parameter BuChangF5=0; S58, calculating the first compensation parameter BuChang by the following formula; BuChang=BuChangF2+BuChangF3+BuChangF4+BuChangF5 It is determined whether the first compensation parameter BuChang is greater than 1. If so, the compensation criterion BZ=1; if not, the compensation criterion BZ=0.

10. The control method according to claim 9, characterized in that: In S6, the method of performing the compensation action through the compensation action subroutine is specifically as follows: S61, determine whether the second compensation parameter BuChangF2 is equal to 1, if not, set the second compensation action parameter bcDataF2[i]=0, where i is 0-399; If yes, the second compensation action parameters bcDataF2[2*i], bcDataF2[2*i+1], bcDataF2[199] and bcDataF2[i+200] are calculated by the following formula; bcDataF2[2*i]=-1*BiF2*M2data[i], where i is 0 to 99; bcDataF2[2*i+1]=(bcDataF2[2*i]+bcDataF2[2*i+2]) / 2, where i is 0 to 98; bcDataF2[199]=(bcDataF2[0]+bcDataF2[198]) / 2; bcDataF2[i+200]=bcDataF2[i], where i is 0 to 199; S62, determine whether the third compensation parameter BuChangF3 is equal to 1, if not, set the third compensation action parameter bcDataF3[i]=0, where i is 0-399; If so, the third compensation action parameters bcDataF3[2*i], bcDataF3[2*i+1], bcDataF3[131], bcDataF3[132], bcDataF3[i+133], bcDataF3[266] and bcDataF3[i+267] are calculated by the following formula; bcDataF3[2*i]=-1*BiF3*M3data[i], where i is 0 to 65; bcDataF3[2*i+1]=(bcDataF3[2*i]+bcDataF3[2*i+2]) / 2, where i ranges from 0 to 64; bcDataF3[131]=(bcDataF3[0]+bcDataF3[130]) / 2; bcDataF3[132]=bcDataF3[131]; bcDataF3[i+133]=bcDataF3[i], where i is 0 to 132; bcDataF3[266]=bcDataF3[265]; bcDataF3[i+267]=bcDataF3[i], where i is 0 to 132; S63, determine whether the fourth compensation parameter BuChangF4 is equal to 1, if not, set the fourth compensation action parameter bcDataF4[i]=0, where i is 0-399; If yes, the fourth compensation action parameters bcDataF4[2*i], bcDataF4[2*i+1], bcDataF4[99], bcDataF4[i+100] and bcDataF4[i+200] are calculated by the following formula; bcDataF4[2*i]=-1*BiF4*M4data[i], where i is 0 to 49; bcDataF4[2*i+1]=(bcDataF4[2*i]+bcDataF4[2*i+2]) / 2, where i ranges from 0 to 48; bcDataF4[99]=(bcDataF4[0]+bcDataF4[98]) / 2; bcDataF4[i+100]=bcDataF4[i], where i is 0 to 99; bcDataF4[i+200]=bcDataF4[i], where i is 0 to 199; S64, determine whether the fifth compensation parameter BuChangF5 is equal to 1, if not, set the fifth compensation action parameter bcDataF5[i]=0, where i is 0-399; If yes, the fifth compensation action parameters bcDataF5[2*i], bcDataF5[2*i+1], bcDataF5[79], bcDataF5[i+80], bcDataF5[i+160] and bcDataF5[i+320] are calculated by the following formula; bcDataF5[2*i]=-1*BiF5*M5data[i], where i ranges from 0 to 39; bcDataF5[2*i+1]=(bcDataF5[2*i]+bcDataF5[2*i+2]) / 2, where i ranges from 0 to 38; bcDataF5[79]=(bcDataF5[0]+bcDataF5[78]) / 2; bcDataF5[i+80]=bcDataF5[i], where i is 0 to 79; bcDataF5[i+160]=bcDataF6[i], where i is 0 to 159; bcDataF5[i+320]=bcDataF6[i], where i is 0 to 79; S65, calculating a first compensation action parameter BuChangV by the following formula, and performing a compensation action according to the first compensation action parameter BuChangV; BuChangV=bcDataF2[i]+bcDataF3[i]+bcDataF4[i]+bcDataF5[i], where i ranges from 0 to 399.

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