Transformer area arc-free circuit breaker with filtering capability and control method

Abstract

The invention discloses a transformer area arc-free circuit breaker with filtering capability and a control method. The transformer area arc-free circuit breaker is connected with a voltage sensor, a current sensor, a mechanical circuit breaker, a filtering module, a wireless communication module and a first IGBT driving circuit through a microprocessor. The microprocessor receives sensing signals of the voltage sensor and the current sensor and control information of the wireless communication module; according to the sensing signals of the voltage sensor and the current sensor and the control information of the wireless communication module, the operation state of the transformer area is calculated, and the mechanical circuit breaker, the first IGBT driving circuit and the filtering module are controlled according to the calculation result. The problem that a traditional circuit breaker cannot meet the new energy requirements of more and more photovoltaic and charging piles and the like in a transformer area is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit breakers, and in particular relates to an arc-free circuit breaker with filtering capability and a control method thereof. Background Art

[0002] Current inventions or utility models have proposed arc-free AC circuit breaker design schemes, such as an intelligent arc-free circuit breaker with patent number ZL200520096776.4, a three-phase arc-free circuit breaker with application number 201020652885.0, a high-breakage arc-free circuit breaker with application number CN201710544678.X, and an arc-extinguishing module for an arc-free miniature circuit breaker with application number 202221641724.0, but all of them have certain defects. Due to the use of new energy, there are more and more charging piles and rooftop photovoltaics in the substation area, and the power quality in the substation area is getting worse and worse. The traditional circuit breaker breaking decision can no longer meet the increasing new energy needs in the substation area. The access to new energy also puts forward new demands for arc-free AC circuit breakers. The present invention designs an arc-free circuit breaker based on the increasing demand for new energy access in existing substations. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present invention provides an arc-free circuit breaker with filtering capability and a control method for a transformer substation, which solves the problem that traditional circuit breakers can no longer meet the increasing demand for new energy sources such as photovoltaics and charging piles in transformer substations.

[0004] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: an arc-free circuit breaker in a transformer area with filtering capability, comprising a voltage sensor, a current sensor, a mechanical circuit breaker, a filtering module, a wireless communication module, a microprocessor, a first IGBT driving circuit and a first IGBT;

[0005] The voltage sensor, the current sensor, the mechanical circuit breaker and the filter module are connected in sequence, the microprocessor is respectively connected to the voltage sensor, the current sensor, the mechanical circuit breaker and the filter module, the wireless communication module and the first IGBT drive circuit, the first IGBT drive circuit is also connected to the first IGBT, one end of the first IGBT is respectively connected to the current sensor and the mechanical circuit breaker, and the other end of the first IGBT is respectively connected to the mechanical circuit breaker and the filter module;

[0006] The voltage sensor is used to collect the three-phase voltage value output by the substation transformer, the current sensor is used to collect the three-phase current value output by the substation transformer, the wireless communication module is used to receive the control information of the substation circuit breaker, the microprocessor is used to calculate the substation operation status according to the three-phase voltage and current values, clock signals and control information output by the substation transformer, and the mechanical circuit breaker, the first IGBT drive circuit and the filter module are controlled according to the calculation results. The thyristor is used to control the current.

[0007] Further: the filter module includes a grid-side inductor, a grid-side resistor, a neutral line resistor, a neutral line capacitor, a filter controller, a filter resistor, a filter inductor, a load-side resistor, and a load-side inductor;

[0008] Among them, one end of the grid-side inductance is connected to the mechanical circuit breaker, the other end of the grid-side inductance is connected to one end of the grid-side resistor, the other end of the grid-side resistor is respectively connected to one end of the neutral line resistor, one end of the filter inductance and one end of the load-side resistor, the other end of the neutral line resistor is connected to the neutral line through the neutral line capacitor, the other end of the filter inductance is connected to the filter controller through the filter resistor, and the other end of the load-side resistor is connected to the substation load through the load-side inductance.

[0009] Further: the filter controller includes a voltage conversion circuit, an upper voltage-controlled capacitor, a lower voltage-controlled capacitor, an output capacitor, a current-controlled inductor, an output inductor, an input positive terminal switch, an output positive terminal switch, an output negative terminal switch, an input negative terminal switch, a switching switch, a positive terminal bridge switch, a positive left interconnection switch, a positive right interconnection switch, a negative left interconnection switch, a negative right interconnection switch, a negative terminal bridge switch, a negative terminal bridge output switch, and a positive terminal bridge output switch;

[0010] The connection terminals A, B and C of the voltage conversion circuit are connected to the power supply A phase, the power supply B phase and the power supply C phase one by one, respectively; the connection terminal N of the voltage conversion circuit is connected to the power supply neutral line, the emitter of the output negative end switch and the input negative end switch, respectively; the connection terminal D of the voltage conversion circuit is connected to the collector of the input positive end switch and the collector of the output positive end switch, respectively; the emitter of the input positive end switch is connected to the emitter of the positive end bridge switch, the collector of the switching switch and the collector of the positive left interconnection switch, respectively; the emitter of the output positive end switch is connected to the collector of the output negative end switch, one end of the output capacitor and the output negative electrode, respectively; the collector of the positive end bridge switch is connected to the collector of the positive end bridge output switch and one end of the upper voltage control capacitor, respectively; the emitter of the positive left interconnection switch is connected to the emitter of the positive right interconnection switch, and the collector of the positive right interconnection switch is connected to the other end of the upper voltage control capacitor and one end of the current control inductor;

[0011] The collector of the input negative switch is respectively connected to the collector of the negative bridge switch, the emitter of the switching switch and the collector of the negative left interconnected switch, the emitter of the negative left interconnected switch is connected to the emitter of the negative right interconnected switch, the collector of the negative right interconnected switch is respectively connected to one end of the lower voltage-controlled capacitor and the other end of the current-controlled inductor, the emitter of the negative bridge switch is connected to the other end of the lower voltage-controlled capacitor and the emitter of the negative bridge output switch, the collector of the negative bridge output switch is respectively connected to the emitter of the positive bridge output switch and one end of the output inductor, and the other end of the output inductor is respectively connected to the other end of the output capacitor and the output positive electrode.

[0012] Further: the voltage conversion circuit includes a first power diode, a second power diode, a third power diode, a connection terminal A, a connection terminal B, a connection terminal C, a connection terminal D and a connection terminal N;

[0013] Among them, the cathode of the first power diode, the cathode of the second power diode and the cathode of the third power diode are all connected to the connection terminal D, and the anode of the first power diode, the anode of the second power diode and the anode of the third power diode are respectively connected to the connection terminal A, the connection terminal B and the connection terminal C one by one.

[0014] Further: the input positive switch, the output positive switch, the output negative switch, the input negative switch, the switching switch, the positive bridge switch, the positive left interconnection switch, the positive right interconnection switch, the negative left interconnection switch, the negative right interconnection switch, the negative bridge switch, the negative bridge output switch and the positive bridge output switch have the same structure, and include: a second IGBT driver and a second IGBT;

[0015] The second IGBT driver is connected to the microprocessor and the gate of the second IGBT respectively.

[0016] A control method for a non-arc circuit breaker in a transformer area with filtering capability comprises the following steps:

[0017] S1, perform initialization operation through the initialization subroutine;

[0018] S2, in response to startF being equal to 1, calling the tripping and compensation calculation subroutine to calculate the tripping criterion;

[0019] S3. In response to the tripping criterion being equal to 1, the tripping action subroutine is called to perform a tripping action.

[0020] Further: S1 comprises the following sub-steps:

[0021] S11, set the low-frequency interrupt clock to 20 milliseconds and the high-frequency interrupt clock to 50 microseconds;

[0022] S12, setting a low-frequency interrupt condition, and setting a low-frequency interrupt subroutine to be called when an interrupt occurs; setting a high-frequency interrupt condition, and setting a high-frequency interrupt subroutine to be called when an interrupt occurs;

[0023] S13. Set variables, including:

[0024] A phase voltage phase zero millisecond counter, A phase voltage phase zero microsecond counter, high frequency interrupt counter represented by CH, value range: 0 to 999, trip voltage threshold represented by VY, trip current threshold represented by IY, compensation threshold represented by BY, trip mark represented by TZ, sensor reading counter represented by CVA, value range: 0 to 999, cycle counter represented by CZQ, value range: 0 to 199, voltage sum represented by SUMV, voltage minimum represented by MINSUMV, voltage minimum threshold represented by MINSUMVG, current sum represented by SUMI, current maximum represented by MAXSUMI, current maximum threshold represented by MAXSUMIG;

[0025] The first reading value of phase A of the voltage sensor is represented by the array AVINA

[400] , the second reading value of phase A of the voltage sensor is represented by the array AVINB

[400] , the floating point value of phase A voltage is represented by the array AFV

[400] , the first reading value of phase A of the current sensor is represented by the array AIINA

[400] , the second reading value of phase A of the current sensor is represented by the array AIINB

[400] , the floating point value of phase A current is represented by the array AFI

[400] , and the compensation of phase A is represented by the array AVBZ

[400] ;

[0026] The B-phase first reading value of the voltage sensor is represented by the array BVINA

[400] , the B-phase second reading value of the voltage sensor is represented by the array BVINB

[400] , the B-phase voltage floating point value is represented by the array BFV

[400] , the B-phase first reading value of the current sensor is represented by the array BIINA

[400] , the B-phase second reading value of the current sensor is represented by the array BIINB

[400] , the B-phase current floating point value is represented by the array BFI

[400] , and the B-phase compensation is represented by the array BVBZ

[400] ;

[0027] The first reading value of the C phase of the voltage sensor is represented by the array CVINA

[400] , the second reading value of the C phase of the voltage sensor is represented by the array CVINB

[400] , the floating point value of the C phase voltage is represented by the array CFV

[400] , the first reading value of the C phase of the current sensor is represented by the array CIINA

[400] , the second reading value of the C phase of the current sensor is represented by the array CIINB

[400] , the floating point value of the C phase current is represented by the array CFI

[400] , and the C phase compensation is represented by the array CVBZ

[400] ;

[0028] The time update data position is represented by PT, the trip calculation variable is represented by FTZ, the trip calculation variable is represented by TZF, the compensation calculation variable is represented by FBZ, the low frequency interrupt mark is represented by FZD, the storage selection mark is represented by SELF, the loop counter is represented by CNTCNN, the start calculation mark is represented by startF, the A phase impedance is represented by AZK, the B phase impedance is represented by BZK, the C phase impedance is represented by CZK, the minimum impedance is represented by MINZK, the impedance trip threshold is represented by ZKYZ, the A phase compensation sum is represented by ASUMBZ, the B phase compensation sum is represented by BSUMBZ, the C phase compensation sum is represented by CSUMBZ, the maximum compensation sum is represented by MAXSUMBZ, and the compensation threshold is represented by BZYZ;

[0029] S14, initialize variables, the initialized variables are specifically:

[0030] MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF=0, ACNTVI=0, BCNTVI=0, CCNTVI= 0, CNTCNN=0, startF=0, FZD=0; FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0;

[0031] AVINA, AVINB, BVINA, BVINB, CVINA, and CVINB are initialized to all zeros;

[0032] S15. Set the first parameter M1data and the comparison variable BiJiao.

[0033] Further: In said S11, the method of calling the low-frequency interrupt subroutine is specifically as follows:

[0034] A1. Determine whether SELF is false. If so, set ACDATA[i] = AVINA[i], where i = 0 to 799, and enter A2;

[0035] If not, set ACDATA[i]=AVINB[i], where i=0-799, and enter A2;

[0036] A2. Invert SELF, and in response to the fact that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero, and AVINA[i+2] is greater than or equal to AVINA[i] in the range of i=2-401, set WZ=i and startF=1.

[0037] Further: In said S12, the method of calling the high-frequency interrupt subroutine is specifically as follows:

[0038] B1, determine whether SELF is false, if so, go to SB2;

[0039] If not, let AVINA be equal to the storage value of the memory corresponding to the voltage sensor, let AIINA be equal to the storage value of the memory corresponding to the current sensor, BVINA be equal to the storage value of the memory corresponding to the voltage sensor, let BIINA be equal to the storage value of the memory corresponding to the current sensor, CVINA be equal to the storage value of the memory corresponding to the voltage sensor, and let CIINA be equal to the storage value of the memory corresponding to the current sensor;

[0040] AFV[CNTCNN]=(AVINA–32768) / 32768

[0041] AFI[CNTCNN]=(AIINA–32768) / 32768

[0042] BFV[CNTCNN]=(BVINA–32768) / 32768

[0043] BFI[CNTCNN]=(BIINA–32768) / 32768

[0044] CFV[CNTCNN]=(CVINA–32768) / 32768

[0045] CFI[CNTCNN]=(CIINA–32768) / 32768

[0046] Enter B3;

[0047] B2. Let AVINB be equal to the storage value of the memory corresponding to the voltage sensor, let AIINB be equal to the storage value of the memory corresponding to the current sensor, BVINB be equal to the storage value of the memory corresponding to the voltage sensor, let BIINB be equal to the storage value of the memory corresponding to the current sensor, CVINB be equal to the storage value of the memory corresponding to the voltage sensor, and let CIINB be equal to the storage value of the memory corresponding to the current sensor;

[0048] AFV[CNTCNN]=(AVINB–32768) / 32768

[0049] AFI[CNTCNN]=(AIINB–32768) / 32768

[0050] BFV[CNTCNN]=(BVINB–32768) / 32768

[0051] BFI[CNTCNN]=(BIINB–32768) / 32768

[0052] CFV[CNTCNN]=(CVINB–32768) / 32768

[0053] CFI[CNTCNN]=(CIINB–32768) / 32768

[0054] Enter B3;

[0055] B3, add 1 to the value of CNTCNN, and in response to CNTCNN being greater than 800, set CNTCNN=0;

[0056] Enter B4;

[0057] B4, in response to FBZ being equal to 1, proceed to B5;

[0058] B5. Determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN-WZ; if not, set WZ1 = 400 + CNTCNN-WZ;

[0059] Enter B6;

[0060] B6. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0061] Enter B7;

[0062] B7, control the A phase circuit and enter B8;

[0063] B8. Add 133 to the WZ value to determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN-WZ; if not, set WZ1 = 400 + CNTCNN-WZ;

[0064] Enter B9;

[0065] B9, in response to WZ1 being greater than 400, subtract 400 from the value of WZ1;

[0066] Enter B10;

[0067] B10, control the B phase circuit and enter B11;

[0068] B11, add 266 to the WZ value to determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN-WZ; if not, set WZ1 = 400 + CNTCNN-WZ and enter B12;

[0069] B12, in response to WZ1 being greater than 400, the value of WZ1 is subtracted by 400, and the process proceeds to B13;

[0070] B13, control the C phase circuit;

[0071] The control methods for the A, B and C phase circuits are the same, specifically:

[0072] In response to AVBZ[WZ1] being greater than or equal to 0.875, then:

[0073] Turn off the output positive switch, the input negative switch, the positive bridge switch, the positive left interconnection switch, the positive right interconnection switch, the negative left interconnection switch, the negative right interconnection switch and the negative bridge output switch;

[0074] Turn on the output negative terminal switch, the input positive terminal switch, the switching switch, the negative terminal bridge switch and the positive terminal bridge output switch;

[0075] In response to AVBZ[WZ1] being less than 0.875 and greater than or equal to 0.625, then:

[0076] Turn off the output positive switch, the changeover switch, the positive bridge switch, the negative left interconnection switch, the negative right interconnection switch, and the negative bridge output switch;

[0077] Turn on the output negative terminal switch, the input positive terminal switch, the input negative terminal switch, the negative terminal bridge switch, the positive terminal bridge output switch, the positive left interconnection switch, and the positive right interconnection switch;

[0078] In response to AVBZ[WZ1] being less than 0.625 and greater than or equal to 0.375, then:

[0079] Turn on the output positive switch, the switching switch, the positive left interconnection switch, and the positive right interconnection switch, and turn off the negative end bridge output switch and the negative end bridge switch;

[0080] Turn on the output negative switch, the input positive switch, the input negative switch, the positive bridge output switch, the positive bridge switch, the negative left interconnection switch, and the negative right interconnection switch;

[0081] In response to AVBZ[WZ1] being less than 0.375 and greater than or equal to 0.125, then:

[0082] Turn off the output negative terminal switch, the switching switch, the positive terminal bridge switch, the negative left interconnection switch, the negative right interconnection switch, and the negative terminal bridge output switch;

[0083] Turn on the output positive switch, input positive switch, input negative switch, positive left interconnection switch, positive right interconnection switch, negative bridge switch, and positive bridge output switch;

[0084] In response to AVBZ[WZ1] being less than 0.125 and greater than or equal to -0.125, then:

[0085] Turn off the output positive switch, the changeover switch, the positive bridge switch, the negative left interconnection switch, the negative right interconnection switch, and the positive bridge output switch;

[0086] Turn on the output negative terminal switch, the input positive terminal switch, the input negative terminal switch, the positive left interconnection switch, the positive right interconnection switch, the negative terminal bridge switch, and the negative terminal bridge output switch;

[0087] In response to AVBZ[WZ1] being less than -0.125 and greater than or equal to -0.375, then:

[0088] Turn off the output positive switch, the changeover switch, the positive left interconnection switch, the positive right interconnection switch, the negative end bridge switch, and the positive end bridge output switch;

[0089] Turn on the output negative terminal switch, the input positive terminal switch, the input negative terminal switch, the positive terminal bridge switch, the negative left interconnection switch, the negative right interconnection switch, and the negative terminal bridge output switch;

[0090] In response to AVBZ[WZ1] being less than -0.375 and greater than or equal to -0.625, then:

[0091] Turn off the output negative terminal switch, the switching switch, the positive terminal bridge switch, the negative left interconnection switch, the negative right interconnection switch, and the positive terminal bridge output switch;

[0092] Turn on the output positive switch, input positive switch, input negative switch, positive left interconnection switch, positive right interconnection switch, negative bridge switch, and negative bridge output switch;

[0093] In response to AVBZ[WZ1] being less than -0.625 and greater than or equal to -0.875, then:

[0094] Turn off the input positive switch, output negative switch, changeover switch, positive left interconnection switch, positive right interconnection switch, negative bridge switch, and positive bridge output switch;

[0095] Turn on the output positive switch, the input negative switch, the positive bridge switch, the negative left interconnection switch, the negative right interconnection switch, and the negative bridge output switch;

[0096] In response to AVBZ[WZ1] being less than -0.875, then:

[0097] Turn off the output negative terminal switch, the positive left interconnection switch, the positive right interconnection switch, the negative left interconnection switch, the negative right interconnection switch, the negative terminal bridge switch, and the positive terminal bridge output switch;

[0098] Turn on the output positive switch, the switching switch, the input positive switch, the input negative switch, the positive bridge switch, and the negative bridge output switch.

[0099] Further: In said S2, the method of calling the tripping and compensation calculation subroutine is specifically:

[0100] S21. Calculate the following data:

[0101]

[0102]

[0103]

[0104]

[0105]

[0106]

[0107] In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0108] S22, calculate the minimum value of SUMVA, SUMVB and SUMVC, and assign it to MINSUMV;

[0109] S23, calculate the maximum value of SUMIA, SUMIB and SUMIC, and assign it to MAXSUMI;

[0110] S24, determine whether MINSUMV is less than MINSUMVG and MAXSUMI is greater than MAXSUMIG. If so, TZF=1; if not, TZF=0;

[0111] S25. Calculate the following data:

[0112] AIBZ[i]=M1data[i]–AFI[i+WZ]

[0113] Wherein, i = 0 to 399;

[0114] WZ1=WZ+133

[0115] In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0116] BIBZ[i]=M1data[i]–BFI[i+WZ1]

[0117] WZ1=WZ+266

[0118] In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0119] CIBZ[i]=M1data[i]–CFI[i+WZ1]

[0120] S26. Calculate the following data:

[0121]

[0122]

[0123]

[0124] S27, calculate the maximum value of ASUMZB, BSUMZB and CSUMZB, and assign it to MAXSUMBZ;

[0125] Determine whether MAXSUMBZ is greater than or equal to BZYZ; if so, set FBZ = 1; if not, set FBZ = 0;

[0126] In S3, the method of calling the tripping action subroutine is specifically as follows:

[0127] S31, controlling the first IGBT to turn on and controlling the mechanical circuit breaker to turn off;

[0128] S32 , controlling the first IGBT to turn off.

[0129] The beneficial effects of the present invention are: an arc-free circuit breaker and control method with filtering capability in a transformer substation, through a microprocessor and a voltage sensor, a current sensor, a mechanical circuit breaker, a filtering module, a wireless communication module, and a first IGBT driving circuit. The microprocessor receives the sensing signals of the voltage sensor and the current sensor, and the control information of the wireless communication module; according to the sensing signals of the voltage sensor and the current sensor, and the control information of the wireless communication module, the transformer substation operation state is calculated, and the mechanical circuit breaker, the first IGBT driving circuit and the filtering module are controlled according to the calculation results, which solves the problem that traditional circuit breakers can no longer meet the increasing demand for new energy sources such as photovoltaics and charging piles in transformer substations. BRIEF DESCRIPTION OF THE DRAWINGS

[0130] Figure 1 The schematic diagram is a structural diagram of an arc-free circuit breaker in a transformer substation with filtering capability.

[0131] Figure 2 This is the structural diagram of the filtering module.

[0132] Figure 3 This is the structural diagram of the filter controller.

[0133] Figure 4 This is the voltage conversion circuit structure diagram.

[0134] Figure 5 This is the switch module structure diagram.

[0135] Figure 6The present invention is a flow chart of a control method of an arc-free circuit breaker in a transformer substation with filtering capability.

[0136] Among them: 1. voltage sensor; 2. current sensor; 3. mechanical circuit breaker; 4. filter module; 5. wireless communication module; 6. microprocessor; 7. first IGBT drive circuit; 8. first IGBT; 21. grid-side inductor; 22. grid-side resistor; 23. neutral line resistor; 24. neutral line capacitor; 25. neutral line; 26. filter controller; 27. filter resistor; 28. filter inductor; 29. ​​load-side resistor; 30. load-side inductor; 41. voltage conversion circuit; 42. upper voltage control capacitor; 43. lower voltage control capacitor; 44. output capacitor; 45. current control inductor; 46. output inductor; 47. output positive pole; 48. output negative pole; 61. input positive terminal switch; 62. output positive terminal switch; 63. , output negative terminal switch; 64, input negative terminal switch; 65, switching switch; 66, positive terminal bridge switch; 67, positive left interconnection switch; 68, positive right interconnection switch; 69, negative left interconnection switch; 70, negative right interconnection switch; 71, negative terminal bridge switch; 72, negative terminal bridge output switch; 73, positive terminal bridge output switch; 81, connecting terminal A; 82, connecting terminal B; 83, connecting terminal C; 84, connecting terminal N; 85-1, first power diode; 85-2, second power diode; 85-3, third power diode; 86, connecting terminal D; 91, second IGBT drive; 92, second IGBT; 93, collector of second IGBT drive; 94, emitter of second IGBT drive. DETAILED DESCRIPTION

[0137] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0138] Embodiment 1:

[0139] like Figure 1 As shown, in one embodiment of the present invention, a non-arc circuit breaker with filtering capability in a transformer area includes a voltage sensor 1, a current sensor 2, a mechanical circuit breaker 3, a filtering module 4, a wireless communication module 5, a microprocessor 6, a first IGBT driving circuit 7 and a first IGBT 8;

[0140] Among them, the voltage sensor 1, the current sensor 2, the mechanical circuit breaker 3 and the filter module 4 are connected in sequence, the microprocessor 6 is respectively connected to the voltage sensor 1, the current sensor 2, the mechanical circuit breaker 3 and the filter module 4, the wireless communication module 5 and the first IGBT drive circuit 7, the first IGBT drive circuit 7 is also connected to the first IGBT 8, one end of the first IGBT 8 is respectively connected to the current sensor 2 and the mechanical circuit breaker 3, and the other end of the first IGBT 8 is respectively connected to the mechanical circuit breaker 3 and the filter module 4;

[0141] The voltage sensor 1 is used to collect the three-phase voltage value output by the substation transformer, the current sensor 2 is used to collect the three-phase current value output by the substation transformer, the wireless communication module 5 is used to receive the control information of the substation circuit breaker, the microprocessor 6 is used to calculate the substation operation status according to the three-phase voltage and current values, clock signals and control information output by the substation transformer, and control the mechanical circuit breaker 3, the first IGBT drive circuit 7 and the filter module 4 according to the calculation results, and the thyristor 9 is used to control the current.

[0142] The output of the substation transformer is a three-phase conductor, which passes through the voltage sensor 1 and the current sensor 2, and is connected to the input end of the mechanical circuit breaker 3. The output end of the mechanical circuit breaker 3 is connected to the input end of the filter module 4. The output end of the filter module 4 is connected to the substation load to supply power to the substation load.

[0143] The voltage sensor 1 and the current sensor 2 collect the voltage and current values ​​of the three phases ABC output by the transformer in the substation, and the sensor output is connected to the analog-to-digital conversion interface of the microprocessor 6.

[0144] like Figure 2 As shown, the filter module 4 includes a grid-side inductor 21, a grid-side resistor 22, a neutral line resistor 23, a neutral line capacitor 24, a filter controller 26, a filter resistor 27, a filter inductor 28, a load-side resistor 29, and a load-side inductor 30;

[0145] Among them, one end of the grid-side inductor 21 is connected to the mechanical circuit breaker 3, the other end of the grid-side inductor 21 is connected to one end of the grid-side resistor 22, the other end of the grid-side resistor 22 is respectively connected to one end of the neutral line resistor 23, one end of the filter inductor 28 and one end of the load-side resistor 29, the other end of the neutral line resistor 23 is connected to the neutral line 25 through the neutral line capacitor 24, the other end of the filter inductor 28 is connected to the filter controller 26 through the filter resistor 27, and the other end of the load-side resistor 29 is connected to the substation load through the load-side inductor 30.

[0146] In this embodiment, there are three filter modules 4 distributed on three phases A, B, and C, with one connected to each phase.

[0147] like Figure 3As shown, the filter controller 26 includes a voltage conversion circuit 41, an upper voltage control capacitor 42, a lower voltage control capacitor 43, an output capacitor 44, a current control inductor 45, an output inductor 46, an input positive terminal switch 61, an output positive terminal switch 62, an output negative terminal switch 63, an input negative terminal switch 64, a switching switch 65, a positive terminal bridge switch 66, a positive left interconnection switch 67, a positive right interconnection switch 68, a negative left interconnection switch 69, a negative right interconnection switch 70, a negative terminal bridge switch 71, a negative terminal bridge output switch 72 and a positive terminal bridge output switch 73;

[0148] The connection terminal A81, the connection terminal B82 and the connection terminal C83 of the voltage conversion circuit 41 are respectively connected to the power supply A phase, the power supply B phase and the power supply C phase in a one-to-one correspondence. The connection terminal N84 of the voltage conversion circuit 41 is respectively connected to the neutral line of the power supply, the emitter of the output negative end switch 63 and the emitter of the input negative end switch 64. The connection terminal D86 of the voltage conversion circuit 41 is respectively connected to the collector of the input positive end switch 61 and the collector of the output positive end switch 62. The emitter of the input positive end switch 61 is respectively connected to the emitter of the positive end bridge switch 66. , the collector of the switching switch 65 is connected to the collector of the positive left interconnection switch 67, the emitter of the output positive end switch 62 is respectively connected to the collector of the output negative end switch 63, one end of the output capacitor 44 and the output negative electrode 48, the collector of the positive end bridge switch 66 is respectively connected to the collector of the positive end bridge output switch 73 and one end of the upper voltage control capacitor 42, the emitter of the positive left interconnection switch 67 is connected to the emitter of the positive right interconnection switch 68, and the collector of the positive right interconnection switch 68 is connected to the other end of the upper voltage control capacitor 42 and one end of the current control inductor 45;

[0149] The collector of the input negative terminal switch 64 is respectively connected to the collector of the negative terminal bridge switch 71, the emitter of the switching switch 65 and the collector of the negative left interconnection switch 69, the emitter of the negative left interconnection switch 69 is connected to the emitter of the negative right interconnection switch 70, the collector of the negative right interconnection switch 70 is respectively connected to one end of the lower voltage control capacitor 43 and the other end of the current control inductor 45, the emitter of the negative terminal bridge switch 71 is connected to the other end of the lower voltage control capacitor 43 and the emitter of the negative terminal bridge output switch 72, the collector of the negative terminal bridge output switch 72 is respectively connected to the emitter of the positive terminal bridge output switch 73 and one end of the output inductor 46, and the other end of the output inductor 46 is respectively connected to the other end of the output capacitor 44 and the output positive electrode 47.

[0150] like Figure 4 As shown, the voltage conversion circuit 41 includes a first power diode 85-1, a second power diode 85-2, a third power diode 85-3, a connection terminal A81, a connection terminal B82, a connection terminal C83, a connection terminal D86 and a connection terminal N84;

[0151] Among them, the cathode of the first power diode 85-1, the cathode of the second power diode 85-2 and the cathode of the third power diode 85-3 are all connected to the connection terminal D86, and the anode of the first power diode 85-1, the anode of the second power diode 85-2 and the anode of the third power diode 85-3 are respectively connected to the connection terminal A81, the connection terminal B82 and the connection terminal C83.

[0152] like Figure 5 As shown, the input positive terminal switch 61, the output positive terminal switch 62, the output negative terminal switch 63, the input negative terminal switch 64, the switching switch 65, the positive terminal bridge switch 66, the positive left interconnection switch 67, the positive right interconnection switch 68, the negative left interconnection switch 69, the negative right interconnection switch 70, the negative terminal bridge switch 71, the negative terminal bridge output switch 72 and the positive terminal bridge output switch 73 have the same structure, and include: a second IGBT driver 91 and a second IGBT 92;

[0153] The second IGBT driver 91 is connected to the microprocessor 6 and the gate of the second IGBT 92 respectively. The second IGBT 92 further includes a collector 93 of the second IGBT driver and an emitter 94 of the second IGBT driver.

[0154] like Figure 6 As shown, a control method for a non-arc circuit breaker in a transformer area with filtering capability comprises the following steps:

[0155] S1, perform initialization operation through the initialization subroutine;

[0156] S2, in response to startF being equal to 1, calling the tripping and compensation calculation subroutine to calculate the tripping criterion;

[0157] S3. In response to the tripping criterion being equal to 1, the tripping action subroutine is called to perform a tripping action.

[0158] The S1 comprises the following sub-steps:

[0159] S11, set the low-frequency interrupt clock to 20 milliseconds and the high-frequency interrupt clock to 50 microseconds;

[0160] S12, setting a low-frequency interrupt condition, and setting a low-frequency interrupt subroutine to be called when an interrupt occurs; setting a high-frequency interrupt condition, and setting a high-frequency interrupt subroutine to be called when an interrupt occurs;

[0161] S13. Set variables, including:

[0162] A phase voltage phase zero millisecond counter, A phase voltage phase zero microsecond counter, high frequency interrupt counter represented by CH, value range: 0 to 999, trip voltage threshold represented by VY, trip current threshold represented by IY, compensation threshold represented by BY, trip mark represented by TZ, sensor reading counter represented by CVA, value range: 0 to 999, cycle counter represented by CZQ, value range: 0 to 199, voltage sum represented by SUMV, voltage minimum represented by MINSUMV, voltage minimum threshold represented by MINSUMVG, current sum represented by SUMI, current maximum represented by MAXSUMI, current maximum threshold represented by MAXSUMIG;

[0163] The first reading value of phase A of voltage sensor 1 is represented by array AVINA

[400] , the second reading value of phase A of voltage sensor 1 is represented by array AVINB

[400] , the floating point value of phase A voltage is represented by array AFV

[400] , the first reading value of phase A of current sensor 2 is represented by array AIINA

[400] , the second reading value of phase A of current sensor 2 is represented by array AIINB

[400] , the floating point value of phase A current is represented by array AFI

[400] , and the compensation of phase A is represented by array AVBZ

[400] ;

[0164] The first B-phase reading value of voltage sensor 1 is represented by array BVINA

[400] , the second B-phase reading value of voltage sensor 1 is represented by array BVINB

[400] , the B-phase voltage floating point value is represented by array BFV

[400] , the first B-phase reading value of current sensor 2 is represented by array BIINA

[400] , the second B-phase reading value of current sensor 2 is represented by array BIINB

[400] , the B-phase current floating point value is represented by array BFI

[400] , and the B-phase compensation is represented by array BVBZ

[400] ;

[0165] The first reading value of phase C of voltage sensor 1 is represented by array CVINA

[400] , the second reading value of phase C of voltage sensor 1 is represented by array CVINB

[400] , the floating point value of phase C voltage is represented by array CFV

[400] , the first reading value of phase C of current sensor 2 is represented by array CIINA

[400] , the second reading value of phase C of current sensor 2 is represented by array CIINB

[400] , the floating point value of phase C current is represented by array CFI

[400] , and the compensation of phase C is represented by array CVBZ

[400] ;

[0166] The time update data position is represented by PT, the trip calculation variable is represented by FTZ, the trip calculation variable is represented by TZF, the compensation calculation variable is represented by FBZ, the low frequency interrupt mark is represented by FZD, the storage selection mark is represented by SELF, the loop counter is represented by CNTCNN, the start calculation mark is represented by startF, the A phase impedance is represented by AZK, the B phase impedance is represented by BZK, the C phase impedance is represented by CZK, the minimum impedance is represented by MINZK, the impedance trip threshold is represented by ZKYZ, the A phase compensation sum is represented by ASUMBZ, the B phase compensation sum is represented by BSUMBZ, the C phase compensation sum is represented by CSUMBZ, the maximum compensation sum is represented by MAXSUMBZ, and the compensation threshold is represented by BZYZ;

[0167] S14, initialize variables, the initialized variables are specifically:

[0168] MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF=0, ACNTVI=0, BCNTVI=0, CCNTVI= 0, CNTCNN=0, startF=0, FZD=0; FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0;

[0169] AVINA, AVINB, BVINA, BVINB, CVINA, and CVINB are initialized to all zeros;

[0170] S15. Set the first parameter M1data and the comparison variable BiJiao.

[0171] M1data

[400] ={0.015707,0.031411,0.047106,0.062791,0.078459,0.094108,0.109734,0.125333,0.140901,0.156434,0.171929,0.187381,0.2 02787,0.218143,0.233445,0.248690,0.263873,0.278991,0.294040,0.309017,0.323917,0.338738,0.353475,0.368125,0.382683,0.397148,0. 411514,0.425779,0.439939,0.453990,0.467930,0.481754,0.495459,0.509041,0.522499,0.535827,0.549023,0.562083,0.575005,0.587785, 0.600420,0.612907,0.625243,0.637424,0.649448,0.661312,0.673013,0.684547,0.695913,0.707107,0.718126,0.728969,0.739631,0.750111 ,0.760406,0.770513,0.780430,0.790155,0.799685,0.809017,0.818150,0.827081,0.835807,0.844328,0.852640,0.860742,0.868632,0.8763 07,0.883766,0.891007,0.898028,0.904827,0.911403,0.917755,0.923880,0.929776,0.935444,0.940881,0.946085,0.951057,0.955793,0.960 294,0.964557,0.968583,0.972370,0.975917,0.979223,0.982287,0.985109,0.987688,0.990024,0.992115,0.993961,0.995562,0.996917,0.9 98027,0.998890,0.999507,0.999877,1.000000,0.999877,0.999507,0.998890,0.998027,0.996917,0.995562,0.993961,0.992115,0.990024,0.987688,0.985109,0.982287,0.979223,0.975917,0.972370,0.968583,0.964557,0.960294,0.955793,0.951057,0.946085,0.940881,0.935444,0.929776,0.923880,0.917755,0.911403,0.904827,0.898028,0.891007,0.883766,0.876307,0.868632,0.860742,0.852640,0.844328,0.835807,0.827081,0.818150,0.809017,0.799685,0.790155,0.780430,0.770513,0.760406,0.750111,0.739631,0.728969,0.718126,0.707107,0.695913,0.684547,0.673013,0.661312,0.649448,0.637424,0.625243,0.612907,0.600420,0.587785,0.575005,0.562083,0.549023,0.535827,0.522499,0.509041,0.495459,0.481754,0.467930,0.453990,0.439939,0.425779,0.411514,0.397148,0.382683,0.368125,0.353475,0.338738,0.323917,0.309017,0.294040,0.278991,0.263873,0.248690,0.233445,0.218143,0.202787,0.187381,0.171929,0.156434,0.140901,0.125333,0.109734,0.094108,0.078459,0.062791,0.047106,0.031411,0.015707,0.000000,-0.015707,-0.031411,-0.047106,-0.062791,-0.078459,-0.094108,-0.109734,-0.125333,-0.140901,-0.156434,-0.171929,-0.187381,-0.202787,-0.218143,-0.233445,-0.248690,-0.263873,-0.278991,-0.294040,-0.309017,-0.323917,-0.338738,-0.353475,-0.368125,-0.382683,-0.397148,-0.411514,-0.425779,-0.439939,-0.453990,-0.467930,-0.481754,-0.495459,-0.509041,-0.522499,-0.535827,-0.549023,-0.562083,-0.575005,-0.587785,-0.600420,-0.612907,-0.625243,-0.637424,-0.649448,-0.661312,-0.673013,-0.684547,-0.695913,-0.707107,-0.718126,-0.728969,-0.739631,-0.750111,-0.760406,-0.770513,-0.780430,-0.790155,-0.799685,-0.809017,-0.818150,-0.827081,-0.835807,-0.844328,-0.852640,-0.860742,-0.868632,-0.876307,-0.883766,-0.891007,-0.898028,-0.904827,-0.911403,-0.917755,-0.923880,-0.929776,-0.935444,-0.940881,-0.946085,-0.951057,-0.955793,-0.960294,-0.964557,-0.968583,-0.972370,-0.975917,-0.979223,-0.982287,-0.985109,-0.987688,-0.990024,-0.992115,-0.993961,-0.995562,-0.996917,-0.998027,-0.998890,-0.999507,-0.999877,-1.000000,-0.999877,-0.999507,-0.998890,-0.998027,-0.996917,-0.995562,-0.993961,-0.992115,-0.990024,-0.987688,-0.985109,-0.982287,-0.979223,-0.975917,-0.972370,-0.968583,-0.964557,-0.960294,-0.955793,-0.951057,-0.946085,-0.940881,-0.935444,-0.929776,-0.923880,-0.917755,-0.911403,-0.904827,-0.898028,-0.891007,-0.883766,-0.876307,-0.868632,-0.860742,-0.852640,-0.844328,-0.835807,-0.827081,-0.8181 50,-0.809017,-0.799685,-0.790155,-0.780430,-0.770513,-0.760406,-0.750111,-0.739631,-0.728969,-0.718126,-0.707107,-0.695913,-0.684547,-0.673013,-0.661312,-0.649448,-0.637424,-0.625243,-0.612907,-0.600420,-0 .587785,-0.575005,-0.562083,-0.549023,-0.535827,-0.522499,-0.509041,-0.495459,-0.481754,-0.467930,-0.453990,-0.439939,-0.425779,-0.411514,-0.397148,-0.382683,-0.368125,-0.353475,-0.338738,-0.323917,-0. 017,-0.294040,-0.278991,-0.263873,-0.248690,-0.233445,-0.218143,-0.202787,-0.187381,-0.171929,-0.156434,-0.140901,-0.125333,-0.109734,-0.094108,-0.078459,-0.062791,-0.047106,-0.031411,-0.015707,-0.000000}.

[0172] In S11, the method of calling the low-frequency interrupt subroutine is specifically as follows:

[0173] A1. Determine whether SELF is false. If so, set ACDATA[i] = AVINA[i], where i = 0 to 799, and enter A2;

[0174] If not, set ACDATA[i]=AVINB[i], where i=0-799, and enter A2;

[0175] A2. Invert SELF, and in response to the fact that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero, and AVINA[i+2] is greater than or equal to AVINA[i] in the range of i=2-401, set WZ=i and startF=1.

[0176] In S12, the method of calling the high-frequency interrupt subroutine is specifically as follows:

[0177] B1, determine whether SELF is false, if so, go to SB2;

[0178] If not, let AVINA be equal to the storage value of the memory corresponding to voltage sensor 1, let AIINA be equal to the storage value of the memory corresponding to current sensor 2, BVINA be equal to the storage value of the memory corresponding to voltage sensor 1, let BIINA be equal to the storage value of the memory corresponding to current sensor 2, CVINA be equal to the storage value of the memory corresponding to voltage sensor 1, let CIINA be equal to the storage value of the memory corresponding to current sensor 2;

[0179] AFV[CNTCNN]=(AVINA–32768) / 32768

[0180] AFI[CNTCNN]=(AIINA–32768) / 32768

[0181] BFV[CNTCNN]=(BVINA–32768) / 32768

[0182] BFI[CNTCNN]=(BIINA–32768) / 32768

[0183] CFV[CNTCNN]=(CVINA–32768) / 32768

[0184] CFI[CNTCNN]=(CIINA–32768) / 32768

[0185] Enter B3;

[0186] B2. Let AVINB be equal to the storage value of the memory corresponding to voltage sensor 1, let AIINB be equal to the storage value of the memory corresponding to current sensor 2, BVINB be equal to the storage value of the memory corresponding to voltage sensor 1, let BIINB be equal to the storage value of the memory corresponding to current sensor 2, CVINB be equal to the storage value of the memory corresponding to voltage sensor 1, let CIINB be equal to the storage value of the memory corresponding to current sensor 2;

[0187] AFV[CNTCNN]=(AVINB–32768) / 32768

[0188] AFI[CNTCNN]=(AIINB–32768) / 32768

[0189] BFV[CNTCNN]=(BVINB–32768) / 32768

[0190] BFI[CNTCNN]=(BIINB–32768) / 32768

[0191] CFV[CNTCNN]=(CVINB–32768) / 32768

[0192] CFI[CNTCNN]=(CIINB–32768) / 32768

[0193] Enter B3;

[0194] B3, add 1 to the value of CNTCNN, and in response to CNTCNN being greater than 800, set CNTCNN=0;

[0195] Enter B4;

[0196] B4, in response to FBZ being equal to 1, proceed to B5;

[0197] B5. Determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN-WZ; if not, set WZ1 = 400 + CNTCNN-WZ;

[0198] Enter B6;

[0199] B6. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0200] Enter B7;

[0201] B7, control the A phase circuit and enter B8;

[0202] B8. Add 133 to the WZ value to determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN-WZ; if not, set WZ1 = 400 + CNTCNN-WZ;

[0203] Enter B9;

[0204] B9, in response to WZ1 being greater than 400, subtract 400 from the value of WZ1;

[0205] Enter B10;

[0206] B10, control the B phase circuit and enter B11;

[0207] B11, add 266 to the WZ value to determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN-WZ; if not, set WZ1 = 400 + CNTCNN-WZ and enter B12;

[0208] B12, in response to WZ1 being greater than 400, the value of WZ1 is subtracted by 400, and the process proceeds to B13;

[0209] B13, control the C phase circuit;

[0210] The control methods for the A, B and C phase circuits are the same, specifically:

[0211] In response to AVBZ[WZ1] being greater than or equal to 0.875, then:

[0212] Turn off the output positive switch 62, the input negative switch 64, the positive bridge switch 66, the positive left interconnection switch 67, the positive right interconnection switch 68, the negative left interconnection switch 69, the negative right interconnection switch 70 and the negative bridge output switch 72;

[0213] Turn on the output negative terminal switch 63, the input positive terminal switch 61, the switching switch 65, the negative terminal bridge switch 71 and the positive terminal bridge output switch 73;

[0214] In response to AVBZ[WZ1] being less than 0.875 and greater than or equal to 0.625, then:

[0215] Turn off the output positive end switch 62, the switching switch 65, the positive end bridge switch 66, the negative left interconnection switch 69, the negative right interconnection switch 70, and the negative end bridge output switch 72;

[0216] Turn on the output negative terminal switch 63, the input positive terminal switch 61, the input negative terminal switch 64, the negative terminal bridge switch 71, the positive terminal bridge output switch 73, the positive left interconnection switch 67, and the positive right interconnection switch 68;

[0217] In response to AVBZ[WZ1] being less than 0.625 and greater than or equal to 0.375, then:

[0218] Turn on the output positive end switch 62, the switching switch 65, the positive left interconnection switch 67, and the positive right interconnection switch 68, and turn off the negative end bridge output switch 72 and the negative end bridge switch 71;

[0219] Turn on the output negative terminal switch 63, the input positive terminal switch 61, the input negative terminal switch 64, the positive terminal bridge output switch 73, the positive terminal bridge switch 66, the negative left interconnection switch 69, and the negative right interconnection switch 70;

[0220] In response to AVBZ[WZ1] being less than 0.375 and greater than or equal to 0.125, then:

[0221] Turn off the output negative terminal switch 63, the switching switch 65, the positive terminal bridge switch 66, the negative left interconnection switch 69, the negative right interconnection switch 70, and the negative terminal bridge output switch 72;

[0222] Turn on the output positive terminal switch 62, the input positive terminal switch 61, the input negative terminal switch 64, the positive left interconnection switch 67, the positive right interconnection switch 68, the negative terminal bridge switch 71, and the positive terminal bridge output switch 73;

[0223] In response to AVBZ[WZ1] being less than 0.125 and greater than or equal to -0.125, then:

[0224] Turn off the output positive end switch 62, the switching switch 65, the positive end bridge switch 66, the negative left interconnection switch 69, the negative right interconnection switch 70, and the positive end bridge output switch 73;

[0225] Turn on the output negative terminal switch 63, the input positive terminal switch 61, the input negative terminal switch 64, the positive left interconnection switch 67, the positive right interconnection switch 68, the negative terminal bridge switch 71, and the negative terminal bridge output switch 72;

[0226] In response to AVBZ[WZ1] being less than -0.125 and greater than or equal to -0.375, then:

[0227] Turn off the output positive end switch 62, the switching switch 65, the positive left interconnection switch 67, the positive right interconnection switch 68, the negative end bridge switch 71, and the positive end bridge output switch 73;

[0228] Turn on the output negative terminal switch 63, the input positive terminal switch 61, the input negative terminal switch 64, the positive terminal bridge switch 66, the negative left interconnection switch 69, the negative right interconnection switch 70, and the negative terminal bridge output switch 72;

[0229] In response to AVBZ[WZ1] being less than -0.375 and greater than or equal to -0.625, then:

[0230] Turn off the output negative terminal switch 63, the switching switch 65, the positive terminal bridge switch 66, the negative left interconnection switch 69, the negative right interconnection switch 70, and the positive terminal bridge output switch 73;

[0231] Turn on the output positive switch 62, the input positive switch 61, the input negative switch 64, the positive left interconnection switch 67, the positive right interconnection switch 68, the negative bridge switch 71, and the negative bridge output switch 72;

[0232] In response to AVBZ[WZ1] being less than -0.625 and greater than or equal to -0.875, then:

[0233] Turn off the input positive switch 61, the output negative switch 63, the switching switch 65, the positive left interconnection switch 67, the positive right interconnection switch 68, the negative end bridge switch 71, and the positive end bridge output switch 73;

[0234] Turn on the output positive terminal switch 62, the input negative terminal switch 64, the positive terminal bridge switch 66, the negative left interconnection switch 69, the negative right interconnection switch 70, and the negative terminal bridge output switch 72;

[0235] In response to AVBZ[WZ1] being less than -0.875, then:

[0236] Turn off the output negative terminal switch 63, the positive left interconnection switch 67, the positive right interconnection switch 68, the negative left interconnection switch 69, the negative right interconnection switch 70, the negative terminal bridge switch 71, and the positive terminal bridge output switch 73;

[0237] The output positive terminal switch 62 , the switching switch 65 , the input positive terminal switch 61 , the input negative terminal switch 64 , the positive terminal bridge switch 66 , and the negative terminal bridge output switch 72 are turned on.

[0238] In S2, the method of calling the tripping and compensation calculation subroutine is specifically as follows:

[0239] S21. Calculate the following data:

[0240]

[0241]

[0242]

[0243]

[0244]

[0245]

[0246] In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0247] S22, calculate the minimum value of SUMVA, SUMVB and SUMVC, and assign it to MINSUMV;

[0248] S23, calculate the maximum value of SUMIA, SUMIB and SUMIC, and assign it to MAXSUMI;

[0249] S24, determine whether MINSUMV is less than MINSUMVG and MAXSUMI is greater than MAXSUMIG. If so, TZF=1; if not, TZF=0;

[0250] S25. Calculate the following data:

[0251] AIBZ[i]=M1data[i]–AFI[i+WZ]

[0252] Wherein, i = 0 to 399;

[0253] WZ1=WZ+133

[0254] In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0255] BIBZ[i]=M1data[i]–BFI[i+WZ1]

[0256] WZ1=WZ+266

[0257] In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0258] CIBZ[i]=M1data[i]–CFI[i+WZ1]

[0259] S26. Calculate the following data:

[0260]

[0261]

[0262]

[0263] S27, calculate the maximum value of ASUMZB, BSUMZB and CSUMZB, and assign it to MAXSUMBZ;

[0264] Determine whether MAXSUMBZ is greater than or equal to BZYZ; if so, set FBZ = 1; if not, set FBZ = 0;

[0265] In S3, the method of calling the tripping action subroutine is specifically as follows:

[0266] S31, controlling the first IGBT8 to turn on, and controlling the mechanical circuit breaker 3 to turn off;

[0267] S32 , controlling the first IGBT8 to turn off.

[0268] In the description of the present invention, it is necessary to understand that the orientation or positional relationship indicated by the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used only for descriptive purposes, and cannot be understood as indicating or implying the relative importance or the number of implicitly specified technical features. Therefore, the features defined by "first", "second", and "third" may explicitly or implicitly include one or more of the features.

Claims

1. A non-arc circuit breaker with filtering capability, characterized in that: It comprises a voltage sensor (1), a current sensor (2), a mechanical circuit breaker (3), a filter module (4), a wireless communication module (5), a microprocessor (6), a first IGBT drive circuit (7) and a first IGBT (8); The voltage sensor (1), the current sensor (2), the mechanical circuit breaker (3) and the filter module (4) are connected in sequence; the microprocessor (6) is respectively connected to the voltage sensor (1), the current sensor (2), the mechanical circuit breaker (3) and the filter module (4); the wireless communication module (5) and the first IGBT drive circuit (7); the first IGBT drive circuit (7) is also connected to the first IGBT (8); one end of the first IGBT (8) is respectively connected to the current sensor (2) and the mechanical circuit breaker (3); and the other end of the first IGBT (8) is respectively connected to the mechanical circuit breaker (3) and the filter module (4); The voltage sensor (1) is used to collect the three-phase voltage values ​​output by the transformer in the substation area; the current sensor (2) is used to collect the three-phase current values ​​output by the transformer in the substation area; the wireless communication module (5) is used to receive the control information of the circuit breaker in the substation area; the microprocessor (6) is used to calculate the operation state of the substation area according to the three-phase voltage and current values ​​output by the transformer in the substation area, the clock signal and the control information; the mechanical circuit breaker (3), the first IGBT drive circuit (7) and the filter module (4) are controlled according to the calculation result; and the thyristor (9) is used to control the current.

2. The arc-free circuit breaker with filtering capability according to claim 1, characterized in that: The filter module (4) includes a grid-side inductor (21), a grid-side resistor (22), a neutral line resistor (23), a neutral line capacitor (24), a filter controller (26), a filter resistor (27), a filter inductor (28), a load-side resistor (29), and a load-side inductor (30); One end of the grid-side inductor (21) is connected to the mechanical circuit breaker (3), the other end of the grid-side inductor (21) is connected to one end of the grid-side resistor (22), the other end of the grid-side resistor (22) is respectively connected to one end of the neutral line resistor (23), one end of the filter inductor (28) and one end of the load-side resistor (29), the other end of the neutral line resistor (23) is connected to the neutral line (25) via the neutral line capacitor (24), the other end of the filter inductor (28) is connected to the filter controller (26) via the filter resistor (27), and the other end of the load-side resistor (29) is connected to the substation load via the load-side inductor (30).

3. The arc-free circuit breaker with filtering capability according to claim 2, characterized in that: The filter controller (26) comprises a voltage conversion circuit (41), an upper voltage control capacitor (42), a lower voltage control capacitor (43), an output capacitor (44), a current control inductor (45), an output inductor (46), an input positive terminal switch (61), an output positive terminal switch (62), an output negative terminal switch (63), an input negative terminal switch (64), a switching switch (65), a positive terminal bridge switch (66), a positive left interconnection switch (67), a positive right interconnection switch (68), a negative left interconnection switch (69), a negative right interconnection switch (70), a negative terminal bridge switch (71), a negative terminal bridge output switch (72) and a positive terminal bridge output switch (73); The connection terminal A (81), the connection terminal B (82) and the connection terminal C (83) of the voltage conversion circuit (41) are respectively connected to the power supply A phase, the power supply B phase and the power supply C phase in a one-to-one correspondence; the connection terminal N (84) of the voltage conversion circuit (41) is respectively connected to the neutral line of the power supply, the emitter of the output negative end switch (63) and the emitter of the input negative end switch (64); the connection terminal D (86) of the voltage conversion circuit (41) is respectively connected to the collector of the input positive end switch (61) and the collector of the output positive end switch (62); the emitter of the input positive end switch (61) is respectively connected to the emitter of the positive end bridge switch (66); , the collector of the switching switch (65) is connected to the collector of the positive left interconnection switch (67), the emitter of the output positive end switch (62) is respectively connected to the collector of the output negative end switch (63), one end of the output capacitor (44) and the output negative electrode (48), the collector of the positive end bridge switch (66) is respectively connected to the collector of the positive end bridge output switch (73) and one end of the upper voltage control capacitor (42), the emitter of the positive left interconnection switch (67) is connected to the emitter of the positive right interconnection switch (68), and the collector of the positive right interconnection switch (68) is connected to the other end of the upper voltage control capacitor (42) and one end of the current control inductor (45); The collector of the input negative terminal switch (64) is respectively connected to the collector of the negative terminal bridge switch (71), the emitter of the switching switch (65) and the collector of the negative left interconnection switch (69); the emitter of the negative left interconnection switch (69) is connected to the emitter of the negative right interconnection switch (70); the collector of the negative right interconnection switch (70) is respectively connected to one end of the lower voltage control capacitor (43) and the other end of the current control inductor (45); the emitter of the negative terminal bridge switch (71) is connected to the other end of the lower voltage control capacitor (43) and the emitter of the negative terminal bridge output switch (72); the collector of the negative terminal bridge output switch (72) is respectively connected to the emitter of the positive terminal bridge output switch (73) and one end of the output inductor (46); the other end of the output inductor (46) is respectively connected to the other end of the output capacitor (44) and the output positive electrode (47).

4. The arc-free circuit breaker with filtering capability according to claim 3, characterized in that: The voltage conversion circuit (41) includes a first power diode (85-1), a second power diode (85-2), a third power diode (85-3), a connection terminal A (81), a connection terminal B (82), a connection terminal C (83), a connection terminal D (86) and a connection terminal N (84); Among them, the cathode of the first power diode (85-1), the cathode of the second power diode (85-2) and the cathode of the third power diode (85-3) are all connected to the connection terminal D (86), and the anode of the first power diode (85-1), the anode of the second power diode (85-2) and the anode of the third power diode (85-3) are respectively connected to the connection terminal A (81), the connection terminal B (82) and the connection terminal C (83) in a one-to-one correspondence.

5. The arc-free circuit breaker with filtering capability according to claim 3, characterized in that: The input positive end switch (61), the output positive end switch (62), the output negative end switch (63), the input negative end switch (64), the switching switch (65), the positive end bridge switch (66), the positive left interconnection switch (67), the positive right interconnection switch (68), the negative left interconnection switch (69), the negative right interconnection switch (70), the negative end bridge switch (71), the negative end bridge output switch (72) and the positive end bridge output switch (73) have the same structure, and include: a second IGBT driver (91) and a second IGBT (92); The second IGBT driver (91) is connected to the microprocessor (6) and the gate of the second IGBT (92) respectively.

6. The control method of the non-arcing circuit breaker in the substation with filtering capability according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1, perform initialization operation through the initialization subroutine; S2, in response to startF being equal to 1, calling the tripping and compensation calculation subroutine to calculate the tripping criterion; S3. In response to the tripping criterion being equal to 1, the tripping action subroutine is called to perform a tripping action.

7. The control method according to claim 6, characterized in that: The S1 comprises the following sub-steps: S11, set the low-frequency interrupt clock to 20 milliseconds and the high-frequency interrupt clock to 50 microseconds; S12, setting the low-frequency interrupt condition, and calling the low-frequency interrupt subroutine when setting the interrupt; Set the high-frequency interrupt condition and call the high-frequency interrupt subroutine when setting the interrupt; S13. Set variables, including: A phase voltage phase zero millisecond counter, A phase voltage phase zero microsecond counter, high frequency interrupt counter represented by CH, value range: 0 to 999, trip voltage threshold represented by VY, trip current threshold represented by IY, compensation threshold represented by BY, trip mark represented by TZ, sensor reading counter represented by CVA, value range: 0 to 999, cycle counter represented by CZQ, value range: 0 to 199, voltage sum represented by SUMV, voltage minimum represented by MINSUMV, voltage minimum threshold represented by MINSUMVG, current sum represented by SUMI, current maximum represented by MAXSUMI, current maximum threshold represented by MAXSUMIG; The first reading value of phase A of the voltage sensor (1) is represented by the array AVINA[400], the second reading value of phase A of the voltage sensor (1) is represented by the array AVINB[400], the floating point value of phase A voltage is represented by the array AFV[400], the first reading value of phase A of the current sensor (2) is represented by the array AIINA[400], the second reading value of phase A of the current sensor (2) is represented by the array AIINB[400], the floating point value of phase A current is represented by the array AFI[400], and the compensation of phase A is represented by the array AVBZ[400]; The first B-phase reading value of the voltage sensor (1) is represented by the array BVINA[400], the second B-phase reading value of the voltage sensor (1) is represented by the array BVINB[400], the B-phase voltage floating point value is represented by the array BFV[400], the first B-phase reading value of the current sensor (2) is represented by the array BIINA[400], the second B-phase reading value of the current sensor (2) is represented by the array BIINB[400], the B-phase current floating point value is represented by the array BFI[400], and the B-phase compensation is represented by the array BVBZ[400]; The first reading value of the C phase of the voltage sensor (1) is represented by the array CVINA[400], the second reading value of the C phase of the voltage sensor (1) is represented by the array CVINB[400], the floating point value of the C phase voltage is represented by the array CFV[400], the first reading value of the C phase of the current sensor (2) is represented by the array CIINA[400], the second reading value of the C phase of the current sensor (2) is represented by the array CIINB[400], the floating point value of the C phase current is represented by the array CFI[400], and the C phase compensation is represented by the array CVBZ[400]; The time update data position is represented by PT, the trip calculation variable is represented by FTZ, the trip calculation variable is represented by TZF, the compensation calculation variable is represented by FBZ, the low frequency interrupt mark is represented by FZD, the storage selection mark is represented by SELF, the loop counter is represented by CNTCNN, the start calculation mark is represented by startF, the A phase impedance is represented by AZK, the B phase impedance is represented by BZK, the C phase impedance is represented by CZK, the minimum impedance is represented by MINZK, the impedance trip threshold is represented by ZKYZ, the A phase compensation sum is represented by ASUMBZ, the B phase compensation sum is represented by BSUMBZ, the C phase compensation sum is represented by CSUMBZ, the maximum compensation sum is represented by MAXSUMBZ, and the compensation threshold is represented by BZYZ; S14, initialize variables, the initialized variables are specifically: MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF=0, ACNTVI=0, BCNTVI=0, CCNTVI= 0, CNTCNN=0, startF=0, FZD=0; FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0; AVINA, AVINB, BVINA, BVINB, CVINA, and CVINB are initialized to all zeros; S15. Set the first parameter M1data and the comparison variable BiJiao.

8. The control method according to claim 7, characterized in that: In S11, the method of calling the low-frequency interrupt subroutine is specifically as follows: A1. Determine whether SELF is false. If so, set ACDATA[i] = AVINA[i], where i = 0 to 799, and enter A2; If not, set ACDATA[i]=AVINB[i], where i=0-799, and enter A2; A2. Invert SELF, and in response to the fact that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero, and AVINA[i+2] is greater than or equal to AVINA[i] in the range of i=2-401, set WZ=i and startF=1.

9. The control method according to claim 8, characterized in that: In S12, the method of calling the high-frequency interrupt subroutine is specifically as follows: B1, determine whether SELF is false, if so, go to SB2; If not, let AVINA be equal to the storage value of the memory corresponding to the voltage sensor (1), let AIINA be equal to the storage value of the memory corresponding to the current sensor (2), BVINA be equal to the storage value of the memory corresponding to the voltage sensor (1), let BIINA be equal to the storage value of the memory corresponding to the current sensor (2), CVINA be equal to the storage value of the memory corresponding to the voltage sensor (1), let CIINA be equal to the storage value of the memory corresponding to the current sensor (2); AFV[CNTCNN]=(AVINA–32768) / 32768 AFI[CNTCNN]=(AIINA–32768) / 32768 BFV[CNTCNN]=(BVINA–32768) / 32768 BFI[CNTCNN]=(BIINA–32768) / 32768 CFV[CNTCNN]=(CVINA–32768) / 32768 CFI[CNTCNN]=(CIINA–32768) / 32768 Enter B3; B2, let AVINB be equal to the storage value of the memory corresponding to the voltage sensor (1), let AIINB be equal to the storage value of the memory corresponding to the current sensor (2), BVINB be equal to the storage value of the memory corresponding to the voltage sensor (1), let BIINB be equal to the storage value of the memory corresponding to the current sensor (2), CVINB be equal to the storage value of the memory corresponding to the voltage sensor (1), let CIINB be equal to the storage value of the memory corresponding to the current sensor (2); AFV[CNTCNN]=(AVINB–32768) / 32768 AFI[CNTCNN]=(AIINB–32768) / 32768 BFV[CNTCNN]=(BVINB–32768) / 32768 BFI[CNTCNN]=(BIINB–32768) / 32768 CFV[CNTCNN]=(CVINB–32768) / 32768 CFI[CNTCNN]=(CIINB–32768) / 32768 Enter B3; B3, add 1 to the value of CNTCNN, and in response to CNTCNN being greater than 800, set CNTCNN=0; Enter B4; B4, in response to FBZ being equal to 1, proceed to B5; B5. Determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN - WZ. If not, let WZ1 = 400 + CNTCNN - WZ; Enter B6; B6. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400; Enter B7; B7, control the A phase circuit and enter B8; B8. Add 133 to the WZ value to determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN - WZ. If not, let WZ1 = 400 + CNTCNN - WZ; Enter B9; B9, in response to WZ1 being greater than 400, subtract 400 from the value of WZ1; Enter B10; B10, control the B phase circuit and enter B11; B11, add 266 to the WZ value to determine whether CNTCNN is greater than WZ. If so, set WZ1 = CNTCNN - WZ; If not, set WZ1=400+CNTCNN-WZ and enter B12; B12, in response to WZ1 being greater than 400, the value of WZ1 is subtracted by 400, and the process proceeds to B13; B13, control the C phase circuit; The control methods for the A, B and C phase circuits are the same, specifically: In response to AVBZ[WZ1] being greater than or equal to 0.875, then: Turning off the output positive end switch (62), the input negative end switch (64), the positive end bridge switch (66), the positive left interconnection switch (67), the positive right interconnection switch (68), the negative left interconnection switch (69), the negative right interconnection switch (70) and the negative end bridge output switch (72); Turning on the output negative end switch (63), the input positive end switch (61), the switching switch (65), the negative end bridge switch (71) and the positive end bridge output switch (73); In response to AVBZ[WZ1] being less than 0.875 and greater than or equal to 0.625, then: Turn off the output positive end switch (62), the switching switch (65), the positive end bridge switch (66), the negative left interconnection switch (69), the negative right interconnection switch (70), and the negative end bridge output switch (72); Turning on the output negative end switch (63), the input positive end switch (61), the input negative end switch (64), the negative end bridge switch (71), the positive end bridge output switch (73), the positive left interconnection switch (67), and the positive right interconnection switch (68); In response to AVBZ[WZ1] being less than 0.625 and greater than or equal to 0.375, then: The output positive end switch (62), the switching switch (65), the positive left interconnection switch (67), and the positive right interconnection switch (68) are turned on, and the negative end bridge output switch (72) and the negative end bridge switch (71) are turned off; Turning on the output negative end switch (63), the input positive end switch (61), the input negative end switch (64), the positive end bridge output switch (73), the positive end bridge switch (66), the negative left interconnection switch (69), and the negative right interconnection switch (70); In response to AVBZ[WZ1] being less than 0.375 and greater than or equal to 0.125, then: Turn off the output negative terminal switch (63), the switching switch (65), the positive terminal bridge switch (66), the negative left interconnection switch (69), the negative right interconnection switch (70), and the negative terminal bridge output switch (72); Turning on the output positive end switch (62), the input positive end switch (61), the input negative end switch (64), the positive left interconnection switch (67), the positive right interconnection switch (68), the negative end bridge switch (71), and the positive end bridge output switch (73); In response to AVBZ[WZ1] being less than 0.125 and greater than or equal to -0.125, then: Turn off the output positive end switch (62), the switching switch (65), the positive end bridge switch (66), the negative left interconnection switch (69), the negative right interconnection switch (70), and the positive end bridge output switch (73); Turning on the output negative end switch (63), the input positive end switch (61), the input negative end switch (64), the positive left interconnection switch (67), the positive right interconnection switch (68), the negative end bridge switch (71), and the negative end bridge output switch (72); In response to AVBZ[WZ1] being less than -0.125 and greater than or equal to -0.375, then: Turn off the output positive end switch (62), the switching switch (65), the positive left interconnection switch (67), the positive right interconnection switch (68), the negative end bridge switch (71), and the positive end bridge output switch (73); Turning on the output negative end switch (63), the input positive end switch (61), the input negative end switch (64), the positive end bridge switch (66), the negative left interconnection switch (69), the negative right interconnection switch (70), and the negative end bridge output switch (72); In response to AVBZ[WZ1] being less than -0.375 and greater than or equal to -0.625, then: Turn off the output negative terminal switch (63), the switching switch (65), the positive terminal bridge switch (66), the negative left interconnection switch (69), the negative right interconnection switch (70), and the positive terminal bridge output switch (73); Turning on the output positive end switch (62), the input positive end switch (61), the input negative end switch (64), the positive left interconnection switch (67), the positive right interconnection switch (68), the negative end bridge switch (71), and the negative end bridge output switch (72); In response to AVBZ[WZ1] being less than -0.625 and greater than or equal to -0.875, then: Turn off the input positive end switch (61), the output negative end switch (63), the switching switch (65), the positive left interconnection switch (67), the positive right interconnection switch (68), the negative end bridge switch (71), and the positive end bridge output switch (73); Turning on the output positive end switch (62), the input negative end switch (64), the positive end bridge switch (66), the negative left interconnection switch (69), the negative right interconnection switch (70), and the negative end bridge output switch (72); In response to AVBZ[WZ1] being less than -0.875, then: Turn off the output negative terminal switch (63), the positive left interconnection switch (67), the positive right interconnection switch (68), the negative left interconnection switch (69), the negative right interconnection switch (70), the negative terminal bridge switch (71), and the positive terminal bridge output switch (73); The output positive end switch (62), the switching switch (65), the input positive end switch (61), the input negative end switch (64), the positive end bridge switch (66), and the negative end bridge output switch (72) are turned on.

10. The control method according to claim 9, characterized in that: In S2, the method of calling the tripping and compensation calculation subroutine is specifically as follows: S21. Calculate the following data: In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400; S22, calculate the minimum value of SUMVA, SUMVB and SUMVC, and assign it to MINSUMV; S23, calculate the maximum value of SUMIA, SUMIB and SUMIC, and assign it to MAXSUMI; S24, determine whether MINSUMV is less than MINSUMVG and MAXSUMI is greater than MAXSUMIG. If so, TZF=1; if not, TZF=0; S25. Calculate the following data: AIBZ[i]=M1data[i]–AFI[i+WZ] Wherein, i = 0 to 399; WZ1=WZ+133 In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400; BIBZ[i]=M1data[i]–BFI[i+WZ1] WZ1=WZ+266 In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400; CIBZ[i]=M1data[i]–CFI[i+WZ1] S26. Calculate the following data: S27, calculate the maximum value of ASUMZB, BSUMZB and CSUMZB, and assign it to MAXSUMBZ; Determine whether MAXSUMBZ is greater than or equal to BZYZ; if so, set FBZ = 1; if not, set FBZ = 0; In S3, the method of calling the tripping action subroutine is specifically as follows: S31, controlling the first IGBT (8) to be turned on, and controlling the mechanical circuit breaker (3) to be turned off; S32 , controlling the first IGBT ( 8 ) to turn off.

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