Shield grid groove type MOSFET and manufacturing method of source polycrystalline silicon of shield grid groove type MOSFET

Abstract

The invention relates to a shielded gate trench metal oxide semiconductor field effect transistor and a source polysilicon manufacturing method thereof. The shielded gate trench metal oxide semiconductor field effect transistor comprises a drain substrate, an epitaxial layer arranged on the drain substrate and a trench. An oxide layer covers the inner wall of the trench, a source polysilicon is arranged in the trench, a gate oxide layer is arranged on the source polysilicon, and a gate polysilicon is arranged on the gate oxide layer. The oxide layer on the lower two sides of the first polycrystalline silicon comprises a step structure formed by two sections of wet etching, and the corner of the source polycrystalline silicon is passivated by means of the two sections of wet etching processes and the two sections of dry etching processes so as to solve point discharge.

Description

Background Art

[0002] Power Metal Oxide Semiconductor Field Effect Transistor, generally referred to as Power MOSFET, is a field effect transistor that can be widely used in analog circuits and digital circuits. It has become the mainstream of power devices, and it occupies a dominant position in the market. It is often used in many electronic power applications. Power Metal Oxide Semiconductor Field Effect Transistor has a very low on-resistance, and because the gate input impedance of the Power Metal Oxide Semiconductor Field Effect Transistor is very large, the power dissipation at the input end is quite small. Furthermore, compared with the Power Bipolar Transistor, the Power Metal Oxide Semiconductor Field Effect Transistor has only a single carrier and does not have the disadvantage of minority carrier storage, so it also has the advantage of very fast switching speed. Therefore, the Power Metal Oxide Semiconductor Field Effect Transistor has become the mainstream of high-frequency and low-voltage (<200V) power components.

[0003] Compared with ordinary trench metal oxide semiconductor field effect transistors, shielded gate trench (SGT) process metal oxide semiconductor field effect transistors are simpler, have lower switching losses, narrow Miller platform, and low internal resistance. Specifically, the SGT process is 3-5 times deeper than the ordinary trench process, and a polysilicon electrode is added under the gate as a shielding electrode or coupling electrode. The shielding electrode is connected to the source electrode, which realizes the function of shielding the gate and the drift region, reduces the Miller capacitance, and speeds up the switching speed of the component. At the same time, it realizes the charge coupling effect, reduces the critical electric field strength of the drift region, reduces the on-resistance of the component, and can reduce the switching loss. Compared with ordinary trench metal oxide semiconductor field effect transistors, the internal resistance of SGT process metal oxide semiconductor field effect transistors is more than 2 times lower.

[0004] In actual SGT processes, defects often occur, resulting in component damage, causing difficulties in the metal oxide semiconductor process and reduced product yield. Summary of the invention

[0005] The present application provides a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor and the shielded gate trench metal oxide semiconductor field effect transistor manufactured thereby, which are used to correct defects generated in the process.

[0006] An embodiment of the present application provides a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor. The method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor includes: providing a drain substrate having an epitaxial layer; etching a trench; configuring an oxide layer to insulate the inner wall of the trench; depositing a first polysilicon; performing a first dry etching process to lower the first polysilicon to below the top of the trench; performing a first wet etching process to lower the oxide layer, retain a portion of the oxide layer on the drain substrate, and expose the first polysilicon in the trench; performing a second dry etching process to lower the first polysilicon; and performing a second wet etching process to remove the oxide layer on the drain substrate and lower the oxide layer in the trench.

[0007] According to the preferred embodiment of the present invention, the method for manufacturing the source polysilicon of the shielded gate trench metal oxide semiconductor field effect transistor further comprises: configuring a gate oxide layer after etching the oxide layer. According to the preferred embodiment of the present invention, the method for manufacturing the source polysilicon of the shielded gate trench metal oxide semiconductor field effect transistor further comprises: configuring a gate oxide layer after etching the oxide layer. According to the preferred embodiment of the present invention, the method for manufacturing the source polysilicon of the shielded gate trench metal oxide semiconductor field effect transistor further comprises: configuring a gate oxide layer after etching the oxide layer after etching the oxide layer.

[0008] The embodiment of the present application further provides a shielded gate trench metal oxide semiconductor field effect transistor, which includes a drain substrate, an epitaxial layer and a trench. The epitaxial layer is arranged on the drain substrate. The inner wall of the trench is covered with an oxide layer, and a source polysilicon is arranged in the trench, a gate oxide layer is arranged on the source polysilicon, and a gate polysilicon is arranged on the gate oxide layer. The oxide layer on both sides of the first polysilicon lowering includes a stepped structure formed by two stages of wet etching, wherein the source polysilicon corner is passivated by two stages of wet etching process and two stages of dry etching process to solve the tip discharge.

[0009] According to the shielded gate trench metal oxide semiconductor field effect transistor described in the preferred embodiment of the present application, wherein the trench further includes a P-type body region and an N+ doped region on one side, wherein the N+ doped region is configured in the P-type body region and adjacent to the trench. According to the shielded gate trench metal oxide semiconductor field effect transistor described in the preferred embodiment of the present invention, wherein the N+ doped region further includes: a P+ doped region configured in the P-type body region and adjacent to the N+ doped region on one side. According to the shielded gate trench metal oxide semiconductor field effect transistor described in the preferred embodiment of the present invention further includes a source metal layer electrically connected to the N+ doped region.

[0010] According to the shielded gate trench metal oxide semiconductor field effect transistor described in the preferred embodiment of the present application, the process of gate polysilicon includes: after the trench on the drain substrate is completed, an oxide layer is configured to insulate the inner wall of the trench; a first polysilicon is deposited; a first dry etching process is performed to lower the first polysilicon to below the top of the trench; a first wet etching process is performed to lower the oxide layer, retain a portion of the oxide layer on the drain substrate, and expose the first polysilicon in the trench; a second dry etching process is performed to lower the first polysilicon; and a second wet etching process is performed to remove the oxide layer on the drain substrate and lower the oxide layer in the trench.

[0011] In summary, the embodiment of the present application adopts two-stage dry etching process and two-stage wet etching process. Therefore, during the second dry etching process, the etching of the first polysilicon will not have the problem of incomplete edge etching. It also further reduces the problem of sharp corners in the upper half of the source polysilicon. Therefore, it also greatly reduces the tip discharge of the source polysilicon and reduces the risk of circuit collapse leading to structural failure.

[0012] In order to further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, so that the purpose, features and concepts of the present invention can be thoroughly and specifically understood. However, the following detailed description and accompanying drawings are only used for reference and explanation of the implementation of the present invention, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are provided to enable a person with ordinary knowledge in the technical field to which the present application belongs to further understand the present application, and are incorporated into and constitute a part of the specification of the present application. The accompanying drawings illustrate exemplary embodiments of the present application, and are used together with the specification of the present application to explain the principles of the present application.

[0014] Figure 1 FIG. 1 is a flow chart of a method for fabricating source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to an embodiment of the present application.

[0015] Figure 2A FIG. 1 is a schematic diagram of step S101 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0016] Figure 2B FIG. 1 is a schematic diagram of step S102 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0017] Figure 2CFIG. 1 is a schematic diagram of step S103 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0018] Figure 2D FIG. 1 is a schematic diagram of step S104 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0019] Figure 2E FIG. 1 is a schematic diagram of step S105 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0020] Figure 2F FIG. 1 is a schematic diagram of step S106 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0021] Figure 3 FIG. 1 is a flow chart of a method for fabricating source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to an embodiment of the present application.

[0022] Figure 4A FIG. 1 is a schematic diagram of step S301 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0023] Figure 4B FIG. 1 is a schematic diagram of step S302 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0024] Figure 4C FIG. 1 is a schematic diagram of step S303 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0025] Figure 4D FIG. 1 is a schematic diagram of step S304 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0026] Figure 4EFIG. 1 is a schematic diagram of step S305 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0027] Figure 4F FIG. 1 is a schematic diagram of step S306 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0028] Figure 4G FIG. 1 is a schematic diagram of step S307 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0029] Figure 4H FIG. 1 is a schematic diagram of step S308 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0030] Fig. 4I FIG. 1 is a schematic diagram of step S309 of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to a preferred embodiment of the present application.

[0031] Figure 5 FIG. 4 is a cross-sectional view of a shielded gate trench metal oxide semiconductor field effect transistor according to a preferred embodiment of the present application. DETAILED DESCRIPTION

[0032] Reference will now be made in detail to the exemplary embodiments of the present application, which are illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and the specification to refer to the same or similar components. In addition, the exemplary embodiments are only one of the implementation methods of the design concept of the present application, and the following examples are not intended to limit the present application.

[0033] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) according to an embodiment of the present invention. Figure 1 In this embodiment, the method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor includes the following steps:

[0034] Step S101: Etching a groove 20. Figure 2A shown.

[0035] Step S102: forming an oxide layer 201 in the trench 20. Figure 2B The oxide layer 201 is mainly used to insulate the inner wall of the trench 20. The oxide layer 201 is specifically implemented as a thermal oxide layer or a deposited oxide layer, but is not limited to these two types.

[0036] Step S103: depositing a first polysilicon 202a. Figure 2C shown.

[0037] Step S104: dry etching is performed to form a source polysilicon 202b. Figure 2D As shown, the etching process removes the first polysilicon 202a from the surface.

[0038] Step S105: Perform wet etching to remove the oxide layer 201 from the surface. Figure 2E shown.

[0039] In the above embodiment, during the etching process in step S104, the portion 230 close to the edge of the first polysilicon 202a is difficult to remove. Figure 2F As shown, the surface of the final structure of the source polysilicon 202b is sunken, resulting in a certain probability that the source polysilicon 202b will discharge at the tip when the shielded gate trench metal oxide semiconductor field effect transistor is subsequently manufactured, and penetrate the gate oxide layer 203, thereby causing the gate polysilicon 204b and the source polysilicon 202b to short-circuit.

[0040] In order to solve the above problems, the present application further provides a method for manufacturing a gate of a shielded gate trench metal oxide semiconductor field effect transistor. Figure 3 FIG. 1 is a flow chart of a method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention. Figure 3 In this embodiment, the method for manufacturing the source polysilicon of the shielded gate trench metal oxide semiconductor field effect transistor comprises the following steps:

[0041] Step S301: Provide a drain substrate having an epitaxial layer. Figure 4A As shown, there is an epitaxial layer 31 on the N+ drain substrate 30.

[0042] Step S302: Etching a groove 301. Figure 4B As shown, a trench 301 is etched on the epitaxial layer 31 .

[0043] Step S303: configuring an oxide layer 302. Figure 4C As shown, the oxide layer is a relatively thick oxide layer, which is used to insulate the inner wall of the trench 301 .

[0044] Step S304: depositing a first polysilicon 303a. Figure 4D As shown, by depositing the first polysilicon, the first polysilicon 303 a is deposited into the trench 301 .

[0045] Step S305: Perform a first dry etching process. Figure 4E As shown, the difference between the first dry etching process and the dry etching process of step S104 is that the first dry etching process is only performed halfway. Therefore, the first dry etching process will generally remove the first polysilicon 303a on the surface and reduce the first polysilicon 303a in the trench 301. The degree of reduction of the first polysilicon 303a in the trench 301 caused by step S305 is not as good as that of step S104.

[0046] Step S306: Perform a first wet etching process. Figure 4F As shown, the first wet etching process is similar to step S105 and is only performed halfway. In other words, after step S306 is completed, the oxide layer 302 is still retained on the surface, but a portion of the oxide layer 302 near the first polysilicon 303a in the trench 301 is removed.

[0047] Step S307: Perform a second dry etching process. Figure 4G As shown, the second dry etching process etches the first polysilicon 303a in the trench 301 to a height within the specification to serve as the source polysilicon 303b.

[0048] A person with ordinary knowledge in the technical field can see that since the first polysilicon 303a in the trench 301 has been exposed outside the oxide layer 302 before step S307, when performing step S307, the dry etching process can directly etch the exposed first polysilicon 303a and avoid the sharp corners (polysilicon sharpness) caused by the edge effect.

[0049] Step S308: Perform a second wet etching process. Figure 4H As shown, the second wet etching process is used to remove the oxide layer 302 on the surface and lower the oxide layer 302 in the trench 301 to expose the first polysilicon 303a as the source polysilicon 303b. After the second wet etching process is completed, the oxide layer 302 in the trench 301 will have a structure similar to a step 320.

[0050] Step S309: configuring a gate oxide layer 304. Fig. 4I As shown, the gate oxide layer 304 is a thin oxide layer used to cover the source polysilicon 303b.

[0051] Step S310: performing polysilicon etching back.

[0052] The subsequent process is to make the gate and necessary transistor configuration to complete the shielded gate trench metal oxide semiconductor field effect transistor. Since the subsequent process can be made by the previous method or the improved method, it will not be described in detail here.

[0053] Above Fig. 4I It is a schematic diagram of the cross section after completing the process step S309. It can be seen that since the present application adopts two-stage dry etching process and two-stage wet etching process, the etching of the first polysilicon 303a during the second dry etching process will not have the problem of incomplete edge etching. It also further reduces the problem of the sharp corner of the upper half of the source polysilicon 303b. Therefore, this embodiment also greatly reduces the probability of discharge at the tip of the source polysilicon 303b during actual use, thereby reducing the risk of circuit breakdown (Breakdown) leading to structural failure.

[0054] Furthermore, in the above embodiment, the reason why the first wet etching process is semi-wet etching and the oxide layer 302 is intentionally retained on the surface is that when the second dry etching process in the subsequent step S307 is performed, there is no need to use a mask, and the residual oxide layer 302 can protect the epitaxial layer of the drain substrate from being damaged. In addition, since the price of the mask is relatively high, the embodiment of the present application also reduces the manufacturing cost. In addition, the above Figure 4A to Figure 4I It is only used to enable those with ordinary knowledge in the technical field to understand the spirit of the present application. The actual process will not have such perfect vertical angles or horizontal lines as shown in the figure. In particular, wet etching usually leads to rounded corners or slopes. Therefore, the cross-sectional view of the shielded gate trench metal oxide semiconductor field effect transistor actually produced according to the present application will correspond to the above figure but not be exactly the same. Therefore, the transistor structure of the present application is not limited to the ideal figure in the above figure.

[0055] Figure 5 FIG. 1 is a cross-sectional view of a shielded gate trench metal oxide semiconductor field effect transistor according to a preferred embodiment of the present application. Figure 5In this embodiment, the structure of the shielded gate trench metal oxide semiconductor field effect transistor includes a drain substrate 30, an epitaxial layer 31 is provided on the drain substrate 30, a trench 301 is arranged on the epitaxial layer 31, and the trench 301 includes an oxide layer 302, a source polysilicon 303b, a gate oxide layer 304, and a gate polysilicon 305b. There are P body doping regions 501 on both sides of the trench 301. The P body doping region 501 includes an N+ doping region 502 adjacent to both sides of the trench 301 and a P+ doping region 503 adjacent to the N+ doping region 502. In addition, a dielectric layer 504 for insulation is arranged on the trench 301. A source metal layer is arranged on the N+ doping region 502, and is electrically connected to the N+ doping region 502 as a source. In this embodiment, it can be seen that the source polysilicon 303b buried in the trench 301 is much thicker than the source polysilicon 303b after the two-stage wet etching and two-stage dry etching processes. Figure 2E The flatness of the source polysilicon 202b is high and the edge is less sharp. Since the wet etching process S306, S308 and the dry etching process S307, S309 do not need to use shielding, the embodiment of the present application can use a lower cost process.

[0056] In summary, the embodiment of the present application adopts two-stage dry etching process and two-stage wet etching process. Therefore, during the second dry etching process, the etching of the first polysilicon 303a will not have the problem of incomplete edge etching. The problem of sharp corners in the upper half of the source polysilicon 303b is further reduced. Therefore, the tip discharge of the source polysilicon 303b is greatly reduced, reducing the risk of circuit collapse leading to structural failure.

[0057] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in view thereof will be suggested to those skilled in the art and are to be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor, characterized in that: include: Providing a drain substrate having an epitaxial layer; etching a groove; Disposing an oxide layer to insulate the inner wall of the trench; depositing a first polysilicon; Performing a first dry etching process to reduce the height of the first polysilicon to below the top of the trench; Performing a first wet etching process to reduce the height of the oxide layer, retain a portion of the oxide layer on the drain substrate, and expose the first polysilicon in the trench; Performing a second dry etching process to reduce the height of the first polysilicon; as well as A second wet etching process is performed to remove the oxide layer on the drain substrate and reduce the oxide layer in the trench.

2. The method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, characterized in that: After etching the oxide layer, the method further comprises: A gate oxide layer is configured.

3. The method for manufacturing source polysilicon of a shielded gate trench metal oxide semiconductor field effect transistor according to claim 1, characterized in that: After a second wet etching process is performed, the oxide layer on both sides of the first polysilicon layer comprises a stepped structure.

4. A shielded gate trench metal oxide semiconductor field effect transistor, characterized in that: include: a drain substrate; an epitaxial layer, disposed on the drain substrate; A trench, the inner wall of which is covered with an oxide layer, a source polysilicon is disposed in the trench, a gate oxide layer is disposed on the source polysilicon, and a gate polysilicon is disposed on the gate oxide layer; Wherein, the oxide layer on both sides of the gate polysilicon lowering comprises a stepped structure formed by two stages of wet etching, The corners of the source polysilicon are passivated by two wet etching processes and two dry etching processes to solve the problem of tip discharge.

5. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 4, characterized in that: On one side of the groove further comprises: a P-type body region; and An N+ doped region is disposed in the P-type body region and is adjacent to the trench.

6. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 5, characterized in that: On one side of the N+ doped region further comprises: A P+ type doping region is disposed in the P type body region and is adjacent to the N+ doping region.

7. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 5, characterized in that: Also includes: A source metal layer is electrically connected to the N+ doped region.

8. The shielded gate trench metal oxide semiconductor field effect transistor according to claim 4, characterized in that: The process of gate polysilicon includes: After the trench on the drain substrate is completed, an oxide layer is disposed to insulate the inner wall of the trench; depositing a first polysilicon; Performing a first dry etching process to lower the first polysilicon to below the top of the trench; Performing a first wet etching process to lower the oxide layer, retain a portion of the oxide layer on the drain substrate, and expose the first polysilicon in the trench; performing a second dry etching process to reduce the first polysilicon; and A second wet etching process is performed to remove the oxide layer on the drain substrate and reduce the oxide layer in the trench.

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