Wafer-level chip TSV packaging structure and packaging method thereof

Abstract

The invention relates to a wafer-level chip TSV packaging structure and a packaging method thereof, belonging to the field of semiconductor manufacturing technology, comprising: a CPU module, a silicon interposer and a substrate connected in sequence, and also comprising a first through silicon via, a metal core and a first insulating layer, wherein a plurality of first through silicon vias are opened in the silicon interposer, and a buffer cavity is opened at the opening of the first through silicon via; the metal core is filled in the first through silicon via, and the CPU module is electrically connected to the circuit etched on the substrate and the silicon interposer through the metal core; the first insulating layer is filled in a section between the first through silicon via and the metal core that does not include the buffer cavity, and the first insulating layer has thermoplasticity; the invention can solve the technical problem in the prior art that the chip is damaged due to thermal expansion of the conductive metal filled in the TSV of the wafer-level chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a wafer-level chip TSV packaging structure and a packaging method thereof. Background Art

[0002] TSV (Through Silicon Via) technology is a basic technology for highly integrated semiconductor packaging structures. It opens through silicon vias on the pins of silicon interposers or grains and fills them with conductive materials to enable vertical interconnection between different grains and substrates, shorten the length of wires, increase signal transmission speed, and reduce volume. It is a major direction of semiconductor development.

[0003] The existing patent with announcement number CN103219325B discloses a multi-dimensional integrated circuit structure and a method for forming the same, wherein each first die includes a TSV connected to a conductive connector (e.g., which may be a C4 bump). TSVs may be formed before forming active or passive devices in each first die and before cutting each first die from a wafer. Although TSVs are part of a wafer, TSVs may be formed by forming an opening through the surface of the first die substrate (such as by etching, grinding, laser technology, combinations thereof, etc.). A thin barrier layer is conformally deposited above the first die substrate and in the opening, such as by CVD, ALD, PVD, thermal oxidation, combinations thereof, etc. The barrier layer may include nitrides or oxynitrides, such as titanium nitride, titanium oxynitride, tantalum nitride, tungsten nitride, combinations thereof, etc.

[0004] The prior art has the following problems:

[0005] Nitride or nitride oxide is used as a barrier layer, which is set between TSV and conductive metal material. When the chip runs at high load, the conductive metal expands due to heat. Nitride or nitride oxide has high hardness. The expanded conductive metal will squeeze the electronic components at both ends of the TSV, causing their connection to fall off, or directly crack the barrier layer, causing damage to the TSV, both of which will cause damage to the chip. Summary of the invention

[0006] The present invention provides a wafer-level chip TSV packaging structure and a packaging method thereof, which can solve the technical problem in the prior art that the chip is damaged due to thermal expansion of conductive metal filled in the TSV of the wafer-level chip.

[0007] In order to achieve the above object, the present invention is implemented by the following technical solutions:

[0008] The present invention provides a wafer-level chip TSV packaging structure, comprising a CPU module, a silicon interposer and a substrate connected in sequence, and also comprising a first silicon through via, a metal core and a first insulating layer, wherein a plurality of first silicon through vias are opened in the silicon interposer, and a buffer cavity is opened at the opening of the first silicon through via; the metal core is filled in the first silicon through via, and the CPU module is electrically connected to the substrate and the circuit etched on the silicon interposer through the metal core; the first insulating layer is filled in a section between the first silicon through via and the metal core that does not include the buffer cavity, and the first insulating layer has thermoplasticity.

[0009] Through the above technical solution, a first thermoplastic insulating layer is used. When the metal core undergoes thermal expansion due to a large amount of heat generated during chip operation, the first thermoplastic insulating layer can be squeezed and deformed to become thinner, thereby preventing the silicon interposer and the metal core from cracking and being damaged due to different thermal expansion coefficients.

[0010] In the present invention, the first insulating layer is a composite material of silicone rubber and boron nitride.

[0011] Through the above technical scheme, a composite material of silicone rubber and boron nitride is used as the first insulating layer. Boron nitride itself has electrical insulation properties. After being added to silicone rubber, it can significantly improve the insulation resistance and dielectric strength of the composite material, effectively prevent current leakage or short circuit in the silicon through hole, ensure the electrical isolation between electronic components, and improve the reliability and stability of the entire circuit; at the same time, boron nitride has a high thermal conductivity. When the electronic device is working, heat will be generated in the silicon through hole. Good heat dissipation performance helps to dissipate the heat in time, prevent heat accumulation from causing local overheating, thereby improving the working efficiency and reliability of the electronic device; further, silicone rubber has good fluidity and formability, and is easy to be filled into the silicon through hole through injection molding, molding and other processes to form a uniform and dense insulating layer.

[0012] In the present invention, the above-mentioned packaging structure also includes a second connecting ball and a second insulating layer, the second connecting ball is connected between the CPU module and the metal core, and the second connecting ball is electrically connected to the CPU module and the circuit etched on the surface of the silicon interposer; the second insulating layer is arranged on the side wall of the buffer cavity and the end face of the silicon interposer, and the second insulating layer insulates and isolates the second connecting ball and the metal core from the silicon interposer.

[0013] Through the above technical solution, the second insulating layer is used to insulate and protect the through silicon via terminal, so as to avoid the second connecting ball being directly electrically connected to the silicon interposer, thereby improving the stability of electrical signal transmission after connection.

[0014] In the present invention, the above-mentioned CPU module includes a first grain, a second grain, a third grain and a fourth grain connected layer by layer, and also includes a second silicon via, a logic unit, a wire, a pin and a logic wire, the second silicon via is opened in the first grain, the second grain and the third grain; the logic unit is connected to the first grain, the second grain, the third grain and the fourth grain; the wire is connected to the outside of the logic unit; a number of pins are electrically connected to the second silicon via or the first silicon via; the logic wire is connected between the wire and the pin, and the logic wire changes its own conductivity based on its own physical properties and environmental factors.

[0015] Through the above technical solution, 3D packaging technology is used in the CPU module to improve the integration of the package. At the same time, the conductivity of the circuit is changed based on the changes in the physical properties of the chip itself by using logic wires, which plays a physical overheating protection at the hardware level and further improves the stability of chip operation.

[0016] In the present invention, the above-mentioned logic wire is a wire made of vanadium dioxide.

[0017] Through the above technical solution, vanadium dioxide is used as a conductor. When the temperature rises, the vanadium dioxide is transformed into a conductor, thereby connecting grains at different levels, thereby sharing the workload of a single grain.

[0018] The present invention also discloses a packaging method of the wafer-level chip TSV packaging structure as described above, which comprises the following steps:

[0019] Step S1: preparing a plurality of wafers;

[0020] Step S2: preparing CPU module dies, functional module dies and silicon interposer on different wafers respectively;

[0021] Step S3: opening through silicon vias at the pin positions of the die and the silicon interposer;

[0022] Step S4: coating a first insulating layer at the through silicon via;

[0023] Step S5: trimming the first insulating layer in the through silicon via and coating it with a second insulating layer, then inserting a pre-prepared metal core, electrically connecting the middle part of the metal core to the surface circuit of the silicon interposer, and electrically connecting the two ends of the metal core to the surface circuit of the grain;

[0024] Step S6: Performing functional testing on the silicon interposer and the die;

[0025] Step S7: cutting the dies and silicon interposer on the wafer;

[0026] Step S8: Solder the silicon interposer to the substrate, solder the CPU module and the functional module to the silicon interposer, and then fill them with epoxy resin.

[0027] Through the above technical solution, the metal filling in the silicon through hole is completed by inserting a prefabricated metal core after coating the first insulating layer, which can effectively control the diameter and tightness of the metal core, thereby obtaining a more stable electrical signal transmission effect.

[0028] In the present invention, the above step S4 further includes the following steps:

[0029] Step S41: placing the wafer into a vacuum furnace, and after evacuation, coating the silicon through vias with silicone rubber, boron nitride composite materials and vulcanizing agent by a robot, introducing inert gas into the vacuum furnace to allow the silicone rubber and boron nitride composite materials to fully contact the silicon through vias, and taking the wafer out of the vacuum furnace after the silicone rubber and boron nitride composite materials are shaped.

[0030] Through the above technical solution, the first insulating layer is fully combined with the through silicon via by coating in a vacuum environment, thereby avoiding the occurrence of air gaps that affect the thermal conductivity efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of a wafer-level chip TSV packaging structure provided by an embodiment of the present invention;

[0033] Figure 2 for Figure 1 A partial enlarged view of the middle A;

[0034] Figure 3 A schematic structural diagram of a third crystal grain provided by an embodiment of the present invention;

[0035] Figure 4 for Figure 3 A partial enlarged view of point B in the middle.

[0036] Icons: 1-silicon interposer; 101-first connection ball; 102-first through silicon via; 2-CPU module; 201-fourth grain; 202-third grain; 203-second grain; 204-first grain; 205-second through silicon via; 206-second connection ball; 207-first insulating layer; 208-metal core; 209-buffer cavity; 210-second insulating layer; 3-functional module; 301-third connection ball; 401-logic unit; 4011-pin; 4012-wire; 4013-logic wire; 402-register; 403-controller; 404-clock; 5-substrate. DETAILED DESCRIPTION

[0037] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0039] In the description of the present invention, it is also necessary to explain that the drawings are only for illustrating the relative positional relationship of different structures and do not represent the actual circuit wiring.

[0040] Example:

[0041] Please refer to Figures 1 to 4 , Figures 1 to 4 An embodiment of the present invention is shown.

[0042] This embodiment provides a wafer-level chip TSV packaging structure, such as Figure 1 and Figure 2 As shown, it includes a CPU module 2, a silicon interposer 1 and a substrate 5 connected in sequence, and also includes a first silicon through via 102, a metal core 208 and a first insulating layer 207. A plurality of first silicon through vias 102 are opened in the silicon interposer 1, and a buffer cavity 209 is opened at the opening of the first silicon through via 102; the metal core 208 is filled in the first silicon through via 102, and the CPU module 2 is electrically connected to the circuit etched on the substrate 5 and the silicon interposer 1 through the metal core 208; the first insulating layer 207 is filled in a section between the first silicon through via 102 and the metal core 208 that does not include the buffer cavity 209, and the first insulating layer 207 has thermoplasticity.

[0043] When in use, the reserved buffer cavity 209 is used to accommodate the first insulating layer 207 that overflows after being squeezed by the metal core 208 due to thermal expansion.

[0044] Through the above technical solution, a first thermoplastic insulating layer 207 is used. When the metal core 208 undergoes thermal expansion due to a large amount of heat generated during chip operation, the first thermoplastic insulating layer 207 is squeezed to deform and thin, thereby preventing the silicon interposer 1 and the metal core 208 from cracking and being damaged due to different thermal expansion coefficients.

[0045] As a preferred implementation, the first insulating layer 207 is a composite material of silicone rubber and boron nitride.

[0046] It should be noted that the first insulating layer 207 is made of a composite material of silicone rubber and boron nitride, not only for its insulation and thermal conductivity, but more importantly for its thermoplasticity to correspond to the thermal deformation of the metal core 208, thereby avoiding damage to the chip caused by the thermal deformation of the metal core 208.

[0047] Through the above technical scheme, a composite material of silicone rubber and boron nitride is used as the first insulating layer 207. Boron nitride itself has electrical insulation properties. After being added to silicone rubber, it can significantly improve the insulation resistance and dielectric strength of the composite material, effectively prevent current leakage or short circuit in the silicon via, ensure the electrical isolation between electronic components, and improve the reliability and stability of the entire circuit; at the same time, boron nitride has a high thermal conductivity. When the electronic device is working, heat will be generated in the silicon via. Good heat dissipation performance helps to dissipate the heat in time, prevent heat accumulation from causing local overheating, thereby improving the working efficiency and reliability of the electronic device; further, silicone rubber has good fluidity and formability, and is easy to be filled into the silicon via through injection molding, molding and other processes to form a uniform and dense insulating layer.

[0048] As a preferred embodiment, the above-mentioned packaging structure also includes a second connecting ball 206 and a second insulating layer 210. The second connecting ball 206 is connected between the CPU module 2 and the metal core 208, and the second connecting ball 206 is electrically connected to the CPU module 2 and the circuit etched on the surface of the silicon interposer 1; the second insulating layer 210 is arranged on the side wall of the buffer cavity 209 and the end face of the silicon interposer 1, and the second insulating layer 210 insulates and isolates the second connecting ball 206 and the metal core 208 from the silicon interposer 1.

[0049] Through the above technical solution, the second insulating layer 210 is used to insulate and protect the TSV terminal, so as to prevent the second connecting ball 206 from being directly electrically connected to the silicon interposer 1, thereby improving the stability of electrical signal transmission after connection.

[0050] As a preferred implementation method, Figure 1 As shown, the CPU module 2 includes a first die 204, a second die 203, a third die 202, a fourth die 201 and a second through silicon via 205 connected layer by layer. Figure 3 and Figure 4 As shown, it also includes a logic unit 401, a wire 4012, a pin 4011 and a logic wire 4013, the second silicon via 205 is opened in the first grain 204, the second grain 203 and the third grain 202; the logic unit 401 is connected to the first grain 204, the second grain 203, the third grain 202 and the fourth grain 201; the wire 4012 is connected to the outside of the logic unit 401; a number of pins 4011 are electrically connected to the second silicon via 205 or the first silicon via 102; the logic wire 4013 is connected between the wire 4012 and the pin 4011, and the logic wire 4013 changes its own conductivity based on its own physical properties and environmental factors.

[0051] It should be noted that if Figure 3 As shown, a chip of the CPU module 2 includes a logic unit 401, a register 402, a controller 403 and a clock 404. When the first chip 204 close to the silicon interposer 1 is overloaded and overheated, the heat resistance of the logic wire 4013 is reduced, so that the second chip 203 is physically connected to share the load of the first chip 204. Similarly, the third chip 202 and the fourth chip 201 are gradually physically connected. The impedance changes and model reflection problems caused by the connection of multiple chips can be optimized at the software level. For example, adaptive equalization technology can be used. Adaptive equalization technology can automatically adjust signal gain and phase and other parameters according to changes in the signal transmission process to compensate for the attenuation and distortion of the signal during the transmission process, including signal changes caused by reflection. It continuously monitors the quality of the signal and dynamically optimizes the equalization effect of the signal according to preset algorithms and criteria, thereby improving the transmission performance of the signal and reducing the impact of factors such as reflection on the signal. As shown in FIG. Figure 3 After the functional module 3 shown is connected to the silicon interposer 1 through the third connection ball 301, the exemplary functional module 3 may be a module for supporting adaptive equalization technology such as a signal processor (DSP) or FPGA, a high-speed analog-to-digital converter (ADC) and a digital-to-analog converter (DAC), and a radio frequency (RF) front-end device.

[0052] Through the above technical solution, 3D packaging technology is used in the CPU module 2 to improve the integration of the package. At the same time, the logic wire 4013 is used to change the conductivity of the circuit based on the change of the physical properties of the chip itself, which plays a physical overheating protection at the hardware level and further improves the stability of the chip operation.

[0053] As a preferred implementation, the logic conductor 4013 is a conductor 4012 made of vanadium dioxide.

[0054] The phase transition temperature of vanadium dioxide is about 68 degrees Celsius. When the temperature is below 68 degrees Celsius, it becomes a transparent insulator, and when the temperature is above 68 degrees Celsius, it becomes a metallic state.

[0055] Through the above technical solution, vanadium dioxide is used as the conductor 4012. When the temperature rises, the vanadium dioxide is transformed into a conductor, thereby connecting grains at different levels, thereby sharing the workload of a single grain.

[0056] This embodiment also provides a packaging method for the wafer-level chip TSV packaging structure as described above, which includes the following steps:

[0057] Step S1: preparing a plurality of wafers;

[0058] Step S2: preparing the crystal grains of the CPU module 2, the crystal grains of the functional module 3 and the silicon interposer 1 on different wafers respectively;

[0059] Step S3: opening a through silicon via at the position of the pin 4011 of the die and the silicon interposer 1;

[0060] Step S4: coating a first insulating layer 207 at the through silicon via;

[0061] Step S5: trimming the first insulating layer 207 in the through silicon via and coating it with a second insulating layer 210, then inserting the pre-prepared metal core 208, electrically connecting the middle part of the metal core 208 to the surface circuit of the silicon interposer 1, and electrically connecting the two ends of the metal core 208 to the surface circuit of the grain;

[0062] Step S6: Performing functional testing on the silicon interposer 1 and the die;

[0063] Step S7: cutting the crystal grains and the silicon interposer 1 on the wafer;

[0064] Step S8: Solder the silicon interposer 1 to the substrate 5, solder the CPU module 2 and the functional module 3 to the silicon interposer 1, and then fill them with epoxy resin.

[0065] Through the above technical solution, the metal filling in the silicon through hole is completed by coating the first insulating layer 207 and then inserting the prefabricated metal core 208, which can effectively control the diameter and tightness of the metal core 208, thereby obtaining a more stable electrical signal transmission effect.

[0066] As a preferred implementation, the above step S4 further includes the following steps:

[0067] Step S41: placing the wafer into a vacuum furnace, and after evacuation, coating the silicon through vias with silicone rubber, boron nitride composite materials and vulcanizing agent by a robot, introducing inert gas into the vacuum furnace to allow the silicone rubber and boron nitride composite materials to fully contact the silicon through vias, and taking the wafer out of the vacuum furnace after the silicone rubber and boron nitride composite materials are shaped.

[0068] Through the above technical solution, the first insulating layer 207 is fully combined with the through silicon via by coating in a vacuum environment, thereby avoiding the occurrence of air gaps that affect the thermal conductivity efficiency.

[0069] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A wafer-level chip TSV packaging structure, comprising a CPU module (2), a silicon interposer (1) and a substrate (5) connected in sequence, characterized in that: Also includes: A plurality of first through silicon vias (102) are formed on the silicon interposer (1), wherein a buffer cavity (209) is formed at the opening of each of the first through silicon vias (102); A metal core (208) filled in the first through-silicon via (102), wherein the CPU module (2) is electrically connected to the substrate (5) and the circuit etched on the silicon interposer (1) via the metal core (208); a first insulating layer (207), filling a section between the first through silicon via (102) and the metal core (208) excluding the buffer cavity (209), the first insulating layer (207) having thermoplasticity; The CPU module (2) comprises a first die (204), a second die (203), a third die (202) and a fourth die (201) which are connected layer by layer, and further comprises: A second through silicon via (205) is opened on the first crystal grain (204), the second crystal grain (203) and the third crystal grain (202); A logic unit (401) connected to the first die (204), the second die (203), the third die (202) and the fourth die (201); A wire (4012) connected to the outside of the logic unit (401); A plurality of pins (4011) electrically connected to the second through silicon via (205) or the first through silicon via (102); The logic wire (4013) is connected between the wire (4012) and the pin (4011), and the logic wire (4013) changes its own conductivity based on its own physical properties and environmental factors.

2. The wafer-level chip TSV packaging structure according to claim 1, characterized in that: The first insulating layer (207) is a composite material composed of silicone rubber and boron nitride.

3. The wafer-level chip TSV packaging structure according to claim 2, characterized in that: Also includes: A second connection ball (206) connected between the CPU module (2) and the metal core (208), the second connection ball (206) being electrically connected to the CPU module (2) and a circuit etched on the surface of the silicon interposer (1); A second insulating layer (210) is arranged on the side wall of the buffer cavity (209) and on the end surface of the silicon intermediate layer (1), and the second insulating layer (210) insulates and isolates the second connecting ball (206) and the metal core (208) from the silicon intermediate layer (1).

4. The wafer-level chip TSV packaging structure according to claim 3, characterized in that: The logic wire (4013) is a wire made of vanadium dioxide.

5. A packaging method for a wafer-level chip TSV packaging structure as claimed in claim 4, characterized in that: The following steps are involved: Step S1: preparing a plurality of wafers; Step S2: preparing CPU module dies, functional module dies and silicon interposer on different wafers respectively; Step S3: opening through silicon vias at the pin positions of the die and the silicon interposer; Step S4: coating a first insulating layer at the through silicon via; Step S5: trimming the first insulating layer in the through silicon via and coating it with a second insulating layer, then inserting a pre-prepared metal core, electrically connecting the middle part of the metal core to the surface circuit of the silicon interposer, and electrically connecting the two ends of the metal core to the surface circuit of the grain; Step S6: Performing functional testing on the silicon interposer and the die; Step S7: cutting the dies and silicon interposer on the wafer; Step S8: Solder the silicon interposer to the substrate, solder the CPU module and the functional module to the silicon interposer, and then fill them with epoxy resin.

6. The packaging method of the wafer-level chip TSV packaging structure according to claim 5, characterized in that: The step S4 further comprises the following steps: Step S41: placing the wafer into a vacuum furnace, and after evacuation, coating the silicon through vias with a silicone rubber and boron nitride composite material and a vulcanizing agent by a robot, introducing an inert gas into the vacuum furnace to allow the silicone rubber and boron nitride composite material to fully contact the silicon through vias, and taking the wafer out of the vacuum furnace after the silicone rubber and boron nitride composite material is shaped.

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