A cross-domain clock synchronization method in time-sensitive networks

Abstract

The present invention relates to a cross-domain clock synchronization method in a time-sensitive network, and belongs to the field of time synchronization technology. The method includes: establishing a multi-domain clock synchronization network topology based on a transit clock; the transit clock obtains the master clock time according to the master domain synchronization message, and interacts with the adjacent device through a link delay measurement message, records the corresponding timestamp and obtains the link delay; the obtained master clock time, each timestamp, and link delay are transmitted to the synchronization error compensation prediction module in the transit clock, the synchronization error compensation prediction module calculates the clock time offset result, and predicts the error compensation; then the local clock is adjusted in frequency and phase according to the calculated error compensation prediction value, and then a slave domain synchronization message is sent to the adjacent slave clock device, and the slave domain synchronization message is forwarded and the clock is corrected in turn. The present invention can eliminate accumulated errors such as jitter, delay variation, and network congestion as much as possible.

Description

Technical Field

[0001] The present invention belongs to the technical field of time synchronization and relates to a cross-domain clock synchronization method in a time-sensitive network. Background Art

[0002] Time-Sensitive Networking (TSN) is a set of standards for real-time, deterministic communications in industries such as industry and the power sector. With the expansion of power grids, the integration of renewable energy sources, and the development of ultra-high voltage (UHV) transmission technology, power grids are becoming increasingly complex and intelligent. In smart grids, applications such as synchronous sampling, fault detection, event sequence recording, event location estimation, and inter-device coordination, while differing in their specific operations, all require precise time synchronization to eliminate discrepancies between local clocks. Therefore, time synchronization in smart grids is crucial for the secure and stable operation of each node. To address this need, the TSN protocol, spearheaded by IEEE 802.1AS, provides a precise time synchronization solution, significantly streamlining the previously redundant synchronization process and improving the efficiency and accuracy of time synchronization.

[0003] IEEE 802.1AS proposes a time-aware network consisting of multiple gPTP domains. Figure 1 An example of a time-aware network consisting of multiple gPTP domains is shown. Specifically, in this example, the network has two time domains, where domain 0 uses the PTP time scale and domain 1 uses the arbitrary (ARB) time scale. All PTP instances belonging to the same domain are required to have direct connections in their physical topology (e.g., time cannot be transferred from one PTP instance in domain 0 to another PTP instance in domain 0 via a time-aware system without domain 0 being active). In addition, a time-aware system in which both domains are active is represented by a slanted inner hatched line, representing two independent active PTP instances.

[0004] like Figure 2 The synchronization message format shown in the figure contains the domainNumber field, which is used to divide synchronization domains. Only clocks within the same synchronization domain can perform clock synchronization related actions. The default value of domainNumber is 0.

[0005] In practical applications, such as Figure 3 As shown, due to the low precision of the crystal oscillator of the slave clock, the clock time will always drift. The clock frequency and phase of the slave clock will continue to shift after being corrected, resulting in the need for continuous correction of the slave clock. Moreover, due to the different crystal oscillator performance of different clocks, the offset caused between synchronization cycles is different.

[0006] Currently, due to the continuous expansion of production scale, the number of network nodes is increasing, and the number of message transmission hops is also increasing. The accuracy of clock synchronization will gradually decrease with the increase in the number of hops, which leads to a decrease in the synchronization accuracy of edge devices and a continuous decrease in the anti-interference ability during the synchronization process. Summary of the Invention

[0007] In view of this, an object of the present invention is to provide a cross-domain clock synchronization method in a time-sensitive network.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] A cross-domain clock synchronization method in a time-sensitive network comprises the following steps:

[0010] S1. Establish a multi-domain clock synchronization network topology based on transit clocks in a multi-clock domain environment of a time-sensitive network;

[0011] S2: The transit clock obtains the master clock time based on the master domain synchronization message, exchanges link delay measurement messages with the adjacent device, records the corresponding timestamp, and obtains the link delay;

[0012] S3. The master clock time, timestamps, and link delay are transmitted to the synchronization error compensation prediction module in the transit clock. The synchronization error compensation prediction module then calculates the clock time offset result based on the adjacent clock frequency ratio and predicts the error compensation.

[0013] S4. The clock correction module in the transit clock adjusts the frequency and phase of the local clock according to the calculated error compensation prediction value, then sends a slave domain synchronization message to the adjacent slave clock device, and forwards the slave domain synchronization message and corrects the clock in turn.

[0014] Furthermore, in step S1, the master clock in the time-sensitive network and the set of synchronization devices B that are directly connected to and synchronized with the master clock are m The clock domain is divided into master domains, and the remaining set of synchronous devices close to the edge of the network is called slave domains. There is a bridge between the master and slave clock domains, namely device i, which is defined as a transit clock.

[0015] The transit clock is in both the master and slave clock domains. In the master clock domain, the transit clock acts as a slave clock, receiving synchronization messages from the clock source and correcting its own time. In the slave clock domain, the transit clock acts as the master clock of the domain, sending synchronization messages. Other devices in the slave clock domain receive synchronization messages sent by the transit clock and correct their own clocks. The transit clock can predict and correct synchronization errors based on the network environment.

[0016] Furthermore, the transit clock is internally provided with a local clock module, a message receiving port, a message sending port, a timestamp generating module, a synchronization error compensation prediction module, and a clock correction module, wherein the local clock is configured as a free-running clock existing in the transit clock entity, providing the transit clock with a time t l ; The timestamp generation module records the timestamps t1~t6 of the message reception and sending moments when the port interacts with the message; the synchronization error compensation prediction module calculates the clock time offset result based on the received message content and timestamp, and predicts the synchronization error compensation value that needs to be compensated; the clock correction module adjusts the local clock by modifying the frequency and phase according to the calculation results.

[0017] Further, in step S2, the transit clock receiving port receives the Sync / Follow_Up message sent by the Grand Master, and parses the master clock time t in the message. M , and record and process timestamps as follows:

[0018] S21. The peer delay initiator sends Pdelay_Req to the peer delay responder and records the time t1 when the message is sent;

[0019] S22. The peer delay responder records the timestamp t2 when it receives the Pdelay_Req. After receiving the Pdelay_Req, it returns a Pdelay_Resp message containing t2 to the peer delay requester, and records the timestamp t3 of the time when the Pdelay_Resp message was sent. It then immediately sends a Pdelay_Resp_Follow_Up message containing t3.

[0020] S23, when the peer delay initiator receives the Pdelay_Resp message, it records the time t4 when the message is received;

[0021] S24. The initiator calculates the link delay d using the timestamps t1, t2, t3, and t4 recorded above.

[0022] Furthermore, in step S24, the link delay d is calculated as follows:

[0023]

[0024] Where gmRR represents the frequency ratio between the master and slave clocks:

[0025]

[0026] gmRR is calculated based on historical data, where (t3) N and (t4) N(t3)0 and (t4)0 represent the time when the delay responder sends the Pdelay_Resp message and the time when the requester receives the Pdelay_Resp message during the Nth link delay measurement, respectively. (t3)0 and (t4)0 represent the time when the delay responder sends the Pdelay_Resp message and the time when the requester receives the Pdelay_Resp message during the first delay measurement.

[0027] Furthermore, in step S3, the synchronization error compensation prediction module predicts the clock time offset compensation value in the following manner:

[0028] S31. Obtain synchronization timestamp and calculate synchronization error: Obtain timestamps from the master clock and slave clock to obtain the master clock time vector T M , from the clock time vector T S and link delay time vector T D , and calculate the time error T E And synchronization error offset;

[0029] S32, collect the T M 、T S 、T D and T E The data is processed into a matrix form. The data set matrix includes input and target output. The Nk samples of the entire data set D={(x1,T E(k+1) ),(x2,T E(k+2) )…,(x i ,T E(k+i) ),…,(x N-k ,T E(N) )}, where input x i =[(T M ) i ,(T s ) i ,(T D ) i ,(T E ) i ], enter x i The form is:

[0030] (T M ) i =(t M(i) ,t M(i+1) ,...,t M(i+k-1) ) T

[0031] (T S ) i =(t S(i) ,t S(i+1) ,...,t S(i+k-1) ) T

[0032] (T D ) i =(t D(i) ,t D(i+1) ,…,t D(i+k-1) ) T

[0033] (T E ) i =(T E(i+1) ,T E(i+2) ,...,T E(i+k-1) ) T

[0034] S33, train the neural network based on the data set, adjust the training parameters according to the output, and output the prediction result offset pre ;

[0035] S34. Determine a threshold range based on the Gaussian distribution of the synchronization error, judge the factors affecting the synchronization error, and then determine the final deviation.

[0036] Furthermore, in step S31, the master clock periodically sends Sync messages and Follow_Up messages. After receiving the Sync message, the slave clock calculates:

[0037] t i =t GM +CF sync +d

[0038] Among them, t i Indicates the time when the transit clock is synchronized and corrected; t GM Indicates the time of the main clock; CF sync Indicates the correction value recorded in the Follow_Up message, including the residence time of each node from the Sync message and the link delay between nodes:

[0039]

[0040] Where x represents each synchronization node before the current node; ρ x Expressed as the residence time within the synchronization device;

[0041] When network fluctuations occur in the network, a delay of μ is generated on the link, and the transit clock time becomes:

[0042] t i =t GM +CF sync +d+μ

[0043] Further we get:

[0044]

[0045] where t' x Indicates the timestamp when the delay request message is received from the clock when there is link delay. d' indicates the link delay caused by network fluctuations.

[0046] Then the offset is expressed as:

[0047]

[0048] Therefore, each time vector as input is expressed as:

[0049] T M =(t M1 ,t M2 ,...t MN ) T

[0050] T S =(t S1 ,t S2 ,...t SN ) T

[0051] T D =(t D1 ,t D2 ,...t DN ) T

[0052] T E =t S -t M

[0053] Among them, t M and t S Respectively represent the timestamps of the master clock and the slave clock during calculation.

[0054] Furthermore, in step S34, the error of the synchronization clock conforms to the Gaussian distribution, that is:

[0055]

[0056] Where x is the clock error, μ is the mean, σ is the standard deviation, 2σ is used as the compensation judgment standard, the error range is set to (θ1, θ2), and the thresholds are set to θ1 = μ-2σ, θ2 = μ+2σ;

[0057] If the synchronization clock error is not within the error range (θ1, θ2), it is considered to be caused by network environment problems. If the synchronization clock error is within (θ1, θ2), it is considered to be caused by frequency changes:

[0058]

[0059] t cmp =|μ real -μ pre |

[0060] Where offset is the actual deviation of the clock, μ real Represents the mean value of the actual synchronization error, μ pre represents the mean of the prediction error, t cmp The difference between the absolute values ​​of the two is the compensation value.

[0061] Furthermore, in step S4, adjacent synchronous clocks forward synchronization messages and perform clock correction after link delay measurement. In the same clock domain, the steps of using synchronization messages to correct time are as follows:

[0062] S41. When the clock receives the Sync message, it records the timestamp of receiving the Sync message.

[0063] S42. The synchronous clock reads the timestamp t5 generated by the master device and the accumulated Correction_Field from the subsequent Follow_Up message. The Correction_Field includes the residence time and link delay of all clock nodes.

[0064] S43, after receiving the synchronization message, synchronously calculate the synchronization error relative to the master clock using the received t5 and t6;

[0065] S44, the synchronization clock adjusts the local clock according to the calculated synchronization error to keep it synchronized with the master clock;

[0066] S45. After the adjustment is completed, the synchronized clock forwards the Sync message to the downstream node, records the timestamp t'5 of sending the Sync message, and includes the timestamp t'5 in the subsequent Follow_Up message.

[0067] S46. Update the Correction_Field in the Follow_Up message, and add its own link delay and residence time to the original values ​​for subsequent clock synchronization.

[0068] The beneficial effects of the present invention are:

[0069] 1) In a multi-hop network, synchronization messages accumulate errors such as jitter, latency variation, and network congestion as they pass through each hop. If we rely solely on the time of the forwarding master clock, these errors will gradually amplify, resulting in a decrease in synchronization accuracy. Using a relay clock can minimize these errors.

[0070] 2) The transit clock has the ability to predict and compensate for synchronization errors, which effectively reduces the accumulation of errors in traditional multi-hop forwarding. This prediction mechanism can maintain high synchronization accuracy at more distant clock nodes.

[0071] 3) Transit clocks enable more localized and adaptive synchronization management by dividing the network into two synchronization domains. Each synchronization domain can be optimized based on local network conditions, thereby reducing synchronization errors caused by latency and fluctuations across the entire network.

[0072] Other advantages, objects, and features of the present invention will be described in part in the following description and, in part, will be apparent to those skilled in the art upon examination of the following description or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below with reference to the accompanying drawings, in which:

[0074] Figure 1 An example diagram of a time-aware network with multiple gPTP domains.

[0075] Figure 2 Schematic diagram of the synchronization message format;

[0076] Figure 3 Schematic diagram of clock deviation;

[0077] Figure 4 This is a topology diagram of a multi-domain clock synchronization network based on a transit clock according to the present invention;

[0078] Figure 5 This is a diagram of the internal framework of the transit clock of the present invention;

[0079] Figure 6 Schematic diagram of the interaction process of the transit clock of the present invention;

[0080] Figure 7 Schematic diagram of the peer-to-peer delay measurement method of the present invention;

[0081] Figure 8 Schematic diagram of the structure of the time error prediction neural network of the present invention. DETAILED DESCRIPTION

[0082] The following describes the embodiments of the present invention by means of specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0083] Among them, the accompanying drawings are only for illustrative purposes and represent only schematic diagrams rather than actual pictures, and should not be understood as limiting the present invention. In order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the dimensions of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the accompanying drawings.

[0084] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "back", etc. indicating directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0085] See also Figures 4 to 8 , which is a cross-domain clock synchronization method in time-sensitive networks.

[0086] Example

[0087] This embodiment proposes a clock synchronization method based on multiple clock domains. The method defines a new clock role, a transit clock, which can divide all synchronization nodes into two synchronization domains. The method predicts and corrects the synchronization error value of the transit clock by performing synchronization error prediction based on a synchronization error model of the network environment. The method includes the following steps:

[0088] S1. Establish a multi-domain clock synchronization network topology based on transit clocks in a multi-clock domain environment of a time-sensitive network;

[0089] S2: The transit clock obtains the master clock time based on the master domain synchronization message, exchanges link delay measurement messages with the adjacent device, records the corresponding timestamp, and obtains the link delay;

[0090] S3. The master clock time, timestamps, and link delay are transmitted to the synchronization error compensation prediction module in the transit clock. The synchronization error compensation prediction module then calculates the clock time offset result based on the adjacent clock frequency ratio and predicts the error compensation.

[0091] S4. The clock correction module in the transit clock adjusts the frequency and phase of the local clock according to the calculated error compensation prediction value, then sends a slave domain synchronization message to the adjacent slave clock device, and forwards the slave domain synchronization message and corrects the clock in turn.

[0092] In step S1 of this embodiment, Figure 4 The multi-domain clock synchronization network topology diagram based on the transit clock shown in the figure is a collection of the master clock and the synchronization equipment that is directly connected and synchronized with the master clock. m , m∈[1,i] is divided into the master clock domain (Master Domain); the remaining set of synchronized devices near the edge of the network is called the slave clock domain (Servant Domain). A "bridge" connects the master and slave clock domains, namely the correspondence clock of device i. The correspondence clock resides in both the master and slave clock domains. In the master clock domain, the correspondence clock acts as a slave clock, receiving synchronization messages from the clock source and correcting its own time. In the slave clock domain, the correspondence clock acts as the master clock of that domain, sending synchronization messages. The remaining devices in the slave clock domain receive synchronization messages from the correspondence clock and correct their own clocks. To improve the synchronization accuracy of synchronized devices in the slave clock domain, the correspondence clock predicts and corrects synchronization errors based on the network environment. This improves the synchronization accuracy and stability of its own clock, thereby improving the stability of devices in the slave clock domain.

[0093] like Figure 5 The framework diagram of the transit clock shown in the figure illustrates the synchronization function of the transit clock. The transit clock is provided with a clock signal by the local clock. The transit clock is equipped with a local clock module, a message receiving port, a message sending port, a timestamp generation module, a synchronization error compensation prediction module, and a clock correction module. The local clock is configured as a free-running clock existing in the transit clock entity, providing the transit clock with the time t l ; The timestamp generation module records the timestamps t1~t6 of the message reception and sending moments when the port interacts with the message; the synchronization error compensation prediction module calculates the clock time offset result based on the received message content and timestamp, and predicts the synchronization error compensation value that needs to be compensated; the clock correction module adjusts the local clock by modifying the frequency and phase according to the calculation results.

[0094] In step S2, the transit clock receiving port receives the Sync / Follow_Up message sent by the Grand Master and parses the master clock time t in the message. M Send Pdelay_Req, Pdelay_resp, and Pdelay_Resp_Follow_Up messages to other adjacent devices, recording the time t1 when the delay measurement requester sends the Pdelay_Req message, the time t2 when the delay measurement responder receives the Pdelay_Req message, the time t3 when the delay measurement responder sends the Pdelay_Resp message, and the time t4 when the delay measurement initiator receives the Pdelay_Resp message, and calculate the link delay d based on t1, t2, t3, and t4. Specifically, if Figure 6 As shown, it includes the following processes:

[0095] S21. The peer delay initiator sends Pdelay_Req to the peer delay responder and records the time when the message is sent, which is recorded as t1.

[0096] S22: The peer delay responder records the timestamp t2 when it receives the Pdelay_Req. After receiving the Pdelay_Req, it returns a Pdelay_Resp message containing the timestamp t2 to the peer delay requester, and records the timestamp t3 of the time the Pdelay_Resp message was sent. It then sends a Pdelay_Resp_Follow_Up message containing the timestamp t3.

[0097] S23. When the peer delay initiator receives the Pdelay_Resp message, it records the timestamp of receiving the message, which is recorded as t4.

[0098] S24, the synchronization correction module of the initiator calculates the link delay d based on the timestamps t1, t2, t3 and t4 recorded above. Let the master clock time be t M , from the clock time t s , under ideal conditions, the offset η of the synchronous clock can be calculated:

[0099] η=t s -t M

[0100] Since the slave clock has lower accuracy than the master clock and has frequency variations, let Δfη represent the time offset caused by the clock frequency variation. After taking the time offset into account, the synchronization offset value η can be changed to:

[0101] ε=η-Δfη=t s -tM

[0102] Δfη=gmRR·(t cur -t fro )t cur Indicates the local time corrected after the synchronization clock receives the synchronization message;

[0103] t fro Expressed as the time that has passed since the clock last received a synchronization message.

[0104] Where gmRR represents the frequency ratio between the master and slave clocks:

[0105]

[0106] When the synchronous clock performs link delay measurement, it exchanges three delay measurement messages with the peer delay responder to obtain four timestamps t1 to t4. The process is as follows: Figure 7 As shown, the corresponding link delay is calculated again, and considering the impact of the change in transit clock frequency, we can get:

[0107] t2-t1=d+Δfη

[0108] t4-t3=d-Δfη

[0109] Where d is the link delay. Substituting it into the above formula, we get the modified link delay measurement formula:

[0110] t2-t1=d+gmRR·(t1-t fro )

[0111] t4-t3=d-gmRR·(t4-t fro )

[0112] Get the corrected link delay d:

[0113]

[0114] In step S3 of this embodiment, the clock synchronization error prediction algorithm of the synchronization error compensation prediction module uses a neural network to perform synchronization prediction. The input of the prediction algorithm is T S ,T M ,T D ,T E Vector, the output is the predicted value TE of the synchronization error pre , the synchronization error prediction algorithm framework is as follows Figure 8 As shown, the time error prediction compensation steps are as follows:

[0115] S31. Obtain synchronization timestamp and calculate synchronization error: Obtain timestamps from the master clock and slave clock to obtain the master clock time vector T M , from the clock time vector T S and link delay time vector T D , and calculate the time error T E And synchronization error offset;

[0116] When the Sync message passes through the transit clock, the transit clock receives the Sync message, corrects and predicts its own clock, and then sends a new Sync message marked with the slave domain identifier to the next clock.

[0117] Let the master clock time be t M , from the clock time t s , under ideal conditions, the offset η of the synchronous clock can be calculated:

[0118] η=t s -t M

[0119] Since the slave clock has lower accuracy than the master clock and has frequency variations, let Δfη represent the time offset caused by the clock frequency variation. After taking the time offset into account, the synchronization offset value η can be changed to:

[0120] ε=η-Δfη=t s -t M

[0121] Δfη=gmRR·(t cur -t fro )t cur Indicates the local time corrected after the synchronization clock receives the synchronization message;

[0122] t fro Expressed as the time that has passed since the clock last received a synchronization message.

[0123] Where gmRR represents the frequency ratio between the master and slave clocks:

[0124]

[0125] When measuring link delay, the synchronized clock exchanges three delay measurement messages with the peer delay responder to obtain four timestamps. These timestamps are used to calculate the corresponding link delay from t1 to t4. Taking into account the influence of the transit clock frequency variation, the following is obtained:

[0126] t2-t1=d+Δfη

[0127] t4-t3=d-Δfη

[0128] Where d is the link delay. Substituting it into the above formula, we get the modified link delay measurement formula:

[0129] t2-t1=d+gmRR·(t1-t fro )

[0130] t4-t3=d-gmRR·(t4-t fro )

[0131] Get the corrected link delay d:

[0132]

[0133] The master clock periodically sends Sync messages and Follow_Up messages. After receiving the Sync message, the slave clock calculates the following:

[0134] t i =t GM +CF sync +d

[0135] where t s Indicates the time when the transit clock has been synchronized and corrected;

[0136] t GM Indicates the time of the master clock;

[0137] CF sync Indicates the correction value recorded in the Follow_Up message, including the residence time of each node from the Sync message and the link delay between nodes:

[0138]

[0139] Where x represents each synchronization node before the current node;

[0140] ρ x Expressed as the dwell time within the synchronized device.

[0141] When network fluctuations occur, a delay of μ is generated on the link, and the transit clock time becomes:

[0142] t i =t GM +CF sync +d+μ

[0143] Combined with the modified path measurement formula, we can get:

[0144]

[0145] where t' xrepresents the timestamp when the delay request message is received from the clock when there is link delay, and d' represents the link delay caused by network environment problems (such as network congestion). Then offset can be expressed as:

[0146]

[0147] The data in the above formula can be calculated by obtaining the timestamps contained in the synchronization messages exchanged between the master and slave clocks. Therefore, each timestamp can be used as the input of the prediction algorithm. gmRR is calculated based on historical data, and because past timestamps with phase information can reflect the trend of clock frequency changes, the input times can be written as:

[0148] T M =(t M1 ,t M2 ,...t MN ) T

[0149] T S =(t S1 ,t S2 ,...t SN ) T

[0150] T D =(t D1 ,t D2 ,...t DN ) T

[0151] Where T M represents the master clock time vector, T S represents the slave clock time vector, T D Represents the link delay time vector. The link delay time is calculated from four timestamps.

[0152] The time difference between the master clock and the slave clock is defined as the time error T E . t M and t S Respectively represent the timestamps of the master clock and the slave clock during calculation:

[0153] T E =t S -t M

[0154] TE is the difference in timestamp value. According to the above formula, the T that needs to be compensated is E It is believed to be the result of clock time drift.

[0155] S32, Dataset Generation: Collect the T M 、TS 、T D and T E The data is processed into a matrix form for further processing. The dataset matrix includes input and target output, and the Nk samples of the entire dataset D = {(x1, T E(k+1) ),(x2,T E(k+2) )…,(x i ,T E(k+i) ),…,(x N-k ,T E(N) )}, where input x i is: x i =[(T M ) i ,(T s ) i ,(T D ) i ,(T E ) i ]. Enter x i The specific form is as follows:

[0156] (T M ) i =(t M(i) ,t M(i+1) ,...,t M(i+k-1) ) T

[0157] (T S ) i =(t S(i) ,t S(i+1) ,...,t S(i+k-1) ) T

[0158] (T D ) i =(t D(i) ,t D(i+1) ,...,t D(i+k-1) ) T

[0159] (T E ) i =(T E(i+1) ,T E(i+2) ,...,T E(i+k-1) ) T

[0160] S33, neural network prediction: Figure 8 As shown, the neural network is trained using the data set, and the training parameters are adjusted according to the output, and the prediction result offset is output. pre ;

[0161] Input layer: The LSTM input layer passes the input data sequence to the subsequent hidden layer, where the data is formatted to suit subsequent calculations;

[0162] Hidden layer: processes each timestamp value in the input layer, accumulates the dependencies between the input data through three gates, and then obtains the output value, i.e., the synchronization error value, through linear transformation and activation function;

[0163] Output layer: outputs the synchronization error value for a period of time in the future.

[0164] S34. Calculate the synchronization error and determine the threshold range based on the Gaussian distribution of the synchronization error, and then determine the factors affecting the synchronization error. Since the error of the synchronization clock roughly conforms to the Gaussian distribution, that is:

[0165]

[0166] Where x is the clock error, μ is the mean, σ is the standard deviation, and 2σ is used as the compensation judgment standard. About 95% of the data are in the interval (μ-2σ, μ+2σ), so the threshold is determined to be θ1=μ-2σ, θ2=μ+2σ.

[0167] If the synchronous clock error is greater than or less than the set threshold, that is, offset < θ1 or offset > θ2, the error is considered to be caused by network environment problems such as link congestion. Since the synchronous clock frequency is relatively stable, the error in the offset range (θ1, θ2) is considered to be caused by frequency variation.

[0168]

[0169] t cmp =|μ real -μ pre |

[0170] Where, offset is the actual deviation of the clock, μ real Represents the mean value of the actual synchronization error, μ pre represents the mean of the prediction error, t cmp It represents the difference between the absolute values ​​of the two, that is, the compensation value.

[0171] In step S4 of this embodiment, adjacent synchronous clocks forward synchronization messages and perform clock correction after link delay measurement. Within the same clock domain, the steps of using synchronization messages to correct time are as follows:

[0172] S41. When receiving the Sync message, the clock records the timestamp t6, which indicates the time when the Sync message is received.

[0173] S42: The synchronous clock reads the timestamp t5 generated by the master device and the accumulated Correction_Field (CFsync) from the subsequent Follow_Up message. This field contains the residence time and link delay of all clock nodes.

[0174] S43, after receiving the synchronization message, the synchronization uses the received t5 and t6 to calculate the synchronization error relative to the master clock

[0175] S44. The synchronized clock adjusts the local clock according to the calculated synchronization error to keep it synchronized with the master clock.

[0176] S45: After the adjustment is completed, the synchronized clock forwards a Sync message to the downstream node, records the timestamp t'5 of the Sync message, and includes the timestamp in the subsequent Follow_Up message.

[0177] S46. In the Follow_Up message, the Correction_Field (CFsync) is updated, and its own link delay and residence time are added to the original CFsync value, ensuring that the correction value received by the downstream node is the cumulative delay on the entire path.

[0178] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should all be included in the scope of the claims of the present invention.

Claims

1. A cross-domain clock synchronization method in a time-sensitive network, characterized by: It includes the following steps: S1. Establish a multi-domain clock synchronization network topology based on transit clocks in a multi-clock domain environment of a time-sensitive network; In step S1, the master clock in the time-sensitive network and the set of synchronization devices directly connected to and synchronized with the master clock are set as m The clock domain is divided into master domains, and the remaining set of synchronous devices close to the edge of the network is called slave domains. There is a bridge between the master and slave clock domains, namely device i, which is defined as a transit clock. The transit clock is located in both the master and slave clock domains. In the master clock domain, the transit clock acts as a slave clock, receiving synchronization messages from the clock source and correcting its own time. In the slave clock domain, the transit clock acts as the master clock of that domain, sending synchronization messages. Other devices in the slave clock domain receive synchronization messages from the transit clock and correct their own clocks. The transit clock can predict and correct synchronization errors based on the network environment. S2: The transit clock obtains the master clock time based on the master domain synchronization message, exchanges link delay measurement messages with the adjacent device, records the corresponding timestamp, and obtains the link delay; S3. The master clock time, timestamps, and link delay are transmitted to the synchronization error compensation prediction module in the transit clock. The synchronization error compensation prediction module then calculates the clock time offset result based on the adjacent clock frequency ratio and predicts the error compensation. In step S3, the synchronization error compensation prediction module predicts the clock time offset compensation value in the following manner: S31. Obtain synchronization timestamp and calculate synchronization error: Obtain timestamps from the master clock and slave clock to obtain the master clock time vector T M , from the clock time vector T S and link delay time vector T D , and calculate the time error T E And synchronization error offset; In step S31, the master clock periodically sends Sync messages and Follow_Up messages. After receiving the Sync message, the slave clock calculates: t i =t GM +CF sync +d Where d represents the link delay; t i Indicates the time when the transit clock is synchronized and corrected; t GM Indicates the time of the main clock; CF sync Indicates the correction value recorded in the Follow_Up message, including the residence time of each node from the Sync message and the link delay between nodes: Where x represents each synchronization node before the current node; ρ x Expressed as the residence time within the synchronization device; When network fluctuations occur in the network, a delay of μ is generated on the link, and the transit clock time becomes: t i =t GM +CF sync +d+μ Further we get: Where gmRR represents the frequency ratio between the master and slave clocks; t' x The timestamp when the slave clock sends and receives the delay request message when there is link delay. d' indicates the link delay caused by network fluctuations. gmRR is the frequency ratio between the master and slave clocks. t2 is the timestamp recorded by the peer delay responder when it receives the Pdelay_Req message. t3 is the timestamp recorded by the peer delay responder when it sends the Pdelay_Resp message. Then the offset is expressed as: Therefore, each time vector as input is expressed as: T M =(t M1 ,t M2 ,...t MN ) T T S =(t S1 ,t S2 ,...t SN ) T T D =(t D1 ,t D2 ,...t DN ) T T E =t S -t M Among them, t M and t S Respectively represent the timestamps of the master clock and the slave clock during calculation; S32, collect the T M 、T S 、T D and T E The data is processed into a matrix form. The data set matrix includes input and target output. The Nk samples of the entire data set D={(x1,T E(k+1) ),(x2,T E(k+2) )…,(x i ,T E(k+i) ),…,(x N-k ,T E(N) )}, where input x i =[(T M ) i ,(T s ) i ,(T D ) i ,(T E ) i ], enter x i The form is: (T M ) i =(t M(i) ,t M(i+1) ,...,t M(i+k-1) ) T (T S ) i =(t S(i) ,t S(i+1) ,...,t S(i+k-1) ) T (T D ) i =(t D(i) ,t D(i+1) ,...,t D(i+k-1) ) T (T E ) i =(T E(i+1) ,T E(i+2) ,...,T E(i+k-1) ) T S33, train the neural network based on the data set, adjust the training parameters according to the output, and output the prediction result offset pre ; S34. Determine a threshold range based on the Gaussian distribution of the synchronization error, determine the factors affecting the synchronization error, and then determine the final deviation. In step S34, the error of the synchronization clock conforms to the Gaussian distribution, that is: Where x is the clock error, μ is the mean, σ is the standard deviation, 2σ is used as the compensation judgment standard, the error range is set to (θ1, θ2), and the thresholds are set to θ1 = μ-2σ, θ2 = μ+2σ; If the synchronization clock error is not within the error range (θ1, θ2), it is considered to be caused by network environment problems. If the synchronization clock error is within (θ1, θ2), it is considered to be caused by frequency changes: t cmp =|μ real -m pre | Where, offset is the actual deviation of the clock, μ real Represents the mean value of the actual synchronization error, μ pre represents the mean of the prediction error, t cmp It represents the difference between the absolute values ​​of the two, that is, the compensation value; S4. The clock correction module in the transit clock adjusts the frequency and phase of the local clock according to the calculated error compensation prediction value, then sends a slave domain synchronization message to the adjacent slave clock device, and forwards the slave domain synchronization message and corrects the clock in turn.

2. The cross-domain clock synchronization method in a time-sensitive network according to claim 1, characterized in that: The transit clock is internally provided with a local clock module, a message receiving port, a message sending port, a timestamp generation module, a synchronization error compensation prediction module, and a clock correction module. The local clock is configured as a free-running clock existing in the transit clock entity, providing the transit clock with a time t l ; The timestamp generation module records the timestamps t1~t6 of the message reception and sending moments when the port interacts with the message; the synchronization error compensation prediction module calculates the clock time offset result based on the received message content and timestamp, and predicts the synchronization error compensation value that needs to be compensated; the clock correction module adjusts the local clock by modifying the frequency and phase according to the calculation results.

3. The cross-domain clock synchronization method in a time-sensitive network according to claim 2, characterized in that: In step S2, the transit clock receiving port receives the Sync / Follow_Up message sent by the Grand Master and parses the master clock time t in the message. M , and record and process timestamps as follows: S21. The peer delay initiator sends Pdelay_Req to the peer delay responder and records the time t1 when the message is sent; S22. The peer delay responder records the timestamp t2 when it receives the Pdelay_Req. After receiving the Pdelay_Req, it returns a Pdelay_Resp message containing t2 to the peer delay requester, and records the timestamp t3 of the time when the Pdelay_Resp message was sent. It then immediately sends a Pdelay_Resp_Follow_Up message containing t3. S23, when the peer delay initiator receives the Pdelay_Resp message, it records the time t4 when the message is received; S24. The initiator calculates the link delay d using the timestamps t1, t2, t3, and t4 recorded above.

4. The cross-domain clock synchronization method in a time-sensitive network according to claim 3, characterized in that: In step S24, the link delay d is calculated as follows: Where gmRR represents the frequency ratio between the master and slave clocks: gmRR is calculated based on historical data, where (t3) N and (t4) N (t3)0 and (t4)0 represent the time when the delay responder sends the Pdelay_Resp message and the time when the requester receives the Pdelay_Resp message during the Nth link delay measurement, respectively. (t3)0 and (t4)0 represent the time when the delay responder sends the Pdelay_Resp message and the time when the requester receives the Pdelay_Resp message during the first delay measurement.

5. The cross-domain clock synchronization method in a time-sensitive network according to claim 4, characterized in that: In step S4, adjacent synchronous clocks forward synchronization messages and perform clock correction after link delay measurement. In the same clock domain, the steps for correcting time using synchronization messages are as follows: S41. When the clock receives the Sync message, it records the timestamp of receiving the Sync message. S42. The synchronous clock reads the timestamp t5 generated by the master device and the accumulated Correction_Field from the subsequent Follow_Up message. The Correction_Field includes the residence time and link delay of all clock nodes. S43, after receiving the synchronization message, synchronously calculate the synchronization error relative to the master clock using the received t5 and t6; S44, the synchronization clock adjusts the local clock according to the calculated synchronization error to keep it synchronized with the master clock; S45. After the adjustment is completed, the synchronized clock forwards the Sync message to the downstream node, records the timestamp t'5 of sending the Sync message, and includes the timestamp t'5 in the subsequent Follow_Up message. S46. Update the Correction_Field in the Follow_Up message, and add its own link delay and residence time to the original values ​​for subsequent clock synchronization.

Images