A reusable Tile architecture design method and apparatus for mid-to-back-end systems

Abstract

This application provides a reusable tile architecture design method and apparatus for mid-to-back-end systems. The method includes: determining the number of rows and columns of cross switches and the location of connection channels based on the number of tiles, wherein each tile integrates a switch and a tile exit module; fixing the first output port of the switch in each tile to the first input port of the corresponding tile exit module; determining routing remapping rules based on the connection rules between tiles and connection channels using a remapping module; converting the routing information input to the tile according to the routing remapping rules and transmitting it to the switch in the tile; establishing an interface connection between each tile and the connection channel; and establishing interconnections between multiple tiles within the connection channel. The technical solution of this application facilitates implementation and integration by front-end designers, as well as comprehensive implementation in the mid-to-back-end, enhancing the reusability of the tile structure.

Description

Technical Field

[0001] This application belongs to the field of network switching architecture, and specifically relates to a reusable Tile architecture design method and apparatus for the mid-to-back end. Background Technology

[0002] High-performance computing clusters achieve efficient interconnection of thousands of computing nodes through advanced system interconnection network architectures. These nodes include, but are not limited to, heterogeneous computing resources such as CPUs, GPUs, and TPUs, collectively forming a powerful network with parallel processing capabilities. Switches are crucial interconnection devices in the network; their switching structure and scheduling algorithms determine their performance and cost.

[0003] Crossbar switching structures are widely used in switches due to their good scalability and high speed. For N×N switching networks, the complexity of crossbar implementation and cabling increases dramatically as the value of N increases. To address this, the N×N switching network is divided into smaller tiles that integrate a routing forwarding module (FTB), input / output buffers, arbitration units, and output units. This relatively centralized arbitration module design effectively reduces the difficulty of back-end cabling.

[0004] However, as the Crossbar scales up, the number of Tiles also increases. Although there are certain patterns in the Tile architecture, it still faces some design and physical implementation problems, including increased complexity of the wiring interfaces; increased difficulty in physical implementation in the middle and back ends; and increased power consumption and latency. Summary of the Invention

[0005] The purpose of this application is to provide a reusable Tile architecture design method and apparatus for the mid-to-back end, aiming to realize a reusable Tile architecture.

[0006] According to a first aspect of this application, a reusable Tile architecture design method for mid-to-back-end systems is provided, comprising:

[0007] The number of rows and columns of the crossbar switch and the location of the connection channel (Chnl) are determined based on the number of tiles, wherein the switch and tile exit module are integrated within the tile;

[0008] The first output port of the switch in each Tile is fixedly connected to the first input port of the corresponding Tile egress module. The remapping module determines the route remapping rules according to the connection rules between the Tile and the connection channel.

[0009] The routing information input to the Tile is converted according to the routing remapping rules and then transmitted to the switch in the Tile. Each Tile is connected to the connection channel through an interface, and interconnection between multiple Tile is established within the connection channel.

[0010] In an optional implementation, the step of fixedly connecting the first output port of the switch within each tile to the first input port of the corresponding tile's output module further includes:

[0011] The first output port of the switch is fixedly connected to the first input port of the Tile output module inside the Tile.

[0012] In an optional implementation, after the first output port of the switch within each tile is fixedly connected to the first input port of the corresponding tile's output module, the method further includes:

[0013] Use the other output ports of the switch as the output ports of the Tile, and use the other input ports of the Tile output module as the input ports of the Tile.

[0014] In an optional implementation, after the remapping module determines the route remapping rules based on the connection rules between the tile and the connection channel, the method further includes:

[0015] When the connection rules between a tile and its connecting channel are changed based on the tile's placement, the corresponding route remapping rules are matched with the changed connection rules.

[0016] In an optional implementation, the remapping module is located in the Tile.

[0017] According to a second aspect of this application, a reusable Tile architecture design apparatus for mid-to-back-end is provided, comprising:

[0018] A layout unit is used to determine the number of rows and columns of cross switches and the location of wiring channels based on the number of tiles, wherein the switches and tile exit modules are integrated within the tiles;

[0019] The connection unit is used to fix the first output port of the switch in each Tile to the first input port of the corresponding Tile exit module, and uses the remapping module to determine the route remapping rules according to the connection rules between the Tile and the connection channel.

[0020] The remapping unit is used to convert the routing information input to the Tile according to the routing remapping rules and transmit it to the switch in the Tile, establish an interface connection between each Tile and the connection channel, and establish interconnection between multiple Tile within the connection channel.

[0021] In an optional implementation, the connection unit is further configured to:

[0022] The first output port of the switch is fixedly connected to the first input port of the Tile output module inside the Tile.

[0023] In an optional implementation, the connection unit is further configured to:

[0024] Use the other output ports of the switch as the output ports of the Tile, and use the other input ports of the Tile output module as the input ports of the Tile.

[0025] In an optional implementation, the connection unit is further configured to:

[0026] When the connection rules between a tile and its connecting channel are changed based on the tile's placement, the corresponding route remapping rules are matched with the changed connection rules.

[0027] In an optional implementation, the remapping module is located in the Tile.

[0028] Compared with related technologies, the technical solution of this application has the following advantages:

[0029] By adding a remapping module to remap the input mapping relationship, the port 0 connection of the Switch module and the Egress module is fixed, which makes the structure of each Tile completely consistent, which is convenient for mid-to-back-end synthesis and only requires the synthesis of two modules. At the same time, since there is one signal inside the Tile, Chnl only needs to handle the connection relationship of 7 signals, which is beneficial to the design and implementation of large-scale Tile architecture.

[0030] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures and processes shown in the description and the accompanying drawings. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 It is a 3×3 Crossbar structure diagram implemented using Tile based on relevant technologies.

[0033] Figure 2 This is a structural diagram of a 3×3 Crossbar composed of improved tiles according to this application.

[0034] Figure 3 This is a flowchart illustrating the reusable Tile architecture design method for the mid-to-back end according to this application.

[0035] Figure 4 It is based on the 5×5 Crossbar structure diagram of this application.

[0036] Figure 5 This is a schematic diagram of the connection relationship between Tile and Chnl according to this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] In related technologies, a 3×3 Crossbar design architecture implemented using a Tile structure is as follows: Figure 1As shown in the diagram (hereinafter referred to as Scheme 1), the input terminal InX has already completed path routing selection in the FTB module. The input terminal InX writes data into the input buffer of each tile in the specified row. The number of buffers is determined by the number of input terminals. Multiple buffer queues send requests to the Switch module. The Switch module selects the exit terminal based on the routing information it carries, and then performs arbitration output. The successfully arbitrated exit information is output from the specified port to the input buffer queue of the Egress (Tile exit, abbreviated as EGR) module. Each Egress module then arbitrates the multiple input buffer information and selects one path for output. Multiple ports of the Switch in a Tile correspond to the port outputs of different Egress modules, such as... Figure 1 The 3×3 Switch shown has 9 inputs and 9 outputs for the entire Crossbar. Each Tile has three inputs and three outputs, with output ports connected to three different Tile. Each Tile contains one Egress output, which arbitrates the inputs of the three Tile. Therefore, in the above structure, each Switch's three outputs are connected to the inputs of the Egress modules of the three Tile in the same column; each Tile has only one Egress output, requiring arbitration of the outputs of the Switch modules of the three Tile in the same column; the three outputs (0, 1, 2) of the Switch correspond to the Egress modules within the three Tile connected in the same column; that is, Switch port 0 is always connected to the first Tile in the same column, Switch port 1 is connected to the second Tile in the same column, and the connection relationship is consistent regardless of the Switch's location; the output ports of the Tile connect to the input ports of other Tile, and the wiring rules and the number of beats are implemented in Chnl, where Chnl is a channel module design architecture used to aggregate long traces of beat logic.

[0039] The above connection relationship introduces the following problems. The connection between the Switch output and the Egress module input port of each Tile in the same column is not fixed; for example, port 0 of Switch0 in Tile0 is connected to port 0 of Egress0, port 1 of Switch3 in Tile3 is connected to port 1 of Egress3, and port 2 of Switch6 in Tile6 is connected to port 2 of Egress6. Therefore, these three Tiles are three different Tile modules for the mid-to-back-end implementation. When using this Tile architecture to implement a large-scale Crossbar, the different placement of Tiles prevents reuse, resulting in a significant workload for the physical implementation in silicon. Furthermore, for front-end designers, the different placement and connection relationships of Tiles in the Crossbar make design implementation and top-level integration relatively cumbersome.

[0040] Another approach in related technologies (hereinafter referred to as Related Approach Two) separates the Switch and Egress modules from a single Tile into two independent and reusable modules. All interface connections between these modules are integrated using Chnl, eliminating integration concerns for the Switch and Egress designs. However, this approach introduces new problems. The backend requires physical implementation of the Tile, Egress, and Chnl modules; specifically, Egress needs independent synthesis. Because the Egress module is independent, all its interface connections are implemented in Chnl, resulting in an additional signal path compared to Related Approach One, consuming additional register and routing resources based on path length. Furthermore, the wiring rules between modules are all implemented in Chnl, making Chnl integration relatively complex.

[0041] In conclusion, combining Switch and Egress into a single tile with a fixed connection relationship is the optimal solution.

[0042] Based on the above analysis, this application provides a reusable Tile architecture design method and apparatus for the mid-to-back end. To address the shortcomings of related structures, the port 0 of the Switch and the input port 0 of the Egress within the Tile are designed to be fixedly connected, and the remaining Switch output ports are used as Tile output ports, and the remaining Egress input ports are used as Tile input ports.

[0043] like Figure 2 As shown, in Figure 1Based on this, the Switch and Egress are integrated into a single Tile. Since the Switch's port 0 and the Egress's port 0 are fixedly connected, when implementing a large-scale Crossbar using multiple Tiles, the basic unit Tile does not need to change its internal connections based on its placement; that is, each Tile constituting the Crossbar is identical. However, the Switch exit selected by the original routing information needs to change. To ensure data transmission correctness, a remap module is added within the Tile to remap the original routing information carried by the data before inputting it into the Switch to match the Chnl connection rules and complete correct data forwarding. The routing information carried by each request message is transformed according to predefined remap rules to adapt to the connection relationships of the current Tile architecture. These remap rules need to match the corresponding Chnl. Interconnection between Tiles is accomplished through Chnl.

[0044] See Figure 3 The flowchart provided in this application shows the reusable Tile architecture design method for the mid-to-back end, which includes: Step 301: Determine the number of rows and columns of the cross switch and the position of Chnl according to the number of Tile, wherein the Tile integrates a Switch and a Tile exit module.

[0045] Specifically, based on the target requirements, the Crossbar structure is determined, that is, the number of rows and columns, and the placement of Chnl are determined according to the number of Tiles; for example... Figure 4 The 25 tiles shown form a 5×5 structure.

[0046] Step 302: Connect the first output port of the Switch within each Tile to the first input port of the corresponding Tile egress module. Utilize the remapping module to determine the route remapping rules based on the connection rules between the Tile and Chnl. These connection rules are determined after the physical placement of the Tile interfaces and Chnl is determined, the interfaces are manually connected, and the ease of implementing the remap algorithm is considered; both factors work together to determine the rules.

[0047] Based on the system routing algorithm, Switch routing information is obtained and used by the Switch within the Tile to determine the Egress exit point. Remap rules are set according to the connection rules between the Tile and the Chnl, as well as the fixed connection port information between the Tile and the Egress module. The first output port (output port 0) of the Switch within the Tile and the first input port (input port 0) of the Egress module are set as a fixed connection, and this set of interfaces is integrated within the Tile. Therefore, routing information entering the Tile needs to be converted by the remap module before being transmitted to the Switch for arbitration, thus ensuring the correctness of data transmission.

[0048] The remap module of each tile infers the exit point of the original data based on the position of the tile in the entire crossbar structure, such as the number of rows and columns.

[0049] For example, the conversion rules can be set as shown in Table 1 below:

[0050] Table 1

[0051]

[0052] Here, Column represents the column number of the Tile in the 5×5 Crossbar, and Switch port i represents the i-th output port (0≤i≤4) of the Switch module inside the Tile. For example, Switch port0 represents going to Egress0, Switch port1 goes to Egress1, and so on. However, because this application fixes the connection between port 0 of the Switch of each Tile and the input port 0 of the Egress, the output of the Switch of tiles not in the first column and the Egress A port will have a "connection change". To ensure the correctness of data transmission, this "connection change" is corrected by remapping and the connection relationship of each port. The connection relationship corresponding to this method is as follows: Figure 5 As shown.

[0053] The connection rules mentioned above can be changed by the designers according to the placement of the tiles, but they need to match the corresponding remap rules to ensure that the data entering the tile is correctly forwarded to the specified output port.

[0054] Step 303: After converting the routing information of the input Tile according to the routing remapping rule, the information is transmitted to the Switch in the Tile. Each Tile is connected to the Chnl via an interface, and multiple interconnections between Tile are established within the Chnl.

[0055] For example, an interface connection is established between each tile and the Chnl, and the interconnection relationship between tiles is implemented within the Chnl. If the number of tiles is increased or decreased, the adjustment is made according to the number of rows and columns, while maintaining the remap and integration connection rules. In addition to port 0, other ports can also be used for fixed connections. For different fixed connection methods, the remap rules and the Chnl integration connection rules are modified synchronously.

[0056] This application modifies the original routing information input to the Switch via remap, thereby ensuring a fixed connection between an output port of the Switch within a Tile and an input port of the Egress. In the Crossbar design using a Tile architecture, the Tile implemented using this application's scheme ensures that all Tiles constituting the Crossbar are completely identical. This method facilitates implementation and integration by front-end designers, as well as comprehensive implementation by mid- and back-end developers, enhancing the reusability of the Tile structure and resulting in high scalability of the Crossbar.

[0057] The following examples illustrate the comparison between the proposed solutions and those of this application. Table 2 shows a comparison between this application and related solutions one and two when implementing an 8×8 Crossbar using a Tile structure. Here, 7 or 8 represents the number of n signals entering Chnl; 1024 represents the data bit width; P refers to the number of steps required in Chnl based on the path length; and multiplying by 2 represents the bidirectional routing of this signal.

[0058] Table 2

[0059]

[0060] For the first relevant scheme, the 8×8 Crossbar has 8 rows and 8 columns, with each row containing 8 tiles (8 columns). The internal connection relationships (Switch and Egress) of each tile are different. One of the 8 signals is implemented within the tile, so the mid- and back-end systems need to synthesize and implement them separately. Tiles with each connection relationship are only reused in different rows.

[0061] For the second related scheme, the Egress module is separated from the first related scheme. In this way, Tile and Egress can be reused, but all interface connections are implemented in Chnl. That is, all 8 signals need to be combined, connected and timed in Chnl, which increases the integration complexity and consumes additional register and line resources.

[0062] As can be seen, the reusable Tile architecture design method for mid-to-back-end systems provided in this application has the following advantages compared to related technologies:

[0063] By adding a remapping module to remap the input mapping relationships, the port 0 connection of the Switch and Egress modules is fixed, thus achieving a completely consistent structure for each Tile. This facilitates mid-to-back-end synthesis and requires only the synthesis of two modules. Furthermore, since one signal exists within the Tile, Chnl only needs to handle the connection relationships of seven signals. As the Crossbar scale increases, the advantages of this method become increasingly significant. The structural approach designed in this paper is highly friendly to mid-to-back-end implementation and beneficial for the design and implementation of large-scale Tile architectures.

[0064] Accordingly, this application provides a reusable Tile architecture design apparatus for the mid-to-back end in a second aspect, comprising:

[0065] A layout unit is used to determine the number of rows and columns of the cross switch and the position of the Chnl based on the number of tiles, wherein the tile integrates Switch and Egress modules;

[0066] The connection unit is used to fix the first output port of the Switch in each Tile to the first input port of the corresponding Egress module, and uses the remapping module to determine the route remapping rules according to the connection rules between the Tile and the Chnl.

[0067] The remapping unit is used to convert the routing information input to the Tile according to the routing remapping rules and transmit it to the Switch in the Tile, establish an interface connection between each Tile and the Chnl, and establish interconnection between multiple Tile within the Chnl.

[0068] The above-mentioned device can be implemented using the reusable Tile architecture design method for the mid-to-back end provided in the first aspect of the embodiment. For specific implementation methods, please refer to the description in the first aspect of the embodiment, which will not be repeated here.

[0069] It is understood that the circuit structures, names, and parameters described in the above embodiments are merely examples. Those skilled in the art can also make readily conceived combinations and adjustments to the structural features of the above embodiments according to their needs, and the concept of this application should not be limited to the specific details of the above examples.

[0070] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A reusable tile architecture design method for mid-to-back-end systems, characterized in that, include: The number of rows and columns of the cross switches and the location of the connecting channels are determined based on the number of tiles, wherein the switches and tile exit modules are integrated within the tiles; The first output port of the switch in each Tile is fixedly connected to the first input port of the corresponding Tile egress module. The remapping module determines the route remapping rules according to the connection rules between the Tile and the connection channel. The routing information input to the Tile is converted according to the routing remapping rules and then transmitted to the switch in the Tile. Each Tile is connected to the connection channel, and an interconnection between multiple Tile is established within the connection channel. The step of fixing the first output port of the switch in each tile to the first input port of the corresponding tile's output module further includes: The first output port of the switch is fixedly connected to the first input port of the Tile output module inside the Tile.

2. The reusable Tile architecture design method for mid-to-back-end systems according to claim 1, characterized in that, After the first output port of the switch in each tile is fixedly connected to the first input port of the corresponding tile output module, the method further includes: Use the other output ports of the switch as the output ports of the Tile, and use the other input ports of the Tile output module as the input ports of the Tile.

3. The reusable Tile architecture design method for mid-to-back-end systems according to claim 1, characterized in that, After determining the route remapping rules using the remapping module based on the connection rules between the tile and the connection channel, the following is also included: When the connection rules between a tile and its connecting channel are changed based on the tile's placement, the corresponding route remapping rules are matched with the changed connection rules.

4. The reusable Tile architecture design method for mid-to-back-end systems according to claim 1, characterized in that, The remapping module is located in the Tile.

5. A reusable tile architecture design device for mid-to-back-end systems, characterized in that, include: A layout unit is used to determine the number of rows and columns of cross switches and the location of wiring channels based on the number of tiles, wherein the switches and tile exit modules are integrated within the tiles; The connection unit is used to fix the first output port of the switch in each Tile to the first input port of the corresponding Tile exit module, and uses the remapping module to determine the route remapping rules according to the connection rules between the Tile and the connection channel. The remapping unit is used to convert the routing information input to the Tile according to the routing remapping rules and transmit it to the switch in the Tile, establish an interface connection between each Tile and the connection channel, and establish interconnection between multiple Tile within the connection channel; The connection unit is further used for: The first output port of the switch is fixedly connected to the first input port of the Tile output module inside the Tile.

6. The reusable Tile architecture design device for mid-to-back-end systems according to claim 5, characterized in that, The connection unit is further used for: Use the other output ports of the switch as the output ports of the Tile, and use the other input ports of the Tile output module as the input ports of the Tile.

7. The reusable Tile architecture design device for mid-to-back-end systems according to claim 5, characterized in that, The connection unit is further used for: When the connection rules between a tile and its connecting channel are changed based on the tile's placement, the corresponding route remapping rules are matched with the changed connection rules.

8. The reusable Tile architecture design device for mid-to-back-end systems according to claim 5, characterized in that, The remapping module is located in the Tile.

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