Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure is provided. The method includes forming a first active region in which first and second semiconductor layers are alternately stacked on a first lower fin element. In plan view, the active region includes a first portion and a second portion narrower than the first portion. The method further includes removing the first semiconductor layer of the first active region. The second semiconductor layer of the first portion of the first active region forms a first nanostructure, and the second semiconductor layer of the second portion of the first active region forms a second nanostructure. The method further includes forming a first gate stack surrounding the first nanostructure, and forming a second gate stack surrounding the second nanostructure. The embodiment of the invention also provides a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more and more complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking semiconductor IC size (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this miniaturization has introduced greater complexity to the semiconductor manufacturing process. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] Multi-gate devices have been introduced in recent years to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCE). One such multi-gate device that has been introduced is the gate-all-around transistor (GAA). GAA devices get their name from the fact that the gate structure can extend around the channel region and provide access to the channel on two or four sides. GAA devices are compatible with traditional complementary metal oxide semiconductor (CMOS) processes, and their structure allows them to be significantly scaled down while maintaining gate control and mitigating SCE. In traditional processes, GAA devices provide channels in silicon nanowires. However, the manufacturing of GAA components integrated around nanowires can be challenging. For example, while current approaches are satisfactory in many aspects, there is still a need for continued improvement. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: forming a first active region, in which a first semiconductor layer and a second semiconductor layer are alternately stacked above a first lower fin element, wherein, in a plan view, the active region includes a first portion and a second portion narrower than the first portion; removing the first semiconductor layer of the first active region, wherein the second semiconductor layer of the first portion of the first active region forms a plurality of first nanostructures, and the second semiconductor layer of the second portion of the first active region forms a plurality of second nanostructures; forming a first gate stack to surround the plurality of first nanostructures; and forming a second gate stack to surround the plurality of second nanostructures.

[0005] According to one aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, comprising: alternately stacking sacrificial layers and channel layers above a substrate; patterning the sacrificial layers, the channel layers, and the substrate to form a first fin structure in a p-type well of the substrate and to form a second fin structure in an n-type well of the substrate, wherein the first fin structure comprises a strip portion and a first protruding portion extending toward the second fin structure; and forming a dummy gate structure across the first fin structure and the second fin structure, wherein the dummy gate structure overlaps with the first protruding portion of the first fin structure.

[0006] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a first pull-down transistor of a first static random access memory unit, wherein the first pull-down transistor comprises: a plurality of first nanostructures; and a first gate stack surrounding the plurality of first nanostructures and extending along a first direction; and a transmission gate transistor of the first static random access memory unit, wherein the transmission gate transistor comprises: a plurality of second nanostructures; and a second gate stack surrounding the plurality of second nanostructures and extending along the first direction, wherein the plurality of first nanostructures have a first size in the first direction, the plurality of second nanostructures have a second size in the first direction, and the first size is greater than the second size. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a perspective view of a semiconductor structure according to some embodiments of the present disclosure.

[0009] Figure 2 A simplified diagram of a static random access memory (SRAM) is shown in accordance with some embodiments of the present disclosure.

[0010] Figure 3A A single-port SRAM cell according to some embodiments of the present disclosure is shown.

[0011] Figure 3B Some embodiments of the present disclosure are shown Figure 3A Alternative illustration of an SRAM cell.

[0012] Figure 4A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP.

[0013] Figure 4B Some embodiments of the present disclosure are shown Figure 4A Configuration of contact plugs on layout.

[0014] Figure 4C Some embodiments of the present disclosure are shown Figure 4A A magnified view of the active region is shown to illustrate more details of the stepped structure of the active region.

[0015] Figure 4D-1 , Figure 4D-2 and Figure 4D-3 It is shown that some embodiments according to the present disclosure Figure 4A A cross-sectional view of a semiconductor structure in which an SRAM cell is formed at one of the intermediate stages corresponding to lines Y1 - Y1 , Y2 - Y2 , and XX.

[0016] Figure 4E-1 , Figure 4E-2 and Figure 4E-3 It is shown that some embodiments according to the present disclosure Figure 4A A cross-sectional view of a semiconductor structure in which an SRAM cell is formed at one of the intermediate stages corresponding to lines Y1 - Y1 , Y2 - Y2 , and XX.

[0017] Figure 4F-1 , Figure 4F-2 and Figure 4F-3 It is shown that according to some embodiments of the present disclosure Figure 4A A cross-sectional view of a semiconductor structure in which an SRAM cell is formed at one of the intermediate stages corresponding to lines Y1 - Y1 , Y2 - Y2 , and XX.

[0018] Figure 4G-1 , Figure 4G-2 and Figure 4G-3 It is shown that some embodiments according to the present disclosure Figure 4A A cross-sectional view of a semiconductor structure in which an SRAM cell is formed at one of the intermediate stages corresponding to lines Y1 - Y1 , Y2 - Y2 , and XX.

[0019] Figure 4D-4 and Figure 4F-4 is with Figure 4D-1 and Figure 4F-1 is a plan view corresponding to plane AA according to some embodiments of the present disclosure.

[0020] Figure 4F-5 According to some embodiments of the present disclosure Figure 4F-1 The plane diagram corresponding to plane BB.

[0021] Figure 5A , Figure 5B and Figure 5C is a plan view showing an active area with smooth steps according to some embodiments of the present disclosure.

[0022] Fig. 6A and Figure 6B is a plan view illustrating the formation of an active region with a sharp step according to some embodiments of the present disclosure.

[0023] Figure 6C-1 and Figure 6C-2 2 are plan views of semiconductor structures of an SRAM cell respectively corresponding to plane AA and plane BB according to some embodiments of the present disclosure.

[0024] Fig. 7A Some embodiments of the present disclosure are shown Figure 2 Layout of the middle half of the GP group of SRAM.

[0025] Figure 7B-1 and Figure 7B-2 According to some embodiments of the present disclosure, Figure 4F-1 Plane AA and plane BB Fig. 7A A plan view of the semiconductor structure of an SRAM cell.

[0026] Fig. 8A Some embodiments of the present disclosure are shown Figure 2 Layout of the middle half of the GP group of SRAM.

[0027] Figure 8B-1 and Figure 8B-2 According to some embodiments of the present disclosure, Figure 4F-1 Plane AA and plane BB Fig. 8A A plan view of the semiconductor structure of an SRAM cell.

[0028] Fig.9A and Fig. 9B is a plan view showing an active area with smooth steps according to some embodiments of the present disclosure.

[0029] Fig. 10A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP.

[0030] Fig. 10B is corresponding to plane BB according to some embodiments of the present disclosure Fig. 10A A plan view of the semiconductor structure of an SRAM cell.

[0031] Fig.11A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP.

[0032] Fig. 11B is corresponding to plane BB according to some embodiments of the present disclosure Fig.11AA plan view of the semiconductor structure of an SRAM cell.

[0033] Fig. 12A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP.

[0034] Fig. 12B is corresponding to plane BB according to some embodiments of the present disclosure Fig. 12A A plan view of the semiconductor structure of an SRAM cell.

[0035] Fig.13A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP.

[0036] Figure 13B-1 and Figure 13B-2 According to some embodiments of the present disclosure Fig.13A The line Y1 -Y1 and the line Y2 -Y2 correspond to a cross-sectional view of the semiconductor structure of the SRAM cell.

[0037] Figure 13B-3 According to some embodiments of the present disclosure Figure 13B-1 The plane diagram corresponding to plane BB.

[0038] Fig.14A Some embodiments of the present disclosure are shown Figure 4A Configuration of backside contact plugs on layout.

[0039] Figure 14B-14E It is shown that some embodiments according to the present disclosure Fig.14A The line Y2 - Y2 corresponds to cross-sectional views of various intermediate stages of the semiconductor structure forming the SRAM cell.

[0040] Fig.15A The configuration of backside contact plugs on the layout of FIG. 13 is shown according to some embodiments of the present disclosure.

[0041] Fig. 15B According to some embodiments of the present disclosure Fig.15A Line Y2 - Y2 corresponds to a cross-sectional view of the semiconductor structure of the SRAM cell.

[0042] Fig.16A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP.

[0043] Figure 16B-1 and Figure 16B-2 According to some embodiments of the present disclosure Fig.16AThe line Y1 -Y1 and the line Y2 -Y2 correspond to a cross-sectional view of the semiconductor structure of the SRAM cell.

[0044] Figure 16B-3 According to some embodiments of the present disclosure Figure 16B-1 The plane diagram corresponding to plane BB.

[0045] Fig.17A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP.

[0046] Figure 17B-1 and Figure 17B-2 According to some embodiments of the present disclosure Fig.17A The line Y1 -Y1 and the line Y2 -Y2 correspond to a cross-sectional view of the semiconductor structure of the SRAM cell.

[0047] Figure 17B-3 According to some embodiments of the present disclosure Figure 17B-1 The plane diagram corresponding to plane BB.

[0048] Fig.18A Some embodiments of the present disclosure are shown Fig.17A Configuration of backside contact plugs on layout.

[0049] Fig.18B According to some embodiments of the present disclosure Fig.18A Line Y2 - Y2 corresponds to a cross-sectional view of the semiconductor structure of the SRAM cell. DETAILED DESCRIPTION

[0050] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0051] Some variations of the embodiments are described. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

[0052] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channels, nanoribbon FETs, all-around gate (GAA) transistor structures) can be patterned by any suitable method. For example, the structure can be patterned using one or more lithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with a pitch smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0053] As component sizes continue to decrease, SRAM devices have also begun to adopt nanostructured transistor (e.g., GAA FET) solutions to improve cell performance, such as improving cell current, operating voltage (e.g., Vmax, Vmin, etc.), SRAM margin (e.g., write margin and / or read margin) and / or operating speed. Aspects of the present disclosure relate to a semiconductor structure for forming an SRAM device including nanostructured transistors. The active region of the semiconductor structure can be formed with a stepped structure, so that independent adjustment of the performance of a pull-down transistor (PD) and a transfer gate transistor (PG) formed on the active region can be achieved. The channel width of the pull-down transistor can be greater than the channel width of the transfer gate transistor. As a result, the pull-down transistor can have a stronger performance than the transfer gate transistor. Therefore, the cell performance of the resulting SRAM cell can be improved, for example, a higher operating voltage (e.g., Vmax), a higher cell current, a wider read margin metric and / or a faster operating speed.

[0054] Figure 1 is a perspective view of a semiconductor structure 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 100 is used to form an SRAM cell. According to some embodiments, the semiconductor structure 100 includes a fin structure 104 on a substrate. Figure 1 One fin structure is shown in FIG. 1 , but the semiconductor structure 100 may include a plurality of fin structures 104 .

[0055] In order to better understand the semiconductor structure 100, XYZ coordinate references are provided in the drawings of the present disclosure. The X-axis and the Y-axis are generally oriented along a lateral (or horizontal) direction parallel to the main surface of the substrate 102. The Y-axis is lateral (e.g., substantially perpendicular) to the X-axis. The Z-axis is generally oriented along a vertical direction perpendicular to the main surface (or XY plane) of the substrate 102.

[0056] According to some embodiments, the fin structure 104 includes a lower fin element 103 formed from a portion of a substrate and an upper fin element formed from an epitaxial stack of alternating first semiconductor layers 106 and second semiconductor layers 108. According to some embodiments, an isolation structure 110 surrounds the lower fin element 103. According to some embodiments, the second semiconductor layer 108 will form a nanostructure (e.g., a nanowire or a nanosheet) and serve as a channel of the resulting nanostructure transistor.

[0057] According to some embodiments, the fin structure 104 extends in the X direction. That is, according to some embodiments, the fin structure 104 has a longitudinal axis parallel to the X direction. The X direction may also be referred to as a channel extension direction. The current of the resulting semiconductor device (ie, nanostructure transistor) flows through the channel along the X direction.

[0058] According to some embodiments, the fin structure 104 includes a channel region and a source / drain region, and the channel region and the source / drain region are arranged in an alternating manner in the X direction. In the present disclosure, the term "source / drain" refers to the source, the drain, or both. It should be noted that in the present disclosure, the source and the drain can be used interchangeably and their structures are basically the same. The gate structure 112 is formed with a longitudinal axis parallel to the Y direction and extends through and / or around the channel region of the fin structure 104. The Y direction may also be referred to as the gate extension direction.

[0059] In addition, if Figure 1 As shown, according to some embodiments, the fin structure 104 is a semiconductor strip with a stepped structure. As used herein, "step" refers to a strip extending in a horizontal direction, with pits or protrusions on one or both sides of the strip. According to some embodiments, the fin structure 104 with a stepped structure may include a wider portion and a narrower portion, so that the transistors forming the wider portion and the narrower portion of the fin structure 104 have different performance (e.g., different saturation currents (Idsat)). Therefore, the cells of the resulting SRAM cell can be optimally enhanced, which will be described in detail later.

[0060] Figure 2 A simplified diagram of an SRAM 30 according to some embodiments of the present disclosure is shown. The SRAM 30 may be an independent device or may be implemented in an IC (e.g., a system on a chip (SOC)). The SRAM 30 includes a cell array formed by a plurality of SRAM cells (or bit cells) 10, and the SRAM cells 10 are arranged in a plurality of rows and columns in the cell array.

[0061] In the manufacture of SRAM cells, the cell array may be surrounded by a plurality of strip cells 20A and a plurality of edge cells 20B, and the strip cells 20A and the edge cells 20B are pseudo cells of the cell array. In some embodiments, the strip cells 20A are arranged to surround the cell array horizontally, and the edge cells 20B are arranged to surround the cell array vertically. The shapes and sizes of the strip cells 20A and the edge cells 20B are determined according to actual applications.

[0062] In some embodiments, the stripe cell 20A and the edge cell 20B have the same shape and size as the SRAM cell 10. In some embodiments, the stripe cell 20A, the edge cell 20B, and the SRAM cell 10 have different shapes and sizes. In addition, in the SRAM 30, each SRAM cell 10 has the same rectangular shape / area, for example, the width and height of the SRAM cell 10 are the same. The configuration of the SRAM cell 10 is described below.

[0063] In the cell array of SRAM 30, although Figure 2 Only one group GP is shown in FIG. 1 , but the SRAM cell 10 may be divided into a plurality of groups GP. Each group GP includes four adjacent SRAM cells 10. A detailed description of the GP group is as follows.

[0064] Figure 3A A single-port SRAM cell 10 according to some embodiments of the present disclosure is shown. The SRAM cell 10 includes a pair of cross-coupled inverters Inverter-1 and Inverter-2, and two pass gate transistors PG-1 and PG-2. Inverters Inverter-1 and Inverter-2 are cross-coupled between nodes N1 and N2 and form a latch.

[0065] The pass gate transistor PG-1 is coupled between the bit line BL and the node N1, the pass gate transistor PG-2 is coupled between the bit line BLB and the node N2, and the complementary bit line BLB is complementary to the bit line BL. The gates of the pass gate transistors PG-1 and PG-2 are coupled to the same word line WL. The pass gate transistors PG-1 and PG-2 are NMOS transistors.

[0066] Figure 3B Some embodiments of the present disclosure are shown Figure 3A Alternative illustration of an SRAM cell. Figure 3B As shown, Figure 3AThe inverter-1 in FIG. 1 includes a pull-up transistor PU-1 and a pull-down transistor PD-1. The pull-up transistor PU-1 is a PMOS transistor, and the pull-down transistor PD-1 is an NMOS transistor. The drains of the pull-up transistor PU-1 and the pull-down transistor PD-1 are connected to a node N1 connected to a transmission gate transistor PG-1. The gates of the pull-up transistor PU-1 and the pull-down transistor PD-1 are coupled to a node N2 connected to a transmission gate transistor PG-2. In addition, the source of the pull-up transistor PU-1 is coupled to a power supply node VDD, and the source of the pull-down transistor PD-1 is coupled to a ground VSS.

[0067] Similarly, if Figure 3B As shown, Figure 3A The inverter Inverter-2 in the embodiment includes a pull-up transistor PU-2 and a pull-down transistor PD-2. The pull-up transistor PU-2 is a PMOS transistor, and the pull-down transistor PD-2 is an NMOS transistor. The drains of the pull-up transistor PU-2 and the pull-down transistor PD-2 are connected to a node N2 connected to a transmission gate transistor PG-2. The gates of the pull-up transistor PU-2 and the pull-down transistor PD-2 are coupled to a node N1 connected to a transmission gate transistor PG-1. In addition, the source of the pull-up transistor PU-2 is coupled to a power supply node VDD, and the source of the pull-down transistor PD-2 is coupled to a ground VSS.

[0068] In some embodiments, the pass-gate transistors PG- 1 and PG- 2 , the pull-up transistors PU- 1 and PU- 2 , and the pull-down transistors PD- 1 and PD- 2 of the SRAM cell 10 are nanostructure transistors (eg, gate-all-around transistors).

[0069] Figure 4A Some embodiments of the present disclosure are shown Figure 1 Layout of the group GP of the SRAM 30 in FIG. The group GP includes four SRAM cells 10_1, 10_2, 10_3, and 10_4, and is formed by an active region 104 (including 104N_1 to 104N_4 and 104P_1 to 104P_4) and a gate stack 136 (including 136_1 to 136_4). The active region 104 may be as follows: Figure 1 According to some embodiments, each active region 104 includes a lower fin element and a nanostructure group on the lower fin element. As used herein, the term "nanostructure group" refers to an active region of a semiconductor structure, which includes multiple semiconductor layers having a cylindrical, strip, and / or sheet shape.

[0070] According to some embodiments, the lower fin element of the active region 104 extends in the X direction, and the gate stack 136 extends through the lower fin element and around the nanostructure in the Y direction. In addition, according to some embodiments, the gate stack 136 is cut into several parts that are electrically and physically isolated from each other.

[0071] In some embodiments, the transistors within the SRAM cells 10_1, 10_2, 10_3, and 10_4 are nanostructure transistors in an N-type well region NW and a P-type well region PW. According to some embodiments, the N-type well regions NW and the P-type well regions PW are arranged alternately. According to some embodiments, the active regions 104N_1 to 104N_4 are formed in the N-type well region NW, and the active regions 104P_1 to 104P_4 are formed in the P-type well region PW. In some embodiments, two active regions 104N or 104P are arranged in one well region PW or NW.

[0072] Two adjacent SRAM cells 10_1 and 10_3 are arranged in the same row of the cell array of the SRAM 30. Two adjacent SRAM cells 10_1 and 10_2 are arranged in the same column of the cell array of the SRAM 30. Two adjacent SRAM cells 10_3 and 10_4 are arranged in the same column of the cell array of the SRAM 30. In other words, two adjacent SRAM cells 10_2 and 10_4 are arranged in the same row of the cell array of the SRAM 30.

[0073] In the SRAM cell 10_1, a pass gate transistor PG-1 is formed at the intersection of the active area 104N_2 and the gate stack 136_1. A pull-down transistor PD-1 is formed at the intersection of the active area 104N_2 and the gate stack 136_2. A pass gate transistor PG-2 is formed at the intersection of the active area 104N_1 and the gate stack 136_2. A pull-down transistor PD-2 is formed at the intersection of the active area 104N_1 and the gate stack 136_1. In addition, in the SRAM cell 10_1, a pull-up transistor PU-1 is formed at the intersection of the active area 104P_2 and the gate stack 136_2. A pull-up transistor PU-2 is formed at the intersection of the active area 104P_1 and the gate stack 136_1. Furthermore, no functional transistors are formed at the intersection of the active region 104P_1 and the gate stack 136_2 and at the intersection of the active region 1042P_2 and the gate stack 136_1 .

[0074] Various contact plugs and their corresponding interconnect vias may be employed to electrically connect the components in each of the SRAM cells 10_1 to 10_4 . Figure 4B Some embodiments of the present disclosure are shown Figure 4A Configuration of contact plugs on the layout.

[0075] For example, in the SRAM cell 10_1, the bit line (BL) (not shown) can be electrically connected to the source terminal of the pass gate transistor PG-1 through the contact plug 150_1, and the complementary bit line (BLB) (not shown) can be electrically connected to the source terminal of the pass gate transistor PG-2 through the connection plug 150_2. In addition, the power supply node VDD (not shown) can be electrically connected to the source terminal of the pull-up transistor PU-1 through the contact plug 150_3, and electrically connected to the source terminal of the pull-down transistor PU-2 through the contact plug 150_4. The ground VSS (not shown) can be electrically connected to the source terminal of the pull-down transistor PD-1 through the contact plug 150_5, and electrically connected to the source terminal of the buck transistor PD-2 through the contact plug 150_6.

[0076] Furthermore, in the SRAM cell 10_1 , drain terminals of the pull-up transistor PU- 1 and the pull-down transistor PD- 1 may be electrically connected to each other through a contact plug 150_7 , and drain terminals of the pull-up transistor PU- 2 and the pull-down transistor PD- 2 may be electrically connected to each other through a contact plug 150_8 .

[0077] In some embodiments, SRAM cell 10_2 is a copy of SRAM cell 10_1 but flipped on the Y axis, SRAM cell 10_3 is a copy of SRAM cell 10_1 but flipped on the X axis, and SRAM cell 10_4 is a copy of SRAM cell 10_3 but flipped on the Y axis.

[0078] According to some embodiments, the active regions 104N and 104P have steps. According to some embodiments, the steps are defined between adjacent gate stacks 136 and overlap with the contact plugs 150. Therefore, in some embodiments, the active regions 104 (eg, 104N_1, 104P_2, 104P_3, and 104N_4) may have a boomerang profile, such as Figure 4A and Figure 4B shown.

[0079] Figure 4C Some embodiments of the present disclosure are shown Figure 4A , to show more details of the stepped structure of the active region 104.

[0080] According to some embodiments, each active region 104N (eg, 104N_3) is a semiconductor strip having a protruding portion 104Q, such as Figure 4CAs shown. According to some embodiments, the protruding portion 104Q extends toward the adjacent active region 104P (e.g., 104P_3) in the Y direction. That is, according to some embodiments, each active region 104N includes a narrower portion 104A and a wider portion 104B. According to some embodiments, the pass gate transistors PG-1 and PG-2 are formed on the narrower portion 104A, and the pull-down transistors PD-1 and PD-2 are formed on the wider portion 104B.

[0081] In some embodiments, the narrower portion 104A has a dimension D1 in the Y direction in a range of about 6 nm to about 65 nm. In some embodiments, the wider portion 104B has a dimension D2 in the Y direction. Dimension D2 is greater than dimension D1, and dimension D2 is in a range of about 6 nm to about 65 nm. In some embodiments, the gate stack 136 ( Figure 4A ) of the gate length (i.e., the dimension in the X direction) is in the range of about 5 nm to about 29 nm. The ratio of dimension D1 to the gate length is in the range of about 0.6 to about 4.5. The ratio of dimension D2 to the gate length is in the range of about 0.6 to about 4.5.

[0082] According to some embodiments of the present disclosure, by forming an active region 104N with a step, independent adjustment of the performance of n-channel nanostructure transistors (e.g., pull-down transistors PD-1 and PD-2 and pass gate transistors PG-1 and PG-2) can be achieved, which in turn can optimally adjust the cell performance of the resulting SRAM cell according to some embodiments, such as current, operating voltage (Vmax) and / or read margin metrics.

[0083] Because the channel width (e.g., dimension D2) of the pull-down transistors PD-1 and PD-2 is greater than the channel width (e.g., dimension D1) of the pass-gate transistors PG-1 and PG-2, the “β ratio” of the saturation current (“Idsat”), i.e., the ratio of the Idsat of the pull-down transistors to the Idsat of the pass-gate transistors, may increase, e.g., to be greater than 1, which may improve the cell performance of the resulting SRAM cell, such as a higher operating voltage (e.g., Vmax), a higher cell current, a wider read margin metric, and / or a faster operating speed.

[0084] In some embodiments, the ratio of dimension D2 to dimension D1 (D2 / D1) is in the range of about 1.02 to about 3. If the ratio is too small (e.g., less than 1.02), the β ratio may increase too little, and the cell performance of the resulting SRAM may not be significantly improved. If the ratio is too large (e.g., greater than 3), the cell performance (e.g., Vmax) of the resulting SRAM cell may be reduced. In some embodiments, the ratio (D2 / D1) is in the range of about 1.02 to about 2.5. If the ratio is too large (e.g., greater than 2.5), the read margin metric may be overly compressed, resulting in the resulting SRAM cell may not have a good read / write margin balance.

[0085] In some embodiments where the active area is formed by a single patterning process, the step of the active area may occupy a certain distance in the X direction to convert the profile change of the active area. As a result, in some embodiments, the ratio (D2 / D1) is in the range of about 1.02 to about 2. If the ratio is too large (e.g., greater than 2), the step transition may be too long, so that the active area may have an undesirable profile. In some embodiments where the SRAM cell has a very small cell height (e.g., a high-density SRAM cell), the ratio (D2 / D1) is in the range of about 1.02 to about 1.5.

[0086] In some embodiments, Figure 4C As shown, the distance D3 between the narrower portions 104A of adjacent active regions 104N (e.g., 104N_2 and 104N_3) is substantially equal to the spacing D4 between the wider portions 104B (e.g., 104N_2 and 104N_3) of adjacent active regions 1042. In some embodiments, the distance D3 is in the range of about 20 nm to about 60 nm. The ratio of the distance D3 to the gate length is in the range of about 2 to about 5. In some embodiments, the distance D4 is in the range of about 20 nm to about 60 nm. The ratio of the distance D4 to the gate length is in the range of about 2 to about 5.

[0087] According to an embodiment of the present disclosure, since the distance D4 remains substantially equal to the distance D3 , the risk of merging between the N-type source / drain features of the adjacent pull-down transistors PD- 1 and PD- 2 may not increase.

[0088] According to some embodiments, the side wall S1 of the narrower portion 104A extending in the X direction is connected to the side wall S2 of the wider portion 104B extending in the X direction through the connecting wall S3. Figure 4C As shown, the connecting wall S3 extends a distance D5 (ie, the size of the protruding portion 104Q) in the Y direction. In some embodiments, the distance D5 is in a range of about 2 nm to about 30 nm. The ratio of the distance D5 to the gate length is in a range of about 0.1 to about 2.

[0089] According to some embodiments, each active region 104N (eg, 104N_3 ) has a sidewall S4 facing an adjacent active region 104N (eg, 104N_2 ). In some embodiments, the sidewall S4 extends continuously in the X direction without a step.

[0090] According to some embodiments, Figure 4C As shown, each active region 104P includes a first portion 104C and a second portion 104D offset from the first portion 104C. That is, according to some embodiments, each active region 104P (e.g., 104P_3) has a recess on a side facing the adjacent active region 104N (e.g., 104N_3) and a protrusion (e.g., 104P_4) on a side facing the adjacent inactive region 104P. According to some embodiments, the first portion 104C is a dummy region on which no functional transistor is formed, and the pull-up transistors PU-1 and PU-2 are formed on the second portion 104D.

[0091] In some embodiments, the first portion 104C and the second portion 104D have the same dimension D6 in the Y direction. Figure 4A-4C In some embodiments of the SRAM having a high current design, dimension D6 is smaller than dimension D1 of the narrower portion 104A of the active region 104N, and dimension D6 is in a range of about 6 nm to about 35 nm. A ratio of dimension D6 to gate length is in a range of about 0.6 to about 2.

[0092] In some embodiments, the distance D7 between the narrower portion 104A of the active region 104N and the first portion 104C of the active region 104P is substantially equal to the distance D8 between the wider portion 104B of the active region 104N and the second portion 104D of the active region 104. In some embodiments, the distances D7 and D8 are in the range of about 20 nm to about 60 nm. The ratio of the distance D7 to the gate length is in the range of about 2 to about 5. The ratio of the distance D8 to the gate length is in the range of about 2 to about 5.

[0093] According to an embodiment of the present disclosure, since the distance D8 remains substantially equal to the distance D7, the risk of merging between the N-type source / drain component of the pull-down transistor PD-1 or PD-2 and the P-type source / drain component of the adjacent pull-up transistor PU-1 or PU-2 may not increase.

[0094] According to some embodiments, the side wall S5 of the first portion 104C extending along the X direction is connected to the side wall S6 of the second portion 104D extending along the X direction through the connecting wall S7. Figure 4CAs shown, the connecting wall S7 extends a distance D9 in the Y direction. In some embodiments, the distance D9 is in a range of about 2 nm to about 15 nm. The ratio of the distance D9 to the gate length is in a range of about 0.1 to about 2. In some embodiments, the connecting wall S7 is aligned with the connecting wall S3. In some embodiments, the ratio of the distance D5 to the distance D9 (D5 / D9) is equal to or greater than 1.

[0095] In some embodiments, the distance D10 between adjacent active regions 104P (eg, 104P_3 and 104P_4 ) is equal to or greater than the distance D8 between the wider portion 104B of the active region 104N and the second portion 104D of the active region 104P.

[0096] Return to reference Figure 4A , Figure 4A Reference cross sections used in subsequent figures according to some embodiments are shown. Cross section XX is located in a plane parallel to the longitudinal axis (X direction) of active region 104 and passes through active region 104. Cross section Y1-Y1 is located in a plane parallel to the longitudinal axis (Y direction) of gate stack 136 and passes through gate stack 136_2. Cross section Y2-Y2 is located in a plane parallel to the longitudinal axis (Y direction) of gate stack 136 and passes through the source / drain region of active region 104 (e.g., the source terminal of pull-down transistor PD-1).

[0097] According to some embodiments, Figure 4D-1 to Figure 4G-3 1 is a cross-sectional view showing various intermediate stages of forming a semiconductor structure 100_1 of an SRAM cell, wherein Figure 4D-1 , Figure 4E-1 , Figure 4F-1 and Figure 4G-1 Corresponding to the section Y1-Y1, Figure 4D-2 , Figure 4E-2 , Figure 4F-2 and Figure 4G-2 Corresponding to the section Y2-Y2, Figure 4D-3 , Figure 4E-3 , Figure 4F-3 and Figure 4G-3 Corresponds to section XX.

[0098] Figure 4D-1 , Figure 4D-2 and Figure 4D-3 The semiconductor structure 100_1 is shown after forming a fin structure 104 , an isolation structure 110 , and a dummy gate structure 112 according to some embodiments. Figure 4D-4 is with Figure 4D-1 The plane AA passes through the lower fin element 103 .

[0099] According to some embodiments, a substrate 102 is provided, such as Figure 4D-1 , Figure 4D-2 and Figure 4D-3 As shown. The substrate 102 may be part of a semiconductor wafer, a semiconductor chip (or die), etc. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the substrate 102 includes: an elemental semiconductor, such as germanium; a compound semiconductor, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In addition, the substrate 102 may optionally include an epitaxial layer (epi layer), may be strained to improve performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features.

[0100] According to some embodiments, Figure 4D-1 and Figure 4D-2 As shown, an N-type well region NW and a P-type well region PW are formed in the substrate 102. In some embodiments, the N-type well region NW and the P-type well region PW are stacked in an alternating manner, and they have different conductivity types. In some embodiments, the N-type well region NW and the P-type well region PW are formed by an ion implantation process. For example, according to some embodiments, a patterned mask layer (such as a photoresist layer and / or a hard mask layer) is formed to cover a region of the substrate 102 where a P-type well region is predetermined to be formed, and then an n-type dopant (such as phosphorus or arsenic) is implanted into the substrate 102, thereby forming an n-type well region NW. Similarly, according to some embodiments, a patterned mask layer (such as a photoresist layer and / or a hard mask layer) is formed to cover a region of the substrate 102 where an n-type well region is predetermined to be formed, and then a p-type dopant (such as boron or BF2) is implanted into the substrate 102, thereby forming a p-type well region PW.

[0101] According to some embodiments, Figure 4D-1 to Figure 4D-4 As shown, an active region 104 (including 104N and 104P) is formed on a substrate 102. According to some embodiments, active regions 104N_3 and 104N_4 are formed on two corresponding P-type well regions PW, and active regions 104P_3 and 104P_4 are formed on an N-type region NW between the two P-type well regions PW. In some embodiments, active regions 104N and 104P extend in the X direction. That is, according to some embodiments, active regions 104N and 104P have longitudinal axes parallel to the X direction.

[0102] According to some embodiments, the formation of 104N and 104P includes forming an epitaxial stack on substrate 102 using an epitaxial growth process. According to some embodiments, the epitaxial stack includes alternating first semiconductor layers 106 and second semiconductor layers 108. The epitaxial growth process may be molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE), or another suitable technique.

[0103] In some embodiments, the first semiconductor layer 106 is made of a first semiconductor material and the second semiconductor layer 108 is made of a second semiconductor material. According to some embodiments, the first semiconductor material used for the first semiconductor layer 106 has a different lattice constant than the second semiconductor material used for the second semiconductor layer 108. In some embodiments, the first semiconductor material and the second semiconductor material have different oxidation rates and / or etching selectivities. In some embodiments, the first semiconductor layer 106 is made of SiGe, wherein the percentage of germanium (Ge) in the SiGe is in the range of about 20 atomic % to about 50 atomic %, and the second semiconductor layer 108 is made of pure silicon or substantially pure silicon. In some embodiments, the first semiconductor layer 106 is Si 1-x Ge x , wherein x is greater than about 0.3, or Ge (x=1.0), the second semiconductor layer 108 is Si or Si 1-y Ge y , where y is less than about 0.4 and x>y.

[0104] According to some embodiments, the first semiconductor layer 106 is configured as a sacrificial layer and will be removed to form a gap to accommodate the gate material, and the second semiconductor layer 108 will form a nanostructure (e.g., a nanowire or a nanosheet) that extends laterally between the source / drain features and serves as a channel for the resulting semiconductor device (e.g., a nanostructure transistor).

[0105] In some embodiments, the thickness of each first semiconductor layer 106 is in a range from about 3 nm to about 20 nm, such as about 4 nm to about 12 nm. In some embodiments, the thickness of each second semiconductor layer 108 is in a range from about 2 nm to about 20 nm, such as about 2 nm to about 10 nm. Figure 4D-1 to Figure 4D-3 Three first semiconductor layers 106 and three second semiconductor layers 108 are shown in FIG. 1 , but the number is not limited to three, and may be 1, 2, or more than 3, or less than ten.

[0106] According to some embodiments, the epitaxial stack including the first semiconductor layer 106 and the second semiconductor layer 108 and the well regions NW and PW below is patterned into active regions 104N and 104P. In some embodiments, the patterning process includes forming a patterned hard mask layer (not shown) on the epitaxial stack using a photolithography process. According to some embodiments, an etching process is then performed to remove portions of the epitaxial stack and the well regions NW and PW that are not covered by the patterned hard mask layer, thereby forming trenches and active regions 104N and 104P protruding from between the trenches. The etching process may be an anisotropic etching process, such as dry plasma etching.

[0107] In accordance with some embodiments, the portion of substrate 102 protruding from between the trenches forms lower fin elements 103 of active regions 104N and 104P. In accordance with some embodiments, the remaining portion of the epitaxial stack (including first semiconductor layer 106 and second semiconductor layer 108) forms upper fin elements of active regions 104N and 104P over the respective lower fin elements 103.

[0108] Figure 4D-4 1 shows the profile and configuration of the lower fin elements 103 of the active regions 104N and 104P according to some embodiments, which is similar to that described above in Figure 4A-4C 104N and 104P described in . Therefore, the repeated parts will not be described again. It should be noted that due to the characteristics of the lithography and etching processes, the step of the active area may occupy a certain distance (such as a transition region TR) to convert its profile change. The step with the transition region TR can be called a "smooth step". In some embodiments, according to some embodiments, the connecting walls S3 and S7 can be linear sidewalls inclined between the X direction and the Y direction, or can be curved sidewalls (for example, having a smiling profile), such as Figure 4D-4 According to some embodiments, the larger the size of the step (eg, distances D5 and D9), the longer the transition region TR.

[0109] In some other embodiments, through more than one patterning process, the active region 104 may be formed as a step without a transition region, with Figure 4A-4C The active areas 104 of the illustrated layouts have substantially the same contour. A step without a transition region TR may be referred to as a "sharp step".

[0110] According to some embodiments, a cutting process is performed on the active region 104P (eg, 104P_3 and 104P_4) to cut the active region 104P into a plurality of sections isolated from each other, such as Figure 4D-2 and Figure 4D-4 As shown. The cutting process may include photolithography and etching processes. According to some embodiments, during the cutting process, the upper fin element of the active region 104P is removed, and the lower fin element 103 of the active region 104P is also recessed.

[0111] According to some embodiments, isolation structure 110 is formed to surround lower fin element 103 of active regions 104N and 104P, such as Figure 4D-1 and Figure 4D-2 According to some embodiments, isolation structure 110 is configured to electrically isolate active regions 104N and 104P, and is also referred to as a shallow trench isolation (STI) feature.

[0112] According to some embodiments, the formation of the isolation structure 110 includes forming an insulating material to overfill the trench. In some embodiments, the insulating material is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, multiple layers thereof, and / or combinations thereof. In some embodiments, the insulating material is deposited using a process including CVD (such as low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), high aspect ratio process (HARP), or flowable CVD (FCVD)), atomic layer deposition (ALD), another suitable technique, and / or combinations thereof.

[0113] According to some embodiments, a planarization process is performed on the insulating material to remove the insulating material from the top of the active regions 104N and 104P. The planarization may be a chemical mechanical polishing (CMP), an etch back process, or a combination thereof. According to some embodiments, the insulating material is then recessed by an etching process (such as dry plasma etching and / or wet chemical etching) until the upper fin elements of the active regions 104N and 104P are exposed.

[0114] According to some embodiments, Figure 4D-1 , Figure 4D-3 and Figure 4D-4 As shown, a dummy gate structure 112 (including 112_1 to 112_4) is formed on the semiconductor structure 100_1. According to some embodiments, the dummy gate structure 112 extends through and surrounds the channel regions of the active regions 104N and 104P and the isolation structure 110. According to some embodiments, the dummy gate structure 112 is configured as a sacrificial structure and is replaced by the gate stack ( Figure 4A In some embodiments, the dummy gate structure 112 extends in the Y direction. That is, according to some embodiments, the dummy gate structure 112 has a longitudinal axis parallel to the Y direction.

[0115] In some embodiments, the connecting walls S3 and S7 are located between adjacent dummy gate structures 112. Figure 4D-4 In some embodiments, the transition region TR may be smaller than the pitch P of the dummy gate structure 112 , for example, approximately half of the pitch P.

[0116] According to some embodiments, Figure 4D-1 and Figure 4D-3 As shown, each dummy gate structure 112 includes a dummy gate dielectric layer 114 and a dummy gate electrode layer 116 formed on the dummy gate dielectric layer 114. In some embodiments, the dummy gate dielectric layer 114 is made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiO2), HfO2, HfZrO, HfSiO, HfTiO, HfAlO and / or a combination thereof. In some embodiments, the dielectric material is formed using ALD, CVD, thermal oxidation, physical vapor deposition (PVD), another suitable technique and / or a combination thereof.

[0117] In some embodiments, the dummy gate electrode layer 116 is made of a semiconductor material such as polysilicon, polycrystalline silicon germanium. In some embodiments, the dummy gate electrode layer 116 is made of a conductive material, such as a metal nitride, a metal silicide, a metal and / or a combination thereof. In some embodiments, the material for the dummy gate electrode layer 116 is formed using CVD, another suitable technique and / or a combination thereof.

[0118] In some embodiments, the formation of the dummy gate structure 112 includes globally and conformally depositing a dielectric material for the dummy gate dielectric layer 114 on the semiconductor structure 100_1, depositing a material for the dummy gate electrode layer 116 on the dielectric material, planarizing the material for the dummy gate electrode layer 116, and patterning the dielectric material and the material for the dummy gate layer 116 into the dummy gate structure 112. According to some embodiments, the patterning process includes forming a patterned hard mask layer (not shown) on the material for the dummy gate electrode layer 116 to cover the channel region of the active regions 104N and 104P. According to some embodiments, the material of the dummy gate electrode layer 116 and the dielectric material that are not covered by the patterned hard mask layer are etched away until the source / drain regions of the active regions 104N and 104P are exposed.

[0119] Figure 4E-1 , Figure 4E-2 and Figure 4E-3 The semiconductor structure 100_1 is shown after forming a gate spacer 118, a fin spacer 120, source / drain features 122N and 122P, an inner spacer 124, a semiconductor isolation feature 126, a dielectric isolation feature 128, a contact etch stop layer 132, and a first interlayer dielectric layer 134, according to some embodiments.

[0120] According to some embodiments, the gate spacer 118 is formed on opposite sides of the dummy gate structure 112, and the fin spacer 120 is formed along opposite sidewalls of the active region 104, such as Figure 4E-2 and Figure 4E-3As shown. According to some embodiments, the gate spacer 118 extends in the Y direction and passes through the active region 104 and the isolation structure 110. According to some embodiments, the gate spacer 118 is used to offset the subsequently formed source / drain features and separate the source / source features from the gate structure. According to some embodiments, the fin spacer 120 extends in the X direction. According to some embodiments, the fin spacer 120 can be used to limit the growth of epitaxial materials to prevent adjacent epitaxial materials from merging with each other.

[0121] In some embodiments, the gate spacer layer 118 and the fin spacer layer 120 are made of a silicon-containing dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon oxycarbonitride (SiOCN), and / or oxygen-doped silicon carbide (Si(O)CN). In some embodiments, the formation of the gate spacer layer 118 and the fin spacer layer 120 includes globally and conformally depositing a dielectric material on the semiconductor structure 100_1 using ALD, CVD (such as LPCVD, PECVD, HDP-CVD, or HARP), another suitable method, and / or a combination thereof, followed by an anisotropic etching process.

[0122] According to some embodiments, the vertical portions of the dielectric material remaining on opposite sides of the dummy gate structure 112 serve as gate spacers 118. According to some embodiments, the vertical portions of the dielectric material remaining on opposite sides of the active regions 104N and 104P serve as fin spacers 120.

[0123] According to some embodiments, Figure 4E-2 and Figure 4E-3 As shown, source / drain features 122N and 122P are formed in and / or over source / drain regions of active regions 104N and 104P. According to some embodiments, the formation of source / drain features 122 includes recessing the source / drain regions of active regions 104N and 104P using dummy gate structure 112 and gate spacer 118 as a mask to form source / source recesses on opposite sides of dummy gate structure 122. According to some embodiments, the source / drain recesses may extend into lower fin element 103. In some embodiments, the recessing process includes an anisotropic etching process, (dry plasma etching), an isotropic etching process (such as dry chemical etching), remote plasma etching or wet chemical etching, or a combination thereof. In some embodiments, fin spacer 120 and isolation structure 110 are also recessed in the etching process.

[0124] Thereafter, according to some embodiments, an etching process is performed to laterally recess the first semiconductor layer 106 of the active regions 104N and 104P from the source / drain recesses to form recesses, and then an internal spacer layer 124 is formed in the recesses, such as Figure 4E-3According to some embodiments, the inner spacer layer 124 is formed to abut against the recessed side surface of the first semiconductor layer 106. In some embodiments, the inner spacer layer 124 extends directly below the gate spacer layer 118.

[0125] According to some embodiments, the inner spacer layer 124 can avoid direct contact between the source / drain components and the gate stack, and is configured to reduce parasitic capacitance (i.e., Cgs and Cgd) between the gate stack and the source / drain components. In some embodiments, the inner spacer layer 124 is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon oxycarbon nitride (SiOCN), and / or oxygen-doped silicon carbide nitride (Si(O)CN).

[0126] In some embodiments, the inner spacer layer 124 is formed by depositing a dielectric material for the inner spacer layer 124 on the semiconductor structure 100_1 to fill the recess, and then etching back the dielectric material to remove the dielectric material outside the recess. According to some embodiments, the portion of the dielectric material remaining in the recess is used as the inner spacer layer 124. In some embodiments, the deposition process includes ALD, CVD (such as PECVD, LPCVD or HARP), another suitable technology or a combination thereof. In some embodiments, the etching back process includes an anisotropic etching process (such as dry plasma etching), an isotropic etching process (such as dry chemical etching), remote plasma etching or wet chemical etching, or a combination thereof.

[0127] According to some embodiments, semiconductor isolation features 126 are formed in source / drain recesses above lower fin elements 103, such as Figure 4E-2 and Figure 4E-3 In some embodiments, the semiconductor isolation feature 126 is made of an epitaxial semiconductor material, such as undoped silicon formed by MBE, MOCVD or VPE, another suitable technique, or a combination thereof.

[0128] According to some embodiments, Figure 4E-2 and Figure 4E-3 As shown, a dielectric isolation feature 128 is formed on the semiconductor isolation feature 126 in the source / drain recesses. In some embodiments, the dielectric isolation feature 128 is in direct contact with the semiconductor isolation feature 126 and the bottommost internal spacer layer 124.

[0129] In some embodiments, the dielectric isolation features 128 are made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbon nitride (SiOCN) and / or oxygen-doped silicon carbide nitride (Si(O)CN), or made of a high-k dielectric material (e.g., having a dielectric constant greater than about 7.9), such as LaO, AlO, AlON, ZrO, HfO, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, or a combination thereof. In some embodiments, the dielectric isolation features 128 are deposited using a technique such as ALD, CVD (such as HDP-CVD, LPCVD, or PECVD), another suitable technique, or a combination thereof, followed by an etch-back process.

[0130] According to some embodiments, Figure 4E-2 and Figure 4E-3 As shown, source / drain features 122N and 122P are formed on dielectric isolation features 128 in source / drain recesses. According to some embodiments, source / drain features 122N and 122P are formed on opposite sides of dummy gate structure 112. In some embodiments, source / drain feature 122N has a different conductivity type than source / source feature 122P. The formation may include one or more epitaxial growth processes. These epitaxial growth processes may be MBE, MOCVD or VPE, another suitable technique or a combination thereof.

[0131] In some embodiments, the source / drain component 122N and the source / source component 122P may be formed separately. For example, a patterned mask layer (e.g., a photoresist layer and / or a hard mask layer) may be formed to cover the semiconductor structure 100_1 on the N-type well region NW, and then the source / drain component 122N may be grown. Thereafter, the patterned mask layer may be removed. Similarly, a patterned mask layer (e.g., a photoresist layer and / or a hard mask layer) may be formed to cover the semiconductor structure 100_1 on the P-type well region PW, and then the source / drain component 122P may be grown. Thereafter, the patterned mask layer may be removed.

[0132] In some embodiments, source / drain features 122N and 122P are in-situ doped during the epitaxial process. In some embodiments, during the epitaxial growth process, source / drain feature 122N is doped with an n-type dopant. For example, the n-type dopant may be phosphorus (P) or arsenic (As). For example, n-type source / drain feature 122N may be epitaxially grown silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiPC), silicon phosphoarsenide (SiPAs), silicon arsenide (SiAs), silicon (Si), or a combination thereof doped with phosphorus and / or arsenic. In some embodiments, the concentration of the dopant (e.g., P) in source / drain feature 122N is about 2×1019 cm -3 About 3×10 21 cm -3 within the range.

[0133] In some embodiments, the source / drain features 122P are doped with a p-type dopant during the epitaxial growth process. For example, the p-type dopant may be boron (B) or BF2. For example, the p-type source / drain features 122P may be epitaxially grown silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium (Ge), silicon (Si), or a combination thereof doped with boron (B). In some embodiments, the concentration of the dopant (e.g., B) in the source / drain features 122P is about 1×10 19 cm -3 About 6×10 20 cm -3 In some embodiments, the n-type source / drain component 122N and the p-type source / drain component 122P are made of different epitaxial materials. For example, the n-type source / drain component 122N is made of SiP, and the p-type source / drain component 122P is made of SiGe.

[0134] According to some embodiments, Figure 4E-2 and Figure 4E-3 As shown, a contact etch stop layer 132 is formed on the semiconductor structure 100_1 to cover the source / drain features 122N and 122P. In some embodiments, the contact etch stop layer 132 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbide (Si(O)CN), or a combination thereof. In some embodiments, the dielectric material for the contact etch stop layer 132 is globally conformally deposited on the semiconductor structure 100_1 using CVD (such as LPCVD, PECVD, HDP-CVD, or HARP), ALD, another suitable method, or a combination thereof.

[0135] Thereafter, according to some embodiments, a first interlayer dielectric layer 134 is formed on the contact etch stop layer 132 to fill the space between the dummy gate structures 112, such as Figure 4E-2 and Figure 4E-3 In some embodiments, the first interlayer dielectric layer 134 is made of a dielectric material, such as undoped silicate glass (USG), doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or another suitable dielectric material.

[0136] In some embodiments, the first interlayer dielectric layer 134 and the contact etch stop layer 132 are made of different materials, and the etching selectivity is greatly different. In some embodiments, the dielectric material for the first interlayer dielectric layer 134 is deposited using a technique such as CVD (such as HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, and / or a combination thereof. According to some embodiments, the dielectric material of the contact etch stop layer 132 and the first interlayer dielectric layer 134 above the dummy gate electrode layer 116 is removed using a technique such as CMP until the top surface of the dummy gate electrode layer 116 is exposed.

[0137] Figure 4F-1 , Figure 4F-2 and Figure 4F-3 The semiconductor structure 100_1 is shown after forming a gate stack 136 and a gate isolation structure 144 , in accordance with some embodiments. Figure 4F-4 is with Figure 4F-1 The plan view corresponding to the AA plane. Figure 4F-5 is with Figure 4F-1 The plane BB passes through the second semiconductor layer 108.

[0138] According to some embodiments, one or more etching processes are used to remove the dummy gate structure 112 to form a gate trench. According to some embodiments, the gate trench exposes the channel region of the active regions 104N and 104P. In some embodiments, the gate trench also exposes the inner sidewall of the gate spacer 118 facing the channel region.

[0139] According to some embodiments, the first semiconductor layer 106 of the active regions 104N and 104P is removed using an etching process to form a gap. The internal spacer layer 124 can be used as an etching stop layer in the etching process, which can protect the source / drain components 122N and 122P from damage. In some embodiments, the gap also exposes the inner sidewall of the internal spacer layer 124 facing the channel region. The etching process for removing the dummy gate structure 112 and the first semiconductor layer 106 can be an anisotropic etching process (such as dry plasma etching), an isotropic etching process (such as dry chemical etching), remote plasma etching or wet chemical etching, and / or a combination thereof.

[0140] According to some embodiments, after the etching process, the main surface of the second semiconductor layer 108 is exposed. According to some embodiments, the exposed second semiconductor layer 108 of the active regions 104N and 104P forms a group of nanostructures 108 used as a channel layer of a resulting semiconductor device (e.g., a nanostructure transistor such as a GAA-FET).

[0141] According to some embodiments, the final gate stack 136 (including 136_1 to 136_4) is formed in the gate trench and the gap, thereby encapsulating the nanostructure 108, such as Figure 4F-1 , Figure 4F-3 , Figure 4F-4 and Figure 4F-5 As shown. In some embodiments, the final gate stack 136 extends in the Y direction. That is, according to some embodiments, the final gate stack 136 has a longitudinal axis parallel to the Y direction. The final gate stack 136 is coupled to the channel region so that current can flow between the source / drain regions during operation. In some embodiments, each final gate stack 136 includes an interface layer 138, a gate dielectric layer 140, and a metal gate electrode layer 142 (including 142N and 142P), as shown. Figure 4F-1 , Figure 4F-3 and Figure 4F-5 shown.

[0142] In some embodiments, the interface layer 138 is made of chemically formed silicon oxide. In some embodiments, the interface layer 138 is formed using one or more cleaning processes, such as including ozone (O3), an ammonia-hydrogen peroxide-water mixture, and / or a hydrochloric acid-hydrogen peroxide-water mixture. According to some embodiments, the semiconductor material from the nanostructures 108 and the lower fin element 103 is oxidized to form the interface layer 138.

[0143] According to some embodiments, gate dielectric layer 140 is conformally formed along interface layer 138, the upper surface of isolation structure 110, the sidewalls of gate spacer layer 118, and the sidewalls of internal spacer layer 124. Gate dielectric layer 140 is made of a high-k dielectric layer. In some embodiments, the high-k dielectric layer is a dielectric material with a high dielectric constant (k value), for example, greater than 7.9, for example, greater than 13. In some embodiments, the high-k dielectric layer includes hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, Al2O3, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO2, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfCiO, (Ba, Sr)TiO3 (BST), Si3N4, oxynitride (SiON), combinations thereof, or another suitable material. The high-k dielectric layer can be deposited using ALD, PVD, CVD, and / or another suitable technique.

[0144] According to some embodiments, a metal gate electrode layer 142N is formed on the P-type well region PW, and a metal gate electrode layer 142P is formed on the N-type well region NW. In some embodiments, the metal gate electrode layers 142N and 142P are made of a variety of conductive materials, such as metals, metal alloys, conductive metal oxides and / or metal nitrides, another suitable conductive material, and / or combinations thereof. For example, the metal gate electrode layers 142N and 142P may be made of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Re, Ir, Co, Ni, another suitable conductive material, or a multilayer thereof.

[0145] The metal gate electrode layers 142N and 142P may be a multilayer structure having various combinations of a diffusion barrier layer, a work function layer having a selected work function to improve device performance (e.g., threshold voltage) of n-channel FETs and p-channel FETs, a cap layer to prevent oxidation of the work function layer, a glue layer to adhere the work function layer to the next layer, a metal fill layer to reduce the overall resistance of the gate stack, and / or another suitable layer. The metal gate electrode layers 142N and 142P may be formed using ALD, PVD, CVD, electron beam evaporation, or another suitable technique. The metal gate electrode layers 142N and 142P may be formed for n-channel FETs and p-channel FETs, respectively, which may use different work function materials. In an alternative embodiment, the conductive material of the metal gate electrode layer 142N is the same as the conductive material of the metal gate electrode 142P.

[0146] According to some embodiments, a planarization process such as CMP may be performed on the semiconductor structure 100_1 to remove the materials of the gate dielectric layer 140 and the metal gate electrode layers 142N and 142P formed over the first interlayer dielectric layer 134. The final gate stack 136 wrapped around the nanostructure 108 is combined with the adjacent source / drain features 122N or 122P to form a nanostructure transistor.

[0147] According to some embodiments, transistors formed on nanostructures 108 (of active region 104N) in P-type well region PW are n-channel nanostructure transistors, such as pull-down transistors PD-1 and PD-2 and pass-gate transistors PG-1 and PG-2. According to some embodiments, transistors formed on nanostructures 108 (of active region 104P) in N-type well region NW are p-channel nanostructure transistors, such as pull-up transistors PU-1 and PU-2.

[0148] According to some embodiments, the nanostructures 108 of the pass-gate transistors PG-1 and PG-2 have a dimension D1 in the Y direction that is substantially equal to the dimension D1 of the narrower portion 104A of the active area 104N. According to some embodiments, the nanostructures 108 of the pull-down transistors PD-1 and PD-2 have a dimension D2 in the Y direction that is substantially equal to the dimension D2 of the wider portion 104B of the active area 104N. The dimension D2 is greater than the dimension D1 by a distance D5. According to some embodiments, the nanostructures 108 of the pull-up transistors PU-1 and PU-2 have a dimension D6 in the Y direction that is substantially equal to the dimension D6 of the second portion 104D of the active area 104P.

[0149] According to some embodiments of the present disclosure, since the nanostructure 108 of the pull-down transistors PD-1 and PD-2 is wider than the nanostructure 108 of the pass-gate transistors PG-1 and PG-2, the saturation current β ratio may be increased, which may improve the cell performance of the resulting SRAM cell, such as a higher operating voltage (Vmax) and a higher cell current, a wider read margin metric, and / or a faster operating speed.

[0150] According to some embodiments, the gate isolation structure 144 is formed in and / or through the final gate stack 136, the gate spacer layer 118, the first interlayer dielectric layer 134, and the contact etch stop layer 132, such as Figure 4F-1 , Figure 4F-2 , Figure 4F-4 and Figure 4F-5 According to some embodiments, the gate stack 136 is cut into several segments physically and electrically isolated from each other by a gate isolation structure 144. The gate isolation structure 144 may also be referred to as a cut metal gate (CMG) pattern.

[0151] According to some embodiments, Figure 4F-1 and Figure 4F-2 As shown, the gate isolation structure 144 extends through the gate stack 136 to a deeper position than the portion through the first interlayer dielectric layer 134. Figure 4F-4 and Figure 4F-5 As shown, the portion of the gate isolation structure 144 passing through the gate stack 136 is wider than the portion of the gate isolation structure 144 passing through the first interlayer dielectric layer 134, which can reduce the overlapping area between the gate stack 136 and the source / drain features 122N / 122P, thereby reducing the parasitic capacitance of the resulting SRAM cell.

[0152] The gate isolation structure 144 is made of a dielectric material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbon nitride (Si(O)CN), silicon oxide (SiO2), or a high-k dielectric material such as LaO, AlO, AlON, ZrO, HfO, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, or a combination thereof.

[0153] The formation of the gate isolation structure 144 includes patterning the semiconductor structure 100_1 using photolithography and etching processes to form a gate cut opening (wherein the gate isolation structure 44 will be formed). The etching process may include dry etching, such as reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, capacitively coupled plasma (CCP) etching, another suitable method or a combination thereof. According to some embodiments, the formation of the gate isolation structure 144 also includes depositing a dielectric material for the gate isolation structure 144 to overfill the gate cut opening. In some embodiments, the deposition process is ALD, CVD (such as LPCVD, PECVD, HDP-CVD or HARP), another suitable technology or a combination thereof. Thereafter, according to some embodiments, a planarization process is performed on the dielectric material of the gate isolation structure 144 until the first interlayer dielectric layer 134 is exposed. Planarization may be CMP, a back etch process or a combination thereof.

[0154] Figure 4G-1 , Figure 4G-2 and Figure 4G-3 The semiconductor structure 100_1 is illustrated after forming an etch stop layer 146 , a second interlayer dielectric layer 148 , a contact plug 150 , an etch stop layer 156 , a third interlayer dielectric layer 158 , and a via 160 , in accordance with some embodiments.

[0155] According to some embodiments, Figure 4G-1 to Figure 4G-3 As shown, an etch stop layer 146 and a second interlayer dielectric layer 148 are sequentially formed on the semiconductor structure 100_1. In some embodiments, the etch stop layer 146 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the second interlayer dielectric layer 148 is made of a dielectric material, such as USG, BPSG, FSG, PSG, BSG, and / or another suitable dielectric material. In some embodiments, the etch stop layer 146 and the second interlayer dielectric layer 148 are deposited using CVD (such as HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, or a combination thereof.

[0156] According to some embodiments, contact plug 150 is formed through second interlayer dielectric layer 148, etch stop layer 146, first interlayer dielectric layer 134, and contact etch stop layer 132. According to some embodiments, contact plug 150 is connected to source / drain feature 122N / 122P. In some embodiments, formation of contact plug 150 includes patterning semiconductor structure 100_1 using photolithography and etching processes to form contact openings (where contact plugs will be formed) until source / drain feature 122N / 122P is exposed. The etching process may include dry etching, such as RIE, NBE, ICP etching, CCP etching, another suitable method, or a combination thereof.

[0157] According to some embodiments, silicide layer 152 is formed on the exposed surfaces of source / drain features 122N and 122P. In some embodiments, silicide layer 152 is made of WSi, NiSi, TiSi and / or CoSi. In some embodiments, the formation of silicide layer 152 includes depositing a metal material and then performing one or more annealing processes. According to some embodiments, semiconductor material (e.g., Si) from source / drain features 122N and 122P reacts with a metal material to form silicide layer 152. Then, unreacted metal material is removed, for example, using wet etching.

[0158] According to some embodiments, a deposition process and an etch-back process are used to form contact pads 154 along sidewalls of the contact openings. In some embodiments, contact pads 154 are made of an insulating material, such as a dielectric material (e.g., SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, SiN, HfSi, or SiO); or undoped silicon (Si).

[0159] Afterwards, according to some embodiments, one or more conductive materials for contact plug 150 are deposited to overfill the contact opening. In some embodiments, one or more conductive materials are deposited using CVD, PVD, electron beam evaporation, ALD, ECP, ELD, another suitable method, or a combination thereof to overfill the contact opening. One or more conductive materials on second interlayer dielectric layer 148 are planarized using, for example, CMP.

[0160] The contact plug 150 may have a multilayer structure. For example, a barrier / adhesion layer (not shown) may be optionally deposited along the sidewalls and bottom surface of the contact opening. The barrier / adhesion layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), another suitable material or a combination thereof. A bulk metal layer is then deposited on the barrier / adhesion layer (if formed) to fill the remainder of the contact opening. In some embodiments, the bulk metal layer is made of one or more conductive materials having low resistance and good gap filling capability, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), another suitable metal material or a combination thereof.

[0161] According to some embodiments, Figure 4G-1 to Figure 4G-3 As shown, an etch stop layer 156 and a third interlayer dielectric layer 158 are sequentially formed on the semiconductor structure 100_1. In some embodiments, the etch stop layer 156 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the third interlayer dielectric layer 158 is made of a dielectric material, such as USG, BPSG, FSG, PSG, BSG, and / or another suitable dielectric material. In some embodiments, the etch stop layer 156 and the third interlayer dielectric layer 158 are deposited using CVD (such as HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, or a combination thereof.

[0162] According to some embodiments, via 160 is formed to land on contact plug 150 and gate stack 136, such as Figure 4G-1 and Figure 4G-2 According to some embodiments, the via 160 electrically connected to the source / drain terminal of the nanostructure transistor through the contact plug 150 may also be referred to as a source / drain via (VS or VD). The via 160 electrically connected to the gate terminal of the nanostructure transistor may also be referred to as a gate via (VG).

[0163] In some embodiments, the formation of the through hole 160 includes patterning the semiconductor structure 100_1 using a photolithography and etching process to form a through hole opening (where the through hole 160 will be formed). The etching process may include dry etching, such as RIE, NBE, ICP etching, CCP etching, another suitable method or a combination thereof. Thereafter, according to some embodiments, one or more conductive materials are deposited using CVD, PVD, electron beam evaporation, ALD, ECP, ELD, another suitable method or a combination thereof to overfill the through hole opening. One or more conductive materials on the upper surface of the third interlayer dielectric layer 158 are planarized using, for example, CMP.

[0164] The via 160 may have a multilayer structure. For example, a barrier / adhesion layer (not shown) may optionally be deposited along the sidewalls and bottom surface of the via opening. The barrier layer may be made of Ta, TaN, Ti, TiN, CoW, another suitable material, or a combination thereof. A bulk metal layer is then deposited on the barrier / adhesion layer (if formed) to fill the remainder of the via opening. In some embodiments, the bulk metal layer is made of one or more conductive materials, such as Co, Ni, W, Ti, Ta, Cu, Rh, Ir, Pt, Al, Ru, Mo, or a combination thereof.

[0165] The semiconductor structure 100_1 may undergo further front-side BEOL processes to form various interconnected conductive features (not shown), such as metal layers and vias between two adjacent metal layers, on the semiconductor structure 100_1. According to an embodiment of the present disclosure, without increasing the cell height of the SRAM cell, by forming the stepped active regions 104N and 104P, the channel width of the pull-down transistor is increased, thereby improving the cell performance of the resulting SRAM cell, while preventing an increase in the risk of source / drain merging.

[0166] Figure 5A , Figure 5B and Figure 5C is a plan view showing an active region with a smooth step according to some embodiments of the present disclosure. In addition to the size of the transition region TR of the active region, Figure 5A , Figure 5B and Figure 5C Examples and Figure 4A to Figure 4G-3 The embodiments are similar.

[0167] Due to the characteristics of the photolithography and etching processes, the transition region TR of the active region 104N may have various sizes. Figure 5AAs shown, the transition region TR of the active region 104N is confined between the gate spacers 118 and does not overlap the gate spacers 118. In some embodiments, the transition region TR of the active region 104N extends directly below the adjacent dummy gate structure 112 (or the adjacent gate stack 136), such as Figure 5B In some embodiments, Figure 5C As shown, the transition region TR of the active region 104N is confined between adjacent dummy gate structures 112 (or adjacent gate stacks 136 ) and does not overlap with adjacent dummy gate structures 112 (or adjacent gate stacks 136 ). Figure 5A , Figure 5B and Figure 5C Only active region 104N is shown with various smooth steps, but active region 104P also has a similar step profile.

[0168] Fig. 6A and Figure 6B is a plan view illustrating the formation of an active region with a sharp step according to some embodiments of the present disclosure. Fig. 6A and Figure 6B is the plan view corresponding to plane AA.

[0169] According to some embodiments, two patterning processes may be used to perform the formation of active regions 104N and 104P. In some embodiments, a first patterning process (including photolithography and etching processes) is performed on the epitaxial stack (including the first semiconductor layer 106 and the second semiconductor layer 108) and the underlying well regions NW and PW to form active regions 104N and 104P. Fig. 6A As shown, active regions 104N and 104P are semiconductor strips without steps, according to some embodiments.

[0170] According to some embodiments, a second patterning process (including photolithography and etching processes) is then performed on active regions 104N and 104P to partially cut active regions 104N and 104P, thereby forming steps on the sides of active regions 104N and 104P, such as Figure 6B According to some embodiments, the mask patterns used in the first and second photolithography processes do not have a stepped profile, and thus the active regions 104N and 104P may be formed with sharp steps.

[0171] like Figure 6B As shown, according to some embodiments, the lower fin elements 103 of the active regions 104N and 104P may have Figure 4A The active regions 104P and 104N of the illustrated layout have substantially the same profile. According to some embodiments, connecting walls S3 and S7 extend in the Y direction. In some embodiments, connecting wall S7 is aligned with connecting wall S3.

[0172] Figure 6C-1 and Figure 6C-2 is a plan view of a semiconductor structure 100_1 of an SRAM cell according to some embodiments of the present disclosure, corresponding to plane AA and plane BB respectively. According to some embodiments, Figure 6B The active regions 104N and 104P perform Figure 4D-1 to Figure 4G-3 The above steps described in the above are used to form the nanostructure transistor of the SRAM cell, such as Figure 6C-1 and Figure 6C-2 shown.

[0173] Fig. 7A Some embodiments of the present disclosure are shown Figure 2 Layout of the middle half of the GP group of SRAM. Figure 7B-1 and Figure 7B-2 yes Fig. 7A 1 is a plan view of a semiconductor structure 100_2 of an SRAM cell, corresponding to plane AA and plane BB.

[0174] According to some embodiments, Fig. 7A As shown, the step of active area 104N may overlap (e.g., directly above) the gate stack 136 of pull-down transistors PD-1 and PD-2, and the step of active area 104P may overlap (e.g., directly below) the gate stack 136 of pull-up transistors PU-1 and PU-2. Figure 7B-1 As shown, the lower fin elements 103 of the active regions 104N and 104P have sharp steps and have the same Fig. 7A The active areas 104N and 104P of the illustrated layout are of substantially identical outlines.

[0175] In some embodiments, the nanostructure 108 of the pull-down transistors PD-1 and PD-2 has a step on the side facing the pull-up transistors PU-1 and PU-2, such as Figure 7B-2 According to some embodiments, the nanostructure 108 of the pull-down transistors PD-1 and PD-2 includes a narrower portion with a size D1 and a wider portion with a size D2. Accordingly, the nanostructure 108 of the pull-up transistors PU-1 and PU-2 has steps on opposite sides.

[0176] Fig. 8A Some embodiments of the present disclosure are shown Figure 2 Layout of the middle half of the GP group of SRAM. Figure 8B-1 and Figure 8B-2 yes Fig. 8A 1 is a plan view of a semiconductor structure 100_3 of an SRAM cell, corresponding to plane AA and plane BB.

[0177] According to some embodiments, the step of active region 104N may overlap (be directly below) gate stacks 136 of pass-gate transistors PG-1 and PG-2, and active region 104P may have no step, such as Fig. 8A According to some embodiments, Figure 8B-1 As shown, the lower fin element 103 of the active area 104N has a sharp step and has the same Fig. 8A The active regions 104N of the illustrated layouts have substantially the same outline.

[0178] In some embodiments, Figure 8B-2 As shown, the nanostructure 108 of the pass-gate transistors PG-1 and PG-2 has a step on the side facing the pull-up transistors PU-1 and PU-2. Figure 7B-2 As shown, nanostructure 108 of pass-gate transistors PG- 1 and PG- 2 includes a narrower portion having a dimension D1 and a wider portion having a dimension D2 .

[0179] Fig.9A is a plan view showing an active region according to some embodiments of the present disclosure. Fig.9A An embodiment similar to Figure 7A to Figure 7B-2 In some embodiments, the active region 104N has a smooth step. Fig.9A As shown, the transition region TR of the active region 104N overlaps with (is directly below) the gate stacks 136 (or dummy gate structures 112 ) of the pull-down transistors PD- 1 and PD- 2 .

[0180] Fig. 9B is a plan view showing an active region according to some embodiments of the present disclosure. Fig. 9B An embodiment similar to Figure 8A to Figure 8B-2 In some embodiments, the active region 104N has a smooth step. Fig. 9B As shown, the transition region TR of the active region 104N overlaps with (is directly below) the gate stacks 136 (or dummy gate structures 112 ) of the pass-gate transistors PG- 1 and PG- 2 .

[0181] Fig. 10A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP. Fig. 10B yes Fig. 10A 1 is a plan view of the semiconductor structure 100_4 of the SRAM cell, corresponding to plane BB. Fig. 10A and Fig. 10B An embodiment similar to Figure 4A to Figure 4G-3 , except that the active area 104N has protrusions on opposite sides.

[0182] According to some embodiments, in some embodiments where the risk of merging between the N-type source / drain features of adjacent pull-down transistors PD-1 and PD-2 is relatively low, such as Fig. 10A As shown, each active region 104N includes protruding portions 104Q and 104Q'. According to some embodiments, protruding portion 104Q extends a distance D5 toward the adjacent active region 104P in the Y direction, and protruding portion 104Q' extends a distance D5' toward the adjacent active region 104N in the Y direction. In some embodiments, distance D5' is substantially equal to distance D5.

[0183] In some embodiments, Fig. 10A As shown, a distance D3 between the narrower portions 104A of adjacent active regions 104N is greater than a distance D4 between the wider portions 104B of adjacent active regions 104N.

[0184] In some embodiments, a distance D7 between the narrower portion 104A of the active region 104N and the first portion 104C of the active region 104P is substantially equal to a distance D8 between the wider portion 104B of the active region 104N and the second portion 104D of the active region 104P.

[0185] According to some embodiments, the lower fin elements 103 of the active regions 104N and 104P may have Fig. 10A The active regions 104P and 104N of the illustrated layout have substantially the same profile. In some other embodiments, the lower fin elements 103 of the active regions 104N and 104P may have the above-described smooth step.

[0186] Fig.11A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP. Fig. 11B yes Fig.11A 1 is a plan view of a semiconductor structure 100_5 of an SRAM cell, corresponding to plane BB. Fig.11A and Fig. 11B An embodiment similar to Figure 4A to Figure 4G-3 , except that the active area 104P has no step.

[0187] In some embodiments where the risk of merging between the N-type source / drain features of the pull-down transistor PD-1 or PD-2 and the P-type source / drain features of the adjacent pull-up transistor PU-1 or PU-2 is relatively low, the active region 104P is a semiconductor strip without a step. In some embodiments, a distance D7 between the narrower portion 104A of the active region 104N and the first portion 104C of the active region 104P is greater than a distance D8 between the wider portion 104B of the active region 104N and the second portion 104D of the active region 104.

[0188] According to some embodiments, the lower fin elements 103 of the active regions 104N and 104P may have Fig.11A The active regions 104P and 104N of the illustrated layout have substantially the same profile. In some other embodiments, the lower fin element 103 of the active region 104N may have the above-mentioned smooth step.

[0189] Fig. 12A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP. Fig. 12B is corresponding to plane BB according to some embodiments of the present disclosure Fig. 12A FIG. 1 is a plan view of a semiconductor structure 100_6 of an SRAM cell. Fig. 12A and Fig. 12B An embodiment similar to Fig. 10A and 10B , except that the active area 104P has no step.

[0190] In some embodiments where the risk of merging between source / drain features is relatively low, a distance D3 between the narrower portions 104A of adjacent active regions 104N is greater than a distance D4 between the wider portions 104B of adjacent active regions 104, and a distance D7 between the narrower portion 104A of the active region 104N and the first portion 104C of the active region 104P is greater than a distance D8 between the wider portion 104B of the active region 104N and the second portion 104D of the active region 104P.

[0191] According to some embodiments, the lower fin elements 103 of the active regions 104N and 104P may have Fig. 12A The active regions 104P and 104N of the illustrated layout have substantially the same profile. In some other embodiments, the lower fin element 103 of the active region 104N may have the above-mentioned smooth step.

[0192] Fig.13A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP. Figure 13B-1 and Figure 13B-2 is with Fig.13A The cross-sectional view of the semiconductor structure 100_7 of the SRAM cell corresponding to the line Y1 -Y1 and the line Y2 -Y2 . Figure 13B-3 is with Figure 13B-1 The plane diagram corresponding to plane BB. Figure 13A to Figure 13B-3 An embodiment similar to Figure 4A to Figure 4G-3 In the embodiment, the semiconductor structure 100_7 can be used for a high-density designed SRAM.

[0193] In some embodiments, dimension D6 of active region 104P (or nanostructure 108 of pull-up transistors PU- 1 and PU- 2 ) is substantially equal to dimension D1 of narrower portion 104A of active region 104N (or nanostructure 108 of pass-gate transistors PG- 1 and PG- 2 ).

[0194] Fig.14A Some embodiments of the present disclosure are shown Figure 4A Configuration of the backside contact plug 208 on the layout.

[0195] According to some embodiments, source terminals of pull-down transistors PD-1 and PD-2 are electrically connected to a backside VSS power rail through backside contact plugs 208. The backside power rail can reduce the overall resistance of BEOL (back-end of line) metal layers and / or the complexity of substrate frontside metal wiring.

[0196] Figure 14B-14E It is shown that according to some embodiments of the present disclosure, Fig.14A The Y2 - Y2 line corresponds to a cross-sectional view of the semiconductor structure 100_8 in which the SRAM unit is formed at various intermediate stages.

[0197] Fig. 14B The semiconductor structure 100_6 is shown after flipping the semiconductor structure 100_8 according to some embodiments.

[0198] According to some embodiments, the semiconductor structure 100_8 is turned upside down, such as Fig. 14B In some embodiments, a carrier substrate (not shown) may be formed and seal the front side of the semiconductor structure 100_6 before flipping the semiconductor structure 100_8 to protect the components of the semiconductor structure 100 during subsequent backside processes. According to some embodiments, after flipping the semiconductor structure 100_8, the back side of the substrate 102 (the back side of the semiconductor structure 100_8) faces upward.

[0199] Fig. 14C The semiconductor structure 100_8 is shown after a removal process according to some embodiments.

[0200] According to some embodiments, the substrate 102 and the well regions PW and NW are removed from the back side of the semiconductor structure 100_8 using a planarization process such as CMP, an etching process, or a combination thereof, until the isolation structure 110 is exposed. Fig. 14C In some embodiments, the lower fin element 103 may also be thinned during the removal process.

[0201] Fig.14D The semiconductor structure 100_8 is shown after forming a contact opening 206 in accordance with some embodiments.

[0202] According to some embodiments, Fig.14D As shown, the lower fin element 103 is patterned using a photolithography and etching process to form a contact opening 206. According to some embodiments, the patterning process includes forming a mask layer 202 on the back side of the semiconductor structure 100_8. According to some embodiments, the mask layer 202 has an opening 204 corresponding to the source / drain feature 122N of the pull-down transistor PD-1.

[0203] The mask layer 202 may be made of silicon nitride, silicon oxide, carbon-doped silicon dioxide (e.g., SiO2:C), metal oxides (e.g., AlO, TiO, LaO, HfO, etc.), a nitrogen-free anti-reflective layer (NFARL), titanium nitride (TiN), boron nitride (BN), a multilayer thereof, another suitable material, or a combination thereof. For example, the mask layer 202 is deposited on the back side of the semiconductor structure 100_8, and then a photoresist is formed on the material of the mask layer by spin coating, and the photoresist is patterned by exposing the photoresist to light using an appropriate photomask. The exposed or unexposed portions of the photoresist may be removed depending on whether a positive photoresist or a negative photoresist is used. The material of the mask layer 202 may be etched using the patterned photoresist layer to form an opening 204.

[0204] According to some embodiments, the patterning process further includes performing an etching process using the mask layer 202 to remove the lower fin element 103, the semiconductor isolation feature 126, and the dielectric isolation feature 128, thereby forming a contact opening 206 exposing the source / drain feature 122N. The etching process may include dry etching, such as RIE, NBE, ICP etching, CCP etching, another suitable method, or a combination thereof.

[0205] Fig.14E FIG. 1 shows the semiconductor structure 100_8 after forming the backside contact plug 208 according to some embodiments. It should be noted that Fig.14E The semiconductor structure 100 in FIG. 1 is shown with its front side facing upward.

[0206] According to some embodiments, a silicide layer 210 is formed on the backside of the source / drain features 122N exposed from the contact opening 206, such as Fig.14E As shown. In some embodiments, the silicide layer 210 is made of WSi, NiSi, TiSi and / or CoSi. In some embodiments, the formation of the silicide layer 210 includes depositing a metal material and then performing one or more annealing processes. According to some embodiments, the semiconductor material (e.g., Si) from the source / drain feature 122N reacts with the metal material to form the silicide layer 210.

[0207] According to some embodiments, Fig.14EAs shown, a backside contact plug 208 is then formed on the silicide layer 210 in the contact opening 206. According to some embodiments, the contact plug 208 is electrically connected to a backside VSS power supply line formed subsequently. In some embodiments, a dimension D2 of the backside contact plug 208 in the Y direction is larger than a dimension D1 of the lower fin element 103 located directly below the pass gate transistor PG-1 (i.e., the narrower portion 104A of the active region 104N).

[0208] According to some embodiments, the formation of contact plug 208 includes depositing one or more conductive materials to make contact plug 208 overfill contact opening 206. In some embodiments, CVD, PVD, electron beam evaporation, ALD, ECP, ELD, another suitable method, or a combination thereof are used to deposit the one or more conductive materials to overfill contact opening 206. The one or more conductive materials are planarized using, for example, CMP until mask layer 202 is exposed.

[0209] The contact plug 208 may have a multi-layer structure. For example, a barrier / adhesion layer (not shown) may be optionally deposited along the sidewalls and bottom surface of the contact opening 206. The barrier layer may be made of Ta, TaN, Ti, TiN, CoW, another suitable material, or a combination thereof. A bulk metal layer is then deposited on the barrier / adhesion layer (if formed) to fill the remaining portion of the contact opening 206. In some embodiments, the bulk metal layer is made of one or more conductive materials, such as Co, Ni, W, Ti, Ta, Cu, Rh, Ir, Pt, Al, Ru, Mo, or a combination thereof.

[0210] The semiconductor structure 100_8 may undergo further backside BEOL processes to form various interconnected conductive features (not shown) on the backside of the semiconductor structure 100 , such as a backside metal layer, vias between two adjacent metal layers, a passivation layer, bump pads, etc.

[0211] Fig.15A Some embodiments of the present disclosure are shown Fig.13A Configuration of the backside contact plug 208 on the layout. Fig. 15B is corresponding to Fig.15A 1 is a cross-sectional view of the semiconductor structure 100_9 of the SRAM cell taken along line Y2-Y2.

[0212] In some embodiments, semiconductor structure 100_9 may be used for SRAM with high density design. According to some embodiments, source terminals of pull-down transistor PD-1 and pull-down transistor PD-2 are electrically connected to the backside VSS power rail through backside contact plug 208, such as Fig.15A According to some embodiments, the material and formation of the backside contact plug 208 are similar to those described above. Figure 14B-14EThe material or formation of the backside contact plug 208 described in hereinafter may be the same or similar.

[0213] Compared with SRAMs with high current designs, the active area of ​​SRAMs with high density designs is relatively narrow, so the process of forming backside contact plugs is more difficult. In the embodiment of the present disclosure, the active area 104N includes a wider portion 104B on which the pull-down transistor is formed, which can reduce the process difficulty of forming the backside contact plug electrically connected to the VSS power rail.

[0214] According to some embodiments, the lower fin elements 103 of the active regions 104N and 104P may have Fig.15A The active regions 104P and 104N of the illustrated layout have substantially the same profile. In some other embodiments, the lower fin element 103 of the active region 104P may have the above-mentioned smooth step.

[0215] Fig.16A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP. Figure 16B-1 and Figure 16B-2 is with Fig.16A A cross-sectional view of the semiconductor structure 100_10 of the SRAM cell corresponding to the line Y1 -Y1 and the line Y2 -Y2 . Figure 16B-3 is with Figure 16B-1 The plane diagram corresponding to plane BB.

[0216] In some embodiments, Fig.16A The SRAM has a high current design. According to some embodiments, as Fig.16A As shown, each active region 104N is a semiconductor strip without a step. In some embodiments, the active region 104N has a dimension D1 in the Y direction. According to some embodiments, each active region 104P is a semiconductor strip with a protruding portion 104R, such as Fig.16A According to some embodiments, the protruding portion 104R extends toward the adjacent active region 104P in the Y direction by a distance D9. That is, according to some embodiments, Fig.16A As shown, each active region 104P includes a narrower first portion 104C and a wider second portion 104D. According to some embodiments, the first portion 104C is a dummy region on which no functional transistor is formed, and the pull-up transistors PU-1 and PU-2 are formed on the wider second portion 104D. In some embodiments, the first portion 104C has a dimension D6 in the Y direction. In some embodiments, the dimension D6' of the second portion 104D is greater than the dimension D6 and less than the dimension D1.

[0217] According to some embodiments of the present disclosure, by forming the active region 104P with a step, the pull-down transistors PD-1 and PD-2 can have a wider channel width (e.g., dimension D6') without increasing the cell height of the SRAM cell. Therefore, the "alpha ratio" of the saturation current, i.e., the ratio of the Idsat of the pull-up transistor to the Idsat of the pass-gate transistor, may be increased, which may improve the cell performance of the resulting SRAM cell, such as a higher operating voltage (e.g., Vmax and / or Vmin), a higher cell current, a wider read margin metric, and / or a faster operating speed.

[0218] In some embodiments, the distance D9 is in a range of about 2 nm to about 30 nm. The ratio of the distance D9 to the gate length is in a range of about 2 to about 5. The dimension D6 is in a range of about 6 nm to about 35 nm. The ratio of the dimension D6 to the gate length is in a range of about 0.6 to about 2. In some embodiments, the dimension D6' is in a range of about 6 nm to about 35 nm. The ratio of the dimension D6' to the gate length is in a range of about 0.6 to about 2.

[0219] In some embodiments, the ratio of dimension D6' to dimension D6 (D6' / D6) is in the range of about 1.02 to about 2. If the ratio is too small (e.g., less than 1.02), the α ratio may increase too little, and the cell performance of the resulting SRAM may not be significantly improved. If the ratio is too large (e.g., greater than 2), the step transition may be too long, so that the active area may have an undesirable profile.

[0220] Fig.17A Some embodiments of the present disclosure are shown Figure 2 Layout of the SRAM group GP. Figure 17B-1 and Figure 17B-2 is with Fig.17A A cross-sectional view of the semiconductor structure 100_11 of the SRAM cell corresponding to the line Y1 -Y1 and the line Y2 -Y2 . Figure 17B-3 is with Figure 17B-1 In addition to the semiconductor structure 100_11 being applicable to a SRAM having a high-density design, Figure 17A to Figure 17B-3 An embodiment similar to Figure 16A to Figure 16B-3 Implementation example.

[0221] In some embodiments, dimension D6 of first portion 104C of active region 104P is substantially equal to dimension D1 of narrower portion 104A of active region 104N (or nanostructures 108 of pass-gate transistors PG-1 and PG-2 and pull-down transistors PD-1 and PD-2). In some embodiments, dimension D6' of second portion 104D of active region 104P (or nanostructures 108 of pull-up transistors PU-1 and PU-2) is greater than dimension D1.

[0222] Fig.18A Some embodiments of the present disclosure are shown Fig.17A Configuration of the backside contact plug 208 on the layout. Fig.18B is corresponding to Fig.18A 1 is a cross-sectional view of the semiconductor structure 100_12 of the SRAM cell taken along line Y2-Y2.

[0223] In some embodiments, the semiconductor structure 100_12 may be used for a SRAM having a high density design. Fig.18A As shown, the source terminals of the pull-up transistors PU-1 and PU-2 are electrically connected to the backside VDD power rail through the backside contact plugs 208. According to some embodiments, the material and formation of the backside contact plugs 208 are similar to those described above. Figure 14B-14E The materials and formation of the backside contact plug 208 are described in .

[0224] Compared with SRAM with high current design, the active area of ​​SRAM with high density design is relatively narrow, so the process of forming backside contact plug is more difficult. In the embodiment of the present disclosure, the active area 104P includes a wider second portion 104D forming a pull-up transistor, which can reduce the process difficulty of forming a backside contact plug electrically connected to the VDD power rail.

[0225] As described above, aspects of the present disclosure relate to semiconductor structures for forming SRAM devices including nanostructured transistors. The active region 104N may have a step, so that independent adjustment of the performance of the pull-down transistor PD-1 / PD-2 and the pass-gate transistor PG-1 / PG-2 may be achieved. Because the channel width of the pull-down transistor PD-1 / PD-2 is greater than the channel width of the pass-gate transistor PG-1 / PG-2, the beta ratio of the saturation current may be increased, which may improve the cell performance of the resulting SRAM cell, such as a higher operating voltage (e.g., Vmax), a higher cell current, a wider read margin metric, and / or a faster operating speed.

[0226] Embodiments of semiconductor structures and methods of forming the same may be provided. The method of forming the semiconductor structure may include forming an active region. A first portion of the active region may be wider than a second portion of the active region. As a result, a pull-down transistor formed on the first portion of the active region may have a stronger performance than a transfer gate transistor formed on the second portion of the active region. Therefore, the cell performance of the resulting SRAM cell may be improved.

[0227] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first active region in which a first semiconductor layer and a second semiconductor layer are alternately stacked above a first lower fin element. In a plan view, the first active region includes a first portion and a second portion narrower than the first portion. The method also includes removing the first semiconductor layer of the first active region. The second semiconductor layer of the first portion of the first active region forms a plurality of first nanostructures, and the second semiconductor layer of the second portion of the first active region forms a plurality of second nanostructures. The method also includes forming a first gate stack surrounding the first nanostructure, and forming a second gate stack surrounding the second nanostructure.

[0228] In some embodiments, the first gate stack surrounds the plurality of first nanostructures to form a pull-down transistor of the SRAM cell, and the first gate stack surrounds the plurality of second nanostructures to form a pass-gate transistor of the SRAM cell.

[0229] In some embodiments, the method also includes: forming a second active region in which the first semiconductor layer and the second semiconductor layer are alternately stacked above the second lower fin element; removing the first semiconductor layer of the second active region to form a plurality of third nanostructures and a plurality of fourth nanostructures; forming a first gate stack to surround the plurality of third nanostructures; and forming a second gate stack to surround the plurality of second nanostructures, wherein a first distance between the plurality of first nanostructures and the plurality of third nanostructures is substantially equal to a second distance between the plurality of second nanostructures and the plurality of fourth nanostructures.

[0230] In some embodiments, in a plan view, a first portion of the first active region has a first sidewall extending along a first horizontal direction, a second portion of the second active region has a second sidewall extending along the first horizontal direction, and the first sidewall is connected to the second sidewall by a connecting wall.

[0231] In some embodiments, the connecting wall extends in a second horizontal direction perpendicular to the first horizontal direction.

[0232] In some embodiments, the connecting wall is curved or a straight line extending in a direction inclined to the first horizontal direction.

[0233] In some embodiments, the connecting wall overlaps the first gate stack or the second gate stack.

[0234] In some embodiments, the method further includes forming a source / drain feature on the first lower fin element to abut both the plurality of first nanostructures and the plurality of second nanostructures.

[0235] In some embodiments, the method further includes: patterning the first lower fin element to form an opening exposing a bottom of the source / drain feature; and forming a contact plug in the opening.

[0236] In some embodiments, a method for forming a semiconductor structure is provided. The method includes alternately stacking a sacrificial layer and a channel layer above a substrate, and patterning the sacrificial layer, the channel layer, and the substrate to form a first fin structure in a p-type well of the substrate and a second fin structure in an n-type well of the substrate. The first fin structure includes a strip portion and a first protruding portion extending toward the second fin structure. The method also includes forming a dummy gate structure across the first fin structure and the second fin structure. The dummy gate structure overlaps the first protruding portion of the first fin structure.

[0237] In some embodiments, the protruding portion of the first active region extends a distance toward the second fin structure in a first direction parallel to a longitudinal axis of the first dummy gate structure.

[0238] In some embodiments, the stripe portion of the first active region has a first size in the first direction, and the second fin structure has a second size in the first direction, and the second size is substantially equal to the first size.

[0239] In some embodiments, the sacrificial layer, the channel layer, and the substrate are patterned to form a third fin structure in a p-type well of the substrate, and the first fin structure includes a second protruding portion extending toward the third fin structure.

[0240] In some embodiments, patterning the sacrificial layer, the channel layer, and the substrate includes: etching the sacrificial layer, the channel layer, and the substrate in a first etching process to form a first semiconductor strip and a second semiconductor strip; and etching the first semiconductor strip and the second semiconductor strip in a second etching process after the first etching process, wherein the first semiconductor strip is partially cut to form a first fin structure, and the second semiconductor strip is partially removed to form a second fin structure.

[0241] In some embodiments, the method further includes: removing the dummy gate structure; removing the sacrificial layers of the first fin structure and the second fin structure; and forming a gate stack surrounding the channel layer of the first fin structure and the second fin structure.

[0242] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first pull-down transistor of a first static random access memory cell and a transmission gate transistor of the first static random access memory cell. The first pull-down transistor includes a plurality of first nanostructures and a first gate stack surrounding the first nanostructure and extending along a first direction. The transmission gate transistor includes a plurality of second nanostructures and a second gate stack surrounding the plurality of second nanostructures and extending along the first direction. The plurality of first nanostructures have a first size in the first direction, the plurality of second nanostructures have a second size in the second direction, and the first size is greater than the second size.

[0243] In some embodiments, the first pull-down transistor and the pass-gate transistor share source / drain features.

[0244] In some embodiments, the semiconductor structure further includes: a pull-up transistor of the first static random access memory cell, wherein the pull-up transistor includes: a plurality of third nanostructures; and a first gate stack surrounding the plurality of third nanostructures; and a fin element located below the plurality of third nanostructures, wherein, in a plan view, the fin element is a strip extending along a second direction, the strip having a step overlapping the plurality of third nanostructures, the step having a recess on a first side facing the plurality of first nanostructures, and the step having a protrusion on a second side opposite to the first side.

[0245] In some embodiments, the semiconductor structure further includes: a fin element located below the plurality of first nanostructures and the plurality of second nanostructures, wherein the fin element is a strip extending along the second direction, the strip has a step overlapping the plurality of first nanostructures, and the step has two protrusions on opposite sides.

[0246] In some embodiments, the semiconductor structure further includes: a second pull-down transistor of a second static random access memory cell, wherein the second pull-down transistor includes: a plurality of third nanostructures; and a third gate stack surrounding the plurality of third nanostructures and extending along the first direction, wherein the first pull-down transistor and the second pull-down transistor share a source / drain component; a first contact plug located on a backside surface of the source / drain component; and a second contact plug located on a frontside surface of the source / drain component.

[0247] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first active region in which a first semiconductor layer and a second semiconductor layer are alternately stacked above a first lower fin element, wherein, in a plan view, the active region includes a first portion and a second portion narrower than the first portion; removing the first semiconductor layer of the first active region, wherein the second semiconductor layer of the first portion of the first active region forms a plurality of first nanostructures, and the second semiconductor layer of the second portion of the first active region forms a plurality of second nanostructures; forming a first gate stack to surround the plurality of first nanostructures; and A second gate stack is formed to surround the plurality of second nanostructures.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first gate stack surrounds the plurality of first nanostructures to form a pull-down transistor of a static random access memory cell, and the second gate stack surrounds the plurality of second nanostructures to form a pass-gate transistor of the static random access memory cell.

3. The method for forming a semiconductor structure according to claim 1, further comprising: forming a second active region in which the first semiconductor layer and the second semiconductor layer are alternately stacked above a second lower fin element; removing the first semiconductor layer of the second active region to form a plurality of third nanostructures and a plurality of fourth nanostructures; forming the first gate stack to surround the plurality of third nanostructures; as well as forming the second gate stack to surround the plurality of fourth nanostructures, Wherein, a first distance between the plurality of first nanostructures and the plurality of third nanostructures is substantially equal to a second distance between the plurality of second nanostructures and the plurality of fourth nanostructures.

4. The method for forming a semiconductor structure according to claim 1, wherein: In a plan view, the first portion of the first active region has a first sidewall extending along a first horizontal direction, the second portion of the second active region has a second sidewall extending along the first horizontal direction, and the first sidewall is connected to the second sidewall through a connecting wall.

5. The method for forming a semiconductor structure according to claim 1, further comprising: A source / drain feature is formed on the first lower fin element to abut both the plurality of first nanostructures and the plurality of second nanostructures.

6. The method for forming a semiconductor structure according to claim 5, further comprising: patterning the first lower fin element to form an opening exposing a bottom of the source / drain feature; as well as A contact plug is formed in the opening.

7. A method of forming a semiconductor structure, comprising: alternately stacking sacrificial layers and channel layers over the substrate; Patterning the sacrificial layer, the channel layer, and the substrate to form a first fin structure in a p-type well of the substrate and a second fin structure in an n-type well of the substrate, wherein the first fin structure includes a strip portion and a first protruding portion extending toward the second fin structure; and A dummy gate structure is formed across the first fin structure and the second fin structure, wherein the dummy gate structure overlaps the first protruding portion of the first fin structure.

8. The method for forming a semiconductor structure according to claim 7, wherein: The first protruding portion of the first active region extends a distance toward the second fin structure in a first direction parallel to a longitudinal axis of the first dummy gate structure.

9. The method for forming a semiconductor structure according to claim 7, wherein: The sacrificial layer, the channel layer, and the substrate are patterned to form a third fin structure in the p-type well of the substrate, and the first fin structure includes a second protruding portion extending toward the third fin structure.

10. A semiconductor structure comprising: A first pull-down transistor of a first static random access memory cell, wherein the first pull-down transistor comprises: a plurality of first nanostructures; and A first gate stack surrounding the plurality of first nanostructures and extending along a first direction; and The transmission gate transistor of the first static random access memory cell, wherein the transmission gate transistor comprises: a plurality of second nanostructures; and a second gate stack surrounding the plurality of second nanostructures and extending along the first direction, The plurality of first nanostructures have a first size in the first direction, the plurality of second nanostructures have a second size in the first direction, and the first size is greater than the second size.

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