A method for manufacturing a three-dimensional memory and the three-dimensional memory itself.

Abstract

This invention discloses a method for manufacturing a three-dimensional memory and the three-dimensional memory itself, relating to the field of semiconductor manufacturing technology, to solve the problem of high thermal budget in existing technologies for forming single-crystal semiconductor channels. The method for manufacturing the three-dimensional memory includes: providing a substrate, the substrate comprising a substrate, a stacked structure, a semiconductor active layer, and an inter-electrode dielectric layer; a through-hole is provided within the stacked structure, and the semiconductor active layer fills the bottom of the through-hole; a cylindrical induction structure and a semiconductor structure are formed on the sidewalls of the through-hole; the induction structure and the semiconductor structure are sequentially disposed on the semiconductor active layer along the thickness direction of the substrate; a second type of dielectric isolation layer is filled within the through-hole; the semiconductor structure and the induction structure are subjected to induced annealing to crystallize and modify the semiconductor structure into a single-crystal semiconductor layer; after induced annealing, the induction structure is located on top of the single-crystal semiconductor layer. The method for manufacturing a three-dimensional memory provided by this invention is used to form a single-crystal semiconductor channel with a lower thermal budget.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a three-dimensional memory and the three-dimensional memory itself. Background Technology

[0002] With technological advancements, traditional two-dimensional (2D) memories cannot meet the demands for storage speed and density, leading to the design and development of 3D memories. To improve density and speed, 3D memories require an increased number of stacked storage cells, resulting in longer vertical channels, increased resistance, and decreased current. Furthermore, the high resistance of vertical semiconductor channels in traditional non-single-crystal phases further reduces the conduction current, and the grain boundaries cause random telegraph noise fluctuations and decreased carrier mobility, leading to read or write errors. While error-correcting algorithms can mitigate the impact of errors, the large area occupied by error-correcting circuits reduces the storage density of 3D memories. Therefore, 3D memories with single-crystal semiconductor channels have become the inevitable choice.

[0003] However, in existing technologies, converting a non-single-crystal semiconductor channel into a single-crystal semiconductor channel typically involves heating and melting the non-single-crystal semiconductor channel, then cooling it to form a single-crystal semiconductor channel. This method places high demands on the thermal budget of the entire 3D memory. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a three-dimensional memory and a three-dimensional memory, which provides a method for manufacturing a single-crystal semiconductor channel in a three-dimensional memory with a lower thermal budget.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for manufacturing a three-dimensional memory. This method includes: providing a substrate, the substrate comprising a substrate, a stacked structure, a semiconductor active layer, and an inter-electrode dielectric layer. The stacked structure is disposed on the substrate. The stacked structure includes a first-type dielectric isolation layer and a sacrificial layer sequentially layered along the thickness direction of the substrate. In the stacked structure, the bottom and top layers are both first-type dielectric isolation layers. A through-hole is provided within the stacked structure, and the semiconductor active layer fills the bottom of the through-hole. The inter-electrode dielectric layer is disposed on the semiconductor active layer and covers the sidewall surface of the through-hole.

[0006] Next, a cylindrical induction structure and a semiconductor structure are formed on the sidewalls of the via. The induction structure and the semiconductor structure are sequentially disposed on the semiconductor active layer along the thickness direction of the substrate. The projection of the semiconductor structure onto the semiconductor active layer overlaps the projection of the induction structure onto the semiconductor active layer. The material of the induction structure is a compound of semiconductor and metal in the semiconductor active layer. The crystal phase of the semiconductor structure is a non-single-crystal phase.

[0007] Next, a second type of dielectric isolation layer is filled into the through hole, with the end of the second type of dielectric isolation layer away from the bottom of the through hole flush with the stacked structure.

[0008] Next, the semiconductor structure and the induced structure are subjected to induced annealing to crystallize and modify the semiconductor structure into a single-crystal semiconductor layer. After induced annealing, the induced structure is located on top of the single-crystal semiconductor layer.

[0009] In the above-described scheme, the manufacturing method provided by this invention includes at least two first-type dielectric isolation layers and at least one sacrificial layer. A cylindrical induction structure and a semiconductor structure are sequentially formed on the sidewalls of the vias along the thickness direction of the substrate, with the top of the semiconductor structure flush with the top of the inter-electrode dielectric layer. The induction structure can induce crystallization and modification of non-single-crystal semiconductor structures into single-crystal semiconductor layers during induced annealing, i.e., forming single-crystal channels on the sidewalls of the vias. Furthermore, after induced annealing, the cylindrical induction structure is located on top of the cylindrical single-crystal semiconductor layer, and the cylindrical single-crystal semiconductor layer is located on the cylindrical active semiconductor layer; their positions are interchanged. This means the induction structure crystallizes and modifies all non-single-crystal semiconductor structures. This crystallization modification is complete and sufficient, leaving no residual polycrystalline components, allowing the three-dimensional memory manufactured using the method provided by this invention to possess all the advantages of using single-crystal channels. Furthermore, under the induced catalysis of the induced structure, it is beneficial to reduce the crystallization modification temperature and shorten the crystallization modification time. The thermal budget of the present invention is greatly reduced compared with the scheme of heating and melting the channel and then cooling it to crystallize and modify the polycrystalline channel into a single crystal channel used in the prior art. The impact on the structure of the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided by the present invention is small, and the three-dimensional memory manufactured by the present invention can have better performance.

[0010] Furthermore, the projection of the semiconductor structure onto the active semiconductor layer overlaps the projection of the induced structure onto the active semiconductor layer. In other words, the ring width of the semiconductor structure along the cross-section parallel to the substrate direction is greater than or equal to the ring width of the induced structure along the cross-section parallel to the substrate direction. This ensures that no induced structure remains under the single-crystal semiconductor layer and / or between the single-crystal semiconductor layer and the second-type dielectric isolation layer after induced annealing. The induced structure is located at the top of the single-crystal semiconductor layer, i.e., the top of the via, and is no longer enclosed by the structure of the three-dimensional memory.

[0011] As one possible implementation, the annealing temperature for induced annealing is greater than or equal to 450°C and less than or equal to 600°C. This setting, where the semiconductor structure and the induced structure are induced annealed at this temperature, avoids excessive internal stress accumulation, warping, or cracking in the three-dimensional memory manufactured according to this invention due to excessively high annealing temperatures, resulting in low thermal budget requirements.

[0012] As one possible implementation, the annealing time for induced annealing is greater than or equal to 0.5 hours and less than or equal to 30 hours. In this case, performing induced annealing on the semiconductor structure and the induced structure within this time range can avoid incomplete crystallization modification of the semiconductor structure due to excessively short annealing time, and also avoid excessive internal stress accumulation, warping, or cracking of the three-dimensional memory manufactured according to this invention due to excessively long annealing time, thereby ensuring good performance and high yield of the three-dimensional memory.

[0013] As one possible implementation, the annealing temperature for induced annealing is greater than or equal to 900°C and less than or equal to 1200°C, and the annealing time for induced annealing is greater than or equal to 2s and less than or equal to 20s. In this case, induced annealing of the semiconductor structure and the induced structure at a higher temperature and for a shorter time achieves induced crystallization modification of the semiconductor structure, resulting in a lower thermal budget while ensuring sufficient crystallization modification of the semiconductor structure into a single-crystal semiconductor layer.

[0014] As one possible implementation, forming a cylindrical induction structure and a semiconductor structure on the sidewall of a via includes: First, forming an induction metal layer on the stacked structure, on the sidewall of the via, and at the bottom of the via. Next, removing the induction metal layer on the stacked structure and the induction metal layer at the bottom of the via, retaining the induction metal layer on the sidewall of the via. Next, performing reactive annealing on the remaining induction metal layer and the semiconductor active layer, converting the portion of the remaining induction metal layer in contact with the semiconductor active layer into an induction structure. Next, removing the induction metal layer that has not been converted into an induction structure. Next, forming a semiconductor structure on the stacked structure, on the sidewall of the via, and at the bottom of the via. Next, removing the semiconductor structure on the stacked structure and the semiconductor structure at the bottom of the via, retaining the semiconductor structure on the sidewall of the via. In this case, forming a cylindrical induction structure first, and then forming a cylindrical semiconductor structure, eliminates the need to etch the induction structure, which is a compound of semiconductor and metal, thus avoiding the need to etch difficult-to-etch semiconductor and metal compounds, thereby increasing the manufacturing speed and yield of the manufacturing method provided by the present invention.

[0015] As one possible implementation, forming a cylindrical induction structure and a semiconductor structure on the sidewall of a via includes: First, forming an induction metal layer on the stacked structure, on the sidewall of the via, and at the bottom of the via. Next, performing reactive annealing on the induction metal layer and the active semiconductor layer, converting the portion of the induction metal layer in contact with the active semiconductor layer into an induction structure. Next, removing the induction metal layer that has not been converted into an induction structure. Next, forming a semiconductor structure on the stacked structure, on the sidewall of the via, and at the bottom of the via. Next, removing the semiconductor structure located on the stacked structure and the semiconductor structure located at the bottom of the via, retaining only the semiconductor structure located on the sidewall of the via; removing the induction metal layer located at the bottom of the via, retaining the induction metal layer located on the sidewall of the via. In this case, a sheet-like induction structure is first formed on the active semiconductor layer at the bottom of the via, followed by the formation of the semiconductor structure, and then the induction structure and the semiconductor structure are patterned. The two patterning processes can share a single mask, which can reduce the cost of the manufacturing method provided by this invention.

[0016] As one possible implementation, the reaction annealing temperature is greater than or equal to 180°C and less than or equal to 300°C. Under these conditions, reaction annealing of the inducing metal layer within this temperature range ensures effective reaction between the inducing metal layer and the semiconductor active layer, forming a semiconductor-metal compound. This avoids the situation where the inducing metal layer and the semiconductor active layer cannot react effectively due to excessively low temperatures, thus guaranteeing the effectiveness of subsequent induced crystallization modification. It also prevents excessively high temperatures from affecting other structures, which could lead to stress accumulation and potential damage.

[0017] As one possible implementation, the annealing time for reactive annealing is greater than or equal to 15s and less than or equal to 300s.

[0018] This setup, allowing for reactive annealing of the induced metal layer within this timeframe, ensures effective reaction between the induced metal layer and the semiconductor active layer, forming a semiconductor-metal compound. It avoids situations where the reaction time is too short, preventing the non-induced metal layer from reacting effectively with the semiconductor active layer, thus guaranteeing the effectiveness of subsequent induced crystallization modification. It also prevents excessively long reaction times from increasing the thermal budget and affecting other structures.

[0019] As one possible implementation, the thickness of the induced metal layer is greater than or equal to 0.5 nm and less than or equal to 30 nm. In this case, problems such as ineffective reaction between the induced metal layer and the semiconductor active layer due to excessively thin induced metal layer thickness, uneven height of the formed induced structure along the thickness direction of the stacked structure and along the direction perpendicular to the thickness direction of the stacked structure, and excessively low height of the formed induced structure along the thickness direction of the stacked structure and along the direction perpendicular to the thickness direction of the stacked structure can be avoided, ensuring effective subsequent induced annealing. It also avoids excessively thick induced metal layers, which would lead to excessively high material and time costs in forming the induced metal layer, thus helping to control costs and improve yield. Furthermore, excessively thick induced metal layers may crack due to stress, damaging the 3D memory; a thickness within the aforementioned range can also improve yield and reduce costs.

[0020] As one possible implementation, either wet etching or dry etching is used to remove the inducing metal layer that has not been converted into an induced structure. In this case, wet etching, with its lower temperature, allows for selective removal, effectively removing the necessary portions while preventing the increased thermal budget of the process caused by the high temperature of dry etching. Dry etching allows for more precise removal of the inducing metal layer that has not been converted into an induced structure, and it has less impact on other structures of the three-dimensional memory manufactured according to this invention, thus ensuring the performance of the three-dimensional memory manufactured according to this invention.

[0021] As one possible implementation, the material for the inducing metal layer includes at least one of nickel, palladium, aluminum, copper, iron, or tungsten. In this case, the aforementioned materials and semiconductor structures can all form an induced structure after reactive annealing, effectively inducing the crystallization of the semiconductor structure into a single-crystal semiconductor layer. Furthermore, in the manufacturing method of the three-dimensional memory provided by this invention, different materials for the inducing metal layer can be selected based on the material of the semiconductor structure, the width and depth of the vias, and the thermal budget, to achieve the optimal effect under each condition.

[0022] As one possible implementation, the height of the induced structure along the thickness direction of the stacked structure is greater than or equal to 0.5 nm and less than or equal to 30 nm. In this case, it ensures that the induced structure has a suitable height, enabling it to effectively induce annealing and crystallize the semiconductor structure into a single-crystal semiconductor layer, avoiding the ineffectiveness due to insufficient height. It also prevents the induced structure from being too tall, which could lead to difficulty in complete removal and leave large gaps on the inner walls of vias after removal, thus affecting the performance of the topmost three-dimensional memory cell.

[0023] As one possible implementation, after performing induced annealing on the semiconductor structure and the induced structure, the manufacturing method of the three-dimensional memory provided by the present invention further includes: removing the induced structure. Removing the induced structure can avoid adverse effects on the yield and performance of the three-dimensional memory formed by subsequent processing, and the single-crystal channel without induced metal contamination can improve the working performance of the three-dimensional memory manufactured using the manufacturing method of the three-dimensional memory provided by the present invention.

[0024] Secondly, the present invention also provides a three-dimensional memory. This three-dimensional memory is manufactured using the manufacturing method of the three-dimensional memory provided in the first aspect.

[0025] The beneficial effects of the second aspect and its various embodiments in this invention can be referred to the analysis of the beneficial effects of the three-dimensional memory manufactured by the first aspect and its various embodiments described above, and will not be repeated here. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0027] Figure 1 A flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;

[0028] Figure 2 A flowchart illustrating one embodiment of the manufacturing method for a three-dimensional memory provided in this invention, which involves forming a cylindrical induction structure and a semiconductor structure on the sidewall of a through-hole;

[0029] Figure 3 A flowchart illustrating another embodiment of the manufacturing method for a three-dimensional memory provided in this invention, which involves forming a cylindrical induction structure and a semiconductor structure on the sidewall of a through-hole;

[0030] Figure 4 This is a schematic diagram of a stacked structure formed on a substrate in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram illustrating the formation of at least a through-hole penetrating the stacked structure within the stacked structure in an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of forming a semiconductor active layer at the bottom of a via in an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of an inter-electrode dielectric layer forming on the semiconductor active layer to cover the sidewalls of vias, as described in an embodiment of the present invention.

[0034] Figure 8This is a schematic diagram of a cylindrical induction structure and a semiconductor structure formed on the sidewall of a through hole in an embodiment of the present invention;

[0035] Figure 9 This is a schematic diagram of filling the through-hole with a second type of dielectric isolation layer in an embodiment of the present invention;

[0036] Figure 10 This is a schematic diagram illustrating the induced annealing process performed on the semiconductor structure and the induced structure in an embodiment of the present invention;

[0037] Figure 11 This is a schematic diagram illustrating the removal of the induced structure in an embodiment of the present invention;

[0038] Figures 12 to 17 A schematic diagram of a first embodiment of the manufacturing method of a three-dimensional memory provided in this invention, illustrating the formation of a cylindrical induction structure and a semiconductor structure on the sidewall of a through-hole;

[0039] Figures 18 to 22 A schematic diagram of a second embodiment of the manufacturing method for a three-dimensional memory provided in this invention, illustrating the formation of a cylindrical induction structure and a semiconductor structure on the sidewall of a via.

[0040] Figure 23 This is a schematic diagram of the formation of a second type of dielectric isolation layer in the through-hole and on the stacked structure in an embodiment of the present invention;

[0041] Figure label:

[0042] 100 - Substrate, 200 - Stacked structure

[0043] 201 - Type I dielectric isolation layer; 202 - Sacrificial layer.

[0044] 300 - Through-hole, 301 - Semiconductor active layer

[0045] 302 - Inter-electrode dielectric layer, 410 - Inducing metal layer,

[0046] 420 - Induced structure, 510 - Semiconductor structure

[0047] 520 - Single crystal semiconductor layer, 600 - Type II dielectric isolation layer. Detailed Implementation

[0048] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0049] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0050] Furthermore, the terms "first type" and "second type" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first type" or "second type" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0051] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0052] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0053] With the development of technology, traditional two-dimensional (2D) memories can no longer meet the ever-increasing demands for storage speed and density. Therefore, 3D memories, which vertically "stack" traditional 2D memories, have been designed and developed. As the total number of word lines in a 3D memory device increases, i.e., the number of stacked layers increases, the vertical channels in the stacked structure become longer, thus increasing the resistance of the vertical channels and reducing the channel current. Furthermore, the high resistance of traditional non-single-crystal semiconductor channels further reduces the conduction current. In addition, the grain-to-grain boundaries in non-single-crystal semiconductor channels act as charge trapping sites, leading to additional random telegraph noise fluctuations and a decrease in carrier mobility. This random instability can cause significant read / write errors. One known technique for partially mitigating the impact of read / write errors is the use of error-correcting codes (ECC). However, the circuitry required to execute ECC occupies a relatively large chip area, thus offsetting the benefits gained from using 3D memories. Therefore, using single-crystal channels with lower resistance becomes the inevitable choice.

[0054] In existing technologies, converting a non-single-crystal semiconductor channel into a single-crystal semiconductor channel typically involves heating and melting the non-single-crystal semiconductor channel, then cooling it to form a single-crystal semiconductor channel. This method places high demands on the thermal budget of the entire 3D memory. Furthermore, uneven heating can easily leave non-single-crystal phase components in the channel, which will still increase the channel resistance, reduce the channel conduction current, and cause random instability.

[0055] To solve the above problems, firstly, please refer to... Figure 1 This invention provides a method for manufacturing a three-dimensional memory, which includes: First, please refer to... Figure 7 A substrate is provided, comprising a substrate 100, a stacked structure 200, a semiconductor active layer 301, and an inter-electrode dielectric layer 302. The stacked structure 200 is disposed on the substrate 100. The stacked structure 200 includes a first-type dielectric isolation layer 201 and a sacrificial layer 202 sequentially layered along the thickness direction of the substrate 100. In the stacked structure 200, the bottom and top layers are both first-type dielectric isolation layers 201; a through-hole 300 is provided in the stacked structure 200, and the semiconductor active layer 301 fills the bottom of the through-hole 300. The inter-electrode dielectric layer 302 is disposed on the semiconductor active layer 301 and covers the sidewall surface of the through-hole 300.

[0056] Next, please refer to Figure 8A cylindrical induced structure 420 and a non-single-crystal semiconductor structure 510 are formed on the sidewall of the via 300. The induced structure 420 and the semiconductor structure 510 are sequentially disposed on the semiconductor active layer 301 along the thickness direction of the substrate. The projection of the semiconductor structure 510 onto the semiconductor active layer 301 overlaps the projection of the induced structure 420 onto the semiconductor active layer 301. The material of the induced structure is a compound of semiconductor and metal in the semiconductor active layer. The crystal phase of the semiconductor structure is a non-single-crystal phase.

[0057] Next, please refer to Figure 9 A second type of dielectric isolation layer 600 is filled in the through hole 300, and one end of the second type of dielectric isolation layer 600 away from the bottom of the through hole 300 is flush with the stacked structure 200.

[0058] Next, please refer to Figure 10 The semiconductor structure 510 and the induced structure 420 are subjected to induced annealing to crystallize and modify the semiconductor structure 510 into a single-crystal semiconductor layer 520. After induced annealing, the induced structure 420 is located on top of the single-crystal semiconductor layer 520.

[0059] In the manufacturing method provided by the embodiments of the present invention, the stacked structure includes at least two first-type dielectric isolation layers and at least one sacrificial layer. A cylindrical induction structure 420 and a semiconductor structure 510 are sequentially formed on the sidewall of the via 300 of the stacked structure 200 along the thickness direction of the substrate. The top of the semiconductor structure 510 is flush with the top of the inter-electrode dielectric layer 302. The induction structure 420 can crystallize and modify the non-single-crystal semiconductor structure 510 into a single-crystal semiconductor layer 520, that is, to form a single-crystal channel on the sidewall of the via 300. Specifically, when the semiconductor structure 510 and the induction structure 420 are subjected to induced annealing, the induction structure 420 will crystallize and modify the non-single-crystal semiconductor structure 510 into a single-crystal semiconductor layer 520, thereby realizing the preparation of a single-crystal channel. Furthermore, after induced annealing, the cylindrical induced structure 420 is located on top of the cylindrical single-crystal semiconductor layer 520, and the cylindrical single-crystal semiconductor layer 520 is located on the cylindrical active semiconductor layer 301. Their positions have been exchanged. That is, the induced structure 420 has performed crystallization modification on all non-single-crystal semiconductor structures 510. This crystallization modification is complete and sufficient, leaving no residual polycrystalline components. This allows the three-dimensional memory manufactured using the method provided in this embodiment to possess all the advantages of using a single-crystal channel. Compared to the prior art, which uses a method of heating and cooling a non-single-crystal channel to form a single-crystal channel, converting the non-single-crystal channel into a single-crystal channel, this method is prone to leaving non-single-crystal components in the channel due to uneven heating, resulting in more stable operation. Furthermore, the induced annealing process involves lower temperatures and shorter times, significantly reducing the thermal budget compared to existing methods that involve heating and melting the channel before cooling to crystallize and modify a polycrystalline channel into a single-crystal channel. This minimizes the impact on the structure of the three-dimensional memory manufactured using the method described in this embodiment, resulting in better performance. Additionally, the projection of the semiconductor structure 510 onto the active semiconductor layer 301 covers the projection of the induced structure 420 onto the active semiconductor layer 301. Specifically, the circumferential width of the semiconductor structure 510 along the direction parallel to the substrate 100 is greater than or equal to the circumferential width of the induced structure 420 along the same direction. This ensures that no induced structure 420 remains under the single-crystal semiconductor layer 520 or between the single-crystal semiconductor layer 520 and the second type of dielectric isolation layer 600 after induced annealing. The induced structure 420 is located at the top of the single-crystal semiconductor layer 520, i.e., the top of the via 300, and is no longer enclosed by the structure of the three-dimensional memory, allowing for direct removal.

[0060] The following will be based on Figures 1 to 22 The cross-sectional view shown illustrates the manufacturing process. Specifically, the method for manufacturing this three-dimensional memory includes the following steps:

[0061] First, please refer to Figure 4 A substrate 100 is provided. In this embodiment of the invention, the material and thickness of the substrate 100 are not specifically limited, as long as they can be applied to the manufacturing method of the three-dimensional memory provided in this embodiment. The substrate 100 can be used to support the device structure thereon. Exemplarily, the material of the substrate 100 includes at least one of silicon, germanium, germanium-silicon, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. Preferably, the material of the substrate 100 is silicon.

[0062] Next, please refer to Figure 4 The method for forming a stacked structure in the embodiments of the present invention may include a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to form a stacked structure 200 on a substrate 100. The stacked structure 200 includes at least two first-type dielectric isolation layers 201 and at least one sacrificial layer 202 alternately disposed along the thickness direction of the substrate 100.

[0063] Regarding the sacrificial layer 202, it serves as a pre-occupier within the stacked structure 200. After subsequent processes fabricate the floating gate structure and word lines in the vias, the sacrificial layer 202 is removed, and a memory cell structure is formed at the original sacrificial layer 202. The thickness of the sacrificial layer 202 is determined by the size of the memory cells included in the three-dimensional memory manufactured according to the embodiments of the present invention, and the embodiments of the present invention do not specifically limit it. The material of the sacrificial layer 202 should be as easy to remove as possible while meeting the requirements of its occupying function. For example, the material of the sacrificial layer 202 may be at least one of polymer, nitride, and germanium-silicon; the thickness of the sacrificial layer 202 is greater than or equal to 5 nm and less than or equal to 500 nm.

[0064] Regarding the first type of isolation dielectric layer, it serves as an insulating layer between the stacked memory cells of the three-dimensional memory formed by subsequent processes. It separates the stacked memory cells included in the three-dimensional memory manufactured according to embodiments of the present invention, isolating the stacked memory cells from each other and reducing interference. The thickness of the first type of isolation dielectric layer can be determined based on the size of the memory cells and the leakage current parameters between the stacked memory cells; embodiments of the present invention do not impose specific limitations on the thickness of the first type of isolation dielectric layer. The material of the first type of isolation dielectric layer can be at least one of silicon oxide, hafnium oxide, silicon carbide, or silicon nitride, or other materials that can meet the insulation performance requirements of the three-dimensional memory manufactured according to embodiments of the present invention. Optionally, the material of the first type of isolation dielectric layer is silicon oxide, because the process of using silicon oxide in three-dimensional memory is relatively mature and widely adopted. Using silicon oxide as the material of the first type of isolation dielectric layer can result in a higher yield and lower cost for the manufacturing method of the three-dimensional memory provided by embodiments of the present invention.

[0065] For example, the thickness of the at least two first-type dielectric isolation layers 201 formed is the same, and the thickness of the at least one sacrificial layer 202 formed is the same. In this case, the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided in this embodiment of the invention includes memory cells of the same size, and the voltage, current, and other conditions for operating the memory cells are also the same, which facilitates the use of the three-dimensional memory manufactured by this embodiment of the invention in other electronic systems. In addition, the thickness of the first-type dielectric isolation layers formed can be different, and the thickness of the sacrificial layer 202 formed can also be different. The thickness of the first-type dielectric isolation layers formed and the thickness of the sacrificial layer 202 formed can be determined according to the performance requirements of the three-dimensional memory manufactured by this embodiment of the invention and the design requirements of the memory cells.

[0066] It should be noted that in the stacked structure 200, both the bottom and top layers are first-type dielectric isolation layers 201. In this case, having the bottom layer of the stacked structure 200 as a first-type dielectric isolation layer 201 prevents leakage current from the transistor formed on the bottom layer of the stacked structure 200 to the substrate 100, thus ensuring the performance of the transistor formed on the bottom layer of the stacked structure 200. Simultaneously, having the top layer of the stacked structure 200 as a first-type dielectric isolation layer 201 prevents leakage current from the transistor formed on the bottom layer of the stacked structure 200 to other structures subsequently formed on the stacked structure 200, thus ensuring the performance of the transistor formed on the bottom layer of the stacked structure 200. The first type of dielectric isolation layer 201 can also serve as a protective layer to prevent the storage cells formed on the top layer of the stacked structure 200 of the three-dimensional memory manufactured in this embodiment of the invention from being damaged during subsequent processing, thus ensuring performance. Furthermore, if a planarization process is used to remove the induced structure 420 in subsequent processes, the first type of dielectric isolation layer 201 can be appropriately thickened and gradually removed along the thickness direction of the substrate together with the induced structure 420 until the induced structure 420 is completely removed.

[0067] Next, please refer to Figure 5 Through-holes 300 can be formed within the stacked structure 200 using processes such as photolithography and etching. The through-holes 300 may penetrate only the stacked structure 200 or extend into the substrate 100. The manufacturing method provided in this embodiment of the invention does not specifically limit the depth of the through-holes 300, which can reduce the precision requirements of the process for forming the through-holes 300 and reduce the cost of the manufacturing method provided in this embodiment of the invention. For example, when forming the through-holes 300 using an etching process, if the etching machine or the type of etching process used has low precision and cannot form through-holes 300 that only penetrate the stacked structure 200, through-holes 300 extending into the substrate 100 can be formed. Then, the through-holes 300 can be backfilled through epitaxy to the point where they only penetrate the stacked structure 200, or the portion of the through-holes 300 extending into the substrate 100 can be filled during the subsequent formation of the semiconductor active layer 301.

[0068] Furthermore, the embodiments of the present invention do not limit the size and shape of the through hole 300, as long as it meets the performance requirements of the three-dimensional memory manufactured by the embodiments of the present invention and the precision requirements of the manufacturing process of the through hole 300. For example, the through hole 300 can be cylindrical, square prism, hexagonal prism, etc.

[0069] As for the number of vias 300, the embodiments of the present invention do not limit it, and can be determined according to the number of stacked layers and the number of storage cells to be manufactured.

[0070] Next, please refer to Figure 6 An epitaxial process can be used to form a semiconductor active layer 301 at the bottom of the via 300. The thickness of the formed semiconductor active layer 301 is at least the sum of the thicknesses of a first-type dielectric isolation layer 201 and a sacrificial layer 202. The material of the semiconductor active layer 301 includes silicon, germanium, and germanium-silicon. In subsequent steps, the semiconductor active layer 301 can be used as part of the select transistor structure of the three-dimensional memory manufactured by the manufacturing method of the three-dimensional memory provided in this embodiment of the invention. If the top morphology of the formed semiconductor active layer 301 is uneven, such as forming a diamond morphology, a semiconductor active layer 301 thicker than designed can be formed first, and then the semiconductor active layer 301 can be etched back to make the top of the semiconductor active layer 301 more flat, which facilitates the subsequent formation of the inducing metal layer 410 and the semiconductor structure 510 on the semiconductor active layer 301.

[0071] Next, please refer to Figure 7 The method for forming an inter-electrode dielectric layer 302 covering the sidewalls of via 300 on the semiconductor active layer 301 can employ thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The inter-electrode dielectric layer 302 may include a charge blocking layer, a charge trapping layer, and a tunneling layer. Specifically, a tunneling layer is formed on the sidewalls of the via 300, a charge trapping layer is formed on the tunneling layer, and a charge blocking layer is formed on the charge trapping layer. In this step, the tunneling layer, the charge trapping layer, and the charge blocking layer are sequentially deposited along the inner walls of each via 300. The material of the charge blocking layer can be silicon oxide, the material of the charge trapping layer can be silicon nitride or SiON, and the material of the tunneling layer can be silicon oxide to form an "ONO" (Oxide-Nitride-Oxide) structure.

[0072] Next, please refer to Figure 8A cylindrical induction structure 420 and a semiconductor structure 510 are formed on the sidewall of the via 300. The induction structure 420 and semiconductor structure 510 are sequentially disposed on the semiconductor active layer 301 along the thickness direction of the substrate. The top of the semiconductor structure 510 is flush with the top of the inter-electrode dielectric layer 302. The projection of the semiconductor structure 510 onto the semiconductor active layer 301 overlaps the projection of the induction structure 420 onto the semiconductor active layer 301. That is, the circumferential width of the semiconductor structure 510 along the direction parallel to the substrate 100 is greater than or equal to the circumferential width of the induction structure 420 along the direction parallel to the substrate 100. In this case, it can be ensured that after induced annealing, no induction structure 420 will remain under the single-crystal semiconductor layer 520 and / or between the single-crystal semiconductor layer 520 and the second type of dielectric isolation layer 600. The induction structure 420 is located at the top of the single-crystal semiconductor layer 520, i.e., the top of the via 300, and is no longer enclosed by the structure of the three-dimensional memory, and can be directly removed.

[0073] In addition, the materials of semiconductor structure 510 include silicon, germanium, and germanium-silicon. The materials of semiconductor structure 510 are the same as those of semiconductor active layer 301, so as to enable semiconductor structure 510 to be subsequently induced and catalyzed into single-crystal semiconductor layer 520, that is, single-crystal channel.

[0074] Regarding the method of forming the cylindrical induction structure 420 and semiconductor structure 510 on the sidewall of the via 300, the embodiments of the present invention provide two implementation methods. It should be noted that the method of forming the cylindrical induction structure 420 and semiconductor structure 510 on the sidewall of the via 300 is not limited to these two implementation methods, and a more suitable method can be selected according to actual needs.

[0075] First implementation method: Please refer to... Figure 2 The cylindrical induction structure 420 and semiconductor structure 510 formed on the sidewall of the through-hole 300 include:

[0076] First, please refer to Figure 12 An induced metal layer 410 is formed on the sidewalls of the stacked structure 200 and the bottom of the via 300 using, for example, isotropic deposition. This embodiment of the invention does not impose specific limitations on the thickness or material of the induced metal layer 410; a suitable method and thickness can be selected according to actual needs.

[0077] Specifically, the material of the inducing metal layer 410 includes at least one of nickel, palladium, aluminum, copper, iron, or tungsten. All of the aforementioned materials can form the inducing structure 420 after reactive annealing and can effectively induce the semiconductor structure 510 to crystallize into a single-crystal semiconductor layer 520. Furthermore, in the manufacturing method of the three-dimensional memory provided in this embodiment of the invention, different materials of the inducing metal layer 410 can be selected according to the different materials of the semiconductor structure 510, the width and depth of the channel, and the thermal budget, to achieve better results under each condition.

[0078] For example, when the semiconductor structure 510 is made of silicon, the material of the inducing metal layer 410 is selected from nickel, iron, copper, palladium, tungsten, or aluminum. When the semiconductor structure 510 is made of germanium, the material of the inducing metal layer 410 is selected from nickel, iron, or copper. When the semiconductor structure 510 is made of silicon-germanium, the material of the inducing metal layer 410 is selected from nickel.

[0079] Optionally, the material of the inducing metal layer 410 is nickel, because nickel has a good effect on inducing crystallization modification of the semiconductor structure 510.

[0080] For example, the thickness of the surface of the induced metal layer 410 extending beyond the stacked structure 200, the surface of the sidewall of the via 300, and the surface of the semiconductor active layer 301 is greater than or equal to 3 nm and less than or equal to 30 nm.

[0081] In this case, problems such as ineffective reaction between the induced metal layer 410 and the semiconductor active layer 301 due to excessively thin induced metal layer 410, failure to form induced structure 420 after induced metal layer 410 formation, uneven height of the formed induced structure 420 along the thickness direction of the stacked structure 200 and along the direction perpendicular to the thickness direction of the stacked structure 200, and excessively low height of the formed induced structure 420 along the thickness direction of the stacked structure 200 and along the direction perpendicular to the thickness direction of the stacked structure 200 can be avoided, ensuring effective subsequent induced annealing. It also avoids excessively high material and time costs due to excessively thick induced metal layer 410, which is beneficial for cost control and yield improvement. Furthermore, an excessively thick induced metal layer 410 may crack due to stress, damaging the 3D memory; keeping the thickness of the induced metal layer 410 within the aforementioned range can also improve yield and reduce costs.

[0082] Next, please refer to Figure 13 Dry etching methods, such as reactive ion etching (RIE) and ion beam etching (IBE), can be used to remove the induced metal layer 410 located on the stacked structure and the induced metal layer 410 located at the bottom of the via 300, leaving only the induced metal layer 410 located on the sidewall of the via 300.

[0083] Next, please refer to Figure 14The inducing metal layer 410 and the semiconductor active layer 301 are subjected to reactive annealing, transforming the portion of the inducing metal layer 410 in contact with the semiconductor active layer 301 into an induced structure 420. It should be noted that the induced structure 420 formed in this step can penetrate into the semiconductor active layer 301. Furthermore, this embodiment of the invention does not impose specific limitations on the annealing time and temperature, or the thickness of the formed induced structure 420, in this step; appropriate annealing time, annealing temperature, and the thickness of the formed induced structure 420 can be selected according to actual needs.

[0084] For example, the annealing time for the reactive annealing treatment is greater than or equal to 15 s and less than or equal to 300 s. In this case, performing reactive annealing treatment on the induced metal layer within this time range ensures that the induced metal layer 410 reacts effectively with the semiconductor active layer 301 to form a semiconductor-metal compound. This avoids the situation where the induced metal layer 410 and the semiconductor active layer 301 cannot react effectively due to too short a time, thereby ensuring the effect of subsequent induced crystallization modification. It also prevents the thermal budget from being increased due to excessive time, which could affect other structures.

[0085] For example, the annealing temperature for the reaction annealing treatment is greater than or equal to 180°C and less than or equal to 300°C. Performing reaction annealing on the induced metal layer 410 within this temperature range ensures effective reaction between the induced metal layer 410 and the semiconductor active layer 301, forming a semiconductor-metal compound. This avoids situations where the induced metal layer 410 and the semiconductor active layer 301 fail to react effectively due to excessively low temperatures, thereby guaranteeing the effectiveness of subsequent induced crystallization modification. Furthermore, it prevents unnecessary increases in thermal budget due to excessively high temperatures.

[0086] For example, the thickness of the induced metal layer 410 is greater than or equal to 0.5 nm and less than or equal to 30 nm. In this case, it can avoid the following problems: the induced metal layer 410 is too thin, which would lead to ineffective reaction between the induced metal layer 410 and the semiconductor active layer 301; the height of the formed induced structure 420 along the thickness direction of the stacked structure 200 and the height along the direction perpendicular to the thickness direction of the stacked structure 200 would be uneven; and the height of the formed induced structure 420 along the thickness direction of the stacked structure 200 and the height along the direction perpendicular to the thickness direction of the stacked structure 200 would be too low, which would affect whether the subsequent induced annealing process can be effectively performed.

[0087] For example, the height of the induced structure 420 along the thickness direction of the stacked structure 200 is greater than or equal to 0.5 nm and less than or equal to 30 nm. In this case, within this height range, it can be ensured that the induced structure 420 has a suitable height, enabling it to effectively induce annealing to crystallize and modify the semiconductor structure 510 into a single-crystal semiconductor layer 520, avoiding the inability to achieve the desired effect due to insufficient height. It also prevents the induced structure 420 from being too high, making it difficult to completely remove the structure later, and leaving a large gap on the inner wall of the via 300 after removal, thereby affecting the performance of the uppermost three-dimensional memory cell.

[0088] Next, please refer to Figure 15 The induced metal layer 410 that has not been converted into the induced structure 420 is selectively removed using processes such as wet etching or dry etching. Wet etching, with its lower temperature, allows for selective removal, effectively eliminating the need for removal while avoiding the increased thermal budget of dry etching. Dry etching, on the other hand, allows for more precise removal of the induced metal layer that has not been converted into the induced structure, and it has minimal impact on other structures of the three-dimensional memory manufactured in this embodiment, thus ensuring the performance of the three-dimensional memory manufactured in this embodiment.

[0089] For example, when the material of the inducing metal layer 410 is nickel, the inducing metal layer 410 can be removed by using a mixture of concentrated sulfuric acid and hydrogen peroxide, i.e., SPM semiconductor cleaning solution; the inducing metal layer 410 can also be removed by using a cleaning solution such as aqua regia, which is a mixture of concentrated hydrochloric acid and concentrated nitric acid; or the inducing metal layer 410 can be removed by plasma etching.

[0090] Next, please refer to Figure 16 A semiconductor structure 510 is formed on the sidewalls of the stacked structure 200, the via 300, and the active semiconductor layer 301 using deposition processes such as chemical vapor deposition, physical vapor deposition, electroplating, spin coating, or evaporation. It should be noted that the embodiments of the present invention do not limit the thickness of the semiconductor structure 510; a suitable thickness for the semiconductor structure 510 can be selected according to actual needs.

[0091] Next, please refer to Figure 17The semiconductor structure 510 located on the stacked structure 200 and the semiconductor structure 510 located at the bottom of the via 300 are removed using a process such as anisotropic etching. Only the semiconductor structure 510 located on the sidewall of the via 300 is retained, excluding the inducing structure 420 located on the sidewall of the via 300 and the semiconductor structure 510 located on the sidewall of the via 300. The projection of the semiconductor structure 510 on the active semiconductor layer 301 covers the projection of the inducing structure 420 on the active semiconductor layer 301. That is, the annular width of the semiconductor structure 510 along the direction parallel to the substrate 100 is greater than or equal to the annular width of the inducing structure 420 along the direction parallel to the substrate 100. Specifically, the annular width of the semiconductor structure 510 along the direction parallel to the substrate 100 is 0 nm to 1 nm larger than the annular width of the inducing structure 420 along the direction parallel to the substrate 100.

[0092] In this case, a cylindrical induced structure 420 is formed first, and then a cylindrical semiconductor structure 510 is formed. There is no need to etch the induced structure, which is a compound of semiconductor and metal, thus avoiding the need to etch difficult-to-etch semiconductor and metal compounds, thereby improving the manufacturing speed and yield of the manufacturing method provided in this embodiment of the invention.

[0093] Second implementation method: Please refer to Figure 3 A cylindrical induction structure 420 and a semiconductor structure 510 are formed on the sidewall of the through-hole 300, including:

[0094] First, an induced metal layer 410 can be formed on the stacked structure 200, the sidewalls of the via 300, and the bottom semiconductor active layer 301 of the via 300 using processes such as physical vapor deposition. The material and thickness of the induced metal layer can be found in the previous text and will not be repeated here.

[0095] Next, the induced metal layer 410 and the semiconductor active layer 301 are subjected to reactive annealing, so that the portion of the induced metal layer 410 in contact with the semiconductor active layer 301 is transformed into the induced structure 420. The annealing time and temperature, etc., can be found in the previous text and will not be repeated here.

[0096] Next, the induced metal layer 410 that has not been converted into the induced structure 420 is removed by dry etching and other processes.

[0097] Next, a semiconductor structure 510 is formed on the stacked structure 200, on the sidewalls of the via 300, and on the bottom semiconductor active layer 301 of the via 300 using deposition processes such as chemical vapor deposition, physical vapor deposition, electroplating, or evaporation. It should be noted that this embodiment of the invention does not limit the thickness of the semiconductor structure 510; a suitable thickness can be selected according to actual needs.

[0098] Next, a process such as anisotropic etching is used to remove the semiconductor structure 510 located on the stacked structure 200 and the semiconductor structure 510 located at the bottom of the via 300, leaving only the semiconductor structure 510 located on the sidewall of the via 300; the inducing metal layer 410 located at the bottom of the via 300 is removed, leaving only the inducing metal layer 410 located on the sidewall of the via 300.

[0099] In this configuration, the projection of semiconductor structure 510 onto the active semiconductor layer 301 overlaps with the projection of induced structure 420 onto the active semiconductor layer. That is, the circumferential width of the semiconductor structure 510 along the direction parallel to the substrate 100 is equal to the circumferential width of the induced structure along the direction parallel to the substrate. First, a thin sheet-like induced structure 420 is formed on the active semiconductor layer 301 at the bottom of the via 300, followed by the formation of semiconductor structure 510. Then, the induced structure 420 and semiconductor structure 510 are patterned. The two patterning processes can share the same mask, reducing the cost of the manufacturing method provided in this embodiment. Furthermore, the induced structure 420 and semiconductor structure 510 form a self-aligned process, which helps reduce the process complexity of the three-dimensional memory manufacturing method provided in this embodiment and improves the yield of the three-dimensional memory manufactured in this embodiment.

[0100] Next, please refer to Figure 23 and Figure 9 The method for forming the second type of dielectric isolation layer 600 within the via 300 and on the stacked structure 200 may include thin film deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof, wherein the second type of dielectric isolation layer 600 is filled within the via 300, and one end of the second type of dielectric isolation layer 600 away from the bottom of the via 300 is flush with the stacked structure 200. For details, please refer to... Figure 23 First, a second type of dielectric isolation layer 600 is formed within the through-hole 300 and on the stacked structure 200; please refer to Figure 9 The method for removing the second type of dielectric isolation layer 600 above the stacked structure 200 includes at least one of chemical mechanical polishing, reverse etching or other known planarization processes, and then removing the second type of dielectric isolation layer 600 above the stacked structure 200, leaving only the second type of dielectric isolation layer 600 located in the via 300.

[0101] It should be noted that, in order to ensure that the second type of dielectric isolation layer 600 can completely fill the through hole 300, an excessive amount of the second type of dielectric isolation layer 600 can be formed first, and then the second type of dielectric isolation layer 600 higher than the stacked structure 200 can be removed.

[0102] It should be noted that the embodiments of the present invention do not limit the material of the second type of dielectric isolation layer 600, and appropriate materials can be selected according to actual needs.

[0103] For example, the material of the second type of isolation dielectric layer includes at least one of silicon oxide, hafnium oxide, silicon carbide, or silicon nitride. Preferably, the material of the second type of isolation dielectric layer is silicon oxide, because silicon oxide is the most mature and widely used material in three-dimensional memory, and the application of silicon oxide can make the manufacturing method of the three-dimensional memory provided in the embodiments of the present invention have a high yield and lower cost.

[0104] Next, please refer to Figure 10 The semiconductor structure 510 and the induced structure 420 are subjected to induced annealing to crystallize and modify the semiconductor structure 510 into a single-crystal semiconductor layer 520. After induced annealing, the induced structure 420 is located on top of the single-crystal semiconductor layer 520. In this case, after induced annealing, the induced structure 420 is located on top of the single-crystal semiconductor layer 520, i.e., on top of the via 300, and is no longer enclosed by the structure of the three-dimensional memory manufactured in this embodiment of the invention. Instead, it is directly exposed and can be directly removed in subsequent steps. This helps to avoid the residual induced structure 420 from adversely affecting the yield and performance of the three-dimensional memory formed after subsequent processing. The single-crystal channel without induced metal contamination can improve the working performance of the three-dimensional memory manufactured using the manufacturing method of the three-dimensional memory provided in this embodiment of the invention. Compared with forming the induced structure on top of the semiconductor structure and then performing induced annealing, which leaves residues in the via, and removing the induced structure requires etching from the substrate direction and then backfilling, the manufacturing method provided in this embodiment of the invention makes it easier to remove the induced structure, which helps to reduce process complexity.

[0105] It should be noted that the embodiments of the present invention do not impose specific limitations on the annealing time and annealing temperature of the reaction annealing in this step, and appropriate annealing time and annealing temperature of the reaction annealing can be selected according to actual needs.

[0106] As one possible implementation, the annealing temperature for induced annealing is greater than or equal to 450°C and less than or equal to 600°C, and the annealing time is greater than or equal to 0.5 h and less than or equal to 30 h. Performing induced annealing on semiconductor structure 510 and induced structure 420 at this temperature has minimal impact on other structures and results in low thermal budget requirements. Performing induced annealing on semiconductor structure 510 and induced structure 420 within this time range avoids both incomplete crystallization modification of semiconductor structure 510 due to excessively short annealing time and increased thermal budget due to excessively long annealing time, thus preventing any impact on the structural integrity of the three-dimensional memory and ensuring good performance and high yield of the three-dimensional memory.

[0107] Please note that when the annealing temperature for induced annealing is greater than or equal to 450°C and less than or equal to 600°C, the annealing time can also be determined based on the crystallization rate of the semiconductor structure transforming from a non-single-crystal phase to a single-crystal phase from bottom to top and the length of the semiconductor structure along the substrate thickness direction. For example, when the induced structure is nickel silicide, the length of the semiconductor structure along the substrate thickness direction is 2000 nm, and the crystallization rate of the nickel silicide on the semiconductor structure is 500 nm / h, the annealing time for induced annealing is greater than or equal to 4 h and less than or equal to 30 h.

[0108] As one possible implementation, the annealing temperature for the induced annealing process is greater than or equal to 900°C and less than or equal to 1200°C, and the annealing time for the induced annealing process is greater than or equal to 2 seconds and less than or equal to 20 seconds. In this case, the aforementioned rapid annealing achieves induced crystallization modification of the semiconductor structure 510 at a higher temperature and a shorter time, resulting in a lower thermal budget provided that the semiconductor structure 510 is fully crystallized and modified into a single-crystal semiconductor layer 520.

[0109] Next, please refer to Figure 11 After the induced annealing is completed, that is, after the crystallization modification of the semiconductor structure 510, the induced structure 420 is located above the single crystal semiconductor layer 520, that is, at the top of the channel. The induced structure 420 is removed by methods such as planarization or etching.

[0110] This configuration results in a lower thermal budget for removing the induced structure 420 via planarization, and the top layer of the stacked structure 200 can be planarized simultaneously, reducing process steps and increasing yield. Removing the induced structure 420 via etching allows for precise removal of only the induced structure 420, minimizing impact on other structures of the three-dimensional memory manufactured according to this embodiment and ensuring the structural integrity of the three-dimensional memory.

[0111] Furthermore, removing the induced structure 420 can avoid adverse effects on the yield and performance of the three-dimensional memory formed after subsequent processing. The single-crystal channel without induced metal contamination can improve the working performance of the three-dimensional memory manufactured using the manufacturing method of the three-dimensional memory provided in the embodiments of the present invention.

[0112] It should be noted that after induced annealing, i.e., after the crystallization modification of the semiconductor structure 510, the induced structure 420 is located above the single-crystal semiconductor layer 520, i.e., at the top of the channel. Therefore, the induced structure 420 may not need to be removed. Alternatively, the induced structure 420 can be removed during subsequent processing of the three-dimensional memory manufactured according to the manufacturing method provided in this embodiment of the invention, or it can be retained according to performance requirements or processing needs.

[0113] Secondly, please refer to Figure 11 The present invention also provides a three-dimensional memory. This three-dimensional memory is manufactured using the manufacturing method of the three-dimensional memory provided in the first aspect.

[0114] The beneficial effects of the second aspect and its various embodiments in the present invention can be referred to the analysis of the beneficial effects of the three-dimensional memory manufactured by the first aspect and its various embodiments described above, and will not be repeated here.

[0115] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0116] The above are merely specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention embodiments should be included within the protection scope of the present invention embodiments. Therefore, the protection scope of the present invention embodiments should be determined by the protection scope of the claims.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, include: A substrate is provided, the substrate comprising a substrate, a stacked structure, a semiconductor active layer, and an inter-electrode dielectric layer; the stacked structure is disposed on the substrate; the stacked structure includes a first-type dielectric isolation layer and a sacrificial layer sequentially stacked along the thickness direction of the substrate; in the stacked structure, the bottom and top layers are both first-type dielectric isolation layers; a through-hole is provided in the stacked structure, the semiconductor active layer fills the bottom of the through-hole; the inter-electrode dielectric layer is disposed on the semiconductor active layer and covers the sidewall surface of the through-hole; A cylindrical induction structure and a semiconductor structure are formed on the sidewall of the via; the induction structure and the semiconductor structure are sequentially disposed on the semiconductor active layer along the thickness direction of the substrate; The projection of the semiconductor structure onto the active semiconductor layer covers the projection of the induced structure onto the active semiconductor layer; The material of the induced structure is a compound of semiconductor and metal in the semiconductor active layer; the crystal phase of the material of the semiconductor structure is a non-single crystal phase; A second type of dielectric isolation layer is filled in the through hole, and one end of the second type of dielectric isolation layer away from the bottom of the through hole is flush with the stacked structure. The semiconductor structure and the induced structure are subjected to induced annealing treatment to crystallize and modify the semiconductor structure into a single-crystal semiconductor layer; After induced annealing, the induced structure is located on top of the single-crystal semiconductor layer.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The annealing temperature of the induced annealing treatment is greater than or equal to 450°C and less than or equal to 600°C; and / or the annealing time of the induced annealing treatment is greater than or equal to 0.5h and less than or equal to 30h. Alternatively, the annealing temperature of the induced annealing treatment is greater than or equal to 900°C and less than or equal to 1200°C, and the annealing time of the induced annealing treatment is greater than or equal to 2s and less than or equal to 20s.

3. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of a cylindrical induction structure and a semiconductor structure on the sidewall of the through hole includes: An induction metal layer is formed on the stacked structure, on the sidewalls of the through hole, and at the bottom of the through hole; Remove the inducing metal layer located on the stacked structure and the inducing metal layer located at the bottom of the via, while retaining the inducing metal layer located on the sidewall of the via; The remaining induced metal layer and the semiconductor active layer are subjected to reactive annealing, so that the portion of the remaining induced metal layer in contact with the semiconductor active layer is transformed into the induced structure; Remove the induced metal layer that has not been converted into the induced structure; The semiconductor structure is formed on the stacked structure, on the sidewalls of the via, and at the bottom of the via; Remove the semiconductor structure located on the stacked structure and the semiconductor structure located at the bottom of the via, and retain the semiconductor structure located on the sidewall of the via.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of a cylindrical induction structure and a semiconductor structure on the sidewall of the through hole includes: An induction metal layer is formed on the stacked structure, on the sidewalls of the through hole, and at the bottom of the through hole; The inducing metal layer and the semiconductor active layer are subjected to reactive annealing treatment, so that the portion of the inducing metal layer in contact with the semiconductor active layer is transformed into the inducing structure; Remove the induced metal layer that has not been converted into the induced structure; The semiconductor structure is formed on the stacked structure, on the sidewalls of the via, and at the bottom of the via; Remove the semiconductor structure located on the stacked structure and the semiconductor structure located at the bottom of the via, retaining only the semiconductor structure located on the sidewall of the via; remove the inducing metal layer located at the bottom of the via, retaining the inducing metal layer located on the sidewall of the via.

5. The method for manufacturing a three-dimensional memory according to claim 3 or claim 4, wherein the annealing temperature of the reaction annealing process is greater than or equal to 180°C and less than or equal to 300°C; and / or, the annealing time of the reaction annealing process is greater than or equal to 15s and less than or equal to 300s.

6. The method for manufacturing a three-dimensional memory according to claim 3 or claim 4, wherein the thickness of the induced metal layer is greater than or equal to 0.5 nm and less than or equal to 30 nm.

7. The method for manufacturing a three-dimensional memory according to claim 3 or claim 4, wherein a wet etching process or a dry etching process is used to remove the induced metal layer that has not been converted into the induced structure.

8. The method for manufacturing a three-dimensional memory according to claim 3 or claim 4, characterized in that, The material of the inducing metal layer includes at least one of nickel, palladium, aluminum, copper, iron, and tungsten.

9. The method for manufacturing a three-dimensional memory according to claim 3 or claim 4, wherein the height of the induced structure along the thickness direction of the stacked structure is greater than or equal to 0.5 nm and less than or equal to 30 nm.

10. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, After performing induced annealing on the semiconductor structure and the induced structure, the method for manufacturing the three-dimensional memory further includes removing the induced structure.

11. A three-dimensional memory, characterized in that, The three-dimensional memory is manufactured using the manufacturing method described in any one of claims 1 to 10.

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