Laterally diffused metal oxide semiconductor field effect transistor based on area efficient fin

Abstract

The invention relates to a laterally diffused metal oxide semiconductor field effect transistor based on area efficient fins. In one embodiment, an apparatus includes a substrate having a first doping, the substrate including a first well having a second doping and a second well having a third doping; and a fin disposed on the substrate. The fin is positioned over the first well and extends at least partially over the second well. The fin includes: a first doped region disposed on the first well and having a doping that is lighter than the second doping; and a second doped region disposed on the first well with the third doping.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document and the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for an area efficient architecture for laterally diffused metal oxide semiconductor (LDMOS) fin-based field effect transistors. Background Art

[0004] Fin-based (also known as fin-shaped) field effect transistors (FinFETs) have been widely used in complementary metal oxide semiconductor (CMOS) technology to achieve scalability and space savings. In the context of LDMOS, conventional substrate connections lead to an increase in device array area. As the size of advanced technology nodes continues to decrease, larger footprints and areas correspond to higher and higher costs.

[0005] Thus, methods, systems, and apparatus for area efficient LDMOS FinFETs are provided. Summary of the invention

[0006] Various embodiments describe an area efficient LDMOS FinFET.

[0007] In some embodiments, an apparatus for an area efficient LDMOS FinFET is provided. The apparatus includes a substrate having a first doping, the substrate including a first well having a second doping and a second well having a third doping. The apparatus further includes: a fin disposed on the substrate; a gate disposed on the fin; and a first epitaxial layer having the second doping, wherein the first epitaxial layer is disposed on a first region of the fin and at least a portion of the second well of the substrate. The apparatus further includes a second epitaxial layer having the third doping, wherein the second epitaxial layer is disposed on a second region of the fin and at least a portion of the second well of the substrate.

[0008] In other embodiments, an alternative apparatus for an area efficient LDMOS FinFET is provided. The apparatus includes one or more fins formed of a semiconductor material and disposed on a substrate and extending in a first direction, the one or more fins including an undoped region, a first doped region, and a second doped region. The apparatus further includes: a gate disposed at least partially on the one or more fins, the gate extending across the one or more fins in a second direction; and a dummy gate disposed on the one or more fins, the dummy gate extending in the second direction, wherein the dummy gate has a first side facing the gate and a second side facing away from the gate. The first doped region may be disposed between the gate and the dummy gate, wherein the first doped region has a second doping. The second doped region may be disposed on the second side of the dummy gate, wherein the second doped region has a third doping.

[0009] In other embodiments, an apparatus for an area efficient LDMOS FinFET is provided. The apparatus comprises: a substrate having a first doping, the substrate comprising a first well having a second doping and a second well having a third doping; and a fin disposed on the substrate. The fin is positioned above the first well and extends at least partially above the second well. The fin comprises: a first doped region disposed on the first well and having the second doping; and a second doped region disposed on the first well and having the third doping. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and drawings, wherein like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0011] Figure 1 is a schematic top view of an area efficient LDMOS FinFET according to various embodiments;

[0012] Figure 2 is a schematic diagram of a cross section of an area efficient LDMOS FinFET according to various embodiments;

[0013] Figure 3 is a schematic top view of one arrangement of an LDMOS FinFET array according to various embodiments; and

[0014] Figure 4 is a graph of IV characteristics of an area efficient LDMOS FinFET according to various embodiments. DETAILED DESCRIPTION

[0015] In the following description, for the purpose of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be apparent to one skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reasons, it should not be considered that a single or multiple features of any described embodiment are essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0016] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there may be no intervening elements in a "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0017] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0018] Similarly, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intervening element present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which intervening elements may be present.

[0019] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0020] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intervening processes may occur before and / or after any portion of the described process, and various other procedures may be reordered, added, and / or omitted according to various embodiments.

[0021] Unless otherwise indicated, all numbers used herein to indicate quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, unless otherwise specifically indicated, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms "and" and "or" means "and / or". In addition, the use of the terms "including" and "having" and other forms such as "includes", "included", "has", "have" and "had" should be considered non-exclusive. In addition, terms such as "element" or "component" cover elements and components that make up one unit and elements and components that make up more than one unit, unless otherwise specifically stated.

[0022] As used herein, the phrase "at least one of..." preceding a series of items using the terms "and" or "or" to separate any of the items modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; in contrast, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where the desired selection is "at least one of each of A, B, C," or alternatively "at least one of A, at least one of B, and at least one of C," it is so explicitly described.

[0023] Conventional substrate bonds are typically arranged to surround the LDMOS (or LDMOS array) on all sides, increasing the space occupied by the individual LDMOS FinFETs. The Technology Design Rule Manual (DRM) further specifies a guard ring around the LDMOS array, further increasing the footprint of the LDMOS array.

[0024] In some embodiments, the proposed LDMOS substrate connection structure provides a method for reducing the occupied area of ​​individual LDMOS devices. Specifically, by providing a highly doped epitaxial layer adjacent to the source as a substrate connection, the occupied area of ​​the LDMOS device can be reduced.

[0025] Figure 1 1 is a schematic top view of an area efficient LDMOS FinFET (hereinafter referred to as FinFET 100) according to various embodiments. FinFET 100 includes a drain region 105, a gate 110, a source region 115, a substrate connection 120, one or more first fins 125a to 125d (collectively referred to as "first set of fins 125"), a first dummy gate 130a to 130b, one or more second fins 135a to 135d (collectively referred to as "second set of fins 135"), a second dummy gate 140a to 140b, and a substrate 145. It should be noted that the various components and elements of FinFET 100 are shown in FIG. Figure 1 1 is schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of FinFET 100 are possible and according to various embodiments.

[0026] In various embodiments, the structure of FinFET 100 may be disposed on a substrate 145. Thus, substrate 145 may be a semiconductor substrate, such as but not limited to bulk silicon. In some embodiments, the substrate includes a lightly doped (“p - " or "n - ”) region. For example, in the case of n-type LDMOS (NLDMOS), the substrate 145 may be lightly doped with boron (eg, p - Thus, in various embodiments, the substrate 145 may have an “initial” doping (e.g., lightly p-type or n-type doping) on ​​which a more heavily doped region (e.g., a well) may be formed. Thus, the substrate 145 may further include a more heavily doped (“p + " or "n + ”) regions, which are doped with n-type dopants (e.g., phosphorus) and p-type dopants (e.g., boron), respectively. Thus, a well (interchangeably referred to as a “well region”) refers to a doped region formed within the substrate 145 that serves as the “bulk” or “body” of the FinFET 100, on which (or in which) other components of the device are formed, such as the drain region 105, the gate 110, the source region 115, the substrate connection 120, the first set of fins 125, the first dummy gates 130a to 130b, the second set of fins 135, and the second dummy gates 140a to 140b. A “p-well” refers to a well having p-type doping, and an “n-well” refers to a well having n-type doping.

[0027] In the above embodiments and other embodiments described below, boron and phosphorus are provided as non-limiting examples, and it should be understood that in other embodiments, other dopants may be utilized. For example, suitable dopants may include, but are not limited to, pentavalent atoms (e.g., arsenic, phosphorus, antimony, bismuth, lithium, etc.) for n-type doping and trivalent atoms (e.g., indium, aluminum, gallium, boron, etc.) for p-type doping.

[0028] In various embodiments, the first set of fins 125 and the second set of fins 135 may be first disposed on the substrate 145. The fins may be formed using various processes, including but not limited to growing and / or depositing the fins onto the substrate 145 (e.g., by an epitaxial process), forming the fins via lithography and / or etching, or a combination of processes.

[0029] Next, the gate 110, the first dummy gates 130a-130b, and the second dummy gates 140a-140b may be formed by depositing a gate oxide (e.g., a dielectric layer) over the first and second sets of fins 125, 135, followed by forming the gate 110 and the first and second dummy gates 130a-130b, 140a-140b from the gate oxide. In some examples, the gate 110 and / or the first and second dummy gates 130a-130b, 140a-140b may be patterned first and then deposited onto the substrate 145 and / or the first and second sets of fins 125, 135. In yet other examples, the gate 110 may be referred to as a "gate dielectric layer", and the first and second dummy gates 130a-130b, 140a-140b may be referred to as a "dummy dielectric layer". As used herein, a dummy gate (or dummy dielectric layer) refers to a non-active gate structure used for various purposes. In various examples, the dummy gates may be used as structural support, electrical biasing, electrical isolation, and / or placeholder structures to be subsequently removed or replaced.

[0030] In various embodiments, the drain region 105 may be disposed on the first side of the gate 110. In some embodiments, the drain region 105 is disposed between the first dummy gates 130a to 130b and includes a highly doped portion of the first group of fins 125. In various examples, the first group of fins 125 may include a highly doped portion that is in-situ doped to form at least a portion of the drain region. In some examples, in the case of NLDMOS, all or part of the first group of fins 125 may be in-situ doped with phosphorus. In some embodiments, as part of the in-situ doping process or in addition to the in-situ doping process, an epitaxial layer may be formed over the fin. An epitaxial layer may refer to a structure / layer grown via an epitaxial process. In this example, the epitaxial layer may form at least a portion of a raised source / drain (RSD) structure. In some examples, the epitaxial layer may be heavily doped and formed as part of the drain 105 (also referred to as a "drain / source"). The drain region 105 may be interchangeably referred to as the "drain" or "drain / source" of the FinFET 100. In some examples, the epitaxial layer can be configured to connect one or more first fins 125a to 125d. For example, the epitaxial layer can be extended longitudinally so that the epitaxial layer traverses one or more first fins 125a to 125d, such as Figure 1 Described in.

[0031] Similarly, the source region 115 may be disposed on a second side of the gate 110 (e.g., opposite to the first side of the gate 110). For example, in some embodiments, the source region 115 is disposed between the second dummy gate 140b and the gate 110. Like the drain region 105, the source region 115 may include a highly doped portion of the second group of fins 135. Specifically, the second group of fins 135 may include a first highly doped portion that is in-situ doped to form at least a portion of the source region. In some examples, in the case of NLDMOS, the first portion of the second group of fins 135 may be in-situ doped with phosphorus. Similarly, as part of the in-situ doping process or in addition to the in-situ doping process, a corresponding source side epitaxial layer may be formed over the first portion of the second group of fins 135. The epitaxial layer may be similarly heavily doped and form at least a portion of the source (also referred to as a "source / drain"). The source region 115 may be interchangeably referred to as the "source" or "source / drain" of the FinFET 100. In some examples, the epitaxial layer may be configured to connect one or more second fins 135a to 135d. The epitaxial layer of the source 115 may extend in the longitudinal direction such that it crosses the one or more second fins 135a to 135d extending in the longitudinal direction, such as Figure 1 Described in.

[0032] In various embodiments, the substrate connection 120 may be disposed between the second dummy gate 140a and the second dummy gate 140b adjacent to the source region 115. The substrate connection 120 may also include a highly doped portion of the second set of fins 135. Specifically, the second set of fins 135 may include a second highly doped portion that is in-situ doped to form at least a portion of the substrate connection 120. In the case of NLDMOS, the second portion of the second set of fins 135 may be in-situ doped with boron. In some examples, the substrate connection 120 is a structure directly connected to the p-well and provides a p-type connection to the substrate 145. As with the drain and source regions 105, 115, as part of the in-situ doping process or in addition to the in-situ doping process, the substrate connection 120 may also include a corresponding epitaxial layer ("substrate connection epitaxial layer") formed over the second portion of the second set of fins 135. The substrate connection epitaxial layer may be similarly doped (e.g., p-type) and formed as part of the substrate connection 120. In some examples, the substrate-bonded epitaxial layer can be configured to connect one or more second fins 135 a - 135 d across the respective second portions.

[0033] A substrate link, such as substrate link 120, is configured to provide a connection between source region 115 and substrate 145. Specifically, substrate link 120 may be configured to be in direct contact with the p-well, but to be more lightly doped than the p-well. In some instances, substrate link 120 is doped to a level between the doping of the substrate and the doping of the p-well. In yet other instances, substrate link 120 may be doped to the level of the substrate. As used herein, doping level refers to the doping concentration (e.g., concentration of dopants) in the underlying semiconductor material (e.g., epitaxial layer, fin, and / or substrate). By providing substrate link 120 in close proximity to source region 115, space savings and reduction of minority carrier flow (e.g., parasitic effects) may be achieved.

[0034] Figure 2 is a schematic diagram of a cross section of FinFET 100, 200 taken across line xx according to various embodiments. The cross-sectional view of FinFET 200 shows different portions and structures described above but obscured in the top view. Thus, FinFET 200 includes: a substrate 280 having an undoped / lightly doped region 205, a first well region 210 and a second well region 215, a first channel isolation region 220, a second channel isolation region 225, and a third channel isolation region 230; a drain region 235; a gate 240; a source region 245; a substrate link 250; a first fin 260; a second fin 255; a bridging structure 265; a first dummy gate 270a to 270b; and a second dummy gate 275a to 275b. It should be noted that the various components and elements of FinFET 200 are described in detail in detail. Figure 2 2 is schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of FinFET 200 are possible and in accordance with various embodiments.

[0035] As shown in the cross-sectional view, the substrate 280 may include an undoped / lightly doped region 205. In various examples, the substrate 280 may be lightly doped. For example, in NLDMOS, the undoped / lightly doped region 205 is lightly doped with boron (e.g., p-type). In various examples, the substrate 280 further includes a first well region 210 and a second well region 215. In various examples, the well regions 210, 215 may be heavily doped regions of the substrate 280. For example, in NLDMOS, the first well region 210 may be p-type doped (e.g., boron doped), and the second well region 215 may be n-type doped (e.g., phosphorus doped). In various examples, the substrate 280 further includes trench isolation regions, such as first to third trench isolation regions 220 to 230. The trench isolation region may be a trench formed in the substrate and filled with an oxide material. In some examples, one or more of the first, second, and third trench isolation regions 220 to 230 may be shallow trench isolation (STI) regions. In some examples, one or more of the first, second, and third trench isolation regions 220 - 230 can be deep trench isolation (DTI) regions.

[0036] The first and second fins 260, 255 may be disposed on the substrate 280, wherein the first fin 260 is disposed on the second well region 215, and the second fin 255 is at least partially disposed on the first well region 210 and at least partially disposed on the second well region 215. Each of the first fin 260 and the second fin 255 may include both a doped region (depicted with lighter hatching) and an undoped region (depicted with darker hatching). For example, the undoped region 285 of the second fin 255 may be used as a current flow channel between the gate and the source. In some examples, the doped regions may be doped with different dopant types within the same fin. For example, the first type doped region 290 depicted with horizontal hatching may be one of p-type or n-type doping. The second type doped region 295 depicted with vertical hatching may be doped differently from the first type doped region 290. In one example, if the first type doped region 290 is p-type, then the second type doped region 295 may be n-type. In other embodiments, the first and second type doped regions 290, 295 may be doped with the same type of dopant, but to different levels (e.g., light n-type doping and heavy n-type doping). In some examples, the second fin 255 may include both the first type doped region 290 and the second type doped region 295. The first fin 260 may also include the second type doped region 295.

[0037] As previously mentioned Figure 1As described, the first type doped region 290 of the second fin 255 may form at least a portion of the substrate link 250. The substrate link 250 may further include an epitaxial layer disposed on the first type doped region 290 of the second fin 255. The second type doped region 295 of the second fin 255 may form at least a portion of the source region 245. The source region 245 may further include an epitaxial layer disposed on the second type doped region 295 of the second fin 255. The second type doped region 295 of the first fin 260 may form at least a portion of the drain region 235. The drain region 235 may similarly include an epitaxial layer disposed on the second type doped region 295 of the first fin 260.

[0038] In some other embodiments, the FinFET 200 may further include a bridge 265. The bridge 265 may be a conductive structure (e.g., a metal or other conductive material) configured to couple the source region 245 to the substrate connection 250. In various embodiments, the bridge 265 may be disposed on at least a portion of the source region 245. In some instances, the epitaxial layer of the source region may form at least a portion of a source electrode connected to one or more source regions of one or more corresponding fins. Thus, in some instances, the bridge 265 may be disposed on at least a portion of the source electrode. In some other instances, the bridge 265 may be further disposed on at least a portion of the substrate connection 250. In various embodiments, the bridge 265 is configured to provide a direct connection between the source region 245 and the substrate connection 250, eliminating the need for a separate guard ring, and achieving additional space savings.

[0039] Figure 3 3 is a schematic top view of an LDMOS FinFET array 300 according to various embodiments. The array 300 includes one or more fingers 305a-305m of LDMOS FinFET devices as described above, totaling m fingers, where m is an integer. Each finger 305a-305m may respectively include a stack of n FinFET devices, where n is an integer. Spacers may be utilized to separate the stacked FinFET devices within respective fingers and further between FinFET devices of directly adjacent fingers. In some examples, the spacers include metal oxide and / or other dielectric spacers.

[0040] In some examples, the FinFET devices of adjacent fingers may have flipped orientations (e.g., source-gate-drain for the FinFET device in a first finger, and drain-gate-source for the FinFET device in an adjacent finger). The substrate connections 310a-310n, 320a-320n may be disposed at both ends of the array (e.g., first end 315a and second end 315b). For example, in NLDMOS, p + The substrate connection can be directly placed on the+ At the end on the source region side, the need for a guard ring surrounding the entire array 300 is eliminated.

[0041] Figure 4 Two graphs illustrating IV characteristics of an area efficient LDMOS FinFET according to various embodiments. The first graph 400A depicts drain characteristics of an area efficient LDMOS FinFET relative to an LDMOS FinFET utilizing a conventional guard ring and a conventional substrate tie structure, wherein the characteristics are gate to source (V gs ) values. The second graph 400B depicts the I of the area efficient LDMOS FinFET relative to the LDMOS FinFET using a conventional guard ring and a conventional substrate connection structure. d / V g transfer characteristics, where the characteristics are from drain to source (V ds ) values ​​similarly overlap.

[0042] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may instead be implemented in any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context indicates otherwise, according to several embodiments, this functionality may be distributed throughout various other system components.

[0043] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context indicates otherwise. In addition, the procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized into alternative structural architectures and / or incorporated into other described systems. Therefore, although those embodiments are described with or without some features for ease of description and in order to illustrate aspects of various embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments unless the context indicates otherwise. Therefore, although several embodiments are described above, it will be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: a substrate having a first doping, the substrate comprising a first well having a second doping and a second well having a third doping; a fin disposed on the substrate; a gate disposed on the fin; a first epitaxial layer having the second doping, wherein the first epitaxial layer is disposed on a first region of the fin and at least a portion of the second well of the substrate; and A second epitaxial layer has the third doping, wherein the second epitaxial layer is disposed on a second region of the fin and at least a portion of the second well of the substrate.

2. The device of claim 1 , wherein the first epitaxial layer is a source electrode, the device further comprising: A bridge is disposed on at least a portion of the source electrode, the bridge being configured to couple the source electrode to the second epitaxial layer. 3 . The apparatus of claim 1 , wherein the fin extends in a first direction, and the first and second epitaxial layers extend longitudinally in a second direction different from the first direction. 4 . The apparatus of claim 3 , further comprising one or more fins including the fin, wherein the first epitaxial layer and the second epitaxial layer traverse each of the one or more fins.

5. The apparatus of claim 1, wherein the first epitaxial layer has a first side in contact with the gate and a second side in contact with a dummy dielectric layer, and wherein the second epitaxial layer is separated from the first epitaxial layer by the dummy dielectric layer.

6. The apparatus of claim 1, wherein the first and third doping are p-type doping, and the second doping is n-type doping. The apparatus of claim 4 , wherein the second epitaxial layer is doped with boron.

8. The apparatus of claim 4, wherein the second epitaxial layer is doped with phosphorus.

9. The apparatus of claim 1, wherein the second epitaxial layer is a p-type doped substrate link.

10. A device comprising: One or more fins, which are formed of a semiconductor material and disposed on the substrate and extend in a first direction, wherein the one or more fins include an undoped region, a first doped region, and a second doped region; a gate at least partially disposed on the one or more fins, the gate extending across the one or more fins in a second direction; a dummy gate disposed on the one or more fins, the dummy gate extending in the second direction, wherein the dummy gate has a first side facing the gate and a second side facing away from the gate; wherein the first doped region is disposed between the gate and the dummy gate, wherein the first doped region has a second doping; and The second doped region is disposed on the second side of the dummy gate, wherein the second doped region has a third doping. 11 . The apparatus of claim 10 , further comprising a first epitaxial layer disposed on the first doped region and a second epitaxial layer disposed on the second doped region, wherein the first and second epitaxial layers are disposed on the one or more fins and at least a portion of the substrate. 12 . The apparatus of claim 10 , wherein the second doping is an n-type doping, wherein the third doping is a p-type doping.

13. The apparatus of claim 10, wherein the second doped region is a substrate bond. The device of claim 10 , wherein the second doped region is doped with boron.

15. The apparatus of claim 10, further comprising: A bridge is configured to couple the first doped region to the second doped region.

16. An apparatus comprising: a substrate having a first doping, the substrate comprising a first well having a second doping and a second well having a third doping; a fin disposed on the substrate, wherein the fin is positioned above the first well and extends at least partially above the second well, wherein the fin comprises: a first doped region disposed on the first well and having the second doping; and A second doped region disposed on the first well has the third doping. 17 . The apparatus of claim 16 , wherein the fin further comprises a first epitaxial structure disposed on the first doped region and a second epitaxial structure disposed on the second doped region.

18. The apparatus of claim 16, wherein the first and second doping are p-type doping, wherein the third doping is n-type doping. The device of claim 16 , wherein the first doped region is doped with boron.

20. The apparatus of claim 16, wherein the first doped region is a substrate link having a third doping, wherein the third doping is lighter than the second doping and equal to or heavier than the first doping.

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