Trench gate LDMOS structure and preparation method thereof
By forming inverted L-type gate trench in the LDMOS structure, the problems of high etching process difficulty and lithography accuracy requirements in the prior art are solved, and the effect of reducing etching difficulty and lithography accuracy requirements is achieved.
Patent Information
- Application Number
- CN202411874372.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-04-18
AI Technical Summary
In the prior art, the "T" type trench gate LDMOS structure increases the difficulty of the etching process, resulting in high dependence on high-precision lithography machines, thereby increasing manufacturing costs.
By expanding the key size of the gate trench from the deep trench region to the part of the first conductive type well region connected thereto, an inverted L-type gate trench is formed, which reduces the difficulty of etching, and reduces the accuracy requirements for the lithography machine due to the increase in the diameter size of the part on the gate structure when electrically deduced.
The process window when etching and forming gate trenches is effectively increased, the etching difficulty is reduced, the accuracy requirements for lithography machines are reduced, and the incision accuracy is reduced when forming electrode holes on the gate structure are reduced.
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Figure CN119855217A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a trench gate LDMOS structure and a preparation method thereof. Background Art
[0002] Trench LDMOS has shown significant advantages in the field of power management due to its high integration and current carrying capacity, low on-resistance, fast switching performance, high reliability, low noise, and miniaturization and light weight. Figure 1 As shown, the currently optimized Trench LDMOS structure has a "T"-shaped trench gate, specifically a trench gate structure 20 of the LDMOS structure formed in an insulating deep trench 21. This design not only reduces energy loss and improves efficiency, but also enhances the durability and reliability of the device by improving thermal characteristics. Although the manufacturing process is relatively complex, the high efficiency and high reliability of Trench LDMOS reduce the overall system cost, improve the economy and application range, especially in applications that pursue high efficiency and compact design, such as switching power supplies, DC / DC converters and motor drives, etc., and have become the preferred semiconductor device.
[0003] With the miniaturization and integration of semiconductor devices, Figure 2 As shown, the optimized Trench LDMOS structure places higher requirements on the etching process when forming a gate trench (Trench Gate) 22 with a smaller CD; in addition, as Figure 3 As shown, accordingly, when the trench gate structure 20 is electrically led out, the lead-out electrode hole 23 with a smaller CD also places high demands on the photolithography process; furthermore, the trench gate structure 20 with a small CD also places higher demands on the overlay accuracy during the subsequent electrical lead-out of the trench gate structure, thereby making the preparation of the entire structure highly dependent on a high-precision photolithography machine, thereby increasing the manufacturing cost. Summary of the invention
[0004] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a trench gate LDMOS structure and a preparation method thereof, so as to solve the problem that the “T”-type trench gate LDMOS structure in the prior art increases the difficulty of the etching process and has a high dependence on a high-precision lithography machine, thereby increasing the manufacturing cost.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a trench gate LDMOS structure, the method comprising the following steps:
[0006] Providing a semiconductor substrate, the semiconductor substrate comprising a first conductivity type well region extending inwardly from an upper surface of the semiconductor substrate;
[0007] forming a deep trench extending inward from an upper surface of the first conductive type well region in the first conductive type well region;
[0008] Performing ion implantation on the sidewalls and bottom wall of the deep trench to form a first conductive type doped layer on the surface of the deep trench;
[0009] Filling at least the deep trench with insulating material;
[0010] Etch the insulating material in the partial area of the sidewall of the deep trench from top to bottom to a first preset depth and etch the partial area of the first conductive type well region connected to the partial area of the sidewall of the deep trench from top to bottom to a second preset depth, wherein the second preset depth is less than the first preset depth, to form an inverted L-shaped gate trench;
[0011] forming a gate dielectric layer and a gate conductive layer in the gate trench in sequence to form a gate structure;
[0012] A second conductive type source doping layer and a second conductive type drain doping layer are respectively formed in the first conductive type well regions on both sides of the deep trench, wherein the second conductive type source doping layer is close to one side of the gate structure, the second conductive type drain doping layer is far away from one side of the gate structure, and the first conductive type is opposite to the second conductive type;
[0013] An electrode lead-out structure is formed to electrically lead out the gate structure, the second conductivity type source doped layer, and the second conductivity type drain doped layer respectively.
[0014] Optionally, the diameter of the upper portion of the gate trench is not less than 0.1 μm, and the second preset depth is not less than
[0015] Optionally, before forming the first conductive type doping layer, the method further includes forming a pad oxide layer on the surface of the deep trench.
[0016] Optionally, after at least filling the deep trench with insulating material, the method further includes a step of planarizing the insulating material, wherein the insulating material after planarization is higher than a preset thickness on the surface of the semiconductor substrate, and the insulating material of the preset thickness serves as a hard mask layer.
[0017] Furthermore, the method for forming the gate trench includes:
[0018] forming a hard mask layer and a photoresist layer in sequence on the surface of the semiconductor substrate;
[0019] Patterning the hard mask layer by a photolithography process to form a patterned hard mask layer, wherein the patterned hard mask layer exposes the surface of the insulating material in a partial area of the deep trench sidewall and a partial area of the first conductive type well region connected to the partial area of the deep trench sidewall;
[0020] The insulating material and the first conductive type well region are etched correspondingly using the patterned photoresist layer and the patterned hard mask layer as masks to form the gate trench.
[0021] Furthermore, the method for forming the gate structure includes:
[0022] Forming the gate dielectric layer on the surface of the gate trench by a thermal oxidation process;
[0023] Forming a gate conductive layer on the gate dielectric layer that at least fills the gate trench by a CVD deposition process;
[0024] The gate conductive layer is ground by using a CMP process, and after grinding, the upper surface of the gate conductive layer is lower than the upper surface of the first conductive type well region.
[0025] Furthermore, after forming the gate structure, the method further includes forming an insulating coating layer covering the gate structure on the surface of the semiconductor substrate.
[0026] Furthermore, the semiconductor substrate also includes a second conductive type well region extending inward from the upper surface of the semiconductor substrate, wherein the second conductive type well region is connected to the first conductive type well region; after forming the insulating coating layer, it also includes the step of forming a shallow trench isolation structure in the second conductive type well region.
[0027] The present invention further provides a trench gate LDMOS structure, the trench gate LDMOS structure comprising:
[0028] A semiconductor substrate, the semiconductor substrate comprising a first conductivity type well region extending inwardly from an upper surface of the semiconductor substrate;
[0029] A deep trench extending inward from an upper surface of the first conductive type well region;
[0030] a first conductive type doped layer formed on the surface of the deep trench;
[0031] A gate structure composed of a gate dielectric layer and a gate conductive layer, wherein a portion of the gate structure is formed at a first preset depth in a partial region of a sidewall of the deep trench, and another portion of the gate structure is formed at a second preset depth in a partial region of a well region of the first conductivity type that is connected to the partial region of the sidewall of the deep trench;
[0032] Insulating material, at least filling the deep trench except the gate structure;
[0033] A source doping layer of a second conductivity type and a drain doping layer of a second conductivity type, wherein the source doping layer of the second conductivity type is close to one side of the gate structure, the drain doping layer of the second conductivity type is far away from one side of the gate structure, and the first conductivity type is opposite to the second conductivity type;
[0034] The electrode lead-out structure electrically leads out the gate structure, the second conductivity type source doping layer and the second conductivity type drain doping layer.
[0035] Optionally, the aperture of the upper portion of the gate structure is not less than 0.1 μm, and the second preset depth is not less than
[0036] As described above, the trench gate LDMOS structure and preparation method thereof of the present invention, by expanding the critical dimension (CD) of the gate trench from the deep trench area to the partial area of the first conductive type well region connected thereto, thereby forming an inverted L-shaped gate trench, effectively increasing the process window when etching to form the gate trench and reducing the etching difficulty; in addition, based on the inverted L-shaped gate trench, the formed gate structure is also inverted L-shaped as a whole, so that when the gate structure is electrically led out, due to the increase in the aperture size of the upper part of the gate structure, the lithography process window for forming the lead-out electrode hole on the gate structure is effectively increased, thereby reducing the accuracy requirements for the lithography machine and simultaneously reducing the overlay accuracy when forming the lead-out electrode hole on the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 A schematic diagram of a cross-sectional structure of a trench LDMOS structure is shown as an example.
[0038] Figure 2 Display as Figure 1 Schematic diagram of the cross-sectional structure of the gate trench formed during the preparation process of the Trench LDMOS structure.
[0039] Figure 3 Display as Figure 1 Schematic diagram of the cross-sectional structure of the lead-out electrode hole formed during the preparation process of the Trench LDMOS structure.
[0040] Figures 4 to 19 It shows the cross-sectional structure schematic diagram of each step in the preparation process of the trench gate LDMOS structure of the present invention.
[0041] Component number description
[0042] 10 Semiconductor substrate
[0043] 100 First conductivity type well region
[0044] 101 second conductivity type well region
[0045] 102 Deep Groove
[0046] 103 Oxygen cushion layer
[0047] 104 first conductive type doped layer
[0048] 105 Insulation material
[0049] 106 Hard mask layer
[0050] 107 Photoresist layer
[0051] 108 Patterned hard mask layer
[0052] 11 Gate structure
[0053] 110 Gate trench
[0054] 111 Gate dielectric layer
[0055] 112 gate conductive layer
[0056] 12 Insulation coating
[0057] 13 Shallow Trench Isolation Structure
[0058] 14. Source doping layer of the second conductivity type
[0059] 15. Drain doping layer of the second conductivity type
[0060] 16 Electrode lead structure
[0061] 17 Dielectric layer
[0062] 160 Lead electrode hole
[0063] 20 Trench gate structure
[0064] 21 Insulation deep trench
[0065] 22 Gate trench
[0066] 23 Lead electrode hole DETAILED DESCRIPTION
[0067] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0068] Please refer to 4 to Fig.19 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0069] This embodiment provides a method for preparing a trench gate LDMOS structure, the method comprising the following steps:
[0070] S1, providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conductivity type well region extending inwardly from an upper surface of the semiconductor substrate;
[0071] S2, forming a deep trench extending inward from an upper surface of the first conductive type well region in the first conductive type well region;
[0072] S3, performing ion implantation on the sidewalls and bottom wall of the deep trench to form a first conductive type doping layer on the surface of the deep trench;
[0073] S4, filling at least the deep trench with an insulating material;
[0074] S5, etching the insulating material in the partial area of the sidewall of the deep trench from top to bottom to a first preset depth and etching the partial area of the first conductive type well region connected to the partial area of the sidewall of the deep trench from top to bottom to a second preset depth, wherein the second preset depth is less than the first preset depth, to form an inverted L-shaped gate trench;
[0075] S6, sequentially forming a gate dielectric layer and a gate conductive layer in the gate trench to form a gate structure;
[0076] S7, forming a second conductivity type source doping layer and a second conductivity type drain doping layer in the first conductivity type well regions on both sides of the deep trench, respectively, wherein the second conductivity type source doping layer is close to one side of the gate structure, the second conductivity type drain doping layer is far away from one side of the gate structure, and the first conductivity type is opposite to the second conductivity type;
[0077] S8, forming an electrode lead-out structure to electrically lead out the gate structure, the second conductivity type source doping layer, and the second conductivity type drain doping layer respectively.
[0078] The preparation method of the trench gate LDMOS structure of the present embodiment forms an inverted L-shaped gate trench by expanding the critical dimension (CD) of the gate trench from the deep trench area to a partial area of the first conductive type well region connected thereto, thereby effectively increasing the process window when etching to form the gate trench and reducing the etching difficulty; in addition, based on the inverted L-shaped gate trench, the formed gate structure is also inverted L-shaped as a whole, so that when the gate structure is electrically led out, due to the increase in the aperture size of the upper part of the gate structure, the lithography process window for forming the lead-out electrode hole on the gate structure is effectively increased, thereby reducing the accuracy requirements for the lithography machine and simultaneously reducing the overlay accuracy when forming the lead-out electrode hole on the gate structure.
[0079] The method for preparing the trench gate LDMOS structure of this embodiment is described in detail below with reference to the specific drawings.
[0080] like Figure 4 As shown, step S1 is first performed to provide a semiconductor substrate 10 , wherein the semiconductor substrate 10 includes a first conductivity type well region 100 extending inwardly from an upper surface of the semiconductor substrate 10 .
[0081] The semiconductor substrate 10 may be a semiconductor substrate such as silicon, silicon germanium or silicon carbide, or a semiconductor substrate on which an epitaxial layer has been grown. The semiconductor substrate may be an intrinsic semiconductor substrate or a doped semiconductor substrate. When the semiconductor substrate 10 is a doped semiconductor substrate, the doping type is set according to the type of LDMOS to be formed. For example, when a P-type LDMOS needs to be formed, the semiconductor substrate 10 is a P-type doped semiconductor substrate; when an N-type LDMOS needs to be formed, the semiconductor substrate 10 is an N-type doped semiconductor substrate. In this embodiment, the semiconductor substrate 10 is selected as a silicon substrate.
[0082] As an example, the first conductive type well region 100 can be formed by ion implantation diffusion, and the first conductive type can be P-type or N-type, which is opposite to the doping type of the semiconductor substrate 10. For example, when the semiconductor substrate 10 is a P-type doped semiconductor substrate, the first conductive type well region 100 is an N-type well region; when the semiconductor substrate 10 is an N-type doped semiconductor substrate, the first conductive type well region 100 is a P-type well region.
[0083] As an example, Figure 4As shown, a terminal protection structure is generally formed at the periphery of the device region, so the semiconductor substrate 10 also includes a second conductivity type well region 101 connected to the first conductivity type well region 100, so as to form a required terminal protection structure in the second conductivity type well region 101. The second conductivity type well region 101 can also be formed by ion implantation diffusion. The first conductivity type is opposite to the second conductivity type, that is, when the first conductivity type is N type, the second conductivity type is P type; when the first conductivity type is P type, the second conductivity type is N type.
[0084] like Figure 5 As shown, step S2 is then performed to form a deep trench 102 extending inward from the upper surface of the first conductive type well region 100 in the first conductive type well region 100 .
[0085] The specific parameters of the deep groove 102 , such as depth and width, are not overly restricted and are selected according to actual needs.
[0086] As a specific example, the method for forming the deep groove 102 includes: first, forming a hard mask layer and a photoresist layer in sequence on the surface of the semiconductor substrate 10; then, photolithography patterning the photoresist layer; then, etching the hard mask layer based on the patterned photoresist layer to obtain a patterned hard mask layer; then, etching the exposed semiconductor substrate 10 based on the patterned hard mask layer to obtain the deep groove 102; and finally, removing the patterned hard mask layer.
[0087] As an example, in order to reduce the problem of local electric field concentration in the subsequent LDMOS device, the corners of the formed deep trench 102 may be rounded.
[0088] like Figure 7 As shown, step S3 is then performed to perform ion implantation on the sidewalls and bottom wall of the deep trench 102 to form a first conductive type doped layer 104 on the surface of the deep trench 102. The first conductive type doped layer 104 is subsequently used as a drift region and a channel region of the LDMOS structure.
[0089] like Figure 6As shown, as an example, before forming the first conductive type doping layer 104, a pad oxide layer 103 can be formed on the surface of the deep groove 102. For example, the pad oxide layer 103 can be formed by a chemical vapor deposition process (Chemical Vapor Deposition, CVD) process or a thermal oxidation process. When the semiconductor substrate 10 is selected as a silicon substrate in this embodiment, the pad oxide layer 103 is a silicon oxide pad oxide layer. The pad oxide layer 103 can be used as a surface barrier layer when ion implantation is used to form the first conductive type doping layer 104, so as to effectively reduce the tunneling effect during ion implantation and ensure the uniformity of ion implantation. Preferably, the pad oxide layer 103 is formed by a thermal oxidation process. On the one hand, it can be used as a surface barrier layer when ion implantation is used to form the first conductive type doping layer 104. In addition, the pad oxide layer 103 formed by the thermal oxidation process can repair the surface damage caused when the deep groove 102 is etched.
[0090] As an example, when the first conductive type doping layer 104 is of N-type conductive type, the doping ions may be N-type conductive ions such as P and As; when the first conductive type doping layer 104 is of P-type conductive type, the doping ions may be P-type conductive ions such as B and Al.
[0091] like Figure 8 As shown, step S4 is then performed to fill at least the deep trench 102 with an insulating material 105 .
[0092] The deep trench 102 may be filled with a CVD process or a HARP (High Aspct Ratio Process) process having a strong hole filling capability. The insulating material 105 may be any suitable insulating filling material. When the semiconductor substrate 10 of this embodiment is a silicon substrate, the insulating material is preferably a silicon oxide material.
[0093] like Fig. 9 As shown, as an example, after the insulating material 105 is used to at least fill the deep trench 102, the insulating material 105 can be planarized to facilitate subsequent processes. For example, a chemical mechanical polishing (CMP) process can be used for planarization. After the insulating material 105 is planarized, the surface of the insulating material 105 can be flush with the surface of the semiconductor substrate 10, or it can be higher than the surface of the semiconductor substrate 10 by a preset thickness (such as Fig. 9 In this embodiment, after planarization, the surface of the insulating material 105 is preferably higher than the surface of the semiconductor substrate 10 by a preset thickness. The insulating material of the preset thickness can be directly used as a hard mask layer for subsequent etching to form a gate trench, thereby saving process steps and reducing manufacturing costs.
[0094] like Fig.12 As shown, step S5 is then performed to etch the insulating material 105 in the partial area of the side wall of the deep trench 102 from top to bottom to a first preset depth and to etch the partial area of the first conductive type well region 100 connected to the partial area of the side wall of the deep trench 102 from top to bottom to a second preset depth, wherein the second preset depth is less than the first preset depth, to form an inverted L-shaped gate trench 110.
[0095] It should be noted that the overall shape of the gate trench 110 is an inverted L-shape. As the gate trench 110 is located at the sidewalls of the deep trench 102 in different directions, the inverted L-shape of the gate trench 110 changes accordingly, such as Fig.12 As shown in FIG. 1 , the gate trench 110 is located on the right side wall of the deep trench 102, and the shape of the gate trench 110 is similar to a “Γ” shape; similarly, when the gate trench 110 is located on the left side wall of the deep trench 102, the shape of the gate trench 110 is similar to type.
[0096] like Fig.12 As shown, in this step, the shape of the gate trench 110 is set to an inverted L-shape, and the diameter L of the upper part of the gate trench 110 is significantly increased, thereby effectively increasing the etching process window when etching to form the gate trench 110, and reducing the difficulty of etching. In addition, when etching to form the gate trench 110, the depth ratio of "│" to "─" in the inverted L-shaped gate trench 110 can be achieved by adjusting the etching selectivity of the insulating material 105 and the semiconductor substrate material.
[0097] like Fig.12 As shown, as an example, the diameter L of the upper portion of the gate groove is not less than 0.1 μm. In addition, in order to ensure that the over-etching of the lead-out electrode hole will not penetrate the gate structure during the subsequent process of preparing the electrode lead-out structure of the gate structure, the second preset depth, that is, the depth of the "─" portion in the gate groove 110 is not less than
[0098] As a specific example, the method for forming the gate trench 110 includes the following steps:
[0099] S51, such as Fig. 9As shown, first, a hard mask layer 106 is formed on the surface of the semiconductor substrate 10; it should be noted here that after the insulating material 105 is planarized in step S4, if the surface of the insulating material 105 is flush with the surface of the semiconductor substrate 10, then in this step, a hard mask layer 106 needs to be re-formed on the surface of the semiconductor substrate 10; if the surface of the insulating material 105 is higher than the preset thickness of the surface of the semiconductor substrate 10 after the insulating material 105 is planarized, then the insulating material 105 of the preset thickness is directly used as the hard mask layer 106 of this step.
[0100] S52, such as Fig.10 and Fig.11 As shown, a patterned photoresist layer 107 (eg, Fig.10 As shown), and based on the patterned photoresist layer 107, the hard mask layer 106 is etched to form a patterned hard mask layer 108 (as shown Fig.11 As shown), the patterned hard mask layer 108 exposes the surface of the insulating material 105 in a partial area of the deep trench sidewall and a partial area of the first conductive type well region 100 connected to a partial area of the deep trench sidewall; this step can also effectively reduce the accuracy requirements for the lithography machine.
[0101] S53, such as Fig.12 As shown, the corresponding insulating material 105 and the first conductive type well region 100 are then etched using the patterned photoresist layer 107 and the patterned hard mask layer 108 as masks to form the gate trench 110; finally, the patterned photoresist layer 107 is removed.
[0102] like Fig.14 As shown, step S6 is then performed to sequentially form a gate dielectric layer 111 and a gate conductive layer 112 in the gate trench 110 to form a gate structure 11 .
[0103] When the semiconductor substrate 10 of the present embodiment is a silicon substrate, the gate dielectric layer 111 is a silicon oxide gate dielectric layer, preferably formed by a thermal oxidation process, and the gate conductive layer 112 is a polysilicon gate conductive layer.
[0104] As a specific example, the method for forming the gate structure 11 includes the following steps:
[0105] S61, such as Fig.13 As shown, firstly, the gate dielectric layer 111 is formed on the surface of the gate trench 110 by using a thermal oxidation process.
[0106] S62, such as Fig.13As shown, a gate conductive layer 112 which at least fills the gate trench 110 is formed on the gate dielectric layer 111 by a CVD deposition process.
[0107] S63, such as Fig.14 As shown, the gate conductive layer 112 is ground by using a CMP process, and after grinding, the upper surface of the gate conductive layer 112 is lower than the upper surface of the first conductive type well region 100 .
[0108] like Fig.15 As shown, further, after forming the gate structure 11, the step of forming an insulating coating layer 12 on the surface of the semiconductor substrate to cover the gate structure 11 is also included. Preferably, the material of the insulating coating layer 12 is the same as the insulating material 105, for example, both are silicon oxide materials.
[0109] like Fig.16 As shown, further, after forming the insulating coating layer 12, the step of forming a shallow trench isolation structure 13 in the second conductive type well region 101 is also included; as mentioned above, since after step S63, the upper surface of the gate conductive layer 112 is lower than the upper surface of the first conductive type well region 100, the surface of the gate structure 11 is not easily damaged during the planarization process of the isolation material filled in the shallow trench isolation structure 13.
[0110] like Fig.17 As shown, step S7 is then performed to form a second conductive type source doping layer 14 and a second conductive type drain doping layer 15 in the first conductive type well region 100 on both sides of the deep trench, respectively, wherein the second conductive type source doping layer 14 is close to one side of the gate structure 11, and the second conductive type drain doping layer 15 is far away from one side of the gate structure 11, and the first conductive type is opposite to the second conductive type.
[0111] like Fig.18 and Fig.19 As shown, step S8 is finally performed to form an electrode lead-out structure 16 to electrically lead out the gate structure 11 , the second conductivity type source doped layer 14 , and the second conductivity type drain doped layer 15 .
[0112] As a specific example, the method of forming the electrode lead-out structure 16 includes:
[0113] S81, such as Fig.18 As shown, firstly, a dielectric layer 17 is formed on the insulating coating layer 12, and the dielectric layer 17 is planarized.
[0114] S82, such as Fig.18As shown, the dielectric layer 17 is then photoetched to form a lead-out electrode hole 160 in the corresponding areas of the gate structure 11, the second conductive type source doping layer 14 and the second conductive type drain doping layer 15; as described above, based on the inverted L-shaped gate groove 110, the formed gate structure 11 is also an inverted L-shape as a whole, so that in the photolithography process of this step, due to the increase in the aperture size of the upper part of the gate structure 11, the photolithography process window of the lead-out electrode hole 160 can be effectively increased, thereby reducing the accuracy requirements for the photolithography machine, and at the same time, it can also reduce the overlay accuracy of the lead-out electrode hole 160 formed on the gate structure 11.
[0115] S83, such as Fig.19 As shown, the lead-out electrode hole 160 is then filled with a conductive metal material, and the conductive metal material is planarized to remove the conductive metal material outside the lead-out electrode hole 160 to obtain the electrode lead-out structure 16 .
[0116] This embodiment also provides a trench gate LDMOS structure, which can be prepared by the preparation method described above, but is not limited thereto, and any other suitable preparation method can also be used, as long as the trench gate LDMOS structure can be obtained. When the preparation method described in this embodiment is used to prepare the trench gate LDMOS structure, the beneficial effects that can be achieved can be found in the detailed description of the above preparation method, and will not be repeated below.
[0117] like Fig.19 As shown, the trench gate LDMOS structure includes:
[0118] A semiconductor substrate 10, wherein the semiconductor substrate 10 comprises a first conductivity type well region 100 extending inwardly from an upper surface of the semiconductor substrate;
[0119] Deep trench 102 (eg Figure 5 As shown), the deep trench 102 extends inward from the upper surface of the first conductive type well region 100;
[0120] A first conductive type doped layer 104 formed on the surface of the deep trench 102;
[0121] A gate structure 11 composed of a gate dielectric layer 111 and a gate conductive layer 112, wherein a portion of the gate structure 11 is formed in a partial region of a sidewall of the deep trench 102 at a first preset depth, and another portion of the gate structure 11 is formed in a partial region of the first conductive type well region 100 connected to a partial region of the sidewall of the deep trench at a second preset depth;
[0122] An insulating material 105 at least fills the deep trench 102 except the gate structure 11;
[0123] A second conductive type source doping layer 14 and a second conductive type drain doping layer 15, wherein the second conductive type source doping layer 14 is close to one side of the gate structure 11, the second conductive type drain doping layer 15 is far away from one side of the gate structure 11, and the first conductive type is opposite to the second conductive type;
[0124] The electrode lead-out structure 16 electrically leads out the gate structure 11 , the second conductivity type source doping layer 14 , and the second conductivity type drain doping layer 15 .
[0125] As an example, the diameter of the upper portion of the gate structure 11 is not less than 0.1 μm, and the second preset depth is not less than
[0126] In summary, the present invention provides a trench gate LDMOS structure and a preparation method thereof, by expanding the critical dimension (CD) of the gate trench from the deep trench area to the first conductive type well area connected thereto, thereby forming an inverted L-shaped gate trench, effectively increasing the process window when etching to form the gate trench, and reducing the etching difficulty; in addition, based on the inverted L-shaped gate trench, the formed gate structure is also inverted L-shaped as a whole, so that when the gate structure is electrically led out, due to the increase in the aperture size of the upper part of the gate structure, the photolithography process window for forming the lead-out electrode hole on the gate structure is effectively increased, thereby reducing the precision requirements for the photolithography machine, and at the same time reducing the overlay precision when forming the lead-out electrode hole on the gate structure. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0127] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a trench gate LDMOS structure, characterized in that: The preparation method comprises the following steps: Providing a semiconductor substrate, the semiconductor substrate comprising a first conductivity type well region extending inwardly from an upper surface of the semiconductor substrate; forming a deep trench extending inward from an upper surface of the first conductive type well region in the first conductive type well region; Performing ion implantation on the sidewalls and bottom wall of the deep trench to form a first conductive type doped layer on the surface of the deep trench; Filling at least the deep trench with insulating material; Etch the insulating material in the partial area of the sidewall of the deep trench from top to bottom to a first preset depth and etch the partial area of the first conductive type well region connected to the partial area of the sidewall of the deep trench from top to bottom to a second preset depth, wherein the second preset depth is less than the first preset depth, to form an inverted L-shaped gate trench; forming a gate dielectric layer and a gate conductive layer in the gate trench in sequence to form a gate structure; A second conductive type source doping layer and a second conductive type drain doping layer are respectively formed in the first conductive type well regions on both sides of the deep trench, wherein the second conductive type source doping layer is close to one side of the gate structure, the second conductive type drain doping layer is far away from one side of the gate structure, and the first conductive type is opposite to the second conductive type; An electrode lead-out structure is formed to electrically lead out the gate structure, the second conductivity type source doped layer, and the second conductivity type drain doped layer respectively.
2. The method for preparing a trench gate LDMOS structure according to claim 1, characterized in that: The diameter of the upper portion of the gate trench is not less than 0.1 μm, and the second preset depth is not less than 3. The method for preparing a trench gate LDMOS structure according to claim 1, characterized in that: Before forming the first conductive type doped layer, the method further includes forming a pad oxide layer on the surface of the deep trench.
4. The method for preparing a trench gate LDMOS structure according to claim 1, characterized in that: After the deep trench is at least filled with insulating material, the step of planarizing the insulating material is further included. The insulating material after planarization is higher than a preset thickness on the surface of the semiconductor substrate. The insulating material of the preset thickness serves as a hard mask layer.
5. The method for preparing a trench gate LDMOS structure according to any one of claims 1 to 4, characterized in that: The method of forming the gate trench comprises: forming a hard mask layer and a photoresist layer in sequence on the surface of the semiconductor substrate; Patterning the hard mask layer by a photolithography process to form a patterned hard mask layer, wherein the patterned hard mask layer exposes the surface of the insulating material in a partial area of the deep trench sidewall and a partial area of the first conductive type well region connected to the partial area of the deep trench sidewall; The insulating material and the first conductive type well region are etched correspondingly using the patterned photoresist layer and the patterned hard mask layer as masks to form the gate trench.
6. The method for preparing a trench gate LDMOS structure according to claim 5, characterized in that: The method of forming the gate structure includes: Forming the gate dielectric layer on the surface of the gate trench by a thermal oxidation process; Forming a gate conductive layer on the gate dielectric layer that at least fills the gate trench by a CVD deposition process; The gate conductive layer is ground by using a CMP process, and after grinding, the upper surface of the gate conductive layer is lower than the upper surface of the first conductive type well region.
7. The method for preparing a trench gate LDMOS structure according to claim 6, characterized in that: After forming the gate structure, the method further includes forming an insulating coating layer covering the gate structure on the surface of the semiconductor substrate.
8. The method for preparing a trench gate LDMOS structure according to claim 7, characterized in that: The semiconductor substrate also includes a second conductive type well region extending inward from the upper surface of the semiconductor substrate, wherein the second conductive type well region is connected to the first conductive type well region; after forming the insulating coating layer, the step of forming a shallow trench isolation structure in the second conductive type well region is also included.
9. A trench gate LDMOS structure, characterized in that: The trench gate LDMOS structure comprises: A semiconductor substrate, the semiconductor substrate comprising a first conductivity type well region extending inwardly from an upper surface of the semiconductor substrate; A deep trench extending inward from an upper surface of the first conductive type well region; a first conductive type doped layer formed on the surface of the deep trench; A gate structure composed of a gate dielectric layer and a gate conductive layer, wherein a portion of the gate structure is formed at a first preset depth in a partial region of the deep trench sidewall, and another portion of the gate structure is formed at a second preset depth in a partial region of the first conductive type well region connected to the partial region of the deep trench sidewall; Insulating material, at least filling the deep trench except the gate structure; A source doping layer of a second conductivity type and a drain doping layer of a second conductivity type, wherein the source doping layer of the second conductivity type is close to one side of the gate structure, the drain doping layer of the second conductivity type is far away from one side of the gate structure, and the first conductivity type is opposite to the second conductivity type; The electrode lead-out structure electrically leads out the gate structure, the second conductivity type source doping layer and the second conductivity type drain doping layer.
10. The trench gate LDMOS structure according to claim 9, characterized in that: The diameter of the upper portion of the gate structure is not less than 0.1 μm, and the second preset depth is not less than
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Trench gate ldmos structure and fabrication method therefor
WO2026129573A1