SGT devices

Abstract

The application discloses an SGT device, a drift region, a channel region on the surface of the drift region and a plurality of gate trenches through the channel region. In the cell region, the gate trench is simultaneously formed with an anode field plate and a gate conductive material layer, and the gate conductive material layer also side covers the top region of the drift region at the bottom of the channel region. In the reverse bias, the gate conductive material layer forms the gate field plate for the lateral depletion of the top region of the drift region. In the source field plate lead-out region, the gate trench is formed with the anode field plate and no gate conductive material layer, and a first compensation region is formed at the interface region of the channel region and the bottom drift region, and the first compensation region increases the compensation injection impurities to increase the depletion capacity of the top region of the drift region. The application can ensure that the doping concentration of the drift region in the cell region is higher, thereby reducing the specific on-resistance of the device, eliminate the weakness of the top region of the drift region in the source field plate lead-out region, and thereby improve the voltage resistance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a shielded gate trench (SGT) device. Background Art

[0002] Compared with traditional trench MOSFET, SGT MOSFET adds a source field plate in the drift region. Through the lateral depletion of the drift region by the source field plate, the doping concentration of the drift region can be greatly increased without reducing the breakdown voltage, thereby reducing the specific on-resistance. At the same time, for SGT MOSFET, due to the shielding of the gate by the source field plate, its gate-drain capacitance Cgd is also greatly reduced, and its switching speed is also greatly improved.

[0003] Therefore, SGT MOSFET is replacing trench MOSFET in more and more occasions and becoming the mainstream of power devices.

[0004] The source field plate is usually located directly below the device cell of an SGT MOSFET.

[0005] like Figure 1 As shown in FIG, it is a schematic diagram of the structure of the device unit of the original cell region of the existing SGT MOSFET; Figure 2A FIG. 1 is a schematic diagram of a first structure of the lead-out region of the source field plate 104 of an existing SGT MOSFET. Taking an N-type device as an example, the existing SGT MOSFET includes:

[0006] A heavily doped N-type substrate 101, such as a silicon substrate, is connected to the drain. To minimize backdiffusion, an arsenic substrate 101 is typically used. To reduce the resistance of substrate 101, the doping concentration and thickness of substrate 101 are optimized. The thinned substrate 101 serves as the drain region. The backside of the drain region forms the drain electrode, which is composed of a backside metal layer.

[0007] The drift region 102 , the doping concentration and thickness of the drift region 102 determine the breakdown voltage of the device; the drift region 102 can be uniformly doped or variably doped.

[0008] The source field plate 104 is typically made of polysilicon.

[0009] The shielding dielectric layer 3 between the source field plate 104 and the inner surface of the gate trench is the isolation layer, and its material is usually SiO2. The depth of the source field plate 104 and the thickness of the shielding dielectric layer 3 determine the breakdown voltage of the device. The higher the breakdown voltage of the device, the deeper the source field plate 104. The depth of the source field plate 104 is the longitudinal dimension of the source field plate 104, and the thickness of the shielding dielectric layer 3 is also thicker. For a 100V SGT MOSFET, the depth of the source field plate 104 is usually between 5 and 6μm, and the thickness of the shielding dielectric layer 3 is usually between 10μm and 20μm. between.

[0010] A gate conductive material layer 105 such as a polysilicon gate and a gate oxide layer 106 are formed in the gate trench. Figure 1 In FIG, the gate structure is a top-bottom structure, the gate conductive material layer 105 is located on top of the source field plate 104, and there is an inter-gate dielectric layer 112 therebetween. The inter-gate dielectric layer 112 is usually an oxide layer.

[0011] A P-type doped channel region 107 is formed on the top of the drift region 102, and an active region 108 is formed on the top surface of the channel region 107. A contact hole, also known as a through hole (CT) 109, is formed on the top of the source region 108, passing through the interlayer film 111. The contact hole 109 on the top of the source region 108 also passes through the source region 108 and contacts the channel region 107. Usually, the location where the contact hole 109 is formed on the top of the source region 108 is in the middle of the mesa region (mesa) between the gate trenches. In order to ensure that the contact hole 109 formed on the top of the source region 108 and the channel region 107 can form a good ohmic contact, a through hole injection is usually added directly below the contact hole 109 formed on the top of the source region 108 to form a heavily doped P-type layer. The impurity injected into the through hole is usually BF2, the injection energy is between 10keV and 50keV, and the injection dose is usually 1e14cm -2 ~5e15cm -2 between.

[0012] The top of the source region 108 is formed with a contact hole 109 and is connected to the source electrode formed by the front metal layer 110. The gate conductive material layer 105 is also connected to the gate electrode (not shown) formed by the front metal layer 110. Figure 1 Only the front metal layer 110 corresponding to the source is shown, and the front metal layer 110 corresponding to the gate is not shown. Figure 1 At the corresponding cross-sectional position, when a positive voltage is applied to the gate, the channel is inverted and current flows from the source to the drain.

[0013] For SGT MOSFET, its source field plate 104 needs to be connected to the source. The source field plate 104 is usually connected in the following two ways:

[0014] likeFigure 2A As shown in FIG. 1 , it is a schematic diagram of the first structure of the source field plate lead-out region of the existing SGT MOSFET; in the source field plate lead-out region, the gate trench does not have a gate conductive material layer 105. In the first structure, the source field plate 104 and the gate field plate 105 in the source field plate lead-out region are connected. Figure 1 The source field plates 104 in the original cell region are formed using the same process, undergoing the same deposition and etching back processes, and have the same top surface position. In the source field plate lead-out region, the top area of ​​the source field plate 104 is filled with a dielectric layer 113. The dielectric layer 113 can be implemented using an interlayer film 111 or formed using a dielectric growth process independent of the interlayer film 111. The source field plate 104 in the source field plate lead-out region is connected to the source via a deep contact hole (deep CT) 114 that passes through the interlayer film 111 and the dielectric layer 113. In the source field plate lead-out region, there is usually no source implant, that is, no source region 108 is formed. The source field plate 104 in the original cell region and the source field plate 104 in the source field plate lead-out region are in contact with each other and connected to the source via the deep contact hole 114 at the top of the source field plate 104 in the source field plate lead-out region.

[0015] like Figure 2B FIG. 1 is a schematic diagram of a second structure of a source field plate lead-out region of an existing SGT MOSFET; Figure 2B In the example, the source field plate in the source field plate lead-out region is represented by a separate reference numeral 104a, and Figure 1 Unlike the source field plate 104, the top surface of the source field plate 104a is flush with the gate trench, i.e., it is not etched back below the top surface of the gate trench. In this way, the top of the source field plate 104a is directly connected to the source through a contact hole 109.

[0016] The structures of the original cell region and the source field plate lead-out region are in parallel, and both need to withstand the breakdown voltage of the device; when bearing the breakdown voltage, the source and gate are both at 0 potential; the drain is at high voltage.

[0017] In the cell region, due to the presence of the gate, the gate can also be considered to form a field plate, namely the gate field plate. The depth of the gate field plate is shallower than that of the source field plate 104. For a 100V device, the depth of the gate conductive material layer 105, that is, the longitudinal extension size, is usually between 0.6μm and 1.0μm. The thickness of the gate layer 106 is thinner than the thickness of the shielding dielectric layer 104. For a 100V device, the thickness of the gate layer 106 is usually between The gate conductive material layer 105 also has a lateral depletion effect on the drift region 102, which can reduce the electric field strength at the bottom of the channel region 107. Advances in SGT technology require continuous reductions in specific on-resistance and increases in the doping concentration of the drift region 102. The higher the doping concentration of the drift region 102, the greater the electric field strength at the bottom of the channel. As for the source field plate lead-out region, since there is no gate field plate, the electric field strength at the bottom of the channel increases, making it easier to form a weak point. Summary of the Invention

[0018] The technical problem to be solved by the present invention is to provide an SGT device that can ensure a high doping concentration in the drift region in the original cell region, thereby reducing the device's specific on-resistance, while eliminating the weakness of the top area of ​​the drift region in the source field plate lead-out region and thereby improving the device's withstand voltage.

[0019] To solve the above technical problems, the present invention provides an SGT device comprising:

[0020] A drift region doped with a first conductivity type.

[0021] A second conductivity type doped channel region is formed above the top surface of the drift region.

[0022] A plurality of gate trenches are provided, wherein the gate trenches vertically penetrate the channel region and bottom areas of the gate trenches enter the drift region.

[0023] The SGT device is divided into the primary cell region and the source field plate lead-out region.

[0024] In the primitive cell region, a source field plate and a gate conductive material layer are simultaneously formed in the gate trench, a shielding dielectric layer is separated between the source field plate and the inner surface of the corresponding gate trench, an inter-gate dielectric layer is separated between the source field plate and the gate conductive material layer, and a gate dielectric layer is separated between the gate conductive material layer and the side of the corresponding gate trench; the depth of the gate conductive material layer is greater than the depth of the channel region, and the surface of the channel region covered by the side of the gate conductive material layer is used to form a conductive channel; the gate conductive material layer also covers the top area of ​​the drift region located at the bottom of the channel region, and when reverse biased, the gate conductive material layer forms a gate field plate that laterally depletes the top area of ​​the drift region.

[0025] In the source field plate lead-out region, a source field plate is formed in the gate trench, and a shielding dielectric layer is provided between the source field plate and the inner surface of the corresponding gate trench.

[0026] The source field plate in the original cell region and the source field plate in the source field plate lead-out region are in contact and connected to a source composed of a front metal layer through a contact structure on top of the source field plate in the source field plate lead-out region.

[0027] The gate trench of the source field plate lead-out region does not include the layer of gate conductive material and thus does not have the gate field plate; a first compensation region is further included in the source field plate lead-out region, the first compensation region is located at the interface region of the channel region and the bottom of the drift region, the first compensation region has a second conductive type compensation implant impurity added, the compensation implant impurity increases the depletion capability of the channel region to the top region of the drift region to compensate for the decrease in the depletion capability of the top region of the drift region when the source field plate lead-out region does not have the gate field plate.

[0028] A further improvement is that at the interface region, the compensation implant impurity in the first compensation region is completely located in the drift region or simultaneously extends into the channel region and the drift region.

[0029] A further improvement is that the compensation implant impurity extending into the drift region reduces the net doping concentration of the first conductive type of the drift region.

[0030] A further improvement is that the ion implantation of the compensation implant impurity includes a single implantation or multiple implantations of different energies.

[0031] A further improvement is that when the ion implantation of the compensation implant impurity is a single implantation, the implantation energy includes 40keV, and the implantation dose includes 2e15cm -2 .

[0032] A further improvement is that when the ion implantation of the compensation implant impurity is multiple implantations of different energies, a combination of low-energy high-dose and high-energy low-dose is adopted, the implantation energy corresponding to the low-energy high-dose is lower than the implantation energy corresponding to the high-energy low-dose, but the implantation dose corresponding to the low-energy high-dose is higher than the implantation dose corresponding to the high-energy low-dose.

[0033] A further improvement is that the ion implantation of the compensation implant impurity is twice, the process conditions of the first implantation include an implantation energy of 40keV and an implantation dose of 1e15cm -2 , and the process conditions of the second implantation include an implantation energy of 200keV and an implantation dose of 1e12cm -2 .

[0034] A further improvement is that in the original cell region, a first conductive type heavily doped source region is self-aligned formed in the surface region of the channel region on both sides of the gate trench.

[0035] In the source field plate lead-out region, the surface region of the channel region on both sides of the gate trench is not formed with the source region.

[0036] The compensating implantation of impurities is defined by a photo mask of the source region, and the photoresist used in the compensating implantation of impurities is opposite in polarity to the photoresist used in the implantation of the source region.

[0037] Further improvement is that the top surface of the source field plate of the source field plate lead-out region is lower than the top surface of the gate trench, the gate trench above the top surface of the source field plate is filled with a first dielectric layer, an interlayer film is formed above the top surface of the gate trench, and the contact structure is a deep contact hole that penetrates through the interlayer film and the first dielectric layer.

[0038] Alternatively, the top surface of the source field plate is level with the top surface of the gate trench, an interlayer film is formed above the top surface of the gate structure, and the contact structure is a contact hole that penetrates through the interlayer film.

[0039] Further improvement is that the material of the source field plate includes polysilicon.

[0040] Further improvement is that the material of the shielding dielectric layer includes an oxide layer.

[0041] Further improvement is that, from the bottom of the gate dielectric layer, the thickness of the shielding dielectric layer is uniformly distributed or gradually reduced upwards from the bottom of the gate trench.

[0042] Further improvement is that, when the thickness of the shielding dielectric layer is gradually reduced upwards from the bottom of the gate trench, the doping concentration of the drift region is gradually increased to reduce the specific on-resistance of the device.

[0043] Further improvement is that, in the unit cell region, the gate structure is an up-down structure, and the gate conductive material layer is located on the top of the source field plate.

[0044] Alternatively, in the unit cell region, the gate structure is a left-right structure, and the gate conductive material layer is located on both sides of the top region of the source field plate.

[0045] Further improvement is that the SGT device is an SGT MOSFET, and a drain region heavily doped with the first conductivity type is formed at the bottom of the drift region.

[0046] Further improvement is that the SGT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the SGT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0047] The present invention sets a first compensation region in the source field plate lead-out region, and the first compensation region adds compensation injection impurities of the second conductive type. The compensation injection impurities can increase the depletion ability of the top region of the drift region, so as to compensate for the influence of the lack of a gate field plate in the source field plate lead-out region on the weakened depletion ability of the top region of the drift region, and can ensure that the doping concentration of the drift region in the original cell region is high while reducing the electric field strength of the top region of the drift region in the source field plate lead-out region under reverse bias, thereby eliminating the weakness of the top region of the drift region in the source field plate lead-out region caused by the high doping concentration of the drift region and the lack of a gate field plate in the source field plate lead-out region, and ultimately improving the withstand voltage of the device. Therefore, the present invention can ensure that the doping concentration of the drift region in the original cell region is high, thereby reducing the specific on-resistance of the device, while eliminating the weakness of the top region of the drift region in the source field plate lead-out region and thereby improving the withstand voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0049] Figure 1 It is a schematic diagram of the structure of the device unit of the original cell region of the existing SGT MOSFET;

[0050] Figure 2A This is a schematic diagram of the first structure of the source field plate lead-out region of the existing SGT MOSFET;

[0051] Figure 2B This is a schematic diagram of the second structure of the source field plate lead-out region of the existing SGT MOSFET;

[0052] Figure 3 1 is a schematic structural diagram of a device unit in a primitive region of an SGT device according to a first embodiment of the present invention;

[0053] Figure 4 1 is a schematic structural diagram of the source field plate lead-out region of the SGT device according to the first embodiment of the present invention;

[0054] Figure 5 1 is a schematic structural diagram of a device unit in a primary cell region of an SGT device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0055] like Figure 3 FIG. 1 is a schematic diagram showing the structure of a device unit in the primitive cell region of the SGT device according to the first embodiment of the present invention; FIG. Figure 4 FIG. 1 is a schematic structural diagram of a source field plate lead-out region of an SGT device according to a first embodiment of the present invention. The SGT device according to the first embodiment of the present invention includes:

[0056] The drift region 2 is doped with a first conductivity type.

[0057] A second conductivity type doped channel region 7 is formed on the top surface of the drift region 2 .

[0058] A plurality of gate trenches are provided, wherein the gate trenches longitudinally pass through the channel region 7 and the bottom regions of the gate trenches enter into the drift region 2 .

[0059] The SGT device is divided into the primary cell region and the source field plate lead-out region.

[0060] like Figure 3 As shown, in the original cell region, a source field plate 4 and a gate conductive material layer 5 are simultaneously formed in the gate trench, a shielding dielectric layer 3 is separated between the source field plate 4 and the inner surface of the corresponding gate trench, an inter-gate dielectric layer 12 is separated between the source field plate 4 and the gate conductive material layer 5, and a gate dielectric layer 6 is separated between the gate conductive material layer 5 and the side of the corresponding gate trench; the depth of the gate conductive material layer 5 is greater than the depth of the channel region 7, and the surface of the channel region 7 covered by the side of the gate conductive material layer 5 is used to form a conductive channel; the gate conductive material layer 5 also covers the top area of ​​the drift region 2 located at the bottom of the channel region 7. When reverse biased, the gate conductive material layer 5 forms a gate field plate that laterally depletes the top area of ​​the drift region 2, that is, at the bottom of the channel region 7, the gate conductive material layer 5 serves as a gate field plate.

[0061] In the embodiment of the present invention, the source field plate 4 is made of polysilicon. The gate conductive material layer 5 is made of polysilicon.

[0062] The material of the shielding dielectric layer 3 includes an oxide layer, and the thickness of the shielding dielectric layer 3 is uniformly distributed.

[0063] The material of the gate dielectric layer 6 includes an oxide layer.

[0064] The material of the inter-gate dielectric layer 12 includes an oxide layer.

[0065] In the embodiment of the present invention, in the original cell region, the gate structure is a top-bottom structure, and the gate conductive material layer 5 is located on top of the source field plate 4. In other embodiments, the gate structure may be a left-right structure in the original cell region, and the gate conductive material layer 5 may be located on the left and right sides of the top region of the source field plate 4.

[0066] like Figure 4 As shown, in the source field plate lead-out region, a source field plate 4 is formed in the gate trench, and a shielding dielectric layer 3 is provided between the source field plate 4 and the inner surface of the corresponding gate trench.

[0067] The source field plate 4 in the cell region contacts the source field plate 4 in the source field plate lead-out region and is connected to the source electrode composed of the front metal layer 10 through the contact structure on the top of the source field plate 4 in the source field plate lead-out region. Figure 3 and Figure 4 The front metal layer 10 shown in FIG is used as a source. The front metal layer 10 is also patterned to form a gate. The top of the gate conductive material layer 5 is connected to the gate through a contact hole 9. The front metal layer 10 corresponding to the gate is not in FIG. Figure 3 and Figure 4 The corresponding cross-section position.

[0068] The gate trench of the source field plate lead-out region does not include a gate conductive material layer 5 and thus does not have a gate field plate; the source field plate lead-out region also includes a first compensation region 13, the first compensation region 13 is located at the interface region between the channel region 7 and the drift region 2 at the bottom, and the first compensation region 13 is added with compensating injection impurities of the second conductivity type. The compensating injection impurities increase the depletion ability of the channel region 7 to the top region of the drift region 2 to compensate for the reduction in depletion ability to the top region of the drift region 2 when the source field plate lead-out region does not have a gate field plate.

[0069] In this embodiment of the present invention, at the interface region, the compensating implanted impurities in the first compensation region 13 are completely located within the drift region 2 or extend into both the channel region 7 and the drift region 2. The specific distribution of the compensating implanted impurities in the first compensation region 13 is directly related to the implantation energy of the ion implantation of the compensating implanted impurities. The thermal process experienced by the compensating implanted impurities also affects the distribution of the compensating implanted impurities. The compensating implanted impurities extending into the drift region 2 reduce the net doping concentration of the first conductivity type in the drift region 2, thereby reducing the doping concentration of the first conductivity type in the top region of the drift region 2 in the source field plate lead-out region. The drift region 2 is usually composed of an epitaxial layer doped with the first conductive type formed on a semiconductor substrate. The doping concentration of the drift region 2 can be set according to the requirements in the cell region. By increasing the doping concentration of the drift region 2, the specific on-resistance of the device can be reduced. At the same time, a first compensation region 13 is set separately in the source field plate region, which can reduce the doping concentration at the surface of the top area of ​​the drift region 2 in the source field plate region, thereby eliminating the weaknesses caused by the excessive doping concentration at the surface of the top area of ​​the drift region 2 in the source field plate region and the excessive electric field strength at the surface of the top area of ​​the drift region 2 in the source field plate region due to the absence of a gate field plate.

[0070] In the embodiment of the present invention, the ion implantation for compensating the implanted impurities includes one implantation or multiple implantations with different energies.

[0071] In some embodiments, when the ion implantation of the compensatory implanted impurities is a single implantation, the implantation energy includes 40 keV, the implantation dose includes 2e15 cm -2 .

[0072] In some embodiments, the ion implantation of the compensating impurities is performed in multiple different energy implantations, a combination of low energy high dose and high energy low dose, the low energy high dose corresponds to a lower implantation energy than the high energy low dose but the low energy high dose corresponds to a higher implantation dose than the high energy low dose. Further, the ion implantation of the compensating impurities is performed twice, the first implantation is performed with an implantation energy of 40keV and an implantation dose of 1e15cm-2, and the second implantation is performed with an implantation energy of 200keV and an implantation dose of 1e12cm-2. -2 -2

[0073] As shown in FIG. 1, in the cell region, self-aligned first conductivity type heavily doped source regions 8 are formed in the surface region of the channel region 7 on both sides of the gate trench. Figure 3

[0074] In the source field plate pull-out region, no source regions 8 are formed in the surface region of the channel region 7 on both sides of the gate trench. The source regions 8 are connected to the source through the top contact hole 9, and the top contact hole 9 of the source regions 8 also contacts the bottom channel region 7 through the source regions 8.

[0075] The ion implantation of the compensating impurities is defined by the mask of the source regions 8, and the photoresist used in the ion implantation of the compensating impurities is opposite to the photoresist used in the ion implantation of the source regions 8. For example, the ion implantation of the source regions 8 uses positive photoresist, at this time, after the exposure of the mask of the source regions 8, the cell region is opened, and the source field plate pull-out region is covered by the positive photoresist; the ion implantation of the compensating impurities uses negative photoresist, the cell region is covered by the positive photoresist, and the source field plate pull-out region is opened.

[0076] The ion implantation of the compensating impurities can be performed after the epitaxial layer of the drift region 2 is formed and before the ion implantation of the source regions 8, or after the ion implantation of the source regions 8. When the ion implantation of the compensating impurities is performed after the ion implantation of the source regions 8, the compensating impurities are less subjected to the heat process in the subsequent processes.

[0077] As shown in FIG. 1, in the cell region, self-aligned first conductivity type heavily doped source regions 8 are formed in the surface region of the channel region 7 on both sides of the gate trench. Figure 4 In the embodiment of the present application, the top surface of the source field plate 4 of the source field plate pull-out region is lower than the top surface of the gate trench, the gate trench above the top surface of the source field plate 4 is filled with a first dielectric layer 15, an interlayer film 11 is formed on the top surface of the gate trench, and the contact structure is a deep contact hole 14 which penetrates through the interlayer film 11 and the first dielectric layer 15. Figure 3 In the embodiment of the present application, the source field plate 4 of the source field plate pull-out region and the source field plate 4 in the cell region are formed simultaneously by the same process, and both are subjected to the same etch-back process to lower the top surface. ​​​

[0078] In other embodiments, the top surface of the source field plate 4 is flush with the top surface of the gate trench, an interlayer film 11 is formed on the top surface of the gate structure, and the contact structure is a contact hole 9 that passes through the interlayer film 11 .

[0079] In an embodiment of the present invention, the SGT device is an SGT MOSFET, and a drain region 1 heavily doped with the first conductivity type is formed at the bottom of the drift region 2. In some embodiments, the drain region 1 is formed directly by thinning a semiconductor substrate heavily doped with the first conductivity type, such as a silicon substrate. In some embodiments, the drain region can also be formed by backside ion implantation of the thinned semiconductor substrate to heavily dope it with the first conductivity type.

[0080] In an embodiment of the present invention, the SGT device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the impurity implanted by the ion implantation for the compensatory impurity implantation includes boron. In other embodiments, the SGT device may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0081] In an embodiment of the present invention, a first compensation region 13 is set in the source field plate lead-out region. The first compensation region 13 adds compensation injection impurities of the second conductive type. The compensation injection impurities can increase the depletion ability of the top region of the drift region 2, thereby compensating for the weakening of the depletion ability of the top region of the drift region 2 due to the lack of a gate field plate in the source field plate lead-out region. It can ensure that the doping concentration of the drift region 2 in the original cell region is high while reducing the electric field strength of the top region of the drift region 2 in the source field plate lead-out region under reverse bias, thereby eliminating the weakness of the top region of the drift region 2 in the source field plate lead-out region caused by the high doping concentration of the drift region 2 and the lack of a gate field plate in the source field plate lead-out region, and ultimately improving the withstand voltage of the device. Therefore, the embodiment of the present invention can ensure that the doping concentration of the drift region 2 in the original cell region is high, thereby reducing the specific on-resistance of the device, while eliminating the weakness of the top region of the drift region 2 in the source field plate lead-out region and thereby improving the withstand voltage of the device.

[0082] like Figure 4 , which is a schematic structural diagram of a device unit in the primary cell region of the SGT device of the second embodiment of the present invention; the difference from the SGT device of the first embodiment of the present invention is that in the SGT device of the second embodiment of the present invention, at the bottom of the gate dielectric layer 6, the thickness of the shielding dielectric layer 3a gradually decreases from the bottom of the gate trench upward. Figure 4 Figure 5 Figure 5 The figure shows that the shielding dielectric layer 3a is divided into a first shielding dielectric layer 3a1 and a second shielding dielectric layer 3a2. The thickness of the second shielding dielectric layer 3a2 is thinner than that of the first shielding dielectric layer 3a1. The gradually decreasing thickness of the shielding dielectric layer 3a helps to make the electric field strength of the drift region 2 more uniform at various locations on the side of the gate trench.

[0083] Further, the thickness of the shielding dielectric layer 3 gradually decreases from the bottom of the gate trench upwards, and the doping concentration of the drift region 2 gradually increases, so as to reduce the specific on-resistance of the device.

[0084] The present application can reduce the position of the source field plate lead-out area, and there is no problem of increasing the electric field intensity at the bottom of the channel caused by the gate field plate. For example, in the N-type device, a P-type ion implantation is added at the position of the source lead-out end, i.e. the position of the source field plate lead-out area, by adding a mask (Mask), such as the same mask as the ion implantation of the source region. The P-type ion implantation region is located in the first compensation region 13, and the depth of the first compensation region 13 is deeper than the depth of the channel region 7. The effect is to reduce the doping concentration of the drift region 2 in contact with the channel region 7, thereby reducing the electric field intensity. In addition, the position corresponding to the implantation of the first compensation region 13 is not in the unit cell region of the device, but only in the source lead-out end and its vicinity, so that the influence on the on-resistance of the device can be ignored.

[0085] The present application has been described in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered as falling within the scope of protection of the present application.

Claims

1. An SGT device, characterized in that: include: a drift region doped with a first conductivity type; a second conductivity type doped channel region formed above a top surface of the drift region; a plurality of gate trenches, wherein the gate trenches longitudinally pass through the channel region and bottom areas of the gate trenches enter the drift region; The SGT device is divided into the primary cell region and the source field plate lead-out region; In the cell region, a source field plate and a gate conductive material layer are simultaneously formed in the gate trench; a shielding dielectric layer is separated between the source field plate and the inner surface of the corresponding gate trench; an inter-gate dielectric layer is separated between the source field plate and the gate conductive material layer; and a gate dielectric layer is separated between the gate conductive material layer and the side surface of the corresponding gate trench; the depth of the gate conductive material layer is greater than the depth of the channel region, and the surface of the channel region covered by the side surface of the gate conductive material layer is used to form a conductive channel; The gate conductive material layer also laterally covers the top area of ​​the drift region located at the bottom of the channel region, and when reverse biased, the gate conductive material layer forms a gate field plate that laterally depletes the top area of ​​the drift region; In the source field plate lead-out region, a source field plate is formed in the gate trench, and a shielding dielectric layer is separated between the source field plate and the inner surface of the corresponding gate trench; The source field plate in the cell region is in contact with the source field plate in the source field plate lead-out region and is connected to a source electrode composed of a front metal layer through a contact structure on the top of the source field plate in the source field plate lead-out region; The gate trench of the source field plate lead-out region does not include the gate conductive material layer and thus does not have the gate field plate; the source field plate lead-out region also includes a first compensation region, the first compensation region is located at the interface region between the channel region and the drift region at the bottom, and second conductivity type compensation injection impurities are added to the first compensation region, the compensation injection impurities increase the depletion ability of the channel region to the top region of the drift region, so as to compensate for the reduction in the depletion ability of the top region of the drift region when the source field plate lead-out region does not have the gate field plate; When the ion implantation for compensating the impurity implantation is multiple implantations with different energies, a combination of low energy and high dose and high energy and low dose is adopted. The implantation energy corresponding to the low energy and high dose is lower than the implantation energy of the high energy and low dose, but the implantation dose amount corresponding to the low energy and high dose is higher than the implantation dose of the high energy and low dose.

2. The SGT device according to claim 1, wherein: At the interface region, the compensation implanted impurities in the first compensation region are completely located in the drift region or extend into both the channel region and the drift region.

3. The SGT device according to claim 2, wherein: The compensating implanted impurities extending into the drift region reduce a net doping concentration of the first conductivity type in the drift region.

4. The SGT device according to claim 1, wherein: The number of times of ion implantation for compensating the impurity implantation is two, and the process conditions of the first implantation are as follows: the implantation energy is 40keV, the implantation dose is 1e15cm -2 The process conditions for the second implantation are as follows: implantation energy 200keV, implantation dose 1e12cm -2 .

5. The SGT device according to claim 1, wherein: In the original cell region, a source region heavily doped with a first conductivity type is self-alignedly formed in the surface region of the channel region on both sides of the gate trench; In the source field plate lead-out region, the source region is not formed in the surface areas of the channel region on both sides of the gate trench; The ion implantation of the compensating impurity implantation adopts the mask definition of the source region, and the polarity of the photoresist adopted in the ion implantation of the compensating impurity implantation is opposite to that of the photoresist adopted in the ion implantation of the source region.

6. The SGT device according to claim 1, wherein: The top surface of the source field plate in the source field plate lead-out region is lower than the top surface of the gate trench, the gate trench above the top surface of the source field plate is filled with a first dielectric layer, an interlayer film is formed above the top surface of the gate trench, and the contact structure is a deep contact hole, which passes through the interlayer film and the first dielectric layer; Alternatively, the top surface of the source field plate is flush with the top surface of the gate trench, an interlayer film is formed on the top surface of the gate trench, and the contact structure is a contact hole passing through the interlayer film.

7. The SGT device according to claim 1, wherein: The material of the source field plate includes polysilicon.

8. The SGT device according to claim 1, wherein: The material of the shielding dielectric layer includes an oxide layer.

9. The SGT device according to claim 8, wherein: At the bottom of the gate dielectric layer, from the bottom of the gate trench upwards, the thickness of the shielding dielectric layer is evenly distributed or gradually decreases.

10. The SGT device according to claim 9, wherein: When the thickness of the shielding dielectric layer gradually decreases from the bottom of the gate trench upward, the doping concentration of the drift region gradually increases, so as to reduce the specific on-resistance of the device.

11. The SGT device according to claim 1, wherein: In the primitive cell region, the gate structure is a top-bottom structure, and the gate conductive material layer is located on top of the source field plate; Alternatively, in the original cell region, the gate structure is a left-right structure, and the gate conductive material layer is located on the left and right sides of the top region of the source field plate.

12. The SGT device according to claim 1, wherein: The SGT device is an SGT MOSFET, and a drain region heavily doped with a first conductivity type is formed at the bottom of the drift region.

13. The SGT device according to any one of claims 1 to 12, wherein: The SGT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the SGT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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