Preparation method of semiconductor structure and semiconductor structure
By using a method of implantation followed by etching to form the trench sidewall doped region of a junction field-effect transistor device, the problem of high precision in implantation angle control in traditional methods is solved, thereby achieving stable device performance and simplified process flow.
Patent Information
- Application Number
- CN202511713218.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-02-17
AI Technical Summary
In the fabrication process of traditional junction field-effect transistors, the injection angle control of the trench sidewalls requires high precision. Deviations can easily occur, leading to unstable device performance. Furthermore, etching morphology and ion implantation scattering result in uneven doped regions.
The method of first forming a second type of doped pillar by ion implantation, and then forming cell trenches, bus trenches and doped regions by etching, simplifies the process flow, avoids the high precision requirements of the implantation angle, and ensures the uniformity of the doped region.
It simplifies the process flow, improves the stability and consistency of device performance, reduces process difficulty and cost, ensures uniform distribution of doped regions, reduces the number of photomasks used, and enhances device stability and lifespan.
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Figure CN121548081A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology
[0002] A junction field-effect transistor (JFET) is a voltage-controlled semiconductor device commonly used in amplifier circuits, switching circuits, analog switches, etc.
[0003] In the fabrication of traditional junction field-effect transistors (JFETs), a trench etching and ion implantation method is typically used. Specifically, after etching the trench, ion implantation is performed at an angle to form doped regions on the trench sidewalls. However, this method requires extremely high precision in controlling the implantation angle; even a tiny angular deviation can lead to unsatisfactory doped region positions and concentrations. Furthermore, factors such as mask opening size, etching morphology, and ion scattering within the trench can cause uneven doping concentration distribution on the trench sidewalls. This uneven distribution affects the consistency of the JFET's conductive channel, leading to unstable device performance and potentially even a drop in breakdown voltage.
[0004] The aforementioned technologies suffer from drawbacks, such as the extremely high precision required to control the injection angle for forming the trench sidewalls, which can easily lead to deviations and unstable device performance. Summary of the Invention
[0005] To simplify the method of forming trench sidewalls, this application provides a method for fabricating a semiconductor structure and a semiconductor structure.
[0006] On the one hand, this application provides a method for fabricating a semiconductor structure using the following technical solution: A method for fabricating a semiconductor structure, comprising: S1. Provide a substrate with an epitaxial layer; S2. A JFET layer and a first type of doped layer are sequentially formed on the epitaxial layer. A cell region and a bus region are defined on the surface of the first type of doped layer. S3. A second type of doped pillar extends from the surface of the first type of doped layer to form a second type of doped pillar that penetrates the first type of doped layer and the JFET layer, and the bottom of the second type of doped pillar is located in the epitaxial layer. S6. Etching to form trenches in the second type of doped pillar, wherein a second type of doped region is left between the inner wall of the trench and the outer wall of the second type of doped pillar, the trench including cell trenches formed in the cell region and bus trenches formed in the bus region.
[0007] By adopting the above technical solution, a second type of doped pillar is first formed by implantation, and then cell trenches, bus trenches and second type of doped regions are formed by etching the second type of doped pillar. The process is simple and does not require precise control of the implantation angle to form uniform trench sidewalls as in traditional methods.
[0008] Optionally, in step S3, a mask is formed on the first type of doped layer, a plurality of mask openings are formed on the mask, and the second type of doped pillars are formed from the surface of the first type of doped layer by aligning the mask openings.
[0009] By adopting the above technical solution, the position and size of the second type of doped pillars can be controlled by the mask opening, ensuring the accuracy of the distribution of the second type of doped pillars and avoiding performance fluctuations of the device caused by ion implantation deviation.
[0010] Optionally, the process may further include the following steps between step S3 and step S6: S4. Deposit a first spacer layer on the second type of doped pillar and the mask; S5. Etch the first spacer layer until the top surface of the second type of doped pillar is exposed, and the first spacer layer is left on the sidewall of the mask below the mask opening to form an etched area on the surface of the second type of doped pillar.
[0011] By adopting the above technical solution, a precise etching area is formed through the first spacer layer, providing a positioning reference for the subsequent etching to form cell trenches and bus trenches, thus ensuring the etching accuracy of cell trenches and bus trenches.
[0012] Optionally, in step S6, the etched area is aligned, and the cell trench, the bus trench, and the second type of doped area are etched from the surface of the second type of doped pillar to form the cell trench, the bus trench, and the second type of doped area.
[0013] By adopting the above technical solution, cell trenches and bus trenches are formed in the etched area, ensuring accurate etching of cell trenches and bus trenches and avoiding the risk of short circuits caused by etching misalignment.
[0014] Optionally, after step S6, the following may also be included: The process after step S6 also includes: S7. Remove the mask and the first spacer layer; S8. A second spacer layer is deposited on the cell trench, the bus trench, the second type of doped region and the first type of doped layer; S9. Etch the second spacer layer to expose the bottom surface of the cell trench, the bottom surface of the bus trench, the top surface of the second type doped region and the top surface of the first type doped layer, and leave the second spacer layer on the sidewalls of the cell trench and the bus trench. S10. Deposit a metal layer and anneal to form metal silicide on the first type of doped layer, the second type of doped region, the second spacer layer, the cell trench and the bus trench; S11. Remove the metal silicide on the surface of the second spacer layer to form a cell gate lead on the bottom surface of the cell trench, a bus gate lead on the bottom surface of the bus trench, and a source lead on the top surface of the first type doped layer and the second type doped region. S12. An interlayer dielectric isolation layer is formed on the cell gate lead, the bus gate lead, and the source lead; S13. A plurality of source contact trenches are formed by etching from the surface of the interlayer dielectric isolation layer in the cell region, and a gate contact trench is formed by etching from the surface of the interlayer dielectric isolation layer in the bus region. Both the source contact trenches and the gate contact trenches penetrate the interlayer dielectric isolation layer. S14. Deposit metal and etch to form metal electrodes on the interlayer dielectric isolation layer, the source contact trench and the gate contact trench. The metal electrodes include a metal gate electrically connected to the bus gate lead and a metal source electrically connected to the source lead. S15. A passivation layer is formed on the metal gate and the interlayer dielectric isolation layer, and a contact hole is formed on the passivation layer to expose the metal gate.
[0015] By adopting the above technical solutions, cell gate leads and bus gate leads are formed to control the conduction and cutoff of the JFET layer; source contact trenches and gate contact trenches can be formed in a single process, requiring fewer photomasks and simplifying the processing flow; the formation of a passivation layer can protect the interior of the semiconductor structure from external environmental contamination.
[0016] Optionally, in step S11, the cell gate lead is electrically connected to the bus gate lead.
[0017] By adopting the above technical solution, the cell gate lead is electrically connected to the bus gate lead, ensuring that the bus gate lead can control the conduction and cutoff of all JFET layers through the cell gate lead.
[0018] On the other hand, this application also provides a semiconductor structure using the following technical solution: A semiconductor structure, comprising: Substrates with epitaxial layers; A JFET layer is formed on the epitaxial layer; A first type of doped layer is formed on the JFET layer, and a cell region and a bus region are defined on the surface of the first type of doped layer. The second type of doped pillar extends from the surface of the first type of doped layer and penetrates the first type of doped layer and the JFET layer, and the bottom of the second type of doped pillar is located in the epitaxial layer; trenches are etched in the second type of doped pillar, and a second type of doped region is left between the inner wall of the trench and the outer wall of the second type of doped pillar, the trenches including cell trenches formed in the cell region and bus trenches formed in the bus region.
[0019] By adopting the above technical solution, the cell trenches, bus trenches and second type doped regions formed by implantation followed by etching can ensure a more uniform doping concentration distribution in the second type doped region and ensure more stable performance of semiconductor devices.
[0020] Optionally, it also includes a cell gate lead located on the bottom surface of the cell trench, a bus gate lead located on the bottom surface of the bus trench, and a source lead located on the top surface of the first type of doped layer and the second type of doped region; the cell gate lead is electrically connected to the bus gate lead.
[0021] By adopting the above technical solution, the cell gate lead is electrically connected to the bus gate lead, so that the metal gate can simultaneously control the cell gate and the bus gate, ensuring that all JFET layers can be turned off and turned on at the same time.
[0022] Optionally, an interlayer dielectric isolation layer is provided on both the cell trench and the bus trench, and a metal source electrode electrically connected to the source electrode electrode is provided on the interlayer dielectric isolation layer on the cell region and on the source electrode lead; a metal gate electrode electrically connected to the bus gate lead is provided on the bus gate lead.
[0023] By adopting the above technical solution, the interlayer dielectric isolation layer can isolate the connection path between the metal source and the metal gate, ensuring electrical isolation between the metal source and the metal gate and guaranteeing the stability of the device.
[0024] Optionally, a passivation layer is provided on the interlayer dielectric isolation layer and the metal gate in the bus region, and a contact hole is formed on the passivation layer to expose the metal gate.
[0025] By adopting the above technical solution, the passivation layer can protect the interlayer dielectric isolation layer and the metal gate, preventing moisture and impurities in the external environment from corroding or contaminating the internal structure of the device, thereby improving the stability and lifespan of the device. Contact holes are formed in the passivation layer to expose the metal gate, enabling reliable electrical connection between the metal gate and external drive circuits or other components.
[0026] In summary, this application includes at least one of the following beneficial technical effects: 1. First, a second type of doped pillar is formed by implantation, and then the cell trench, bus trench and second type doped region are formed by etching the second type of doped pillar. The process is simple and does not require precise control of the implantation angle to form a uniform second type doped region as in traditional methods. 2. Forming cell gate leads and bus gate leads to control the conduction and cutoff of the JFET layer; source contact trenches and gate contact trenches can be formed in a single process, requiring fewer photomasks and simplifying the processing flow; forming a passivation layer can protect the interior of the semiconductor structure from external environmental contamination; 3. The cell trenches, bus trenches and second type doped regions formed by implantation followed by etching can ensure a more uniform doping concentration distribution in the second type doped region, thus ensuring more stable performance of semiconductor devices. 4. The passivation layer protects the interlayer dielectric isolation layer and metal gate structure, preventing moisture and impurities from the external environment from corroding or contaminating the internal structure of the device, thus improving the device's stability and lifespan. Contact holes are formed in the passivation layer to expose the metal gate, enabling reliable electrical connection between the metal gate and external drive circuits or other components. Attached Figure Description
[0027] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application; Figure 2 Is execution Figure 1 A sectional view of the structure after step S1; Figure 3 Is execution Figure 1 A sectional view of the structure after step S2; Figure 4 Is execution Figure 1 A sectional view of the structure after step S3; Figure 5 Is execution Figure 1 A sectional view of the structure after step S4; Figure 6 Is execution Figure 1 A sectional view of the structure after step S5; Figure 7 Is execution Figure 1 A sectional view of the structure after step S6; Figure 8 Is execution Figure 1 A sectional view of the structure after step S7; Figure 9 Is execution Figure 1 A sectional view of the structure after step S8; Figure 10 Is execution Figure 1 A sectional view of the structure after step S9; Figure 11 Is execution Figure 1 A sectional view of the structure after step S10; Figure 12 Is execution Figure 1 A sectional view of the structure after step S11; Figure 13 Is execution Figure 1 A sectional view of the structure after step S12; Figure 14 Is execution Figure 1 A sectional view of the structure after step S13; Figure 15 Is execution Figure 1 A sectional view of the structure after step S14; Figure 16 Is execution Figure 1 A sectional view of the structure after step S15; Figure 17 This is a perspective structural diagram of a semiconductor structure according to an embodiment of this application; Figure 18 It is along Figure 17 Sectional view of line A-A'; Figure 19 It is along Figure 17 Sectional view of B-B'.
[0028] Explanation of reference numerals in the attached figures: 10, substrate; 20, epitaxial layer; 30, JFET layer; 40, first type doped layer; 41, mask; 42, mask opening; 43, first spacer layer; 50, second type doped pillar; 51, cell trench; 52, bus trench; 53, second type doped region; 54, second spacer layer; 60, metal layer; 61, metal silicide; 61a, cell gate lead; 61b, bus gate lead; 61c, source lead; 70, interlayer dielectric isolation layer; 71, source contact trench; 72, gate contact trench; 80, metal electrode; 81, metal gate; 82, metal source; 90, passivation layer; 91, contact hole. Detailed Implementation
[0029] The following is in conjunction with the appendix Figure 1-19This application will be described in further detail.
[0030] This application discloses a method for preparing a semiconductor structure.
[0031] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application.
[0032] Reference Figure 1 The method includes the following steps: S1. A substrate 10 having an epitaxial layer 20 is provided.
[0033] S2. A JFET layer 30 and a first type doped layer 40 are sequentially formed on the epitaxial layer 20. A cell region and a bus region are defined on the surface of the first type doped layer 40.
[0034] S3. A second type of doped pillar 50 is formed extending from the surface of the first type of doped layer 40. The second type of doped pillar 50 penetrates the first type of doped layer 40 and the JFET layer 30, and the bottom of the second type of doped pillar 50 is located in the epitaxial layer 20.
[0035] S4. Deposit a first spacer layer 43 on the second type of doped pillar 50 and the mask 41.
[0036] S5. Etch the first spacer layer 43 until the top surface of the second type doped pillar 50 is exposed, and the first spacer layer 43 is left on the sidewall of the mask 41 below the mask opening 42 to form an etched area on the surface of the second type doped pillar 50.
[0037] S6. Etching forms trenches in the second type of doped pillar 50, wherein a second type of doped region 53 is left between the inner wall of the trench and the outer wall of the second type of doped pillar 50, and the trench includes a cell trench 51 formed in the cell region and a bus trench 52 formed in the bus region.
[0038] S7. Remove the mask 41 and the first spacer layer 43.
[0039] S8. A second spacer layer 54 is deposited on the cell trench 51, the bus trench 52, the second type doped region 53 and the first type doped layer 40.
[0040] S9. Etch the second spacer layer 54 to expose the bottom surface of the cell trench 51, the bottom surface of the bus trench 52, the top surface of the second type doped region 53 and the top surface of the first type doped layer 40, and leave the second spacer layer 54 on the sidewalls of the cell trench 51 and the bus trench 52.
[0041] S10, deposit a metal layer 60 and anneal to form a metal silicide 61 on the first type doped layer 40, the second type doped region 53, the second spacer layer 54, the cell trench 51 and the bus trench 52.
[0042] S11. Remove the metal silicide 61 on the surface of the second spacer layer 54 to form a cell gate lead 61a on the bottom surface of the cell trench 51, a bus gate lead 61b on the bottom surface of the bus trench 52, and a source lead 61c on the top surface of the first type doped layer 40 and the second type doped region 53.
[0043] S12, an interlayer dielectric isolation layer 70 is formed on the cell gate lead 61a, the bus gate lead 61b and the source lead 61c.
[0044] S13. A plurality of source contact trenches 71 are formed by etching from the surface of the interlayer dielectric isolation layer 70 in the cell region, and gate contact trenches 72 are formed by etching from the surface of the interlayer dielectric isolation layer 70 in the bus region. Both the source contact trenches 71 and the gate contact trenches 72 penetrate the interlayer dielectric isolation layer 70.
[0045] S14. Deposit metal and etch to form metal electrodes on the interlayer dielectric isolation layer 70, the source contact trench 71 and the gate contact trench 72. The metal electrodes include a metal gate 81 electrically connected to the bus gate lead 61b and a metal source 82 electrically connected to the source lead 61c.
[0046] S15. A passivation layer 90 is formed on the metal gate 81 and the interlayer dielectric isolation layer 70, and a contact hole 91 is formed on the passivation layer 90 to expose the metal gate 81.
[0047] The steps of this method are explained in detail below with reference to the accompanying drawings.
[0048] Figure 2 Is execution Figure 1 A schematic diagram of the structure after step S1. (Refer to...) Figure 2 In step S1, a substrate 10 having an epitaxial layer 20 is provided. The epitaxial layer 20 is generally formed using methods such as vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), or molecular beam epitaxy (MBE). Taking vapor phase epitaxy (VPE) as an example, a silicon-containing gas is introduced into a reaction chamber, and a chemical reaction occurs on the surface of the substrate 10 at a high temperature, causing silicon atoms to deposit on the surface of the substrate 10 to form the epitaxial layer 20.
[0049] Figure 3 Is execution Figure 1A schematic diagram of the structure after step S2. In step S2, a JFET layer 30 and a first-type doped layer 40 are sequentially formed on the epitaxial layer 20. Cell regions and bus regions are defined on the surface of the first-type doped layer 40. The JFET layer 30 and the first-type doped layer 40 can generally be grown epitaxially. For example, a gas containing specific impurities is introduced into a reaction chamber, causing a chemical reaction on the surface of the epitaxial layer 20 at high temperature, thereby achieving the epitaxial growth of the JFET layer 30 and the first-type doped layer 40. Alternatively, ion implantation can be used. For example, the regions of the JFET layer 30 and the first-type doped layer 40 are first defined on the epitaxial layer 20 using photolithography, then dopant ions (such as boron ions or phosphorus ions) are implanted into the designated regions through ion implantation, and finally, annealing is performed to activate the dopant ions and repair lattice damage.
[0050] Figure 4 Is execution Figure 1 A schematic diagram of the structure after step S3. In step S3, a mask 41 is formed on the first type of doped layer 40, and multiple mask openings 42 are formed on the mask 41. Aligning with the mask openings 42, a second type of doped pillar 50 is formed from the surface of the first type of doped layer 40. The second type of doped pillar 50 penetrates the first type of doped layer 40 and the JFET layer 30, and the bottom of the second type of doped pillar 50 is located in the epitaxial layer 20. The second type of doped pillar 50 is generally formed by ion implantation. For example, the desired region is first defined on the epitaxial layer 20 using photolithography, and then P-type impurity ions (such as boron ions) are implanted into the designated location using an ion implantation process. After implantation, an annealing process is performed to activate and diffuse the implanted impurity atoms, forming the second type of doped pillar 50.
[0051] Figure 5 Is execution Figure 1 A schematic diagram of the structure after step S4. In step S4, a first spacer layer 43 is deposited on the second type of doped pillar 50 and the mask 41. The first spacer layer 43 is generally formed using physical vapor deposition (PVD) or chemical vapor deposition (CVD). Taking physical vapor deposition (PVD) as an example, material is transferred from a solid or liquid source to the desired location in a vacuum using physical methods (such as evaporation or sputtering) to form a thin film.
[0052] Figure 6 Is execution Figure 1A schematic diagram of the structure after step S5. In step S5, the first spacer layer 43 is etched until the top surface of the second type of doped pillar 50 is exposed. The first spacer layer 43 remains on the sidewalls of the mask 41 below the mask opening 42, forming an etched area on the surface of the second type of doped pillar 50. The first spacer layer 43 can generally be formed using reactive ion etching (RIE). For example, in reactive ion etching, active materials in the plasma are accelerated and impact the workpiece surface under the action of an electric field, achieving an etching effect combining chemical reaction and physical bombardment. The first spacer layer 43 can also be formed using wet etching, for example, by using a chemical solution to react chemically with the material to be etched, dissolving and removing the material to achieve etching.
[0053] Figure 7 Is execution Figure 1 A schematic diagram of the structure after step S6. In step S6, trenches are formed by etching from the surface of the second type doped pillar 50, aligned with the etching area. A second type doped region 53 is left between the inner wall of the trench and the outer wall of the second type doped pillar 50. The trenches include cellular trenches 51 formed in the cellular region and bus trenches 52 formed in the bus region. The cellular trenches 51 and bus trenches 52 can generally be formed using plasma etching or reactive ion etching methods. Plasma etching generally utilizes high-energy particles in plasma to undergo physical or chemical reactions with the material surface. Reactive ion etching generally combines plasma etching with chemical reactions, using the excitation of reactive gases in the plasma to generate active substances that react chemically with the material surface to produce volatile products, thereby removing the material.
[0054] Figure 8 Is execution Figure 1 A schematic diagram of the structure after step S7. In step S7, the mask 41 and the first spacer layer 43 are removed. The mask 41 and the first spacer layer 43 can generally be removed using a wet etching method. Wet etching typically utilizes the solubility of the mask 41 and the first spacer layer 43 in a specific chemical solution to remove them.
[0055] Figure 9 Is execution Figure 1A schematic diagram of the structure after step S8. In step S8, a second spacer layer 54 is deposited and formed on the cell trench 51, the bus trench 52, the second type of doped region 53, and the first type of doped layer 40. The second spacer layer 54 is generally formed using chemical vapor deposition (CVD). For example, the desired gaseous reactants are introduced into a reaction chamber, and under specific temperature, pressure, and other conditions, the gaseous reactants undergo a chemical reaction and form the second spacer layer 54 at the desired location.
[0056] Figure 10 Is execution Figure 1 A schematic diagram of the structure after step S9. In step S9, the second spacer layer 54 is etched until the bottom surface of the cell trench 51, the bottom surface of the bus trench 52, the top surface of the second type doped region 53, and the top surface of the first type doped layer 40 are exposed, and the second spacer layer 54 remains on the sidewalls of both the cell trench 51 and the bus trench 52. Generally, reactive ion etching (RIE) is used to etch the second spacer layer 54.
[0057] Figure 11 Is execution Figure 1 A schematic diagram of the structure after step S10. In step S10, a metal layer 60 is deposited and annealed to form a metal silicide 61 on the first type of doped layer 40, the second type of doped region 53, the second spacer layer 54, the cell trench 51, and the bus trench 52. The metal layer 60 is generally formed using chemical vapor deposition (CVD). For example, a gaseous reactant containing a metal source is introduced into a reaction chamber. Under specific temperature and pressure conditions, the gaseous reactant undergoes a chemical reaction and forms the metal layer 60 at the desired location. After the metal layer 60 is formed, it undergoes annealing. The annealing temperature is generally between 400-1000°C, and the annealing time depends on the actual needs, typically ranging from a few minutes to tens of minutes. During the annealing process, the metal layer 60 reacts with the underlying material to form the metal silicide 61.
[0058] Figure 12 Is execution Figure 1A schematic diagram of the structure after step S11. In step S11, the second spacer layer 54 and the metal silicide 61 on its surface are removed to form a cell gate lead 61a on the bottom surface of the cell trench 51, a bus gate lead 61b on the bottom surface of the bus trench 52, and a source lead 61c on the top surface of the first type doped layer 40 and the second type doped region 53. Generally, wet etching or dry etching methods are used to remove the second spacer layer 54 and the metal silicide 61 on its surface. The wet etching utilizes the solubility of the second spacer layer 54 and the metal silicide 61 in a specific chemical solution to remove them. For example, when the second spacer layer 54 is an oxide, hydrofluoric acid (HF) solution can be used for etching.
[0059] Figure 13 Is execution Figure 1 A schematic diagram of the structure after step S12. In step S12, an interlayer dielectric isolation layer 70 is formed on the cell gate lead 61a, the bus gate lead 61b, and the source lead 61c. The interlayer dielectric isolation layer 70 can generally be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD).
[0060] Figure 14 Is execution Figure 1 A schematic diagram of the structure after step S13. In step S13, multiple source contact trenches 71 are formed by etching from the surface of the interlayer dielectric isolation layer 70 in the cell region, and gate contact trenches 72 are formed by etching from the surface of the interlayer dielectric isolation layer 70 in the bus region. Both the source contact trenches 71 and the gate contact trenches 72 penetrate the interlayer dielectric isolation layer 70. The source contact trenches 71 and the gate contact trenches 72 can generally be formed using reactive ion etching (RIE) or physical etching (such as ion beam etching).
[0061] Figure 15 Is execution Figure 1 A schematic diagram of the structure after step S14. In step S14, metal electrodes are deposited and etched on the interlayer dielectric isolation layer 70, the source contact trench 71, and the gate contact trench 72. The metal electrodes include a metal gate 81 electrically connected to the bus gate lead 61b and a metal source 82 electrically connected to the source lead 61c. The metal electrodes are generally formed using physical vapor deposition (PVD) or chemical vapor deposition (CVD).
[0062] Figure 16 Is execution Figure 1A schematic diagram of the structure after step S15. In step S15, a passivation layer 90 is formed on the metal gate 81 and the interlayer dielectric isolation layer 70, and a contact hole 91 is formed on the passivation layer 90 to expose the metal gate 81. The passivation layer 90 can generally be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
[0063] In traditional semiconductor device manufacturing processes, the formation of trench sidewalls often requires precise control of the ion implantation angle to ensure uniform doping and consistent device performance. For example, in some early CMOS (Complementary Metal-Oxide-Semiconductor) processes, multiple ion implantations were typically used to form a uniform doping distribution on the trench sidewalls, and the implantation angle needed to be strictly controlled. This not only increased the complexity of the process but could also lead to low production efficiency and increased costs.
[0064] In this embodiment, dopant ions (such as P-type impurity aluminum ions, boron ions, etc.) are first implanted using ion implantation technology to form the second type of doped pillar 50. Then, the cell trench 51, the bus trench 52, and the second type of doped region 53 are formed by etching the second type of doped pillar 50. Compared with the traditional method of forming trench sidewalls by strictly controlling the implantation angle, the cell trench 51, bus trench 52, and the second type of doped region 53 formed by the implantation-then-etching method in this application make the process flow simpler and more efficient, while avoiding the high precision requirements of the implantation angle, thus reducing the process difficulty and complexity.
[0065] In conventional processes, the source contact trench 71 and the gate contact trench 72 are typically formed separately, requiring the use of different photomasks and multiple photolithography steps, increasing the complexity and cost of the process. However, the embodiments of this application can form both the source contact trench 71 and the gate contact trench 72 simultaneously, reducing the number of photomasks used and simplifying the overall process.
[0066] The implementation principle of a semiconductor structure fabrication method according to an embodiment of this application is as follows: first, the second type of doped pillar 50 is formed by implantation, and then the cell trench 51, the bus trench 52 and the second type of doped region 53 are formed by etching the second type of doped pillar 50. The process is simple and does not require precise control of the implantation angle to form a uniform second type of doped region 53 as in traditional methods.
[0067] This application also discloses a semiconductor structure.
[0068] Figure 17 This is a perspective view of a semiconductor structure according to an embodiment of this application. Figure 18 It is along Figure 17Sectional view of line A-A' Figure 19 It is along Figure 17 Sectional view of B-B'.
[0069] Reference Figure 17 , Figure 18 and Figure 19 The semiconductor structure includes a substrate 10, an epitaxial layer 20, a JFET layer 30, a first type doped layer 40, a cell trench 51, a bus trench 52, a second type doped region 53, a metal silicide 61, an interlayer dielectric isolation layer 70, a metal electrode, and a passivation layer 90.
[0070] The substrate 10 is generally made of silicon carbide, which has excellent thermal conductivity and can effectively dissipate the heat generated by the device during operation. The epitaxial layer 20 is formed on the substrate 10, and the epitaxial layer 20 is also generally made of silicon carbide. The epitaxial layer 20 made of silicon carbide has strong radiation resistance and can work normally in some special environments with radiation.
[0071] The materials of the substrate 10 and the epitaxial layer 20 include, but are not limited to, silicon carbide. The doping type of the substrate 10 and the epitaxial layer 20 can be N-type or P-type. This embodiment uses N-type impurities in the epitaxial layer 20 as an example for illustration. It is easy to understand that when P-type impurities are doped in the epitaxial layer 20, all corresponding doping types need to be changed to the opposite type.
[0072] The JFET layer 30 is formed on the epitaxial layer 20, and the first type doped layer 40 is formed on the JFET layer 30. Cell regions and bus regions are defined on the surface of the first type doped layer 40. A second type doped pillar 50 extends from the surface of the first type doped layer 40, penetrating both the first type doped layer 40 and the JFET layer 30, with its bottom located within the epitaxial layer 20. The JFET layer 30 is a junction field-effect transistor layer, typically made of silicon carbide doped with N-type impurities, with a doping concentration typically of 10⁻⁶. 16 cm -3 -10 17 cm -3 The first type of doped layer 40 is generally also made of silicon carbide doped with N impurities, with a doping concentration typically of 10. 16 cm -3 -10 18 cm -3 The second type of doped column 50 is generally formed by doping with p-type impurities, with a doping concentration typically of 10. 16 cm -3 -10 18 cm -3 .
[0073] Cell trenches 51, bus trenches 52, and second-type doped regions 53 are formed by etching the surface of the second-type doped pillar 50. Cell gate leads 61a are formed on the bottom surface of the cell trenches 51, and bus gate leads 61b are formed on the bottom surface of the bus trenches 52. The bus gate leads 61b are electrically connected to the cell gate leads 61a. The cell gate leads 61a and the bus gate leads 61b are generally made of metal silicide.
[0074] Source leads 61c are formed on the top surfaces of both the first type of doped layer 40 and the second type of doped region 53. Interlayer dielectric isolation layers 70 are formed on both the cell trench 51 and the bus trench 52. The interlayer dielectric isolation layer 70 is generally made of insulating materials such as silicon dioxide or silicon nitride. The interlayer dielectric isolation layer 70 is used to isolate the source leads 61c from the cell gate leads 61a and the bus gate leads 61b.
[0075] Source contact trenches 71 located in the cell region and gate contact trenches 72 located in the bus region are formed by etching from the surface of the interlayer dielectric isolation layer 70. Both the source contact trenches 71 and the gate contact trenches 72 penetrate the interlayer dielectric isolation layer 70. Metal source electrodes 82 are formed on the source contact trenches 71 and the interlayer dielectric isolation layer 70, and metal gate electrodes 81 are formed within the gate contact trenches 72. The metal source electrodes 82 are electrically connected to the source lead 61c, and the metal gate electrodes 81 are electrically connected to the bus gate lead 61b. A passivation layer 90 is formed above the metal gate electrodes 81 and the interlayer dielectric isolation layer 70, and contact holes 91 for exposing the metal gate electrodes 81 are formed on the passivation layer 90. The passivation layer 90 is generally made of insulating materials (such as silicon dioxide, silicon nitride, polyimide, etc.). The passivation layer 90 can effectively block the erosion of the internal structure of the semiconductor structure by moisture, oxygen and impurities in the external environment, thereby extending the service life of the semiconductor structure.
[0076] The implementation principle of a semiconductor structure in this application embodiment is as follows: the cell trench 51, the bus trench 52 and the second type of doped region 53 formed by implantation and then etching can ensure that the doping concentration distribution of impurity ions in the second type of doped region 53 is more uniform, and ensure that the performance of the semiconductor device is more stable.
[0077] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: S1. Provide a substrate (10) having an epitaxial layer (20); S2. A JFET layer (30) and a first type doped layer (40) are sequentially formed on the epitaxial layer (20). A cell region and a bus region are defined on the surface of the first type doped layer (40). S3. A second type of doped pillar (50) is formed extending from the surface of the first type of doped layer (40). The second type of doped pillar (50) penetrates the first type of doped layer (40) and the JFET layer (30), and the bottom of the second type of doped pillar (50) is located in the epitaxial layer (20). S6. Etching to form trenches in the second type of doped pillar (50), wherein a second type of doped region (53) is left between the inner wall of the trench and the outer wall of the second type of doped pillar (50), the trenches including cell trenches (51) formed in the cell region and bus trenches (52) formed in the bus region.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, In step S3, a mask (41) is formed on the first type of doped layer (40), and a plurality of mask openings (42) are formed on the mask (41). The mask openings (42) are aligned with the mask openings, and the second type of doped pillars (50) are formed from the surface of the first type of doped layer (40).
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Between step S3 and step S6, the following is also included: S4. Deposit a first spacer layer (43) on the second type of doped pillar (50) and the mask (41); S5. Etch the first spacer layer (43) until the top surface of the second type doped pillar (50) is exposed, and the first spacer layer (43) is left on the sidewall of the mask (41) below the mask opening (42) to form an etched area on the surface of the second type doped pillar (50).
4. The method for preparing a semiconductor structure according to claim 3, characterized in that, In step S6, the etched area is aligned, and the cell trench (51), the bus trench (52), and the second type of doped area (53) are etched from the surface of the second type of doped pillar (50).
5. The method for preparing a semiconductor structure according to claim 3, characterized in that, The process after step S6 also includes: S7. Remove the mask (41) and the first spacer layer (43). S8. A second spacer layer (54) is deposited on the cell trench (51), the bus trench (52), the second type doped region (53), and the first type doped layer (40). S9. Etch the second spacer layer (54) to expose the bottom surface of the cell trench (51), the bottom surface of the bus trench (52), the top surface of the second type doped region (53) and the top surface of the first type doped layer (40), and leave the second spacer layer (54) on the sidewalls of the cell trench (51) and the bus trench (52). S10, deposit a metal layer (60) and anneal to form a metal silicide (61) on the first type doped layer (40), the second type doped region (53), the second spacer layer (54), the cell trench (51) and the bus trench (52); S11. Remove the metal silicide (61) on the surface of the second spacer layer (54) to form a cell gate lead (61a) on the bottom surface of the cell trench (51), a bus gate lead (61b) on the bottom surface of the bus trench (52), and a source lead (61c) on the top surface of the first type doped layer (40) and the second type doped region (53). S12, forming an interlayer dielectric isolation layer (70) on the cell gate lead (61a), the bus gate lead (61b) and the source lead (61c); S13. A plurality of source contact trenches (71) are formed by etching from the surface of the interlayer dielectric isolation layer (70) in the cell region, and a gate contact trench (72) is formed by etching from the surface of the interlayer dielectric isolation layer (70) in the bus region. The source contact trenches (71) and the gate contact trenches (72) both penetrate the interlayer dielectric isolation layer (70). S14. Deposit metal and etch to form metal electrodes on the interlayer dielectric isolation layer (70), the source contact trench (71) and the gate contact trench (72). The metal electrodes include a metal gate (81) electrically connected to the bus gate lead (61b) and a metal source (82) electrically connected to the source lead (61c). S15. Form a passivation layer (90) on the interlayer dielectric isolation layer (70) on the metal gate (81) and the bus region, and open a contact hole (91) on the passivation layer (90) to expose the metal gate (81).
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, In step S11, the cell gate lead (61a) is electrically connected to the bus gate lead (61b).
7. A semiconductor structure, characterized in that, include: Substrate (10) having an epitaxial layer (20); A JFET layer (30) is formed on the epitaxial layer (20); A first type doped layer (40) is formed on the JFET layer (30), and a cell region and a bus region are defined on the surface of the first type doped layer (40). The second type doped pillar (50) extends from the surface of the first type doped layer (40) and penetrates the first type doped layer (40) and the JFET layer (30), and the bottom of the second type doped pillar (50) is located in the epitaxial layer (20); trenches are etched in the second type doped pillar (50), and a second type doped region (53) is left between the inner wall of the trench and the outer wall of the second type doped pillar (50), the trenches include cell trenches (51) formed in the cell region and bus trenches (52) formed in the bus region.
8. The semiconductor structure according to claim 7, characterized in that, It also includes a cell gate lead (61a) located on the bottom surface of the cell trench (51), a bus gate lead (61b) located on the bottom surface of the bus trench (52), and a source lead (61c) located on the top surface of the first type doped layer (40) and the second type doped region (53); the cell gate lead (61a) is electrically connected to the bus gate lead (61b).
9. The semiconductor structure according to claim 8, characterized in that, Interlayer dielectric isolation layer (70) is provided on the cell trench (51) and the bus trench (52). The interlayer dielectric isolation layer (70) on the cell region and the source lead (61c) are provided with a metal source (82) electrically connected to the source lead (61c). The bus gate lead (61b) is provided with a metal gate (81) electrically connected to the bus gate lead (61b).
10. The semiconductor structure according to claim 9, characterized in that, A passivation layer (90) is provided on the interlayer dielectric isolation layer (70) and the metal gate (81) of the bus region. A contact hole (91) is provided on the passivation layer (90) to expose the metal gate (81).