Semiconductor equipment

Abstract

The present invention provides a semiconductor device that improves current spread by reducing saturated drain current, lowering the degree of current concentration at the active source contact, and improving voltage overshooting or non-uniformity of source current at different cell region locations. [Solution] The semiconductor device includes a substrate including a cell region and a peripheral region PERI located outside the cell region, a first conductivity type semiconductor layer located on the upper surface of the substrate, a second conductivity type doping wall region located within the first conductivity type semiconductor layer, a gate electrode located on the first conductivity type semiconductor layer, a gate insulating layer located between the first conductivity type semiconductor layer and the gate electrode, a source electrode 170 located on the second conductivity type doping wall region, and a drain electrode located below the lower surface of the substrate. The source electrode includes a first source electrode 171 located on the gate electrode and a second source electrode 172 located on the first source electrode and having a greater electrical resistance than the first source electrode.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that reduces saturation drain current and prevents circuit short circuits. [Background technology]

[0002] In modern society, semiconductor devices are closely related to our daily lives. In particular, the importance of power semiconductor equipment used in a variety of fields, such as transportation (electric vehicles, railways, electric trams, etc.), renewable energy systems (solar power, wind power, etc.), and mobile devices, is gradually increasing. Power semiconductor devices are semiconductor devices used to handle high voltages and high currents, and perform functions such as power conversion and control in large power systems and high-power electronic devices. Power semiconductor devices possess the ability and durability to handle high power, can handle large amounts of current, and can withstand high voltages. For example, power semiconductor devices handle voltages ranging from several hundred to several thousand volts and currents ranging from tens to several thousand amperes. Power semiconductor devices can minimize power loss and improve the efficiency of electrical energy. Furthermore, power semiconductor devices can operate stably even in environments with high temperatures.

[0003] Such power semiconductor devices can be classified by material, for example, SiC power semiconductor devices and GaN power semiconductor devices. By using SiC or GaN instead of existing silicon wafers (Si wafers) to manufacture power semiconductor devices, the disadvantages of silicon, such as its unstable properties at high temperatures, can be compensated for. SiC power semiconductor devices are resistant to high temperatures and have low power loss, making them suitable for electric vehicles, renewable energy systems, and other applications. GaN power semiconductor devices are expensive, but they are efficient in terms of speed and are suitable for applications such as high-speed charging of mobile devices. Improving the performance and quality of these power semiconductor devices is a daily challenge. [Overview of the project] [Problems that the invention aims to solve]

[0004] The present invention has been made in view of the problems in the above-mentioned conventional semiconductor devices, and the object of the present invention is to achieve drain / source on-resistance (Rds) without adding further resistors outside the circuit (e.g., package or module) and without structural changes in the active source contact region such as changing the channel length. on Without changing the saturation drain current (Id sat The objective is to provide a semiconductor device that can reduce the current concentration of the active source contact, improve voltage overshooting or non-uniformity of source current at different cell region locations, thereby improving current spreading. [Means for solving the problem]

[0005] To achieve the above objective, the semiconductor device according to the present invention comprises a substrate including a cell region and a peripheral region disposed outside the cell region; a first conductivity type semiconductor layer disposed on the upper surface of the substrate; a second conductivity type doping wall region disposed within the first conductivity type semiconductor layer; a gate electrode disposed on the first conductivity type semiconductor layer; a gate insulating layer disposed between the first conductivity type semiconductor layer and the gate electrode; a source electrode disposed on the second conductivity type doping wall region; and a drain electrode disposed below the lower surface of the substrate, wherein the source electrode comprises a first source electrode disposed on the gate electrode; a second source electrode disposed on the first source electrode; and a resistive layer disposed between the first source electrode and the second source electrode, containing a conductive material with greater electrical resistance than the first source electrode.

[0006] Furthermore, a semiconductor device according to the present invention made to achieve the above objectives includes a substrate including a cell region and a peripheral region disposed outside the cell region, a first conductivity type semiconductor layer disposed on the upper surface of the substrate, a second conductivity type doping wall region disposed within the first conductivity type semiconductor layer, a gate electrode disposed on the first conductivity type semiconductor layer, a gate insulating layer disposed between the first conductivity type semiconductor layer and the gate electrode, a source electrode disposed on the second conductivity type doping wall region, and a drain electrode disposed below the lower surface of the substrate, wherein the source electrode includes a first source electrode disposed on the gate electrode, a second source electrode disposed on the first source electrode, and a third source electrode disposed on the second source electrode, characterized in that the second source electrode has a greater electrical resistance than the first source electrode, and the third source electrode has a greater electrical resistance than the second source electrode.

[0007] Furthermore, a semiconductor device according to the present invention made to achieve the above objectives comprises a substrate including a cell region and a peripheral region disposed outside the cell region; a first conductivity type semiconductor layer disposed on the upper surface of the substrate; a second conductivity type doping wall region disposed within the first conductivity type semiconductor layer; a gate electrode disposed on the first conductivity type semiconductor layer; a gate insulating layer disposed between the first conductivity type semiconductor layer and the gate electrode; a source electrode disposed on the second conductivity type doping wall region; and a drain electrode disposed below the lower surface of the substrate, wherein the source electrode includes a first source electrode disposed on the gate electrode and a second source electrode disposed on the first source electrode having a greater electrical resistance than the first source electrode.

[0008] A semiconductor device manufacturing method according to an embodiment of the present invention involves forming a first conductivity type semiconductor layer on the upper surface of a substrate, forming a second conductivity type doping wall region within the first conductivity type semiconductor layer, forming a gate insulating layer and a gate electrode on the first conductivity type semiconductor layer, forming a source electrode on the second conductivity type doping wall region, and forming a drain electrode below the lower surface of the substrate. The source electrode is formed by forming a first source electrode on the gate electrode, forming a second interlayer insulating layer covering the first source electrode, etching the second interlayer insulating layer to expose the first source electrode, forming a resistive layer inside the etched second interlayer insulating layer, and forming a second source electrode on the second interlayer insulating layer and the resistive layer. The resistive layer is made of a conductive material with a higher electrical resistance than the first source electrode.

[0009] Preferably, the first source electrode has a larger area along the first and second directions that intersect each other parallel to the upper surface of the substrate than the cell region. Preferably, the second source electrode is formed with a smaller area along the first and second directions than the first source electrode. Preferably, the resistive layer has a smaller area along the first and second directions than the first source electrode, and the second source electrode and the resistive layer are formed such that only a portion of them overlap each other in the third direction, with the third direction being perpendicular to the upper surface of the substrate. The source electrode is formed by forming a first source electrode on a gate electrode, forming a resistive layer on the first source electrode, forming a second interlayer insulating layer covering the first source electrode and the resistive layer, etching the second interlayer insulating layer to expose the resistive layer, and then forming a second source electrode inside the etched second interlayer insulating layer. Preferably, the resistive layer contains a conductive material with a higher electrical resistance than the first source electrode.

[0010] The source electrode is formed by creating a first source electrode on the gate electrode, creating an initial second interlayer insulating layer covering the first source electrode, etching the first interlayer insulating layer to expose the first source electrode, creating a first resistance layer inside the etched first interlayer insulating layer, creating a first third interlayer insulating layer on the first interlayer insulating layer and the first resistance layer, etching the first third interlayer insulating layer to expose the first resistance layer, creating a first second source electrode inside the etched first third interlayer insulating layer, creating a second interlayer insulating layer covering the first second source electrode, and etching the second interlayer insulating layer... After etching to expose the first second source electrode, a second resistive layer is formed inside the etched second second interlayer insulating layer, a second third interlayer insulating layer is formed on the second second interlayer insulating layer and the second resistive layer, the second third interlayer insulating layer is etched to expose the second resistive layer, and a second second source electrode is formed inside the etched second third interlayer insulating layer, wherein the electrical resistance of the second source electrode is higher the higher it is located in the third direction, where the third direction is perpendicular to the upper surface of the substrate, and it is preferable that the electrical resistance of the resistive layer is higher the higher it is located in the third direction.

[0011] Furthermore, in the method for manufacturing a semiconductor device according to an embodiment of the present invention, a first conductivity type semiconductor layer is formed on the upper surface of a substrate, a second conductivity type doping wall region is formed within the first conductivity type semiconductor layer, a gate insulating layer and a gate electrode are formed on the first conductivity type semiconductor layer, a source electrode is formed on the second conductivity type doping wall region, and a drain electrode is formed below the lower surface of the substrate. The source electrode is formed by forming a first source electrode on the gate electrode, a second source electrode on the first source electrode, and a third source electrode on the second source electrode, wherein the second source electrode has a higher electrical resistance than the first source electrode, and the third source electrode has a higher electrical resistance than the second source electrode.

[0012] Preferably, the source electrode is formed by forming a first source electrode on the gate electrode, forming a second interlayer insulating layer covering the first source electrode, etching the second interlayer insulating layer to expose the first source electrode, forming a second source electrode inside the etched second interlayer insulating layer, and forming a third source electrode on the second interlayer insulating layer and the second source electrode.

[0013] Furthermore, in the embodiment of the present invention, the method for manufacturing a semiconductor device involves forming a first conductivity type semiconductor layer on the upper surface of a substrate, forming a second conductivity type doping wall region within the first conductivity type semiconductor layer, forming a gate insulating layer and a gate electrode on the first conductivity type semiconductor layer, forming a source electrode on the second conductivity type doping wall region, and forming a drain electrode below the lower surface of the substrate. The source electrode is formed by forming a first source electrode on the gate electrode, forming a barrier layer covering the first source electrode, and forming a second source electrode on the barrier layer.

[0014] Preferably, the source electrode is formed by forming a first source electrode on the gate electrode, etching the first source electrode, forming a barrier layer inside the etched first source electrode, and then forming a second source electrode inside the first source electrode where the barrier layer is formed. [Effects of the Invention]

[0015] According to the semiconductor device of the present invention, the drain / source on-resistance (Rds) can be reduced without adding further resistors outside the circuit (e.g., package or module) and without changing the channel length or other structural changes in the active source contact region. on Without changing the saturation drain current (Id sat This reduces the amount of ) and prevents short circuits. Furthermore, it is possible to reduce the current concentration of the active source contact, improve voltage overshooting or unevenness of source current at different cell regions, and thereby improve current spread. [Brief explanation of the drawing]

[0016] [Figure 1] This is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view taken along the line A-A' in Figure 1. [Figure 3] This is a circuit diagram for a semiconductor device according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and corresponds to Figure 2. [Figure 5] This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and corresponds to Figure 2. [Figure 6] This is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view taken along the line A-A' in Figure 6. [Figure 8] This is a plan view showing a morphological embodiment according to an embodiment of the present invention. [Figure 9] This is a cross-sectional view taken along the line A-A' in Figure 8. [Figure 10] This is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 11] This is a cross-sectional view taken along the line A-A' in Figure 10. [Figure 12] This is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 13] This is a cross-sectional view taken along the line A-A' in Figure 12. [Figure 14] This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and corresponds to Figure 13. [Modes for carrying out the invention]

[0017] Next, specific examples of embodiments for implementing the semiconductor device according to the present invention will be described with reference to the drawings.

[0018] The present invention can be realized in various different forms and is not limited to the embodiments described herein. To clearly explain the present invention, unnecessary parts have been omitted, and the same or similar reference numerals are used throughout the specification for identical or similar components. Furthermore, the dimensions and thicknesses of each component shown in the drawings are arbitrary for the sake of explanation and are not necessarily limited to those shown in the present invention. The thickness is enlarged in the drawings to clearly represent various layers and regions. Furthermore, for ease of explanation, the thickness of some layers and regions is exaggerated in the drawings. Furthermore, when we say that a layer, membrane, region, plate, or other part is "on top of" another part, this includes not only cases where it is "directly on top" of the other part, but also cases where the other part is in between them. Conversely, when one part is said to be "directly above" another part, it means that there is no other part in between. Furthermore, being "above" the reference point means being located either above or below the reference point, and does not necessarily mean being located "above" in the opposite direction of gravity.

[0019] Furthermore, when a specification states that a part of it "includes" a certain component, unless otherwise specified, this does not mean that other components are excluded, but rather that other components may be included. Furthermore, throughout the specification, "on a plane" means when the subject is viewed from above, and "on a cross-section" means when the subject is viewed from the side of a cross-section obtained by cutting the subject perpendicularly. Furthermore, throughout the specification, two directions parallel to and perpendicular to the upper surface of the substrate are defined as the first direction D1 and the second direction D2, respectively, and the direction perpendicular to the upper surface of the substrate is described as the third direction D3. For example, the first direction D1 and the second direction D2 could be the length direction and the width direction, respectively, and the third direction D3 could be the thickness direction.

[0020] Figure 1 is a plan view showing the schematic configuration of a semiconductor device according to an embodiment of the present invention, Figure 2 is a cross-sectional view taken along the line A-A' in Figure 1, and Figure 3 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. For clear understanding and simplified illustration, Figure 1 focuses on the first source electrode 171, the second source electrode 172, and the resistive layer 176 of the source electrode 170, as well as the gate pad 155 and gate wiring 156.

[0021] Referring to Figures 1 to 3, the semiconductor device includes a substrate 110, a first conductivity type semiconductor layer 131 disposed on the upper surface of the substrate 110, a second conductivity type doping wall region 133 disposed within the first conductivity type semiconductor layer 131, a gate electrode 150 disposed on the first conductivity type semiconductor layer 131 and the second conductivity type doping wall region 133, a gate insulating layer 151 disposed between the first conductivity type semiconductor layer 131 and the gate electrode 150, a source electrode 170 disposed on the second conductivity type doping wall region 133, and a drain electrode 180 disposed below the lower surface of the substrate 110. The substrate 110 includes a cell region CELL and a peripheral region PERI surrounding the cell region CELL.

[0022] The first source electrode 171 of the source electrode 170, which will be described later, is positioned on top of the cell region CELL. The first source electrode 171 covers the cell region CELL. In other words, the cell region CELL is completely superimposed on the first source electrode 171 in the third direction D3. A gate pad 155 is positioned on one side of the first source electrode 171 in either the first direction D1 or the second direction D2. For example, the gate pad 155 is located in the peripheral region PERI. In addition, gate wiring 156 extending from the gate pad 155 is placed in the peripheral region PERI. The gate wiring 156 is extended to cover the entire peripheral region PERI. In other words, the gate wiring 156 surrounds the first source electrode 171. The first source electrode 171 extends downward in the third direction D3 and makes active source contact with the second conductivity-type doping wall region 133, which will be described later. The gate pad 155 and gate wiring 156 are electrically in contact with the gate electrode 150.

[0023] The substrate 110 is a semiconductor substrate containing SiC. For example, the substrate 110 is made of a 4HSiC substrate. In some cases, the substrate 110 may consist of a 3CSiC substrate, a 6HSiC substrate, or the like. The substrate 110 is doped with a first-type impurity. For example, the first type of conductivity impurity is an n-type impurity. In other words, substrate 110 is doped with n-type. The substrate 110 is doped with a high concentration of n-type polymer. The resistivity of substrate 110 may be between approximately 0.005 Ω·cm and approximately 0.035 Ω·cm. The thickness of the substrate 110 may be between approximately 10 μm and approximately 700 μm. The material, doping type, doping concentration, resistivity, thickness, etc. of the substrate 110 are not limited to these and can be varied in various ways. The substrate 110 has a first surface and a second surface that face each other. The first surface of the substrate 110 is the top surface of the substrate 110, and the second surface of the substrate 110 is the bottom surface of the substrate 110.

[0024] The first conductive semiconductor layer 131 is placed on the first surface, or upper surface, of the substrate 110. The lower surface of the first conductive semiconductor layer 131 is in contact with the upper surface of the substrate 110. However, the invention is not limited to this, and other layers may be further arranged between the substrate 110 and the first conductive semiconductor layer 131. The first conductive semiconductor layer 131 may be an epitaxy layer formed from the substrate 110 using epitaxial growth. The first conductive semiconductor layer 131 contains SiC. For example, the first conductive semiconductor layer 131 includes 4HSiC. The first conductive semiconductor layer 131 is doped with n-type semiconductor. The first conductive semiconductor layer 131 is doped at a low concentration in the n-type configuration. The doping concentration of the first conductive semiconductor layer 131 is lower than the doping concentration of the substrate 110. The doping concentration of the first conductive semiconductor layer 131 is approximately 1 × 10⁻⁶. 15 cm -3 The above is approximately 1 x 10 17 cm -3 The following are possible: The thickness of the first conductive semiconductor layer 131 may be approximately 1 μm or more and approximately 13 μm or less. The material, doping type, and doping concentration of the first conductive semiconductor layer 131 are not limited to these and can be varied in various ways.

[0025] The second conductivity type doping wall region 133 may be located within the first conductivity type semiconductor layer 131. The second conductivity type doping wall region 133 may be located on top of the first conductivity type semiconductor layer 131. The second conductive doping wall region 133 is in contact with the lower surface of the second conductive doping layer 135, which will be described later. The second conductive doping wall region 133 surrounds the lower surface and side surface of the first conductive doping layer 137, which will be described later. At least a partial region of the upper surface of the p-type doping wall region 133 overlaps at least a partial region of a gate electrode 150 and at least a partial region of a gate insulating layer 151, which will be described later, in a third direction D3. The p-type doping wall region 133 extends from the upper surface of the n-type semiconductor layer 131 toward the lower surface of the n-type semiconductor layer 131. That is, the p-type doping wall region 133 extends in the third direction D3 from the upper surface of the n-type semiconductor layer 131.

[0026] The p-type doping wall region 133 is formed in at least a partial region of the n-type semiconductor layer 131 through an ion implantation method. The p-type doping wall region 133 contains SiC. For example, the p-type doping wall region 133 contains 4H SiC. The p-type doping wall region 133 is doped p-type. The p-type doping wall region 133 is doped p-type at a low concentration. The doping concentration of the p-type doping wall region 133 is about 1 × 10 17 cm -3 or more and about 1 × 10 19 cm -3 or less. [[ID=2​​​​​​​​At least a portion of the upper surface of the second conductive doping layer 135 is in contact with the lower surface of the silicide layer 190, which will be described later, but is not limited to this. For example, at least a portion of the upper surface of the second conductive doping layer 135 is in contact with the lower surface of the source electrode 170. In this case, the second conductive doping layer 135 may have a width wider than the width of the source electrode 170.

[0028] The second conductivity-type doping layer 135 extends in the third direction D3 from the upper surface of the first conductivity-type semiconductor layer 131. At this time, the thickness of the second conductive doping layer 135 along the third direction D3 is smaller than the thickness of the second conductive doping wall region 133 along the third direction D3. Furthermore, the second conductive doping layer 135 has a narrower width than the second conductive doping wall region 133. In other words, the second conductive doping layer 135 may be embedded within the second conductive doping wall region 133. The second conductive doping layer 135 is formed in at least a portion of the second conductive doping wall region 133 by an ion implantation method.

[0029] The second conductive doping layer 135 contains SiC. For example, the second conductive doping layer 135 contains 4HSiC. The second conductive doping layer 135 is doped with p-type. The second conductive doping layer 135 forms an ohmic contact with the source electrode 170. As a result, the second conductive doping layer 135 is p-type and doped at a high concentration. In this embodiment, the doping concentration of the second conductive doping layer 135 is higher than the doping concentration of the second conductive doping wall region 133. The doping concentration of the second conductive doping layer 135 is approximately 1 × 10⁻⁶. 18 cm -3 The above is approximately 5 x 10 20 cm -3The following are possible: The substance, doping type, and doping concentration of the second conductive doping layer 135 are not limited to these and can be varied in various ways.

[0030] The first conductive doping layer 137 is placed within the second conductive doping wall region 133. The first conductivity-type doping layer 137 is positioned on top of the first conductivity-type semiconductor layer 131 and surrounds both sides of the second conductivity-type doping layer 135. The upper surface of the first conductive doping layer 137 is superimposed in the third direction D3 on at least a portion of the gate electrode 150 and at least a portion of the gate insulating layer 151, which will be described later. Furthermore, the upper surface of the first conductive doping layer 137 overlaps, but is not limited to, at least a portion of the source electrode 170 (described later) in the third direction D3. The upper surface of the first conductive doping layer 137 is in direct contact with the gate insulating layer 151, which will be described later. The first conductive doping layer 137 extends in the third direction D3 from the upper surface of the first conductive semiconductor layer 131. The first conductive doping layer 137 is embedded within the second conductive doping wall region 133. At this time, the thickness of the first conductive doping layer 137 along the third direction D3 is smaller than the thickness of the second conductive doping wall region 133 along the third direction D3.

[0031] The first conductivity type doping layer 137 is a doping region formed within the first conductivity type semiconductor layer 131 using an ion implantation process. The first conductive doping layer 137 contains SiC. For example, the first conductive doping layer 137 contains 4HSiC. The first conductive doping layer 137 is doped with n-type doping. The first conductive doping layer 137 is doped with a high concentration of n-type doping. The doping concentration of the first conductive doping layer 137 is approximately 1 × 10⁻⁶. 18 cm -3 The above is approximately 5 x 1020 cm -3 The following are possible: The substance, doping type, and doping concentration of the first conductive doping layer 137 are not limited to these and can be varied in various ways.

[0032] The gate electrode 150 is placed on the first conductive semiconductor layer 131. The gate electrode 150 may be separated from the first conductivity type semiconductor layer 131. For example, the gate electrode 150 is separated from the first conductivity type semiconductor layer 131 in a direction perpendicular to it (e.g., the third direction D3) by the gate insulating layer 151. In one embodiment, the semiconductor device has a planar gate structure. In other words, in the semiconductor device, the gate electrode 150 has a flat plate shape with a flat upper surface and a flat lower surface, and the lower surface of the gate electrode 150 is located at a higher level than the uppermost surface of the first conductivity type semiconductor layer 131. However, the semiconductor device according to one embodiment may have a trench-shaped gate structure. For example, in a semiconductor device, a trench of a predetermined depth may be formed in the first conductivity type semiconductor layer 131, and a gate electrode 150 may be disposed inside the trench, separated from the first conductivity type semiconductor layer 131 in a third direction D3.

[0033] Furthermore, the gate electrode 150 is positioned at a distance from the first conductivity type semiconductor layer 131 in the first direction D1 and / or the second direction D2. The gate electrode 150 is superimposed in the third direction D3 on the second conductivity type doping wall region 133 and the first conductivity type doping layer 137. The gate electrode 150 contains a conductive material. For example, the gate electrode 150 contains polysilicon doped with impurities. Other examples include the gate electrode 150, which may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal nitrogen oxide, or a combination thereof. The gate electrode 150 may consist of a single layer or multiple layers.

[0034] The gate insulating layer 151 is placed between the first conductive semiconductor layer 131 and the gate electrode 150. In other words, the gate insulating layer 151 is positioned below the third direction D3 of the gate electrode 150 and covers the lower surface of the gate electrode 150. The gate electrode 150 is insulated from the first conductivity type semiconductor layer 131 by the gate insulating layer 151. The thickness of the gate insulating layer 151 is substantially constant. The gate insulating layer 151 is superimposed on the second conductivity type doping wall region 133 and the first conductivity type doping layer 137 in the third direction D3. The lower surface of the gate insulating layer 151 is in direct contact with the second conductivity type doping wall region 133 and the first conductivity type doping layer 137, but is not limited to this. The gate insulating layer 151 contains an insulating material. For example, the gate insulating layer 151 contains SiO2. However, this is not the only option, and the material of the gate insulating layer 151 can be varied in many ways. As another example, the gate insulating layer 151 may include SiN, SiON, SiC, SiCN, or a combination thereof. The gate insulating layer 151 may consist of a single layer or multiple layers.

[0035] The first interlayer insulating layer 140 is placed on top of the first conductive semiconductor layer 131. For example, the first interlayer insulating layer 140 is placed on top of the gate electrode 150. In other words, the first interlayer insulating layer 140 covers the top and side surfaces of the gate electrode 150. The first interlayer insulating layer 140 covers the side surface of the gate insulating layer 151. The first interlayer insulating layer 140 is also placed on top of the first conductive doping layer 137. The first interlayer insulating layer 140 has a lower surface that is in contact with at least a portion of the upper surface of the first conductive doping layer 137. The gate electrode 150 is insulated from the source electrode 170 by the first interlayer insulating layer 140. The first interlayer insulating layer 140 contains an insulating material. As an example, the first interlayer insulating layer 140 contains the same insulating material as the gate insulating layer 151. For example, the first interlayer insulating layer 140 contains SiO2. However, the first interlayer insulating layer 140 may include various types of insulating materials for insulating the gate electrode 150 from the source electrode 170. For example, the first interlayer insulating layer 140 may include SiOP, SiN, SiN, or a combination thereof. The first interlayer insulating layer 140 may consist of a single layer or multiple layers. When the first interlayer insulating layer 140 is made of the same material as the gate insulating layer 151, the boundary between the first interlayer insulating layer 140 and the gate insulating layer 151 is not clearly defined at the point where the first interlayer insulating layer 140 and the gate insulating layer 151 are in contact.

[0036] The source electrode 170 is placed on the second conductivity type doping wall region 133. A second conductivity type doping layer 135 and a first conductivity type doping layer 137 are arranged between the source electrode 170 and the second conductivity type doping wall region 133. The source electrode 170 is electrically connected to the second conductivity type doping wall region 133 by the second conductivity type doping layer 135. A current or voltage is supplied to the cell region CELL through the source electrode 170. The source electrode 170 includes a first source electrode 171 and a second source electrode 172.

[0037] The first source electrode 171 is positioned on the second conductivity-type doping wall region 133. The first source electrode 171 is positioned on both sides of the gate electrode 150. However, the invention is not limited to this, and the first source electrode 171 may be placed only on one side of the gate electrode 150. The first source electrode 171 is positioned on top of the gate electrode 150. A first interlayer insulating layer 140 is placed between the first source electrode 171 and the gate electrode 150. The first source electrode 171 is separated from the gate electrode 150 by the first interlayer insulating layer 140. The first source electrode 171 is in contact with the side and top surfaces of the first interlayer insulating layer 140. As an example, the first source electrode 171 has a portion located between the gate electrodes 150 and a portion located above the gate electrodes 150.

[0038] The portion of the first source electrode 171 located above the gate electrode 150 is located above the cell region CELL. The portion of the first source electrode 171 located above the gate electrode 150 covers the cell region CELL. The portion of the first source electrode 171 located above the gate electrode 150 lies on a plane (hereinafter referred to as "on the plane") that extends perpendicularly to the third direction D3 in the first direction D1 and the second direction D2. For example, in Figure 1, the area along the first direction D1 and the second direction D2 is larger than that along the cell region CELL. In other words, the portion of the first source electrode 171 located above the gate electrode 150 partially overlaps with the cell region CELL in the third direction D3, while the cell region CELL completely overlaps with the portion of the first source electrode 171 located above the gate electrode 150 in the third direction D3. The portion of the first source electrode 171 located between the gate electrodes 150 is located on both sides of the gate electrode 150. The portion of the first source electrode 171 located between the gate electrodes 150 is surrounded by the gate electrodes 150 with the first interlayer insulating layer 140 in between. However, this is not limited to this, and the portion of the first source electrode 171 located between the gate electrodes 150 may be arranged only on one side of the gate electrode 150.

[0039] The portion of the first source electrode 171 located between the gate electrode 150 is the portion of the first source electrode 171 that extends downward in the third direction D3 toward the second conductivity type doping wall region 133 from the portion located above the gate electrode 150. The portion of the first source electrode 171 located between the gate electrode 150 extends downward in the third direction D3 and makes active source contact with the second conductivity type doping wall region 133. The portion of the first source electrode 171 located between the gate electrode 150 is superimposed on the second conductivity type doping layer 135 and the first conductivity type doping layer 137 in the third direction D3. However, this is not limited to this, and the portion of the first source electrode 171 located between the gate electrode 150 may not overlap the first conductivity type doping layer 137 with the third direction D3. At this time, the upper surface of the first conductive doping layer 137 may be covered by the gate insulating layer 151.

[0040] As an example, the first source electrode 171 is made of tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), ruthenium (Ru), iridium (Ir), and This may include, but is not limited to, sodium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), or combinations thereof. The first source electrode 171 may consist of a single layer or multiple layers.

[0041] The second source electrode 172 is positioned on top of the first source electrode 171. As an example, the second source electrode 172 is positioned in the center of the upper surface of the first source electrode 171. The second source electrode 172 is electrically connected to the first source electrode 171 and applies an externally supplied source voltage to the first source electrode 171 through the second source electrode 172. The second source electrode 172 has a smaller area along the first direction D1 and the second direction D2 than the first source electrode 171 on a plane (for example, Figure 1). In other words, the first source electrode 171 partially overlaps with the second source electrode 172 in the third direction D3, while the second source electrode 172 completely overlaps with the first source electrode 171 in the third direction D3. The second source electrode 172 has a higher electrical resistance than the first source electrode 171.

[0042] For example, the second source electrode 172 may have an electrical resistance 10 times or more greater than that of the first source electrode 171, for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, 90 times or more, 100 times or more, 200 times or more, 300 times or more, 400 times or more, 500 times or more, 600 times or more, 700 times or more, 800 times or more, 900 times or more, 1000 times or more, 2000 times or more, 3000 times or more, 4000 times or more, 5000 times or more, 6000 times or more, 7000 times or more, 8000 times or more, 9000 times or more, or It can be more than 10,000 times, and less than 10,000 times, for example, less than 9,000 times, less than 8,000 times, less than 7,000 times, less than 6,000 times, less than 5,000 times, less than 4,000 times, less than 3,000 times, less than 2,000 times, less than 1,000 times, less than 900 times, less than 800 times, less than 700 times, less than 600 times, less than 500 times, less than 400 times, less than 300 times, less than 200 times, less than 100 times, less than 90 times, less than 80 times, less than 70 times, less than 60 times, less than 50 times, less than 40 times, less than 30 times, or less than 20 times, and can be between 10 and 10,000 times.

[0043] As an example, the electrical resistance of the first source electrode 171 is 1.0 × 10⁻⁶ at 0°C. -8 It can be greater than or equal to Ω·m, for example, 2.0 × 10⁻⁶ -8 Ω m or more, 3.0×10-8 Ω·m or more, 4.0×10 -8 Ω·m or more, 5.0×10 -8 Ω·m or more, 6.0×10 -8 Ω·m or more, 7.0×10 -8 Ω·m or more, 8.0×10 -8 Ω·m or more, also 9.0×10 -8 Ω·m or more is obtained, 10.0×10 -8 Ω·m or less is obtained, for example, 9.0×10 -8 Below Ω·m, 8.0×10 -8 Below Ω·m, 7.0×10 -8 Below Ω·m, 6.0×10 -8 Below Ω·m, 5.0×10 -8 Below Ω·m, 4.0×10 -8 Below Ω·m, 3.0×10 -8 Ω·m or less, and 2.0×10 -8 Ω·m or less is obtained, 1.0×10 -8 Ω·m and above ~ 10.0 × 10 -8 Ω·m or less means る.

[0044] The electrical resistance of the second electrode 172 is 0°C, 10.0×10 -8 Ω·m exceeds であり, for example, えば, 20.0×10 -8 Ω·m or more, 30.0×10 -8 Ω·m or more, 40.0×10 -8 Ω·m or more, 50.0×10 -8 Ω·m or more, 60.0×10 -8 Ω·m or above, 70.0×10 -8 Ω·m or above, 80.0×10 -8 Ω·m or above, 90.0×10 -8 Ω·m or more, 100.0×10 -8 Ω·m or more, 200.0×10 -8 Ω·m or more, 300.0×10 -8 Ω·m or more, 400.0×10 -8 Ω·m or more, 500.0×10 -8 Ω·m or more, 600.0×10 -8 Ω·m or more, 700.0×10 -8 Ω·m or more, 800.0×10 -8 Ω·m or more, also 900.0×10-8 It can be greater than Ω·m, and 1000.0 × 10 -8 It can be less than or equal to Ω·m, for example, 900.0 × 10⁻⁶ -8 Ω m or less, 800.0×10 -8 Ω m or less, 700.0×10 -8 Ω m or less, 600.0×10 -8 Ω m or less, 500.0×10 -8 Ω m or less, 400.0×10 -8 Ω m or less, 300.0×10 -8 Ω m or less, 200.0×10 -8 Ω m or less, 100.0×10 -8 Ω m or less, 90.0×10 -8 Ω m or less, 80.0×10 -8 Ω m or less, 70.0×10 -8 Ω m or less, 60.0×10 -8 Ω m or less, 50.0×10 -8 Ω m or less, 40.0×10 -8 Ω m or less, 30.0×10 -8 Ω m or less, or 20.0×10 -8 It can be less than or equal to Ω·m, and 10.0 × 10 -8 Ω m or more ~1000.0×10 -8 It may be less than or equal to Ω·m, or 100.0 × 10⁻⁶ -8 Ω m or more ~1000.0×10 -8 It may be less than or equal to Ω·m.

[0045] As an example, the electrical resistance of the first source electrode 171 and the second source electrode 172 can be measured by the TLM (transmission line measurement) analysis method. For example, TLM analysis can be performed using McChistory's JVL equipment. According to TLM analysis, the electrical resistance value can be measured based on the length of the first source electrode 171 or the second source electrode 172. For example, the second source electrode 172 can include any material with a higher electrical resistance than the first source electrode 171, without any limitations. For example, the second source electrode 172 may contain palladium (Pd), tin (Sn), tantalum (Ta), chromium (Cr), strontium (St), antimony (Sb), zirconium (Zr), rubidium (Rb), manganese (Mn), polysilicon, tantalum carbide nitride (TaCN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), tantalum aluminum nitride (TaAlN), or a combination thereof, and may consist of a single layer or multiple layers.

[0046] For example, the thickness of the second source electrode 172 can be 10 nm or more, and for example, 20 nm or more, 30 nm or more, 40 nm or more, 50 nm or more, 60 nm or more, 70 nm or more, 80 nm or more, 90 nm or more, 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, 500 nm or more, 600 nm or more, 700 nm or more, 800 nm or more, 900 nm or more, 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, 5 μm or more, 6 μm or more, 7 μm or more, 8 μm or more, or 9 μm or more. It can be 10 μm or less, for example, 9 μm or less, 8 μm or less, 7 μm or less, 6 μm or less, 5 μm or less, 4 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 900 nm or less, 800 nm or less, 700 nm or less, 600 nm or less, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 80 nm or less, 70 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and can be 10 nm or more to 10 μm or less. Here, the thickness of the second source electrode 172 is the shortest distance along the third direction D3 from the lower surface to the upper surface of the second source electrode 172 on a cross-section cut perpendicular to the second direction D2 in the first direction D1 and the third direction D3 (for example, Figure 2).

[0047] The source electrode 170 further includes a resistive layer 176 between the first source electrode 171 and the second source electrode 172. As an example, the first source electrode 171, the resistive layer 176, and the second source electrode 172 are sequentially stacked in the third direction D3. The first source electrode 171 is electrically connected to the second source electrode 172 through the resistive layer 176. In other words, the first source electrode 171 and the second source electrode 172 are separated from each other in the third direction D3 with the resistive layer 176 in between, without directly contacting each other. The resistive layer 176 has a smaller area along the first direction D1 and the second direction D2 than the first source electrode 171 on a plane (for example, Figure 1). In other words, the first source electrode 171 is only partially superimposed on the resistive layer 176 in the third direction D3, while the resistive layer 176 is completely superimposed on the first source electrode 171 in the third direction D3. In this case, the resistive layer 176 may have a smaller area along the first direction D1 and the second direction D2 than the second source electrode 172 on a plane (for example, Figure 1), or it may be substantially the same. Furthermore, the second source electrode 172 and the resistive layer 176 may only partially overlap each other in the third direction D3.

[0048] The resistive layer 176 has a higher electrical resistance than the first source electrode 171. Furthermore, the resistive layer 176 may have an electrical resistance lower than or substantially the same as that of the second source electrode 172. For example, the resistive layer 176 may have an electrical resistance 10 times or more greater than that of the first source electrode 171, for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, or 90 times or more, and may be 100 times or less, for example, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and may be between 10 times and 100 times or less. At this time, the second source electrode 172 may have an electrical resistance that is 10 times or more, for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, or 90 times or more that of the resistance layer 176, and may be 100 times or less, for example, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and may be from 10 times or more to 100 times or less.

[0049] As an example, the electrical resistance of the resistance layer 176 may exceed 10.0×10 -8 Ω·m at 0 °C, for example, 20.0×10 -8 Ω·m or more, 30.0×10 -8 Ω·m or more, 40.0×10 -8 Ω·m or more, 50.0×10 -8 Ω·m or more, 60.0×10 -8 Ω·m or more, 70.0×10 -8 Ω·m or more, 80.0×10 -8 Ω·m or more, or 90.0×10 -8 Ω·m or more, and may be less than 100.0×10 -8 Ω·m, for example, 90.0×10 -8 Ω·m or less, 80.0×10 -8 Ω·m or less, 70.0×10 -8 Ω·m or less, 60.0×10 -8 Ω·m or less, 50.0×10 -8 Ω·m or less, 40.0×10 -8 Ω·m or less, 30.0×10 -8 Ω·m or less, or 20.0×10 -8 Ω·m or less, and may exceed 10.0×10 -8 Ω·m to less than 100.0×10 -8 Ω·m.

[0050] As an example, the electrical resistance of the resistance layer 176 can be measured by the TLM (transmission line measurement) analysis method. For example, TLM analysis can be performed using JVL equipment from McScience. According to TLM analysis, the electrical resistance value is measured based on the length of the resistive layer 176. As an example, the resistive layer 176 may contain, without limitation, a conductive material with a higher electrical resistance than the first source electrode 171. For example, the resistive layer 176 may contain palladium (Pd), tin (Sn), tantalum (Ta), chromium (Cr), strontium (St), antimony (Sb), zirconium (Zr), rubidium (Rb), manganese (Mn), polysilicon, tantalum carbide nitride (TaCN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), tantalum aluminum nitride (TaAlN), or a combination thereof, and may consist of a single layer or multiple layers.

[0051] For example, if the resistive layer 176 contains polysilicon, the electrical resistance of polysilicon will be 10.0 × 10⁻¹⁰ at 0°C, depending on the type and concentration of the doping element. -8 Exceeding Ω m~100.0×10 -8 Adjust to less than Ω·m. For example, the thickness of the resistive layer 176 may be 10 nm or more, for example, 20 nm or more, 30 nm or more, 40 nm or more, 50 nm or more, 60 nm or more, 70 nm or more, 80 nm or more, 90 nm or more, 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, 500 nm or more, 600 nm or more, 700 nm or more, 800 nm or more, 900 nm or more, 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, 5 μm or more, 6 μm or more, 7 μm or more, 8 μm or more, or 9 μm or more. It can be 0 μm or less, for example, 9 μm or less, 8 μm or less, 7 μm or less, 6 μm or less, 5 μm or less, 4 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 900 nm or less, 800 nm or less, 700 nm or less, 600 nm or less, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 80 nm or less, 70 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and it can be 10 nm or more to 10 μm or less. Here, the thickness of the resistive layer 176 is the shortest distance along the third direction D3 from the bottom surface to the top surface of the resistive layer 176 on a cross-section cut perpendicular to the second direction D2 in the first direction D1 and the third direction D3 (for example, Figure 2).

[0052] The second interlayer insulating layer 175 is placed on top of the first source electrode 171. The second interlayer insulating layer 175 covers the upper surface of the first source electrode 171. Furthermore, the second interlayer insulating layer 175 covers the sides of the resistive layer 176. As an example, the second interlayer insulating layer 175 is placed between the first source electrode 171 and the second source electrode 172. The second interlayer insulating layer 175 separates the first source electrode 171 and the second source electrode 172 from each other, while the first source electrode 171 and the second source electrode 172 are electrically connected to each other through the resistive layer 176. The level of the upper surface of the second interlayer insulating layer 175 along the third direction D3 is substantially the same as the level of the upper surface of the resistive layer 176 along the third direction D3. In other words, the upper surface of the second interlayer insulating layer 175 and the upper surface of the resistive layer 176 are coplanar. As a result, the resistive layer 176 is located within the second interlayer insulating layer 175, and the second source electrode 172 is located above the second interlayer insulating layer 175.

[0053] The second interlayer insulating layer 175 contains an insulating material. For example, the second interlayer insulating layer 175 contains SiO2. However, the second interlayer insulating layer 175 may include a variety of insulating materials for insulating the first source electrode 171 and the second source electrode 172. For example, the second interlayer insulating layer 175 may include SiOP, SiN, SiON, or a combination thereof. The second interlayer insulating layer 175 may consist of a single layer or multiple layers.

[0054] In SiC power semiconductor devices, there is a method to regulate the current to prevent short circuits, but in this case, the resistance of channels and other components increases, so the drain / source on-resistance (Rds) on ) will increase. Therefore, Rds on To reduce the amount of noise, reduce the channel length. However, changing the channel length requires an increase in current, resulting in a saturation drain current (Id sat Damages will be incurred. Therefore, Id sat While reducing Rds on It is necessary to maintain this condition to prevent short circuits.

[0055] A semiconductor device according to an embodiment of the present invention includes a first source electrode 171 on which the source electrode 170 is placed on a gate electrode 150, and a second source electrode 172 placed on the first source electrode 171 and having a greater electrical resistance than the first source electrode 171. Alternatively, the source electrode 170 is positioned between the first source electrode 171 and the second source electrode 172, and includes a resistive layer 176 containing a conductive material with greater electrical resistance than the first source electrode 171. In other words, the active source contact region where the source electrode 170 contacts the second conductivity type doping wall region 133 includes a second source electrode 172 or a resistive layer 176, the electrical resistance of which increases as you move upward in the third direction D3.

[0056] According to this, as shown in the circuit diagram in Figure 3, the gate pad 155 on the gate G side is in direct contact with metal, but the current flowing into the source S side is supplied through the second source electrode 172 or the resistive layer 176, which have high electrical resistance. Thus, increasing the local resistance in the source S-side current path allows more current to flow due to the ballast resistance principle, and the voltage drop reduces the potential difference between the gate G and source S. When the potential difference between the gate G and source S decreases, a channel closing effect occurs, limiting the current and preventing a short circuit. Therefore, without adding further resistors outside the circuit (e.g., package or module) and without structural changes in the active source contact region such as changing the channel length, Rds on Without changing Id sat This reduces the amount of stress and prevents short circuits.

[0057] Furthermore, the second source electrode 172 or the resistive layer 176, positioned above the source electrode 170, has relatively high electrical resistance, while the first source electrode 171, positioned below the source electrode 170 and making active source contact, has relatively low electrical resistance. Since the area of ​​the first source electrode 171 is relatively larger than the area of ​​the second source electrode 172 or the resistive layer 176, the current concentration of the active source contact is reduced, improving voltage overshooting or non-uniformity of source current at each cell region, thereby improving current spreading.

[0058] As an example, a semiconductor device is manufactured by forming a first conductivity type semiconductor layer 131 on the upper surface of a substrate 110, forming a second conductivity type doping wall region 133 within the first conductivity type semiconductor layer 131, forming a gate insulating layer 151 and a gate electrode 150 on the first conductivity type semiconductor layer 131, forming a source electrode 170 on the second conductivity type doping wall region 133, and forming a drain electrode 180 below the lower surface of the substrate 100. The source electrode 170 is formed by forming a first source electrode 171 on the gate electrode 150, forming a second interlayer insulating layer 175 covering the first source electrode 171, etching the second interlayer insulating layer 175 to expose the first source electrode 171, forming a resistive layer 176 inside the etched second interlayer insulating layer 175, and forming a second source electrode 172 on the second interlayer insulating layer 175 and the resistive layer 176. At this time, the resistive layer 176 is formed of a material containing a conductive substance that has a higher electrical resistance than the first source electrode 171.

[0059] Furthermore, the first source electrode 171 has a larger area along the first direction D1 and the second direction D2 than the cell region CELL. The second source electrode 172 is formed with a smaller area along the first direction D1 and the second direction D2 than the first source electrode 171. The resistive layer 176 has a smaller area along the first direction D1 and the second direction D2 than the first source electrode 171, and the second source electrode 172 and the resistive layer 176 are formed so that only a portion of them overlap each other in the third direction D3. The semiconductor device further includes a silicide layer 190 disposed between the source electrode 170 and the second conductivity type doping layer 135, and between the source electrode 170 and the first conductivity type doping layer 137.

[0060] The silicide layer 190 is conformally arranged along the interfaces between the source electrode 170 and the second conductivity type doping layer 135, and between the source electrode 170 and the first conductivity type doping layer 137. The lower surface of the silicide layer 190 is in direct contact with the second conductive doping layer 135 and the first conductive doping layer 137. The upper surface of the silicide layer 190 is in direct contact with the source electrode 170. The silicide layer 190 contains a metal silicide material. For example, the silicide layer 190 may contain tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), or a combination thereof.

[0061] In the semiconductor device manufacturing process, a silicidation process is performed on the upper surfaces of the second conductivity type doping layer 135 and the first conductivity type doping layer 137 to form a silicide layer 190. However, the process is not limited to this, and after forming the source electrode 170, an annealing step may be performed to reduce the contact resistance between the second conductivity type doping layer 135 and the source electrode 170, and between the first conductivity type doping layer 137 and the source electrode 170. As a result, the silicide layer 190 is formed along the interfaces between the source electrode 170 and the second conductivity type doping layer 135, and between the source electrode 170 and the first conductivity type doping layer 137.

[0062] The drain electrode 180 is positioned below the second surface of the substrate 110, that is, below the lower surface. The upper surface of the drain electrode 180 is in contact with the lower surface of the substrate 110. The drain electrode 180 makes ohmic contact with the substrate 110. Within the substrate 110, the region in contact with the drain electrode 180 is doped with a relatively higher concentration compared to other regions. However, the invention is not limited to this, and other predetermined layers may be further arranged between the drain electrode 180 and the substrate 110. For example, a silicide layer may be placed between the drain electrode 180 and the substrate 110. The silicide layer contains metal silicide material. The metal silicide layer ensures a smooth electrical connection between the drain electrode 180 and the substrate 110.

[0063] The drain electrode 180 contains a conductive material. For example, the drain electrode 180 may include metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, or conductive metal nitrogen oxide. The drain electrode 180 may be made of the same material as the source electrode 170, or it may be made of a different material. For example, the drain electrode 180 is made of titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium carbide (TiC), titanium aluminum (TiAl), titanium aluminum carbide nitride (TiAlC-N), titanium aluminum carbide (TiAlC), tantalum (Ta), tantalum carbide (TaC), tantalum nitride (TaN), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), tantalum aluminum nitride (TaAlN), tungsten (W), tungsten nitride This may include, but is not limited to, materials (WN), tungsten carbide (WC), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), nickel vanadium (Ni-V), nickel platinum (Ni-Pt), vanadium (V), zinc (Zn), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), ruthenium (Ru), platinum (Pt), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), or combinations thereof. The source electrode 170 may consist of a single layer or multiple layers. The drain electrode 180 may consist of a single layer or multiple layers.

[0064] For example, the thickness of the drain electrode 180 can be 100 nm or more, for example, 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, 5 μm or more, 6 μm or more, 7 μm or more, 8 μm or more, or 9 μm or more, and can be 10 μm or less, for example, 9 μm or less, 8 μm or less, 7 μm or less, 6 μm or less, 5 μm or less, 4 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less, and can be between 100 nm and 10 μm, or between 100 nm and 3 μm.

[0065] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 4 to 14. Figure 4 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and corresponds to Figure 2. The embodiment shown in Figure 4 corresponds to the same part as the embodiment shown in Figure 2, so its explanation will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previously described embodiments.

[0066] Referring to Figure 4, the second interlayer insulating layer 175 is placed on top of the first source electrode 171. The second interlayer insulating layer 175 covers the upper surface of the first source electrode 171. The second interlayer insulating layer 175 covers the top and side surfaces of the resistive layer 176. Furthermore, the second interlayer insulating layer 175 covers the side surface of the second source electrode 172. The level of the upper surface of the second interlayer insulating layer 175 along the third direction D3 is higher than the level of the upper surface of the resistive layer 176 along the third direction D3. As a result, the second interlayer insulating layer 175 covers the upper surface of the resistive layer 176, and the resistive layer 176 is located within the second interlayer insulating layer 175. The level of the upper surface of the second interlayer insulating layer 175 along the third direction D3 is substantially the same as the level of the upper surface of the second source electrode 172 along the third direction D3. In other words, the upper surface of the second interlayer insulating layer 175 and the upper surface of the second source electrode 172 are coplanar. As a result, the second source electrode 172 is located within the second interlayer insulating layer 175.

[0067] As an example, a semiconductor device is manufactured by forming a first conductivity type semiconductor layer 131 on the upper surface of a substrate 110, forming a second conductivity type doping wall region 133 within the first conductivity type semiconductor layer 131, forming a gate insulating layer 151 and a gate electrode 150 on the first conductivity type semiconductor layer 131, forming a source electrode 170 on the second conductivity type doping wall region 133, and forming a drain electrode 180 below the lower surface of the substrate 100. The source electrode 170 is formed by creating a resistive layer 176 on the first source electrode 171, creating a second interlayer insulating layer 175 that covers the first source electrode 171 and the resistive layer 176, etching the second interlayer insulating layer 175 to expose a portion of the resistive layer 176, and then forming the second source electrode 172 inside the etched second interlayer insulating layer 175. In this case, the second interlayer insulating layer 175 can also function as a passivation layer.

[0068] Figure 5 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and corresponds to Figure 2. The embodiment shown in Figure 5 corresponds to the same part as the embodiment shown in Figure 2, so its explanation will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previously described embodiments.

[0069] Referring to Figure 5, the source electrode 170 includes multiple layers of second source electrodes (172_1, 172_2, 172_3) and multiple layers of resistive layers (176_1, 176_2, 176_3). Multiple layers of second source electrodes (172_1, 172_2, 172_3) and multiple layers of resistive layers (176_1, 176_2, 176_3) are alternately stacked in the third direction D3. As an example, Figure 5 shows a source electrode 170 that includes three layers of second source electrodes (172_1, 172_2, 172_3) and three layers of resistive layers (176_1, 176_2, 176_3). In other words, the source electrode 170 includes a first resistive layer (176_1) placed on the first source electrode 171, a first second source electrode (172_1) placed on the first resistive layer (176_1), a second resistive layer (176_2) placed on the first second source electrode (172_1), a second second source electrode (172_2) placed on the second resistive layer (176_2), a third resistive layer (176_3) placed on the second second source electrode (172_2), and a third second source electrode (172_3) placed on the third resistive layer (176_3).

[0070] However, it is not limited to this, and the source electrode 170 may include two or more layers of the second source electrode 172, for example, three or more layers, four or more layers, five or more layers, six or more layers, seven or more layers, eight or more layers, nine or more layers, ten or more layers, twenty or more layers, thirty or more layers, forty or more layers, fifty or more layers, sixty or more layers, seventy or more layers, eighty or more layers, or ninety or more layers, and may include up to 100 layers, for example, 90 or fewer layers, eighty or fewer layers, seventy or fewer layers, sixy or fewer layers, foury or fewer layers, threey or fewer layers, or twoy or fewer layers, and may include two to 100 layers. However, if the number of layers in the second source electrode 172 becomes excessively large, cracks or stress may occur in the second interlayer insulating layer 175 during scribing.

[0071] Furthermore, the source electrode 170 may include two or more resistive layers 176, for example, 3 or more, 4 or more, 5 or more, 6 or more, 7 or more, 8 or more, 9 or more, 10 or more, 20 or more, 30 or more, 40 or more, 50 or more, 60 or more, 70 or more, 80 or more, or 90 or more layers, or 100 or fewer layers, for example, 90 or fewer, 80 or fewer, 70 or fewer, 60 or fewer, 50 or fewer, 40 or fewer, 30 or fewer, 20 or fewer, 10 or fewer, 9 or fewer, 8 or fewer, 7 or fewer, 6 or fewer, 5 or fewer, 4 or fewer, 3 or fewer, or 2 or fewer layers, or 2 or more layers to 100 or fewer layers. However, if the number of resistive layers 176 becomes excessively large, cracks or stress may occur in the second interlayer insulating layer 175 during scribing.

[0072] The electrical resistance of the multi-layered second source electrodes (172_1, 172_2, 172_3) increases as they are positioned higher in the third direction D3. For example, the second source electrode (172_2) may have an electrical resistance 10 times or more greater than the first source electrode (172_1), for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, 90 times or more, 100 times or more, 200 times or more, 300 times or more, 400 times or more, 500 times or more, 600 times or more, 700 times or more, 800 times or more, 900 times or more, 1000 times or more, 2000 times or more, 3000 times or more, 4000 times or more, 5000 times or more, 6000 times or more, 7000 times or more, 8000 times or more, 9000 It can be more than a factor of 10,000 or more, or less than 10,000, for example, less than or equal to 9,000, less than or equal to 8,000, less than or equal to 7,000, less than or equal to 6,000, less than or equal to 5,000, less than or equal to 4,000, less than or equal to 3,000, less than or equal to 2,000, less than or equal to 1,000, less than or equal to 90, less than or equal to 80, less than or equal to 70, less than or equal to 60, less than or equal to 50, less than or equal to 40, less than or equal to 30, or less than or equal to 20, and it can be between 10 and 10,000 times.

[0073] Furthermore, the third second source electrode (172_3) may have an electrical resistance 10 times or more greater than the second second source electrode (172_2), for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, 90 times or more, 100 times or more, 200 times or more, 300 times or more, 400 times or more, 500 times or more, 600 times or more, 700 times or more, 800 times or more, 900 times or more, 1000 times or more, 2000 times or more, 3000 times or more, 4000 times or more, 5000 times or more, 6000 times or more, 7000 times or more, 8000 times or more, 9000 times or more. It can be above, or 10,000 times or more, or 10,000 times or less, for example, 9,000 times or less, 8,000 times or less, 7,000 times or less, 6,000 times or less, 5,000 times or less, 4,000 times or less, 3,000 times or less, 2,000 times or less, 1,000 times or less, 900 times or less, 800 times or less, 700 times or less, 600 times or less, 500 times or less, 400 times or less, 300 times or less, 200 times or less, 100 times or less, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and it can be 10 times or more to 10,000 times or less.

[0074] The electrical resistance of the multiple resistive layers (176_1, 176_2, 176_3) increases as they are positioned higher in the third direction D3. For example, the second resistive layer (176_2) may have an electrical resistance 10 times or more greater than the first resistive layer (176_1), for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, 90 times or more, 100 times or more, 200 times or more, 300 times or more, 400 times or more, 500 times or more, 600 times or more, 700 times or more, 800 times or more, 900 times or more, 1000 times or more, 2000 times or more, 3000 times or more, 4000 times or more, 5000 times or more, 6000 times or more, 7000 times or more, 8000 times or more, 9000 times or more. Or it could be 10,000 times or more, or 10,000 times or less, for example, 9,000 times or less, 8,000 times or less, 7,000 times or less, 6,000 times or less, 5,000 times or less, 4,000 times or less, 3,000 times or less, 2,000 times or less, 1,000 times or less, 900 times or less, 800 times or less, 700 times or less, 600 times or less, 500 times or less, 400 times or less, 300 times or less, 200 times or less, 100 times or less, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and could be 10 times or more to 10,000 times or less.

[0075] Furthermore, the third resistive layer (176_3) may have an electrical resistance 10 times or more greater than the second resistive layer (176_2), for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, 90 times or more, 100 times or more, 200 times or more, 300 times or more, 400 times or more, 500 times or more, 600 times or more, 700 times or more, 800 times or more, 900 times or more, 1000 times or more, 2000 times or more, 3000 times or more, 4000 times or more, 5000 times or more, 6000 times or more, 7000 times or more, 8000 times or more, 9000 times or more, or It can be more than 10,000 times, or less than 10,000 times, for example, less than 9,000 times, less than 8,000 times, less than 7,000 times, less than 6,000 times, less than 5,000 times, less than 4,000 times, less than 3,000 times, less than 2,000 times, less than 1,000 times, less than 900 times, less than 800 times, less than 700 times, less than 600 times, less than 500 times, less than 400 times, less than 300 times, less than 200 times, less than 100 times, less than 90 times, less than 80 times, less than 70 times, less than 60 times, less than 50 times, less than 40 times, less than 30 times, or less than 20 times, and it can be between 10 times and 10,000 times.

[0076] For example, the first resistive layer (176_1) has a higher electrical resistance than the first source electrode 171, and the first second source electrode (172_1) has a higher electrical resistance than the first resistive layer (176_1). The second resistive layer (176_2) has a higher electrical resistance than the first second source electrode (172_1), and the second second source electrode (172_2) has a higher electrical resistance than the second resistive layer (176_2). The third resistive layer (176_3) has a higher electrical resistance than the second second source electrode (172_2), and the third second source electrode (172_3) has a higher electrical resistance than the third resistive layer (176_3).

[0077] For example, the first resistive layer (176_1) may have an electrical resistance 10 times or more greater than that of the first source electrode 171, for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, or 90 times or more, and may be 100 times or less, for example, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and may be 10 times or more to 100 times or less. Furthermore, each of the second source electrodes (172_1, 172_2, 172_3) may have an electrical resistance 10 times or more greater than each of the resistive layers (176_1, 176_2, 176_3) located directly below in the third direction D3. For example, it may be 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, or 90 times or more, and may be 100 times or less. For example, it may be 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and may be between 10 times and 100 times or less.

[0078] The source electrode 170 further includes multiple layers of second interlayer insulating layers (175_1, 175_2, 175_3) and multiple layers of third interlayer insulating layers (177_1, 177_2, 177_3). The multiple interlayer insulating layers (175_1, 175_2, 175_3) each cover the sides of the multiple resistive layers (176_1, 176_2, 176_3). Furthermore, the levels along the third direction D3 on the upper surfaces of the multiple interlayer insulating layers (175_1, 175_2, 175_3) are substantially the same as the levels along the third direction D3 on the upper surfaces of the multiple resistive layers (176_1, 176_2, 176_3). In other words, the upper surfaces of the multiple interlayer insulating layers (175_1, 175_2, 175_3) and the upper surfaces of the multiple resistive layers (176_1, 176_2, 176_3) are coplanar. As a result, the multiple resistive layers (176_1, 176_2, 176_3) are each placed within the multiple interlayer insulating layers (175_1, 175_2, 175_3). For example, the first resistive layer (176_1) is placed within the first interlayer insulating layer (175_1), the second resistive layer (176_2) is placed within the second interlayer insulating layer (175_2), and the third resistive layer (176_3) is placed within the third interlayer insulating layer (175_3).

[0079] The multiple third-layer insulating layers (177_1, 177_2, 177_3) each cover the sides of the multiple second-layer source electrodes (172_1, 172_2, 172_3). Furthermore, the levels along the third direction D3 on the upper surfaces of the multiple third interlayer insulating layers (177_1, 177_2, 177_3) are substantially the same as the levels along the third direction D3 on the upper surfaces of the multiple second source electrodes (172_1, 172_2, 172_3). In other words, the upper surfaces of the multiple third interlayer insulating layers (177_1, 177_2, 177_3) and the upper surfaces of the multiple second source electrodes (172_1, 172_2, 172_3) are coplanar. As a result, the multi-layer second source electrodes (172_1, 172_2, 172_3) are each placed within the multi-layer third interlayer insulating layers (177_1, 177_2, 177_3). For example, the first second source electrode (172_1) is placed within the first third interlayer insulating layer (177_1), the second second source electrode (172_2) is placed within the second third interlayer insulating layer (177_2), and the third second source electrode (172_3) is placed within the third third interlayer insulating layer (177_3).

[0080] The interlayer insulating layers (177_1, 177_2, 177_3) of the multiple third layers contain insulating material. For example, the third interlayer insulating layer (177_1, 177_2, 177_3) contains SiO2. However, the third interlayer insulating layer (177_1, 177_2, 177_3) may include SiOP, SiN, SiON, or a combination thereof. The third interlayer insulating layers (177_1, 177_2, 177_3) may each consist of a single layer or multiple layers.

[0081] As an example, a semiconductor device is manufactured by forming a first conductivity type semiconductor layer 131 on the upper surface of a substrate 110, forming a second conductivity type doping wall region 133 within the first conductivity type semiconductor layer 131, forming a gate insulating layer 151 and a gate electrode 150 on the first conductivity type semiconductor layer 131, forming a source electrode 170 on the second conductivity type doping wall region 133, and forming a drain electrode 180 below the lower surface of the substrate 100. The source electrode 170 is formed by creating a first source electrode 171 on top of the gate electrode 150, creating a first second interlayer insulating layer (175_1) covering the first source electrode 171, etching the first second interlayer insulating layer (175_1) to expose the first source electrode 171, then creating a first resistance layer (176_1) inside the etched first second interlayer insulating layer (175_1), creating a first third interlayer insulating layer (177_1) on top of the first second interlayer insulating layer (175_1) and the first resistance layer (176_1), etching the first third interlayer insulating layer (177_1) to expose the first resistance layer (176_1), and then creating a first second source electrode (172_1) inside the etched first third interlayer insulating layer (177_1). The process involves forming a second interlayer insulating layer (175_2) that covers the first second source electrode (172_1), etching the second interlayer insulating layer (175_2) to expose the first second source electrode (172_1), forming a second resistive layer (176_2) inside the etched second interlayer insulating layer (175_2), forming a second third interlayer insulating layer (177_2) on top of the second interlayer insulating layer (175_2) and the second resistive layer (176_2), etching the second third interlayer insulating layer (177_2) to expose the second resistive layer (176_2), and then forming the second second source electrode (172_2) inside the etched second third interlayer insulating layer (177_2).

[0082] Alternatively, the electrode may be formed by creating a third interlayer insulating layer (175_3) covering the second second source electrode (172_2), etching the third interlayer insulating layer (175_3) to expose the second second source electrode (172_2), then creating a third resistive layer (176_3) inside the etched third interlayer insulating layer (175_3), creating a third third interlayer insulating layer (177_3) on top of the third interlayer insulating layer (175_3) and the third resistive layer (176_3), etching the third third interlayer insulating layer (177_3) to expose the third resistive layer (176_3), and then creating a third second source electrode (172_3) inside the etched third third interlayer insulating layer (177_3). At this time, the electrical resistance of the multiple layers of the second source electrodes (172_1, 172_2, 172_3) increases as they are positioned higher in the third direction D3. Furthermore, the electrical resistance of the multiple resistive layers (176_1, 176_2, 176_3) increases as they are positioned higher in the third direction D3.

[0083] Figure 6 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and Figure 7 is a cross-sectional view taken along the line A-A' in Figure 6. Since the embodiments shown in Figures 6 and 7 correspond to the same parts as the embodiments shown in Figures 1 and 2, their explanation will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previously described embodiments.

[0084] Referring to Figures 6 and 7, the source electrode 170 includes a first source electrode 171, a second source electrode 172, and a third source electrode 173. The second source electrode 172 is positioned on the first source electrode 171, and the third source electrode 173 is positioned on the second source electrode 172. The second source electrode 172 is positioned between the first source electrode 171 and the third source electrode 173. In other words, the first source electrode 171, the second source electrode 172, and the third source electrode 173 are sequentially stacked in the third direction D3. The first source electrode 171 is electrically connected to the third source electrode 173 through the second source electrode 172. In other words, the first source electrode 171 and the third source electrode 173 do not come into direct contact with each other, but are separated from each other in the third direction D3 with the second source electrode 172 in between.

[0085] The second source electrode 172 lies on a plane (hereinafter referred to as "on the plane") that extends perpendicularly in the third direction D3 and in the first direction D1 and the second direction D2. For example, in Figure 6, the area of ​​the second source electrode 172 along the first direction D1 and the second direction D2 is smaller than that of the first source electrode 171. In other words, the first source electrode 171 partially overlaps with the second source electrode 172 in the third direction D3, while the second source electrode 172 completely overlaps with the first source electrode 171 in the third direction D3.

[0086] The second source electrode 172 has a higher electrical resistance than the first source electrode 171. Furthermore, the second source electrode 172 has a lower electrical resistance than the third source electrode 173. For example, the second source electrode 172 may have an electrical resistance 10 times or more greater than that of the first source electrode 171, for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, or 90 times or more, and may be 100 times or less, for example, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and may be between 10 times and 100 times or less.

[0087] As an example, the electrical resistance of the second source electrode 172 is 10.0 × 10 at 0°C. -8 It can exceed Ω·m, for example, 20.0 × 10 -8 Ω m or more, 30.0×10 -8 Ω m or more, 40.0×10 -8 Ω m or more, 50.0×10 -8 Ω m or more, 60.0×10 -8 Ω m or more, 70.0×10 -8 Ω m or more, 80.0×10 -8 Ω·m or greater, or 90.0 × 10⁻⁶ -8 It can be greater than Ω·m, and 100.0 × 10 -8 It can be less than Ω·m, for example, 90.0 × 10 -8 Ω m or less, 80.0×10 -8 Ω m or less, 70.0×10 -8 Ω m or less, 60.0×10 -8 Ω m or less, 50.0×10 -8 Ω m or less, 40.0×10 -8 Ω m or less, 30.0×10 -8 Ω m or less, or 20.0×10 -8 It can be less than or equal to Ω·m, and 10.0 × 10 -8Exceeding Ω m~100.0×10 -8 It may be less than Ω·m.

[0088] For example, the second source electrode 172 may contain, without limitation, a conductive material with a higher electrical resistance than the first source electrode 171. For example, the second source electrode 172 may contain palladium (Pd), tin (Sn), tantalum (Ta), chromium (Cr), strontium (St), antimony (Sb), zirconium (Zr), rubidium (Rb), manganese (Mn), polysilicon, tantalum carbide nitride (TaCN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), tantalum aluminum nitride (TaAlN), or a combination thereof, and may consist of a single layer or multiple layers.

[0089] For example, if the second source electrode 172 contains polysilicon, the electrical resistance of polysilicon is 10.0 × 10⁻⁶ at 0°C, depending on the type and concentration of the doping element. -8 Exceeding Ω m~100.0×10 -8 Adjust to less than Ω·m. For example, the thickness of the second source electrode 172 can be 10 nm or more, and for example, 20 nm or more, 30 nm or more, 40 nm or more, 50 nm or more, 60 nm or more, 70 nm or more, 80 nm or more, 90 nm or more, 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, 500 nm or more, 600 nm or more, 700 nm or more, 800 nm or more, 900 nm or more, 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, 5 μm or more, 6 μm or more, 7 μm or more, 8 μm or more, or 9 μm or more. It can be 10 μm or less, for example, 9 μm or less, 8 μm or less, 7 μm or less, 6 μm or less, 5 μm or less, 4 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 900 nm or less, 800 nm or less, 700 nm or less, 600 nm or less, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 80 nm or less, 70 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and can be 10 nm or more to 10 μm or less. Here, the thickness of the second source electrode 172 is the shortest distance along the third direction D3 from the lower surface to the upper surface of the second source electrode 172 on a cross-section cut perpendicular to the second direction D2, the first direction D1, and the third direction D3 (for example, Figure 7).

[0090] The third source electrode 173 is positioned on top of the second source electrode 172. For example, the third source electrode 173 is positioned in the center of the upper surface of the first source electrode 171. The third source electrode 173 is electrically connected to the first source electrode 171 through the second source electrode 172, and applies an externally supplied source voltage to the second source electrode 172 and the first source electrode 171 through the third source electrode 173. The third source electrode 173 has a smaller area along the first direction D1 and the second direction D2 than the first source electrode 171 on a plane (for example, Figure 6). In other words, the first source electrode 171 partially overlaps with the third source electrode 173 in the third direction D3, while the third source electrode 173 completely overlaps with the first source electrode 171 in the third direction D3. In this case, the area of ​​the second source electrode 172 along the first direction D1 and the second direction D2 on a plane (for example, Figure 6) may be smaller or larger than that of the third source electrode 173, or it may be substantially the same. Furthermore, the second source electrode 172 and the third source electrode 173 may only partially overlap each other in the third direction D3.

[0091] The third source electrode 173 has a higher electrical resistance than the second source electrode 172. For example, the third source electrode 173 may have an electrical resistance 10 times or more greater than that of the second source electrode 172, for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, or 90 times or more, and may be 100 times or less, for example, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and may be between 10 times and 100 times or less. As an example, the electrical resistance of the third source electrode 173 is 100.0 × 10⁻⁶ at 0°C. -8 It can be greater than or equal to Ω·m, for example, 200.0 × 10⁻⁶ -8 Ω m or more, 300.0×10 -8 Ω m or more, 400.0×10 -8 Ω m or more, 500.0×10 -8 Ω m or more, 600.0×10 -8 Ω m or more, 700.0×10 -8 Ω m or more, 800.0×10 -8 Ω·m or greater, or 900.0 × 10⁻⁶ -8 It can be greater than Ω·m, and 1000.0 × 10 -8 It can be less than or equal to Ω·m, for example, 900.0 × 10⁻⁶ -8 Ω m or less, 800.0×10 -8 Ω m or less, 700.0×10 -8 Ω m or less, 600.0×10 -8 Ω m or less, 500.0×10 -8 Ω m or less, 400.0×10 -8 Ω m or less, 300.0×10 -8 Ω m or less, or 200.0×10 -8 It can be less than or equal to Ω·m, and 100.0 × 10 -8Ω m or more ~1000.0×10 -8 It may be less than or equal to Ω·m.

[0092] For example, the third source electrode 173 may include any material with a higher electrical resistance than the second source electrode 172, without any limitations. For example, the third source electrode 173 may contain palladium (Pd), tin (Sn), tantalum (Ta), chromium (Cr), strontium (St), antimony (Sb), zirconium (Zr), rubidium (Rb), manganese (Mn), polysilicon, tantalum carbide nitride (TaCN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), tantalum aluminum nitride (TaAlN), or a combination thereof, and may consist of a single layer or multiple layers.

[0093] For example, the thickness of the third source electrode 173 can be 10 nm or more, and for example, 20 nm or more, 30 nm or more, 40 nm or more, 50 nm or more, 60 nm or more, 70 nm or more, 80 nm or more, 90 nm or more, 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, 500 nm or more, 600 nm or more, 700 nm or more, 800 nm or more, 900 nm or more, 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, 5 μm or more, 6 μm or more, 7 μm or more, 8 μm or more, or 9 μm or more. It can be 10 μm or less, for example, 9 μm or less, 8 μm or less, 7 μm or less, 6 μm or less, 5 μm or less, 4 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 900 nm or less, 800 nm or less, 700 nm or less, 600 nm or less, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 80 nm or less, 70 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and can be 10 nm or more to 10 μm or less. Here, the thickness of the third source electrode 173 is the shortest distance along the third direction D3 from the lower surface to the upper surface of the third source electrode 173 on a cross-section cut perpendicular to the second direction D2, the first direction D1, and the third direction D3 (for example, Figure 7).

[0094] The second interlayer insulating layer 175 is placed on top of the first source electrode 171. The second interlayer insulating layer 175 covers the upper surface of the first source electrode 171. Furthermore, the second interlayer insulating layer 175 covers the side surface of the second source electrode 172. As an example, the second interlayer insulating layer 175 is placed between the first source electrode 171 and the third source electrode 173. The second interlayer insulating layer 175 separates the first source electrode 171 and the third source electrode 173 from each other, while the first source electrode 171 and the third source electrode 173 are electrically connected to each other through the second source electrode 172. The level of the upper surface of the second interlayer insulating layer 175 along the third direction D3 is substantially the same as the level of the upper surface of the second source electrode 172 along the third direction D3. In other words, the upper surface of the second interlayer insulating layer 175 and the upper surface of the second source electrode 172 are coplanar. As a result, the second source electrode 172 is located within the second interlayer insulating layer 175, and the third source electrode 173 is located above the second interlayer insulating layer 175.

[0095] In an embodiment of the present invention, the semiconductor device includes a second source electrode 172 and a third source electrode 173 in the third direction D3, in an active source contact region where the source electrode 170 is in contact with the second conductivity type doping wall region 133, with the electrical resistance increasing as it moves upward. According to this, as shown in the circuit diagram in Figure 3, the gate pad 155 on the gate G side is in direct contact with metal, but the current flowing into the source S side is supplied through the second source electrode 172 and the third source electrode 173, which have high electrical resistance. In this way, increasing the local resistance in the current path on the source S side allows more current to flow due to the ballast resistance principle, and the potential difference between the gate G and source S decreases due to the voltage drop. When the potential difference between the gate G and source S decreases, a channel closing effect occurs, limiting the current and preventing a short circuit. Therefore, without adding further resistors outside the circuit (e.g., package or module) and without structural changes in the active source contact region such as changing the channel length, Rds on Without changing Id sat This reduces the amount of stress and prevents short circuits.

[0096] Furthermore, the second and third source electrodes 172 and 173, located above the first source electrode 171, have relatively high electrical resistance, while the first source electrode 171, located below the source electrode 170 and making active source contact, has relatively low electrical resistance. Since the area of ​​the first source electrode 171 is relatively larger than the area of ​​the second and third source electrodes 172 and 173, the current concentration of the active source contact is reduced, improving voltage overshooting or non-uniformity of source current at each cell region, thereby improving current spreading.

[0097] As an example, a semiconductor device is manufactured by forming a first conductivity type semiconductor layer 131 on the upper surface of a substrate 110, forming a second conductivity type doping wall region 133 within the first conductivity type semiconductor layer 131, forming a gate insulating layer 151 and a gate electrode 150 on the first conductivity type semiconductor layer 131, forming a source electrode 170 on the second conductivity type doping wall region 133, and forming a drain electrode 180 below the lower surface of the substrate 100. The source electrode 170 is formed by forming a first source electrode 171 on the gate electrode 150, a second source electrode 172 on the first source electrode 171, and a third source electrode 173 on the second source electrode 172. The second source electrode 171 has a higher electrical resistance than the first source electrode 171, and the third source electrode 173 has a higher electrical resistance than the second source electrode 172. As an example, the source electrode 170 may be formed by forming a first source electrode 171 on the gate electrode 150, forming a second interlayer insulating layer 175 covering the first source electrode 171, etching the second interlayer insulating layer 175 to expose the first source electrode 171, forming a second source electrode 172 inside the etched second interlayer insulating layer 175, and forming a third source electrode 173 on the second interlayer insulating layer 175 and the second source electrode 172.

[0098] Figure 8 is a plan view showing a semiconductor device according to an embodiment of the present invention, and Figure 9 is a cross-sectional view taken along the line A-A' in Figure 8. Since the embodiments shown in Figures 8 and 9 correspond to the same parts as the embodiments shown in Figures 1 and 2, their explanation will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previously described embodiments.

[0099] Referring to Figures 8 and 9, the second source electrode 172 may have a larger or substantially the same area along the first direction D1 and the second direction D2 than the first source electrode 171 in Figure 8, on a plane that extends perpendicularly in the third direction D3 to the first direction D1 and the second direction D2 (hereinafter referred to as "on the plane"). In other words, the second source electrode 172 may partially or completely overlap with the first source electrode 171 in the third direction D3. Furthermore, the second source electrode 172 covers the cell region CELL. The second source electrode 172 has a larger area along the first direction D1 and the second direction D2 than the cell region CELL on a plane (for example, Figure 8).

[0100] In other words, the second source electrode 172 partially overlaps with the cell region CELL in the third direction D3, while the cell region CELL completely overlaps with the second source electrode 172 in the third direction D3. In this configuration, the resistive layer 176 is positioned between the first source electrode 171 and the second source electrode 172, with multiple resistive layers 176 interposed between the first source electrode 171 and the second source electrode 172. In other words, multiple resistive layers 176 are arranged within a single second interlayer insulating layer 175, spaced apart in the first direction D1 or the second direction D2. Thus, if the areas of the second source electrode 172 and the first source electrode 171 along the first direction D1 and the second direction D2 are similar, and the resistive layer 176 is located only at the connecting component between the second source electrode 172 and the first source electrode 171, the current spreading from the second source electrode 172 can be improved.

[0101] Figure 10 is a plan view showing a semiconductor device according to an embodiment of the present invention, and Figure 11 is a cross-sectional view taken along the line A-A' in Figure 10. Since the embodiments shown in Figures 10 and 11 correspond to the same parts as the embodiments shown in Figures 8 and 9, their explanation will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previously described embodiments. Figures 8 and 9 show that, as in Figures 1 and 2, the second source electrode 172 has a higher electrical resistance than the resistive layer 176. Figures 10 and 11 show the case where the second source electrode 172 has a greater or substantially equal electrical resistance to the resistive layer 176.

[0102] Referring to Figures 10 and 11, the resistive layer 176 and the second source electrode 172 have higher electrical resistance than the first source electrode 171. As an example, the resistive layer 176 and the second source electrode 172 may have an electrical resistance 10 times or more greater than that of the first source electrode 171, for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, or 90 times or more, and may be 100 times or less, for example, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and may be between 10 times and 100 times or less. The second source electrode 172 may have substantially the same electrical resistance as the resistive layer 176, or its electrical resistance may be 10 times or more greater than that of the resistive layer 176, for example, 20 times or more, 30 times or more, 40 times or more, 50 times or more, 60 times or more, 70 times or more, 80 times or more, or 90 times or more, and 100 times or less, for example, 90 times or less, 80 times or less, 70 times or less, 60 times or less, 50 times or less, 40 times or less, 30 times or less, or 20 times or less, and may be 10 times or more to 100 times or less.

[0103] The electrical resistance of the second source electrode 172 and the resistive layer 176 is 10.0 × 10⁻⁶ at 0°C. -8 It can exceed Ω·m, for example, 20.0 × 10 -8 Ω m or more, 30.0×10 -8 Ω m or more, 40.0×10 -8 Ω m or more, 50.0×10 -8 Ω m or more, 60.0×10 -8 Ω m or more, 70.0×10 -8 Ω m or more, 80.0×10 -8 Ω·m or greater, or 90.0 × 10⁻⁶ -8 It can be greater than Ω·m, and 100.0 × 10 -8 It can be less than or equal to Ω·m, for example, 90.0 × 10 -8 Ω m or less, 80.0×10 -8 Ω m or less, 70.0×10 -8 Ω m or less, 60.0×10 -8 Ω m or less, 50.0×10 -8 Ω m or less, 40.0×10 -8 Ω m or less, 30.0×10 -8 Ω m or less, or 20.0×10 -8 It can be less than or equal to Ω·m, and 10.0 × 10 -8 Exceeding Ω m~100.0×10 -8 It may be less than or equal to Ω·m.

[0104] For example, the second source electrode 172 may include any material with a higher electrical resistance than the first source electrode 171, without any limitations. For example, the second source electrode 172 may contain palladium (Pd), tin (Sn), tantalum (Ta), chromium (Cr), strontium (St), antimony (Sb), zirconium (Zr), rubidium (Rb), manganese (Mn), polysilicon, tantalum carbide nitride (TaCN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), tantalum aluminum nitride (TaAlN), or a combination thereof, and may consist of a single layer or multiple layers. As an example, a resistive layer 176 is formed on the first source electrode 171, a second interlayer insulating layer 175 is formed covering the first source electrode 171, the second interlayer insulating layer 175 is etched to expose a portion of the first source electrode 171, then the resistive layer 176 is formed inside the etched second interlayer insulating layer 175, and the second source electrode 172 is simultaneously formed on the upper surface of the second interlayer insulating layer 175. This allows for a reduction in the number of masks used in the process, thereby shortening the process time.

[0105] Figure 12 is a plan view showing a semiconductor device according to an embodiment of the present invention, and Figure 13 is a cross-sectional view taken along the line A-A' in Figure 12. Since the embodiments shown in Figures 12 and 13 correspond to the same parts as the embodiments shown in Figures 1 and 2, their explanation will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previously described embodiments.

[0106] Referring to Figures 12 and 13, the second source electrode 172 is positioned on top of the first source electrode 171. However, unlike those shown in Figures 1 and 2, the resistive layer 176 is not located between the first source electrode 171 and the second source electrode 172. In other words, the first source electrode 171 and the second source electrode 172 are sequentially stacked in the third direction D3. For example, the lower surface of the second source electrode 172 is in direct contact with the upper surface of the first source electrode 171. However, it is not limited to this, and in some embodiments, the barrier layer 178 is placed between the first source electrode 171 and the second source electrode 172. In other words, the first source electrode 171, the barrier layer 178, and the second source electrode 172 are sequentially stacked in the third direction D3.

[0107] The barrier layer 178 can prevent the metallic materials of the first source electrode 171 and the second source electrode 172 from mixing when the second interlayer insulating layer 175 and the resistive layer 176 are not located between the first source electrode 171 and the second source electrode 172. As an example, the barrier layer 178 may contain titanium (Ti), titanium nitride (TiN), titanium tungsten (Ti-W), platinum (Pt), chromium (Cr), or a combination thereof, for example, titanium (Ti), titanium nitride (TiN), or titanium tungsten (Ti-W). The barrier layer 178 may consist of a single layer or multiple layers.

[0108] For example, the thickness of the barrier layer 178 may be 100 nm or more, for example, 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, 5 μm or more, 6 μm or more, 7 μm or more, 8 μm or more, or 9 μm or more, and may be 10 μm or less, for example, 9 μm or less, 8 μm or less, 7 μm or less, 6 μm or less, 5 μm or less, 4 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less, and may be between 100 nm and 10 μm, or between 100 nm and 3 μm.

[0109] As an example, a semiconductor device is manufactured by forming a first conductivity type semiconductor layer 131 on the upper surface of a substrate 110, forming a second conductivity type doping wall region 133 within the first conductivity type semiconductor layer 131, forming a gate insulating layer 151 and a gate electrode 150 on the first conductivity type semiconductor layer 131, forming a source electrode 170 on the second conductivity type doping wall region 133, and forming a drain electrode 180 below the lower surface of the substrate 100. The source electrode 170 may be formed by forming a first source electrode 171 on the gate electrode 150, forming a barrier layer 178 over the first source electrode 171, and forming a second source electrode 172 on the barrier layer 178.

[0110] Figure 14 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and corresponds to Figure 13. The embodiment shown in Figure 14 corresponds to the same part as the embodiment shown in Figure 13, so its explanation will be omitted, and the differences will be explained in detail. Furthermore, the same reference numerals are used for components identical to those in the previously described embodiments.

[0111] Referring to Figure 14, the second source electrode 172 is positioned within the first source electrode 171. In other words, the first source electrode 171 covers the side surface of the second source electrode 172. The level of the upper surface of the second source electrode 172 along the third direction D3 is substantially the same as the level of the upper surface of the first source electrode 171 along the third direction D3. As a result, the second source electrode 172 is positioned within the first source electrode 171. As an example, the lower surface and sides of the second source electrode 172 are covered by the first source electrode 171, and the lower surface and sides of the second source electrode 172 are in direct contact with the first source electrode 171.

[0112] However, it is not limited to this, and in some embodiments, the barrier layer 178 is placed between the first source electrode 171 and the second source electrode 172. In this case, the barrier layer 178 is positioned between the lower surface of the second source electrode 172 and the first source electrode 171, and also between the side surface of the second source electrode 172 and the first source electrode 171. As an example, the source electrode 170 is formed by forming a first source electrode 171 over the gate electrode 150, etching the first source electrode 171, forming a barrier layer 178 inside the etched first source electrode 171, and forming a second source electrode 172 inside the first source electrode 171.

[0113] Note that the present invention is not limited to the above-described embodiments. Various modifications can be made without departing from the technical scope of the present invention.

Description of Reference Numerals

[0114] 110 Substrate 131 First-conductivity-type semiconductor layer 133 Second-conductivity-type doping wall region 135 Second-conductivity-type doping layer 137 First-conductivity-type doping layer 140 First interlayer insulating layer 150 Gate electrode 151 Gate insulating layer 155 Gate pad 156 Gate wiring 170 Source electrode 171 First source electrode 172 Second source electrode 173 Third source electrode 175 Second interlayer insulating layer 176 Resistance layer 177 Third interlayer insulating layer 178 Barrier layer 180 Drain electrode 190 Silicide layer

Claims

1. A semiconductor device, A substrate including a cell region and a peripheral region located outside the cell region, A first conductive semiconductor layer is disposed on the upper surface of the substrate, A second conductivity type doping wall region is disposed within the first conductivity type semiconductor layer, A gate electrode disposed on the first conductive semiconductor layer, A gate insulating layer disposed between the first conductivity type semiconductor layer and the gate electrode, A source electrode positioned on the second conductivity-type doping wall region, It has a drain electrode positioned below the lower surface of the substrate, The source electrode is A first source electrode is disposed on the gate electrode, A second source electrode is placed on the first source electrode, A semiconductor device comprising: a resistive layer disposed between the first source electrode and the second source electrode, the resistive layer containing a conductive material having a greater electrical resistance than the first source electrode.

2. The resistive layer has an electrical resistance that is 10 times greater than that of the first source electrode. The semiconductor device according to claim 1, characterized in that the second source electrode has an electrical resistance 10 times greater than that of the resistive layer.

3. The electrical resistance of the first source electrode is 1.0 × 10⁻¹⁰ at 0°C. －８ Ω・m or more ~ ​​10.0×10 －８ It is less than or equal to Ω・m, The electrical resistance of the aforementioned resistive layer is 10.0 × 10 at 0°C. －８ Exceeding Ω・m~100.0×10 －８ It is less than Ω·m, The electrical resistance of the second source electrode is 100.0 × 10⁻⁶ at 0°C. －８ Ω・m or more ~ ​​1000.0×10 －８ The semiconductor device according to claim 1, characterized in that it is Ω·m or less.

4. The first source electrode has a larger area along the first and second directions that intersect each other parallel to the upper surface of the substrate than the cell region. The second source electrode has a smaller area along the first and second directions than the first source electrode. The resistive layer has a smaller area along the first and second directions than the first source electrode. The second source electrode is completely superimposed on the first source electrode in a third direction perpendicular to the upper surface of the substrate. The resistive layer is superimposed entirely on the first source electrode in the third direction. The first source electrode is superimposed only partially on the second source electrode and the resistive layer in the third direction. The semiconductor device according to claim 1, characterized in that only a portion of the second source electrode and the resistive layer overlap each other in the third direction.

5. The semiconductor device further comprises a second interlayer insulating layer disposed on the first source electrode, The second interlayer insulating layer covers the upper surface of the first source electrode and the side surface of the resistive layer. The level of the upper surface of the second interlayer insulating layer along the third direction is the same as the level of the upper surface of the resistive layer along the third direction. Here, the third direction is the direction perpendicular to the upper surface of the substrate, The resistive layer is located within the second interlayer insulating layer. The semiconductor device according to claim 1, characterized in that the second source electrode is located on the second interlayer insulating layer.

6. The semiconductor device further comprises a second interlayer insulating layer disposed on the first source electrode, The second interlayer insulating layer covers the upper surface of the first source electrode, the upper surface and side surface of the resistive layer, and the side surface of the second source electrode. The level of the upper surface of the second interlayer insulating layer along the third direction is the same as the level of the upper surface of the second source electrode along the third direction. Here, the third direction is the direction perpendicular to the upper surface of the substrate, The semiconductor device according to claim 1, characterized in that the resistive layer and the second source electrode are located within the interlayer insulating layer.

7. The source electrode includes a plurality of second source electrodes and a plurality of resistive layers. The second source electrode and the resistive layer are stacked alternately in the third direction. Here, the third direction is the direction perpendicular to the upper surface of the substrate, The electrical resistance of the second source electrode increases as it is positioned higher in the third direction. The semiconductor device according to claim 1, characterized in that the electrical resistance of the resistive layer increases as it is positioned higher in the third direction.

8. The semiconductor device according to claim 7, characterized in that the source electrode includes two to 100 layers of the second source electrode and two to 100 layers of the resistive layer.

9. A substrate including a cell region and a peripheral region located outside the cell region, A first conductive semiconductor layer is disposed on the upper surface of the substrate, A second conductivity type doping wall region is disposed within the first conductivity type semiconductor layer, A gate electrode disposed on the first conductive semiconductor layer, A gate insulating layer disposed between the first conductivity type semiconductor layer and the gate electrode, A source electrode positioned on the second conductivity-type doping wall region, It has a drain electrode positioned below the lower surface of the substrate, The source electrode is A first source electrode is disposed on the gate electrode, A second source electrode is placed on the first source electrode, The system includes a third source electrode positioned on the second source electrode, The second source electrode has a higher electrical resistance than the first source electrode. A semiconductor device characterized in that the third source electrode has a higher electrical resistance than the second source electrode.

10. The second source electrode has an electrical resistance that is more than 10 times greater than that of the first source electrode. The semiconductor device according to claim 9, characterized in that the third source electrode has an electrical resistance 10 times greater than that of the second source electrode.

11. The electrical resistance of the first source electrode is 1.0 × 10⁻¹⁰ at 0°C. －８ Ω・m or more ~ ​​10.0×10 －８ It is less than or equal to Ω・m, The electrical resistance of the second source electrode is greater than 10.0×10 －８ Ω·m and less than 100.0×10 －８ Ω·m at 0°C, and The electrical resistance of the third source electrode is 100.0 × 10⁻⁶ at 0°C. －８ Ω・m or more ~ ​​1000.0×10 －８ The semiconductor device according to claim 10, characterized in that it is Ω·m or less.

12. The first source electrode has a larger area along the first and second directions that intersect each other parallel to the upper surface of the substrate than the cell region. The second source electrode has a smaller area along the first and second directions than the first source electrode. The third source electrode has a smaller area along the first and second directions than the first source electrode. The second source electrode is completely superimposed on the first source electrode in a third direction perpendicular to the upper surface of the substrate. The third source electrode is superimposed on the first source electrode in the third direction. The first source electrode overlaps only a portion of the second source electrode and the third source electrode in the third direction. The semiconductor device according to claim 9, characterized in that the second source electrode and the third source electrode overlap each other only in the third direction.

13. A substrate including a cell region and a peripheral region located outside the cell region, A first conductive semiconductor layer is disposed on the upper surface of the substrate, A second conductivity type doping wall region is disposed within the first conductivity type semiconductor layer, A gate electrode disposed on the first conductive semiconductor layer, A gate insulating layer disposed between the first conductivity type semiconductor layer and the gate electrode, A source electrode positioned on the second conductivity-type doping wall region, It has a drain electrode positioned below the lower surface of the substrate, The source electrode is A first source electrode is disposed on the gate electrode, A semiconductor device comprising a second source electrode disposed on the first source electrode and having a greater electrical resistance than the first source electrode.

14. The source electrode is disposed between the first source electrode and the second source electrode and further includes a resistive layer containing a conductive material with greater electrical resistance than the first source electrode. The semiconductor device according to claim 13, characterized in that the second source electrode has an electrical resistance greater than or equal to that of the resistive layer.

15. The semiconductor device according to claim 14, characterized in that the resistive layer and the second source electrode have an electrical resistance 10 times greater or more than that of the first source electrode.

16. The electrical resistance of the first source electrode is 1.0 × 10⁻¹⁰ at 0°C. －８ Ω・m or more ~ ​​10.0×10 －８ It is less than or equal to Ω・m, The electrical resistance of the resistive layer and the second source electrode is 10.0 × 10 at 0°C. －８ Exceeding Ω・m~100.0×10 －８ The semiconductor device according to claim 15, characterized in that it is Ω·m or less.

17. The first source electrode has a larger area along the first and second directions that intersect each other parallel to the upper surface of the substrate than the cell region. The second source electrode has a larger area along the first and second directions that intersect each other parallel to the upper surface of the substrate than the first source electrode or the cell region. The resistive layer has a smaller area along the first and second directions than the first and second source electrodes. The resistive layer is completely superimposed on the second source electrode in the third direction. Here, the third direction is the direction perpendicular to the upper surface of the substrate, The semiconductor device according to claim 14, characterized in that the second source electrode is superimposed only partially on the resistive layer in the third direction.

18. The semiconductor device according to claim 13, characterized in that the source electrode further includes a barrier layer disposed between the first source electrode and the second source electrode.

19. The semiconductor device according to claim 18, characterized in that the barrier layer includes titanium (Ti), titanium nitride (TiN), titanium tungsten (Ti-W), platinum (Pt), chromium (Cr), or a combination thereof.

20. The first source electrode covers the side surface of the second source electrode, The level of the upper surface of the first source electrode along the third direction is the same as the level of the upper surface of the second source electrode along the third direction. Here, the third direction is the direction perpendicular to the upper surface of the substrate, The semiconductor device according to claim 13, characterized in that the second source electrode is located within the first source electrode.

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