Split-gate light emitting display with piezoresistive sensing function and manufacturing method thereof

Abstract

The present application relates to the technical field of display manufacturing, and particularly relates to a split gate type light emitting display with a piezoresistive sensing function and a manufacturing method thereof. The split gate type light emitting display with the piezoresistive sensing function comprises: a plurality of pixels, each pixel comprising a red light emitting sub-pixel R, a green light emitting sub-pixel G, a blue light emitting sub-pixel B and a pressure sensing sub-pixel S; a driving back plate, the driving back plate being provided with a plurality of regularly arranged through holes, the driving back plate carrying the plurality of pixels and driving the red light emitting sub-pixel R, the green light emitting sub-pixel G and the blue light emitting sub-pixel to emit light and driving the pressure sensing sub-pixel S to receive pressure information. The split gate type module prepared by using a semiconductor process can not only realize display functions of high resolution, high brightness, high contrast and low response time, but also can receive external pressure information in real time, thereby providing a feasible solution for single-chip integration of touch interaction display.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display manufacturing technology, and particularly relates to a split gate type light emitting display with piezoresistive sensing function and a manufacturing method thereof. BACKGROUND

[0002] With the pursuit of visual experience by consumers, high-definition display products are increasingly popular, which promotes the development of display technology in the direction of higher resolution, higher brightness, higher contrast and lower response time. However, if the display of the prior art wants to receive real-time external pressure information, a pressure sensing device needs to be additionally installed, and the pixel arrangement of the existing display needs to be optimized.

[0003] If the piezoresistive sensor is formed in the manufacturing process of the semiconductor display, a feasible solution is provided for single-chip integration of interactive display. SUMMARY

[0004] The present application solves the technical problem of providing a split gate type light emitting display with piezoresistive sensing function to solve the problems of the prior art in the background.

[0005] The technical solution adopted by the present application to solve the technical problem is: a split gate type light emitting display with piezoresistive sensing function, comprising:

[0006] a plurality of pixels, each pixel comprising a red light emitting sub-pixel R, a green light emitting sub-pixel G, a blue light emitting sub-pixel B and a pressure sensing sub-pixel S;

[0007] a driving backplane, the driving backplane is provided with a plurality of regularly arranged through holes, the red light emitting sub-pixel R, the green light emitting sub-pixel G, the blue light emitting sub-pixel B or the pressure sensing sub-pixel S covers at least one through hole, the driving backplane carries a plurality of pixels and drives the red light emitting sub-pixel R, the green light emitting sub-pixel G and the blue light emitting sub-pixel to emit light respectively and drives the pressure sensing sub-pixel S to receive pressure information;

[0008] The red light emitting sub-pixel R, the green light emitting sub-pixel G, the blue light emitting sub-pixel B and the pressure sensing sub-pixel S all comprise an anode, a semiconductor device, an ITO thin film layer and an Al layer, the anode is arranged on the driving backplane and covers at least one through hole, the semiconductor device is located on the side of the anode away from the driving backplane, the ITO thin film layer is located on the side of the semiconductor device away from the driving backplane, and the Al layer is arranged on the ITO thin film layer.

[0009] Further, the semiconductor device comprises an N-type high-doped region, an N-type epitaxial layer, a gate, a P-region, an N+ region, a P+ region and a metal layer, the N-type high-doped region is located on the side of the anode away from the driving backplane, the N-type high-doped region is formed with the N-type epitaxial layer, the gate is arranged in the N-type epitaxial layer and is divided into two sections, the P-region is arranged on the upper surface of the N-type epitaxial layer avoiding the gate, the N+ region is arranged on the upper surface of the P+ region, the N+ region is provided with an oxide layer, the oxide layer is provided with a through hole, the P+ region is arranged in the P-region below the through hole, the oxide layer is provided with a metal layer, and the metal layer has a metal joint extending into the through hole and connected with the P+ region.

[0010] Further, the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B each comprise a P-pad layer, a P-GaN layer, an MQW layer, an n-GaN layer and an N-pad layer arranged in sequence on the Al layer.

[0011] Further, the Al layer in the pressure sensing sub-pixel S is provided with a Si layer with a hollow structure, the Si layer is provided with a SiO2 layer, the SiO2 layer is provided with P-type silicon, the P-type silicon is connected with a P-type single-crystal silicon sensing film with a piezoresistive electrode, a through hole is provided from the upper surface of the P-type silicon to the lower bottom surface of the Si layer, and the through hole is provided with tungsten connected with the P-type single-crystal silicon sensing film and the Al layer.

[0012] Further, it further comprises an interlayer dielectric layer and a common cathode, the interlayer dielectric layer is produced to be filled between the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure sensing sub-pixel S, the interlayer dielectric layer corresponding to the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B is provided with an electrode groove, the common cathode is arranged on the side of the interlayer dielectric layer away from the driving backplane and covers the electrode groove, and the common cathode is in contact with the upper surfaces of the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B through the electrode groove, and in the pressure sensing sub-pixel S, the common cathode is connected with the piezoresistive electrode of the P-type single-crystal silicon sensing film.

[0013] Further, it further comprises a thin film packaging layer, the thin film packaging layer is located on the side of the common cathode away from the driving backplane and covers the common cathode.

[0014] Further, a manufacturing method of the split-gate type light-emitting display with pressure resistance sensing function is provided, comprising the following steps:

[0015] S1, forming a plurality of regularly arranged through holes on the driving backplane, filling the through holes with conductive material, and then forming a plurality of anodes on the upper surface of the driving backplane, and each anode covers at least one through hole;

[0016] S2, growing N-type high-doped region, N-type epitaxial layer and oxide layer on the driving backboard and anode in turn to form a semiconductor layer;

[0017] S3, patterning the semiconductor layer, filling the removed part by interlayer dielectric layer, and polishing the interlayer dielectric layer by chemical mechanical polishing process to make the upper surface of the interlayer dielectric layer flush with the upper surface of the oxide layer;

[0018] S4, etching the trench structure and growing the gate oxide layer, and depositing the polysilicon gate in the trench;

[0019] S5, polishing the polysilicon layer by chemical mechanical polishing process to make the upper surface of the interlayer dielectric layer flush with the upper surface of the N-type epitaxial layer, and then partially etching the polysilicon gate to form a section of the gate;

[0020] S6, regrowing the oxide layer on the polysilicon gate, depositing the polysilicon again to form another section of the gate, and depositing a layer of oxide film to form a split gate structure;

[0021] S7, ion implantation on the N-type epitaxial layer to form P- region and N+ region in turn, avoiding the split gate structure;

[0022] S8, depositing the oxide layer on the upper surface of the N+ region, etching the via hole, ion implantation through the via hole to form P+ region on the upper part of the P- region, depositing the metal layer on the oxide layer, and the metal layer contacts with the P+ region through the via hole;

[0023] S9, depositing ITO thin film layer and Al layer on the metal layer, depositing the interlayer dielectric layer again, and polishing the interlayer dielectric layer by chemical mechanical polishing process to make the upper surface of the interlayer dielectric layer flush with the upper surface of the Al layer;

[0024] S10, connecting the RGB LED chips in the red light-emitting sub-pixel R, green light-emitting sub-pixel G and blue light-emitting sub-pixel B with the driving backboard by using mass transfer and vacuum bonding technology;

[0025] S11, depositing Si layer on the Al layer of the pressure sensing sub-pixel S and patterning to form a hollow structure, growing a layer of thin SiO2 layer and P-type silicon on the top of the Si layer of the hollow structure in turn, then performing deep silicon etching to punch, and then depositing tungsten in the hole by CVD process, and then binding the P-type single crystal silicon sensing film with piezoresistive electrode by bonding process;

[0026] S12, finally, growing common cathode and thin film packaging layer.

[0027] Another method for manufacturing a split gate type light-emitting display with pressure resistance sensing function is also mentioned, which comprises the following steps:

[0028] Sa, form a plurality of regularly arranged via holes on the driving backplane, fill the via holes with conductive material, and then form a plurality of anodes on the surface of the driving backplane, and each anode covers at least one via hole;

[0029] Sb, sequentially grow an N-type high-doped region, an N-type epitaxial layer, and an oxide layer on the driving backplane and the anodes to form a semiconductor layer;

[0030] Sc, pattern the semiconductor layer, fill the removed part with an interlayer dielectric layer, and use a chemical mechanical polishing process to polish the interlayer dielectric layer so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the oxide layer;

[0031] Sd, etch a trench structure and grow a gate oxide layer, and deposit a polysilicon gate in the trench;

[0032] Se, use a chemical mechanical polishing process to polish the polysilicon layer so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the N-type epitaxial layer, and then partially etch the polysilicon gate to form a section of the gate;

[0033] Sf, regrow an oxide layer on the surface of the polysilicon gate and the N-type epitaxial layer above it, deposit polysilicon again to form another section of the gate, and deposit an oxide film on top to form a split gate structure;

[0034] Sg, ion implantation on the N-type epitaxial layer to form a P- region and an N+ region in sequence, avoiding the split gate structure;

[0035] Sh, deposit an oxide layer on the upper surface of the N+ region, then etch a via hole, ion implantation through the via hole to form a P+ region on the upper part of the P- region, deposit a metal layer on the oxide layer, and the metal layer contacts the P+ region through the via hole;

[0036] Si, deposit an ITO thin film layer and an Al layer on the metal layer, produce an interlayer dielectric layer again, and use a chemical mechanical polishing process to polish the interlayer dielectric layer so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the Al layer;

[0037] Sj, use mass transfer and vacuum bonding technology to connect RGB LED chips in red light-emitting sub-pixels R, green light-emitting sub-pixels G, and blue light-emitting sub-pixels B with the driving backplane;

[0038] Sk, deposit a Si layer on the Al layer of the pressure sensing sub-pixel S and pattern it to form a hollow structure, grow a thin SiO2 layer and P-type silicon in sequence on the top of the Si layer of the hollow structure, then perform deep silicon etching to punch holes, and then use CVD process to deposit tungsten in the holes, and then bind the P-type single crystal silicon sensing film with a piezoresistive electrode through the bonding process;

[0039] Sl, finally, grow a common cathode and a thin film packaging layer.

[0040] The application has the advantages that the sub-grid type module prepared by using the semiconductor process can realize the display functions of high resolution, high brightness, high contrast and low response time, and can receive the external pressure information in real time, and provides a feasible solution for the single-chip integration of touch interactive display. BRIEF DESCRIPTION OF DRAWINGS

[0041] The application will be further described below in combination with the drawings and examples.

[0042] Figure 1 is a structural schematic diagram of the embodiment one of the application.

[0043] Figure 2 is a schematic diagram of step 1 of the embodiment one of the application.

[0044] Figure 3 is a schematic diagram of step 2 of the embodiment one of the application.

[0045] Figure 4 is a schematic diagram of step 3 of the embodiment one of the application.

[0046] Figure 5 is a schematic diagram of step 4 of the embodiment one of the application.

[0047] Figure 6 is a schematic diagram of step 5 of the embodiment one of the application.

[0048] Figure 7 is a schematic diagram of step 6 of the embodiment one of the application.

[0049] Figure 8 is a schematic diagram of step 7 of the embodiment one of the application.

[0050] Figure 9 is a schematic diagram of step 8 of the embodiment one of the application.

[0051] Figure 10 is a schematic diagram of step 9 of the embodiment one of the application.

[0052] Figure 11 is a schematic diagram of step 10 of the embodiment one of the application.

[0053] Figure 12 is a schematic diagram of step 11 of the embodiment one of the application.

[0054] Figure 13 is a schematic diagram of step 12 of the embodiment one of the application.

[0055] Figure 14 is a structural schematic diagram of the embodiment two of the application.

[0056] Figure 15 is a schematic diagram of step a of the embodiment two of the application.

[0057] Figure 16 is a schematic diagram of step b of embodiment two of the present application.

[0058] Figure 17 is a schematic diagram of step c of embodiment two of the present application.

[0059] Figure 18 is a schematic diagram of step d of embodiment two of the present application.

[0060] Figure 19 is a schematic diagram of step e of embodiment two of the present application.

[0061] Figure 20 is a schematic diagram of step f of embodiment two of the present application.

[0062] Figure 21 is a schematic diagram of step g of embodiment two of the present application.

[0063] Figure 22 is a schematic diagram of step h of embodiment two of the present application.

[0064] Figure 23 is a schematic diagram of step i of embodiment two of the present application.

[0065] Figure 24 is a schematic diagram of step j of embodiment two of the present application.

[0066] Figure 25 is a schematic diagram of step k of embodiment two of the present application.

[0067] Figure 26 is a schematic diagram of step l of embodiment two of the present application.

[0068] Figure 27 is a schematic diagram of the optimized pixel arrangement scheme of embodiment one and embodiment two of the present application.

[0069] Figure 28 is a schematic diagram of the driving circuit of embodiment one and embodiment two of the present application.

[0070] Figure: 1, driving back plate; 2, via hole; 3, anode; 4, semiconductor device; 41, N-type high-doped region; 42, N-type epitaxial layer; 43, gate; 44, P- region; 45, N+ region; 46, P+ region; 47, metal layer; 48, oxide layer; 5, ITO thin film layer; 6, Al layer; 7, interlayer dielectric layer; 8, common cathode; 9, thin film packaging layer; 10, P-pad layer; 11, P-GaN layer; 12, MQW layer; 13, n-GaN layer; 14, N-pad layer; 15, Si layer; 16, SiO2 layer; 17, P-type silicon; 18, P-type monocrystalline silicon sensing thin film; 19, tungsten. DETAILED DESCRIPTION

[0071] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0072] Example 1

[0073] like Figure 1 As shown, a grid-type light-emitting display with piezoresistive sensing function includes: multiple pixels, each pixel including a red light-emitting sub-pixel R, a green light-emitting sub-pixel G, a blue light-emitting sub-pixel B, and a pressure-sensing sub-pixel S; a driving backplate 1, on which a plurality of regularly arranged vias 2 are provided, wherein the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B, or the pressure-sensing sub-pixel S covers at least one via 2; the driving backplate 1 carries multiple pixels and drives the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, and the blue light-emitting sub-pixel to emit light and drives the pressure-sensing sub-pixel S to receive pressure information; the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B, and the pressure-sensing sub-pixel S each include an anode 3, a semiconductor device 4, an ITO thin film layer 5, and an Al layer 6; the anode 3 is disposed on the driving backplate 1 and covers at least one via 2; the semiconductor device 4 is located on the side of the anode 3 away from the driving backplate 1; the ITO thin film layer 5 is located on the side of the semiconductor device 4 away from the driving backplate 1; and the Al layer 6 is disposed on the ITO thin film layer 5.

[0074] It also includes an interlayer dielectric layer 7 and a common cathode 8. The interlayer dielectric layer 7 is filled between the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure-sensing sub-pixel S. Electrode grooves are formed on the interlayer dielectric layer 7 corresponding to the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B. The common cathode 8 is located on the side of the interlayer dielectric layer 7 away from the driving backplate 1 and covers the electrode grooves. The common cathode 8 is in contact with the upper surfaces of the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B through the electrode grooves. In the pressure-sensing sub-pixel S, the common cathode 8 is connected to the piezoresistive electrode of the P-type single crystal silicon sensing film.

[0075] It also includes a thin-film encapsulation layer 9, which is located on the side of the common cathode 8 away from the drive backplate 1 and covers the common cathode 8.

[0076] The semiconductor device 4 includes an N-type highly doped region 41, an N-type epitaxial layer 42, a gate 43, a P- region 44, an N+ region 45, a P+ region 46, and a metal layer 47. The N-type highly doped region 41 is located on the side of the anode 3 away from the driving backplate 1. An N-type epitaxial layer 42 is formed on the N-type highly doped region 41. The gate 43 is disposed in the N-type epitaxial layer 42 and is divided into two sections. The P- region 44 is disposed on the upper surface of the N-type epitaxial layer 4 that avoids the gate 43. The N+ region 45 is disposed on the upper surface of the P+ region 46. An oxide layer 48 is disposed on the N+ region 45. A via is disposed on the oxide layer 48. The P+ region 46 is disposed in the P-44 below the via. A metal layer 47 is disposed on the oxide layer 48. The metal layer 47 has a metal connector that extends into the via and connects to the P+ region 46.

[0077] The red light-emitting sub-pixel R, the green light-emitting sub-pixel G, and the blue light-emitting sub-pixel B each include a P-pad layer 10, a P-GaN layer 11, an MQW layer 12, an n-GaN layer 13, and an N-pad layer 14 sequentially disposed on the Al layer 6. The pressure-sensing sub-pixel S has a Si layer 15 with a hollow structure on the Al layer 6, a SiO2 layer 16 on the Si layer 15, a P-type silicon layer 17 on the SiO2 layer 16, and a P-type single-crystal silicon sensing film 18 with a piezoresistive electrode connected to the P-type silicon layer 17. A through-hole is provided from the upper surface of the P-type silicon layer 17 to the lower surface of the Si layer 15, and a tungsten 19 connecting the P-type single-crystal silicon sensing film 18 and the Al layer 6 is disposed within the through-hole.

[0078] The method for manufacturing a grid-type light-emitting display with piezoresistive sensing function according to Embodiment 1 is as follows:

[0079] Step 1: As Figure 2 As shown, a number of regularly arranged vias 2 are formed on the drive backplate 1, and conductive material is filled in the vias 2. Subsequently, a number of anodes 3 are formed on the upper surface of the drive backplate 1, and each anode 3 covers at least one via 2.

[0080] Step 2: As Figure 3 As shown, an N-type highly doped region 41, an N-type epitaxial layer 42, and an oxide layer 48 are sequentially grown on the driving backplate 1 and the anode 3 to form a semiconductor layer;

[0081] Step 3: As Figure 4 As shown, the patterned semiconductor layer is filled with the removed portion by the interlayer dielectric layer 7, and the interlayer dielectric layer 7 is smoothed by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the oxide layer 48.

[0082] Step 4: As Figure 5 As shown, a trench structure is etched and a gate oxide layer 48 is grown, and a polysilicon gate 43 is deposited in the trench.

[0083] Step 5: AsFigure 6 As shown, the polysilicon layer is polished using a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the N-type epitaxial layer 42. Then, the polysilicon gate 43 is partially etched to form a gate section.

[0084] Step 6: As Figure 7 As shown, an oxide layer 48 is regrown on the polysilicon gate 43, polysilicon is deposited again to form another gate segment, and an oxide film is deposited on it to form a gate splitting structure.

[0085] Step 7: As Figure 8 As shown, P-region 44 and N+ region 45 are sequentially formed on the N-type epitaxial layer 42 by ion implantation, avoiding the gate structure;

[0086] Step 8: As Figure 9 As shown, after depositing an oxide layer 48 on the upper surface of the N+ region 45, a via is etched. Ions are implanted through the via to form a P+ region 46 on the upper part of the P- region 44. A metal layer 47 is deposited on the oxide layer 48. The metal layer 47 passes through the via and contacts the P+ region 46.

[0087] Step 9: As Figure 10 As shown, an ITO thin film layer 5 and an Al layer 6 are deposited on the metal layer 47, and an interlayer dielectric layer 7 is produced again. The interlayer dielectric layer 7 is then ground using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the Al layer 6.

[0088] Step 10: As Figure 11 As shown, the RGB LED chips (including P-pad layer 10, P-GaN layer 11, MQW layer 12, n-GaN layer 13 and N-pad layer 14 arranged sequentially) in the red light-emitting sub-pixel R, green light-emitting sub-pixel G and blue light-emitting sub-pixel B are connected to the driver backplane 1 using mass transfer and vacuum bonding technology.

[0089] Step 11: As Figure 12 As shown, a Si layer 15 is deposited on the Al layer 6 of the pressure sensing sub-pixel S and patterned to form a hollow structure. A thin SiO2 layer 16 and a P-type silicon 17 are grown sequentially on the top of the Si layer 15 of the hollow structure. After deep silicon etching and hole drilling, tungsten 19 is deposited in the hole using CVD process. Then, a P-type single crystal silicon sensing film 18 with a piezoresistive electrode is bonded by bonding process.

[0090] Step 12: As Figure 13 As shown, finally, the common cathode 8 and the thin film encapsulation layer 9 are grown, and the current flow is shown by the red arrow inside the semiconductor device 4.

[0091] Example 2

[0092] The difference from Example 1 is as follows: Figure 14As shown, the section of the gate located at the bottom of the trench is longer than the section at the bottom of the trench in Embodiment 1, and the position of the oxide layer 48 grown on this section is different. The oxide layer 48 is grown on the surface of the gate section and the N-type epitaxial layer 42 above it.

[0093] The fabrication method of the grid-type light-emitting display with piezoresistive sensing function in Example 2 is as follows:

[0094] Step a: As Figure 15 As shown, a number of regularly arranged vias 2 are formed on the drive backplate 1, and conductive material is filled in the vias 2. Subsequently, a number of anodes 3 are formed on the upper surface of the drive backplate 1, and each anode 3 covers at least one via 2.

[0095] Step b: As Figure 16 As shown, an N-type highly doped region 41, an N-type epitaxial layer 42, and an oxide layer 48 are sequentially grown on the driving backplate 1 and the anode 3 to form a semiconductor layer;

[0096] Step c: As Figure 17 As shown, the patterned semiconductor layer is filled with the removed portion by the interlayer dielectric layer 7, and the interlayer dielectric layer 7 is smoothed by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the oxide layer 48.

[0097] Step d: As Figure 18 As shown, a trench structure is etched and a gate oxide layer 48 is grown, and a polysilicon gate 43 is deposited in the trench.

[0098] Step e: as Figure 19 As shown, the polysilicon layer is polished using a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the N-type epitaxial layer 42. Then, the polysilicon gate 43 is partially etched to form a gate section.

[0099] Step f: as Figure 20 As shown, an oxide layer 48 is regrown on the surface of the polysilicon gate 43 and the N-type epitaxial layer 42 above it, polysilicon is deposited again to form another gate segment, and an oxide film is deposited on it to form a gate splitting structure.

[0100] Step g: as Figure 21 As shown, P-region 44 and N+ region 45 are sequentially formed on the N-type epitaxial layer 42 by ion implantation, avoiding the gate structure;

[0101] Step h: as Figure 22 As shown, after depositing an oxide layer 48 on the upper surface of the N+ region 45, a via is etched. Ions are implanted through the via to form a P+ region 46 on the upper part of the P- region 44. A metal layer 47 is deposited on the oxide layer. The metal layer 47 passes through the via and contacts the P+ region 46.

[0102] Step i: AsFigure 23 As shown, an ITO thin film layer 5 and an Al layer 6 are deposited on the metal layer 47, and an interlayer dielectric layer 7 is produced again. The interlayer dielectric layer 7 is then ground using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the Al layer 6.

[0103] Step j: as Figure 24 As shown, RGB LED chips (including P-pad layer 10, P-GaN layer 11, MQW layer 12, n-GaN layer 13 and N-pad layer 14 arranged sequentially) in red light-emitting sub-pixel R, green light-emitting sub-pixel G and blue light-emitting sub-pixel B) are connected to the driver backplane 1 using mass transfer and vacuum bonding technology.

[0104] Step k: as follows Figure 25 As shown, a Si layer 15 is deposited on the Al layer 6 of the pressure sensing sub-pixel S and patterned to form a hollow structure. A thin SiO2 layer 16 and a P-type silicon 17 are grown sequentially on the top of the Si layer 15 of the hollow structure. After deep silicon etching and hole drilling, tungsten 19 is deposited in the hole using CVD process. Then, a P-type single crystal silicon sensing film 18 with a piezoresistive electrode is bonded by bonding process.

[0105] Step 1: As Figure 26 As shown, finally, the common cathode 8 and the thin film encapsulation layer 9 are grown, and the current flow is shown by the red arrow inside the semiconductor device 4.

[0106] The optimized pixel arrangement schemes of Embodiment 1 and Embodiment 2 are as follows: Figure 27 As shown, a pixel includes a red luminous sub-pixel R, a green luminous sub-pixel G, a blue luminous sub-pixel B, and a pressure-sensing sub-pixel S. Spatially, a square has four vertices, each containing the pressure-sensing sub-pixels S and blue luminous sub-pixels B at its two diagonal vertices, and the red luminous sub-pixels R and green luminous sub-pixels G at the remaining two vertices. The side length of the square is equal to the pixel width. Four groups of red luminous sub-pixels R, green luminous sub-pixels G, blue luminous sub-pixels B, or pressure-sensing sub-pixels S share a single mask opening.

[0107] Example 1 and Example 2 adopt Figure 27 The pixel optimization arrangement scheme shown, combined with the high-resolution driving backplane 1, can break through the physical limits of the existing high-resolution metal mask FMM, achieving high resolution, high brightness, and high contrast display, while having a low response time.

[0108] Example 1 and Example 2 are combined as follows Figure 28 The driving circuit shown can improve the performance and reliability of the display, and has the advantages of high integration, low power consumption, high speed and good stability, making it widely applicable.

[0109] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A grid-type light-emitting display equipped with piezoresistive sensing function, characterized in that, include: Multiple pixels, each of which includes a red light-emitting sub-pixel R, a green light-emitting sub-pixel G, a blue light-emitting sub-pixel B, and a pressure-sensing sub-pixel S; A driving backplate (1) is provided with a number of regularly arranged vias (2). The red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B or the pressure-sensing sub-pixel S cover at least one via (2). The driving backplate (1) carries multiple pixels and drives the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel to emit light and drives the pressure-sensing sub-pixel S to receive pressure information. The red light-emitting sub-pixel R, green light-emitting sub-pixel G, blue light-emitting sub-pixel B and pressure-sensing sub-pixel S each include an anode (3), a semiconductor device (4), an ITO thin film layer (5) and an Al layer (6). The anode (3) is disposed on the driving backplate (1) and covers at least one via (2). The semiconductor device (4) is located on the side of the anode (3) away from the driving backplate (1). The ITO thin film layer (5) is located on the side of the semiconductor device (4) away from the driving backplate (1). The Al layer (6) is disposed on the ITO thin film layer (5). The pressure sensing sub-pixel S has an Al layer (6) with a hollow structure, a Si layer (15) with a hollow structure, a SiO2 layer (16) with a SiO2 layer (16), a P-type silicon (17) with a piezoresistive electrode connected to the P-type silicon (17), and a through hole from the upper surface of the P-type silicon (17) to the lower surface of the Si layer (15), and a tungsten (19) connecting the P-type silicon (18) and the Al layer (6) is provided in the through hole.

2. The grid-type light-emitting display with piezoresistive sensing function according to claim 1, characterized in that: The semiconductor device (4) includes an N-type highly doped region (41), an N-type epitaxial layer (42), a gate (43), a P- region (44), an N+ region (45), a P+ region (46), and a metal layer (47). The N-type highly doped region (41) is located on the side of the anode (3) away from the driving backplate (1). An N-type epitaxial layer (42) is formed on the N-type highly doped region (41). The gate (43) is disposed within the N-type epitaxial layer (42) and is divided into two segments. Region (44) is disposed on the upper surface of N-type epitaxial layer (42) that avoids gate (43), N+ region (45) is disposed on the upper surface of P+ region (46), N+ region (45) is provided with oxide layer (48), oxide layer (49) is provided with via, P+ region (46) is disposed in P- region (44) below via, oxide layer (19) is provided with metal layer (47), metal layer (47) has metal connector that extends into via and connects to P+ region (46).

3. The grid-type light-emitting display with piezoresistive sensing function according to claim 1, characterized in that: The red light-emitting sub-pixel R, the green light-emitting sub-pixel G, and the blue light-emitting sub-pixel B each include a P-pad layer (10), a P-GaN layer (11), an MQW layer (12), an n-GaN layer (13), and an N-pad layer (14) sequentially arranged on the Al layer (6).

4. The grid-type light-emitting display with piezoresistive sensing function according to claim 1, characterized in that: It also includes an interlayer dielectric layer (7) and a common cathode (8). The interlayer dielectric layer (7) is filled between the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure-sensing sub-pixel S. Electrode grooves are formed on the interlayer dielectric layer (7) corresponding to the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B. The common cathode (8) is disposed on the side of the interlayer dielectric layer (7) away from the driving backplate (1) and covers the electrode grooves. The common cathode (8) is in contact with the upper surfaces of the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B through the electrode grooves. In the pressure-sensing sub-pixel S, the common cathode (8) is connected to the piezoresistive electrode of the P-type single crystal silicon sensing film (18).

5. The grid-type light-emitting display with piezoresistive sensing function according to claim 4, characterized in that: It also includes a thin film encapsulation layer (9), which is located on the side of the common cathode (8) away from the drive backplate (1) and covers the common cathode (8).

6. A method for manufacturing a grid-type light-emitting display with piezoresistive sensing function as described in any one of claims 1 to 5, characterized in that, Includes the following steps: S1. A number of regularly arranged vias (2) are formed on the drive backplate (1), and conductive material is filled in the vias (2). Then, a number of anodes (3) are formed on the upper surface of the drive backplate (1), and each anode (3) covers at least one via (2). S2. An N-type highly doped region (41), an N-type epitaxial layer (42), and an oxide layer (48) are sequentially grown on the driving backplate (1) and the anode (3) to form a semiconductor layer; S3, patterned semiconductor layer, the removed part is filled by interlayer dielectric layer (7), and the interlayer dielectric layer (7) is smoothed by chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of oxide layer (48); S4. Etch trench structure and grow gate oxide layer (48), deposit polysilicon gate (43) in trench. S5. The polysilicon layer is ground flat using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the N-type epitaxial layer (42), and then the polysilicon gate (43) is partially etched to form a gate section. S6. An oxide layer (48) is regrown on the polysilicon gate, polysilicon is deposited again to form another gate segment, and an oxide film is deposited on it to form a gate segment structure. S7. On the N-type epitaxial layer (42), P-region (44) and N+ region (45) are sequentially formed by ion implantation, avoiding the gate structure. S8. After depositing an oxide layer (48) on the upper surface of the N+ region (45), a via is etched. An ion implantation is performed through the via to form a P+ region (46) on the upper part of the P- region (44). A metal layer (47) is deposited on the oxide layer (48). The metal layer (47) passes through the via and contacts the P+ region (46). S9. An ITO thin film layer (5) and an Al layer (6) are deposited on the metal layer (47), and an interlayer dielectric layer (7) is produced again. The interlayer dielectric layer (7) is then ground using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the Al layer (6). S10. Use mass transfer and vacuum bonding technology to connect the RGB LED chips in the red light-emitting sub-pixel R, green light-emitting sub-pixel G, and blue light-emitting sub-pixel B to the driving backplane (1); S11. A Si layer (15) is deposited on the Al layer (6) of the pressure sensing sub-pixel S and patterned to form a hollow structure. A thin SiO2 layer (16) and a P-type silicon (17) are grown sequentially on the top of the Si layer (15) of the hollow structure. Then, after deep silicon etching and hole drilling, tungsten (19) is deposited in the hole using CVD process. Then, a P-type single crystal silicon sensing film with a piezoresistive electrode (18) is bonded by bonding process. S12. Finally, grow the common cathode (8) and the thin film encapsulation layer (9).

7. A method for manufacturing a grid-type light-emitting display with piezoresistive sensing function as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Sa, A number of regularly arranged vias (2) are formed on the drive backplate (1), and conductive material is filled in the vias (2). Subsequently, a number of anodes (3) are formed on the upper surface of the drive backplate (1), and each anode (3) covers at least one via (2). Sb, an N-type highly doped region (41), an N-type epitaxial layer (42) and an oxide layer (48) are sequentially grown on the driving backplate (1) and the anode to form a semiconductor layer; Sc, patterned semiconductor layer, the removed part is filled by interlayer dielectric layer (7), and the interlayer dielectric layer (7) is ground flat by chemical mechanical grinding process, so that the upper surface of interlayer dielectric layer (7) is flush with the upper surface of oxide layer (48); Sd, etch trench structure and grow gate oxide layer (48), deposit polysilicon gate (43) in trench. Se, use chemical mechanical grinding process to grind the polysilicon layer so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the N-type epitaxial layer (42), and then partially etch the polysilicon gate (43) to form a gate section; Sf, an oxide layer (48) is regrown on the surface of the polysilicon gate (43) and the N-type epitaxial layer (42) above it, polysilicon is deposited again to form another gate segment, and an oxide film is deposited on it to form a gate split structure; Sg, avoiding the gate structure, ion implantation is performed on the N-type epitaxial layer (42) to sequentially form the P- region (44) and the N+ region (45). Sh、After depositing an oxide layer (48) on the upper surface of the N+ region (45), a via is etched. An ion implantation is performed through the via to form a P+ region (46) on the upper part of the P- region (44). A metal layer (47) is deposited on the oxide layer (48). The metal layer (47) passes through the via and contacts the P+ region (46). Si, deposit an ITO thin film layer (5) and an Al layer (6) on the metal layer (47), produce an interlayer dielectric layer (7) again, and use a chemical mechanical grinding process to grind the interlayer dielectric layer (7) so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the Al layer (6); Sj. Using mass transfer and vacuum bonding technology, the RGB LED chips in the red light-emitting sub-pixel R, green light-emitting sub-pixel G, and blue light-emitting sub-pixel B are connected to the driver backplane (1). Sk, deposit a Si layer (15) on the Al layer (6) of the pressure sensing sub-pixel S and pattern it to form a hollow structure. On the top of the Si layer (15) of the hollow structure, grow a thin SiO2 layer (16) and a P-type silicon (17) in sequence. Then, perform deep silicon etching to drill holes and use CVD process to deposit tungsten (19) in the holes. Then, use bonding process to bind the P-type single crystal silicon sensing film with piezoresistive electrode (18). Sl, Finally, grow the common cathode (8) and the thin film encapsulation layer (9).

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