Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a plurality of first sub-pixels, each first sub-pixel comprises a first pixel circuit, the layout structure of a part of the first pixel circuits is a first pattern structure, the layout structure of the other part of the first pixel circuits is a second pattern structure, and the first pattern structures and the second pattern structures are mirror image structures of each other. According to the display panel and the display device provided by the embodiment of the invention, the problem of non-uniform display can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, users have higher and higher requirements on the display performance of display panels. For example, high-resolution display panels have become a development direction of display products.

[0003] However, the display panel in the related art still has the problem of uneven display. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which can improve the problem of uneven display of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising: a plurality of first sub-pixels, the first sub-pixels comprising a first pixel circuit, the layout structure of a portion of the first pixel circuit being a first pattern structure, the layout structure of another portion of the first pixel circuit being a second pattern structure, the first pattern structure and the second pattern structure being mirror images of each other.

[0006] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel as described in the embodiment of the first aspect.

[0007] According to the display panel provided by the embodiment of the present application, the layout structure of multiple first sub-pixels of the same color is no longer designed to have only one pattern structure, but the layout structure of part of the first sub-pixels is designed to be a first pattern structure, and the layout structure of another part of the first sub-pixels is designed to be a second pattern structure, and the first pattern structure and the second pattern structure are mirror images of each other. In this way, even if there is an alignment accuracy offset in the preparation process, the capacitance deviations of the first sub-pixels of the two pattern structures of the same luminous color caused by the alignment accuracy offset can offset each other, thereby making the bright and dark effects of the multiple first sub-pixels of the same luminous color offset each other, thereby improving the low grayscale Mura problem caused by the first sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0009] Figure 1 A schematic diagram showing a pixel arrangement of a display panel provided in a comparative example of the present application is shown;

[0010] Figure 2A schematic diagram showing two pattern structures that are mirror images of each other in a display panel provided in an embodiment of the present application;

[0011] Figure 3 A schematic diagram showing a pixel arrangement of a display panel provided by an embodiment of the present application is shown;

[0012] Figure 4 A schematic diagram showing a module structure of a sub-pixel in a display panel provided by an embodiment of the present application is shown;

[0013] Figure 5 A schematic diagram showing a structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0014] Figure 6 A schematic diagram showing a layout structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0015] Figure 7 Another schematic diagram of pixel arrangement of a display panel provided in an embodiment of the present application is shown;

[0016] Figure 8 A schematic diagram showing another pixel arrangement of a display panel provided in an embodiment of the present application is shown;

[0017] Fig. 9 A schematic diagram showing another pixel arrangement of a display panel provided in an embodiment of the present application is shown;

[0018] Fig.10 A schematic diagram showing another pixel arrangement of a display panel provided in an embodiment of the present application is shown;

[0019] Fig.11 A schematic diagram showing a layout structure of a semiconductor layer in a display panel provided in an embodiment of the present application;

[0020] Fig.12 A schematic diagram showing a layout structure of a gate metal layer in a display panel provided in an embodiment of the present application;

[0021] Fig.13 A schematic diagram showing a layout structure of a capacitor metal layer in a display panel provided in an embodiment of the present application;

[0022] Fig.14 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0024] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0025] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0026] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0027] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0028] The term "connect" may mean "electrically connected" or "not electrically connected through an intermediate transistor". The term "drive" may mean "control" or "operate". The term "portion" may mean "local". The term "pattern" may mean "component". The term "end" may mean "end segment" or "end edge". The display panel may be a display device or a module / portion of a display device.

[0029] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0030] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0031] In order to achieve high resolution and high performance of the display panel, a sub-pixel mirror design is usually adopted to save layout space.

[0032] For a more intuitive understanding of the mirror design solution, as a comparison, please refer to Figure 1 , Figure 1 In the figure, boxes filled with the same pattern represent sub-pixels of the same luminous color, and rectangular boxes filled with different patterns represent sub-pixels of different luminous colors. Figure 1 The rectangular box filled with a dot pattern represents a red sub-pixel, the rectangular box filled with a horizontal line pattern represents a green sub-pixel, and the rectangular box filled with a grid pattern represents a blue sub-pixel. A and B represent two mirrored pattern structures on the Layout graphic. For example, A and B represent the pattern structure on the Layout graphic as follows: Figure 2 As shown, the A-Sub sub-pixel having the structure shown in A and the B-Sub sub-pixel having the structure shown in B are mirror images of each other on the Layout graphic.

[0033] like Figure 1 As shown in FIG. 1 , the A-Sub sub-pixels and the B-Sub sub-pixels are arranged alternately on the left and right. However, the inventors of the present application have found that the use of Figure 1 The structure shown is prone to obvious display unevenness (Mura).

[0034] This is because, in the manufacturing process, it is impossible to ensure that there is no offset in the alignment accuracy. When the alignment accuracy is offset left or right in the process, because the A-Sub sub-pixel and the B-Sub sub-pixel are mirror images of each other, the capacitance of the key nodes in the sub-pixel may be too large or too small. For example, the capacitance of the key nodes in the sub-pixel includes the capacitance between the node N1 connected to the gate of the driving transistor and the data line Data. For example, the capacitance of the key nodes in the A-Sub sub-pixel may be too large, resulting in the A-Sub sub-pixel being darker; and the capacitance of the key nodes in the B-Sub sub-pixel may be too small, resulting in the B-Sub sub-pixel being brighter. However, Figure 1 In the structure shown, sub-pixels of the same luminous color are all A-Sub sub-pixels, or, are all B-Sub sub-pixels ( Figure 1 In the figure, the red and blue sub-pixels are both A-Sub sub-pixels, and the green sub-pixels are all B-Sub sub-pixels. For sub-pixels of the same luminous color, the deviation in the capacitance of the key nodes in the sub-pixels caused by the deviation in the alignment accuracy cannot be offset. As the degree of alignment accuracy deviation at different positions varies, low grayscale Mura problems are easily caused.

[0035] In view of the above research findings of the inventors, the embodiments of the present application consider improving the layout structure of sub-pixels of the same luminous color, designing the layout structure of some sub-pixels in the same luminous color as a first pattern structure, and designing the layout structure of another part of the sub-pixels as a second pattern structure, and the first pattern structure and the second pattern structure are mirror structures of each other; in this way, the capacitance deviations of sub-pixels of the two pattern structures of the same luminous color caused by the offset of the alignment accuracy can offset each other, so that the bright and dark effects of sub-pixels of the same luminous color offset each other, thereby improving the low grayscale Mura problem.

[0036] Specifically, an embodiment of the present application provides a display panel and a display device, and the embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0037] The embodiment of the present application provides a display panel. For example, the display panel may be an organic light emitting diode (OLED) display panel. Of course, in other examples, the display panel may also be a micro light emitting diode (Micro LED) display panel, an LED display panel, etc.

[0038] Figure 3 A schematic diagram of a pixel arrangement of a display panel provided in an embodiment of the present application is shown. Figure 3 In the subsequent schematic diagrams showing pixel arrangement, boxes filled with the same pattern represent sub-pixels of the same luminous color, and rectangular boxes filled with different patterns represent sub-pixels of different luminous colors. Figure 3 The rectangular box filled with a dot pattern represents a red sub-pixel R, the rectangular box filled with a horizontal line pattern represents a green sub-pixel G, and the rectangular box filled with a grid pattern represents a blue sub-pixel. Figure 3 As shown, the display panel includes sub-pixels of multiple luminous colors, which are arranged in an array in a first direction X and a second direction Y that intersect.

[0039] The display panel includes a plurality of first sub-pixels 11. Figure 4 As shown, the first sub-pixel 11 includes a first pixel circuit 111. The first sub-pixel 11 also includes a first light-emitting element 112, and the first pixel circuit 111 is used to drive the first light-emitting element 112 to emit light. As an example, the circuit structure of the first pixel circuit 111 includes but is not limited to the following: Figure 5 The circuit structure shown.

[0040] The plurality of first sub-pixels include a plurality of first pixel circuits, among which the layout structure of some of the first pixel circuits is the first layout structure, and the layout structure of another portion of the first pixel circuits is the second pattern structure, and the first pattern structure and the second pattern structure are mirror images of each other. Here, it can be understood that: the orthographic projection of the layout structure of some of the first pixel circuits on the plane where the display panel is located is the first pattern structure, and the orthographic projection of the layout structure of another portion of the first pixel circuits on the plane where the display panel is located is the second pattern structure, and in the first direction X, the first pattern structure and the second pattern structure are mirror images of each other.

[0041] For example, Figure 3 The first sub-pixel having the first pattern structure is marked as a first-type first sub-pixel 11a, and the first pattern structure of the first-type first sub-pixel 11a is marked as A1. Figure 3 The first sub-pixel with the second pattern structure is marked as the second-type first sub-pixel 11b, and the second pattern structure of the second-type first sub-pixel 11b is marked as B1. Figure 2 , the first pattern structure A1 and the second pattern structure B1 are mirror images of each other. It should be noted that, Figure 2 It is only used to explain the form of two pattern structures that are mirror images of each other, and is not used to limit the shapes of the two pattern structures to be Figure 2 Shape shown.

[0042] Each pixel circuit usually includes a transistor and a capacitor. The pixel circuit also includes connecting lines between components. In addition, the pixel circuit also needs to be connected to signal lines for transmitting various signals. The layout structure of the pixel circuit may include at least one of transistors, capacitors, connecting lines between components and signal lines for transmitting various signals.

[0043] As an example, the circuit structure of the first pixel circuit 111 is as follows Figure 3 The structure shown in FIG. 1 may include a first pixel circuit having a first pattern structure A1 and a first pixel circuit having a second pattern structure B1. Figure 6 For example, the display panel includes a semiconductor layer poly and a gate metal layer M01, a capacitor metal layer MC and a second metal layer M02 which are stacked sequentially and away from each other on a first side of the semiconductor layer poly. The display panel may also include a light shielding metal layer M00, which is located on a second side of the semiconductor layer poly, and the second side of the semiconductor layer poly is opposite to the first side thereof. Figure 6 The pattern structure of the first pixel circuit in the semiconductor layer poly, the gate metal layer M01, the capacitor metal layer MC and the second metal layer M02 is shown. Figure 6 The diagram shown does not show the layout of the film layer where the light-emitting element is located. Figure 6 The structures filled with the same pattern represent the structures of the same film layer, and the structures filled with different patterns represent the structures of different film layers. In addition, the material of the semiconductor layer poly includes but is not limited to polycrystalline silicon, indium gallium zinc oxide, single crystal silicon, etc.

[0044] In the present application, the luminous colors of multiple first sub-pixels are the same. It should be noted that any sub-pixel of any color can be used as the first sub-pixel 11. In the drawings of the present application, the first sub-pixel 11 is illustrated as a red sub-pixel, which is not intended to limit the present application. For example, in other examples, the first sub-pixel may also be a green sub-pixel, or the first sub-pixel may also be a blue sub-pixel.

[0045] The technical concept of the present application is that, for a plurality of sub-pixels of the same color, the layout structure includes two pattern structures that are mirror images of each other.

[0046] For example, the layout structure of some red sub-pixels in a plurality of red sub-pixels and the layout structure of another portion of red sub-pixels belong to a pattern structure that is a mirror image of each other. For another example, the layout structure of some blue sub-pixels in a plurality of blue sub-pixels and the layout structure of another portion of blue sub-pixels belong to a pattern structure that is a mirror image of each other. For another example, the layout structure of some green sub-pixels in a plurality of green sub-pixels and the layout structure of another portion of green sub-pixels belong to a pattern structure that is a mirror image of each other.

[0047] It should be noted that the two pattern structures are mirror images of each other, and a certain error may be allowed. For example, if 80% or more of the two pattern structures are mirror images of each other, the two pattern structures may be considered to be mirror images of each other.

[0048] According to the display panel provided by the embodiment of the present application, the layout structure of multiple first sub-pixels of the same color is no longer designed to have only one pattern structure, but the layout structure of part of the first sub-pixels is designed to be a first pattern structure, and the layout structure of another part of the first sub-pixels is designed to be a second pattern structure, and the first pattern structure and the second pattern structure are mirror images of each other. In this way, even if there is an alignment accuracy offset in the preparation process, the capacitance deviations of the first sub-pixels of the two pattern structures of the same luminous color caused by the alignment accuracy offset can offset each other, thereby making the bright and dark effects of the multiple first sub-pixels of the same luminous color offset each other, thereby improving the low grayscale Mura problem caused by the first sub-pixels.

[0049] In some embodiments, Figure 3 As shown, the display panel further includes a plurality of second sub-pixels 12 and a plurality of third sub-pixels 13, and the luminous colors of the first sub-pixel 11, the second sub-pixel 12, and the third sub-pixel 13 are different from each other. For example, the colors of each sub-pixel include but are not limited to: the first sub-pixel 11 is a red sub-pixel, the second sub-pixel 12 is a blue sub-pixel, and the third sub-pixel 13 is a green sub-pixel. Of course, in other examples, it is also possible that: the first sub-pixel 11 is a red sub-pixel, the second sub-pixel 12 is a green sub-pixel, and the third sub-pixel 13 is a blue sub-pixel.

[0050] For example, Figure 4 As shown, the second sub-pixel 12 includes a second pixel circuit 121. The second sub-pixel 12 also includes a second light-emitting element 122, and the second pixel circuit 121 is used to drive the second light-emitting element 122 to emit light. As an example, the circuit structure of the second pixel circuit 121 includes but is not limited to the following: Figure 5 The circuit structure shown.

[0051] The plurality of second sub-pixels include a plurality of second pixel circuits, wherein the layout structure of some of the second pixel circuits is the third layout structure, and the layout structure of another portion of the second pixel circuits is the fourth pattern structure, and the third pattern structure and the fourth pattern structure are mirror images of each other. Here, it can be understood that: the orthographic projection of the layout structure of some of the second pixel circuits on the plane where the display panel is located is the third pattern structure, and the orthographic projection of the layout structure of another portion of the second pixel circuits on the plane where the display panel is located is the fourth pattern structure, and in the first direction X, the third pattern structure and the fourth pattern structure are mirror images of each other.

[0052] For example, Figure 3 The second sub-pixel with the third pattern structure is marked as the first-type second sub-pixel 12a, and the third pattern structure of the first-type second sub-pixel 12a is marked as A2. Figure 3The second sub-pixel with the fourth pattern structure is marked as the second-type second sub-pixel 12b, and the fourth pattern structure of the second-type second sub-pixel 12b is marked as B2. Figure 2 , the third pattern structure A2 and the fourth pattern structure B2 are mirror images of each other.

[0053] As an example, the circuit structure of the second pixel circuit 121 is as follows Figure 3 The structure shown in FIG. 1 may also be a layout structure of a second pixel circuit having a third pattern structure A2 and a second pixel circuit having a fourth pattern structure B2. Figure 6 shown.

[0054] For example, Figure 4 As shown, the third sub-pixel 13 includes a third pixel circuit 131. The third sub-pixel 13 also includes a third light-emitting element 132, and the third pixel circuit 131 is used to drive the third light-emitting element 132 to emit light. As an example, the circuit structure of the third pixel circuit 131 includes but is not limited to the following: Figure 5 The circuit structure shown.

[0055] The plurality of third sub-pixels include a plurality of third pixel circuits, wherein the layout structure of some of the third pixel circuits is the fifth layout structure, and the layout structure of another portion of the third pixel circuits is the sixth pattern structure, and the fifth pattern structure and the sixth pattern structure are mirror images of each other. Here, it can be understood that: the orthographic projection of the layout structure of some of the third pixel circuits on the plane where the display panel is located is the fifth pattern structure, and the orthographic projection of the layout structure of another portion of the third pixel circuits on the plane where the display panel is located is the sixth pattern structure, and in the first direction X, the fifth pattern structure and the sixth pattern structure are mirror images of each other.

[0056] For example, Figure 3 The third sub-pixel with the fifth pattern structure is marked as the first-type third sub-pixel 13a, and the fifth pattern structure of the first-type third sub-pixel 13a is marked as A3. Figure 3 The third sub-pixel with the sixth pattern structure is marked as the second-type third sub-pixel 13b, and the sixth pattern structure of the second-type third sub-pixel 13b is marked as B3. Figure 2 , the fifth pattern structure A3 and the sixth pattern structure B3 are mirror images of each other.

[0057] As an example, the circuit structure of the third pixel circuit 131 is as follows Figure 3 The structure shown in FIG. 1 may also be a layout structure of a third pixel circuit having a fifth pattern structure A3 and a third pixel circuit having a sixth pattern structure B3. Figure 6 shown.

[0058] In this embodiment, for any one of the three luminous color sub-pixels, the layout structure of part of the sub-pixels and the layout structure of another part of the sub-pixels are designed as mirror-image pattern structures. In this way, for multiple sub-pixels of any luminous color, the capacitance deviations of the sub-pixels of the two pattern structures of the same luminous color caused by the offset of the alignment accuracy can be offset, so that the bright and dark effects of the multiple sub-pixels of the same luminous color can be offset, thereby better improving the low grayscale Mura problem.

[0059] In some embodiments, the equivalent circuit structures of the first pixel circuit, the second pixel circuit and the third pixel circuit may be the same.

[0060] In some embodiments, the first pattern structure A1, the third pattern structure A2 and the fifth pattern structure A3 may be the same, and the second pattern structure B1, the fourth pattern structure B2 and the sixth pattern structure B3 may be the same. Two or more pattern structures being the same may mean that the patterns are almost overlapped after being stacked in a top view.

[0061] For example, Figure 6 As shown, the first pattern structure A1, the third pattern structure A2 and the fifth pattern structure A3 may all be shown in the left half, and the second pattern structure B1, the fourth pattern structure B2 and the sixth pattern structure B3 may all be shown in the right half.

[0062] In this embodiment, the display panel includes sub-pixels of three luminous colors, and the total pattern structure of the pixel circuit in the display panel includes only two types, and for multiple sub-pixels of each luminous color, two mirror-image pattern structures are included. In this way, fewer types of pattern structures are used, and the effect of offsetting the bright and dark sub-pixels of each luminous color can be achieved, which can reduce the design difficulty and process difficulty.

[0063] An exemplary arrangement of the pattern structure is introduced below.

[0064] When the first pattern structure A1, the third pattern structure A2 and the fifth pattern structure A3 are the same pattern structure, and the second pattern structure B1, the fourth pattern structure B2 and the sixth pattern structure B3 are the same pattern structure, the arrangement of the sub-pixels of multiple colors and the pattern structure of each sub-pixel can be as follows: Figures 7 to 10 As shown in any one of the accompanying drawings.

[0065] Please refer to Figures 7 to 10 As shown in any of the figures, the display panel includes a plurality of circuit column groups 20 arranged in a first direction X, and the circuit column group 20 includes a first circuit column 21, a second circuit column 22, a third circuit column 23 and a fourth circuit column 24 arranged in sequence in the first direction X.

[0066] Each circuit column includes a plurality of pixel circuits of a plurality of sub-pixels arranged in the second direction Y. The first sub-pixel 11 includes a first pixel circuit, the second sub-pixel 12 includes a second pixel circuit, and the third sub-pixel 13 includes a third pixel circuit.

[0067] Exemplarily, the first circuit column 21 includes first pixel circuits and second pixel circuits alternately arranged in the second direction Y.

[0068] The second circuit column 22 includes a plurality of third pixel circuits arranged in the second direction Y. As shown in FIG.

[0069] The third circuit column 23 includes first pixel circuits and second pixel circuits which are alternately arranged in the second direction Y.

[0070] The fourth circuit column 24 includes a plurality of third pixel circuits arranged in the second direction Y. As shown in FIG.

[0071] It can be understood that the first circuit column 21, the second circuit column 22, the third circuit column 23 and the fourth circuit column 24 correspond to the first pixel column, the second pixel column, the third pixel column and the fourth pixel column respectively, the first pixel column includes the first sub-pixels 11 and the second sub-pixels 12 arranged alternately in the second direction Y, the second pixel column includes a plurality of third sub-pixels 13 arranged in the second direction Y, the third pixel column includes the first sub-pixels 11 and the second sub-pixels 12 arranged alternately in the second direction Y, and the fourth pixel column includes a plurality of third sub-pixels 13 arranged in the second direction Y.

[0072] The pattern structure of the pixel circuits in the first circuit column 21 is one of the first pattern structure and the second pattern structure, and the pattern structure of the pixel circuits in the third circuit column 23 is the other of the first pattern structure and the second pattern structure; the pattern structure of the pixel circuits in the second circuit column 22 is one of the first pattern structure and the second pattern structure, and the pattern structure of the pixel circuits in the fourth circuit column 24 is the other of the first pattern structure and the second pattern structure.

[0073] As an example, the pattern structure of the pixel circuit in the first circuit column 21 is the first pattern structure, and the pattern structure of the pixel circuit in the third circuit column 23 is the second pattern structure; the pattern structure of the pixel circuit in the second circuit column 22 is the second pattern structure, and the pattern structure of the pixel circuit in the fourth circuit column 24 is the first pattern structure.

[0074] For ease of explanation, Figures 7 to 10It is illustrated that: the first pattern structure, the third pattern structure and the fifth pattern structure are the same first type pattern structure A, the second pattern structure, the fourth pattern structure and the sixth pattern structure are the same second type pattern structure B, and the first type pattern structure A and the second type pattern structure B are mirror images of each other. The first type first sub-pixel 11a, the first type second sub-pixel 12a and the first type third sub-pixel 13a include the first type pattern structure A, and the second type first sub-pixel 11b, the second type second sub-pixel 12b and the second type third sub-pixel 13b include the second type pattern structure B.

[0075] For example, Figure 7 As shown, the pattern structure of the pixel circuits in the first circuit column 21 is the first pattern structure A, the pattern structure of the pixel circuits in the second circuit column 22 is the second pattern structure B, the pattern structure of the pixel circuits in the third circuit column 23 is the second pattern structure B, and the pattern structure of the pixel circuits in the fourth circuit column 24 is the first pattern structure A. In the first direction, the pattern structure of the pixel circuits is arranged as: ABBA.

[0076] As another example, Figure 8 As shown, the pattern structure of the pixel circuits in the first circuit column 21 is the second pattern structure B, the pattern structure of the pixel circuits in the second circuit column 22 is the second pattern structure B, the pattern structure of the pixel circuits in the third circuit column 23 is the first pattern structure A, and the pattern structure of the pixel circuits in the fourth circuit column 24 is the first pattern structure A. In the first direction, the pattern structure of the pixel circuits is arranged as: BBAA.

[0077] As another example, Fig. 9 As shown, the pattern structure of the pixel circuits in the first circuit column 21 is the first pattern structure A, the pattern structure of the pixel circuits in the second circuit column 22 is the first pattern structure A, the pattern structure of the pixel circuits in the third circuit column 23 is the second pattern structure B, and the pattern structure of the pixel circuits in the fourth circuit column 24 is the second pattern structure B. In the first direction, the pattern structure of the pixel circuits is arranged as: AABB.

[0078] As another example, Fig.10 As shown, the pattern structure of the pixel circuits in the first circuit column 21 is the second pattern structure B, the pattern structure of the pixel circuits in the second circuit column 22 is the first pattern structure A, the pattern structure of the pixel circuits in the third circuit column 23 is the first pattern structure A, and the pattern structure of the pixel circuits in the fourth circuit column 24 is the second pattern structure B. In the first direction, the pattern structure of the pixel circuits is arranged as: BAAB.

[0079] In the above embodiment, in the second direction, the pattern structures of the multiple pixel circuits in the same column are the same, for example, the pattern structures of the multiple pixel circuits in the same column are all the first type of pattern structure A, or the pattern structures of the multiple pixel circuits in the same column are all the second type of pattern structure B. In this way, when preparing the pixel circuits in the same column, the deviation of the alignment accuracy can be ensured to be basically the same, and the difficulty of process preparation can be avoided.

[0080] like Figure 6 As shown, the layout structure of the pixel circuit may include pattern structures in multiple film layers, for example, the pixel circuit includes a semiconductor layer poly, a gate metal layer M01, a capacitor metal layer MC, and a second metal layer M02. For example, the pattern structure of the semiconductor layer is called a semiconductor pattern, and the semiconductor pattern may include an active layer of a transistor in the pixel circuit.

[0081] In some embodiments, Fig.11 As shown, the first pattern structure includes a first semiconductor pattern P1, and the second pattern structure includes a second semiconductor pattern P2; in the first direction X, adjacent first semiconductor patterns P1 and second semiconductor patterns P2 are connected to each other, and in the first direction X, two adjacent first semiconductor patterns P1 are disconnected from each other, and two adjacent second semiconductor patterns P2 are disconnected from each other.

[0082] In this embodiment, Fig.11 Corresponds to Figure 7 The ABBA pattern arrangement structure shown in the figure. The first circuit column 21 includes the first semiconductor pattern P1, the second circuit column 22 includes the second semiconductor pattern P2, the third circuit column 23 includes the second semiconductor pattern P2, and the fourth circuit column 24 includes the first semiconductor pattern P1. The first semiconductor pattern P1 and the second semiconductor pattern P2 are mirror images of each other.

[0083] It should be noted that Fig.11 The pattern selected by a purple dashed box can represent a semiconductor pattern. Fig.11 A total of 16 semiconductor patterns in 2 rows and 8 columns are shown.

[0084] In the first direction X, the adjacent first semiconductor pattern P1 and the second semiconductor pattern P2 are interconnected. Here, interconnection means that the adjacent first semiconductor pattern P1 and the second semiconductor pattern P2 in the first direction X are interconnected through semiconductor wiring. That is to say, in the semiconductor layer, the adjacent first semiconductor pattern P1 and the second semiconductor pattern P2 are connected as a whole. For example, in the semiconductor layer, the first semiconductor pattern P1 and the second semiconductor pattern P2 in the adjacent first circuit column 21 and the second circuit column 22 and located in the same row are connected as a whole. For another example, in the semiconductor layer, the first semiconductor pattern P1 and the second semiconductor pattern P2 in the adjacent third circuit column 23 and the fourth circuit column 24 and located in the same row are connected as a whole.

[0085] In the first direction X, two adjacent first semiconductor patterns P1 are disconnected from each other, which means that no semiconductor wiring is connected between the two adjacent first semiconductor patterns P1 in the first direction X. That is, in the semiconductor layer, the two adjacent first semiconductor patterns P1 in the first direction X are independent of each other. For example, in the semiconductor layer, the two first semiconductor patterns P1 in the adjacent fourth circuit column 24 and the first circuit column 21 and located in the same row are independent of each other.

[0086] In the first direction X, two adjacent second semiconductor patterns P2 are disconnected from each other, which means that no semiconductor trace is connected between the two adjacent second semiconductor patterns P2 in the first direction X. That is, in the semiconductor layer, two adjacent second semiconductor patterns P2 in the first direction X are independent of each other. For example, in the semiconductor layer, two second semiconductor patterns P2 in the adjacent second circuit column 22 and the third circuit column 23 and located in the same row are independent of each other.

[0087] Different parts of the semiconductor pattern are used to form active layers of different transistors in the pixel circuit. Different transistors in the pixel circuit have different functions. For example, the driving transistor is used to generate a driving current, some transistors are used to reset the anode of the light-emitting element, some transistors are used to reset the gate of the driving transistor, and some transistors are used to provide a power signal PVDD to the source of the driving transistor, and so on.

[0088] In this embodiment, when the first semiconductor pattern P1 and the second semiconductor pattern P2 adjacent to each other in the first direction X are connected to each other, it is convenient to provide the same signal to the pixel circuits to which the first semiconductor pattern P1 and the second semiconductor pattern P2 belong respectively, thereby simplifying the layout. When two adjacent first semiconductor patterns P1 are disconnected from each other in the first direction X, it is possible to avoid the signals of the two first semiconductor patterns P1 from forming crosstalk, so as to ensure that the pixel circuits to which the two first semiconductor patterns P1 belong can all work normally. Similarly, when two adjacent second semiconductor patterns P2 are disconnected from each other in the first direction X, it is possible to avoid the signals of the two second semiconductor patterns P2 from forming crosstalk, so as to ensure that the pixel circuits to which the two second semiconductor patterns P2 belong can all work normally.

[0089] In some embodiments, please refer to Figure 5 and Fig.11 , the pixel circuits of the display panel all include a first transistor M7, and the first transistor M7 is used to reset the light-emitting element of the display panel. The first electrode of the first transistor M7 is connected to the reset signal line Vref, and the second electrode of the first transistor M7 is connected to the anode of the light-emitting element. The first pixel circuit, the second pixel circuit, and the third pixel circuit all include a first transistor, and the first transistor in each pixel circuit is used to reset the light-emitting element connected to each pixel circuit.

[0090] The first transistor includes a first active layer, and the first semiconductor pattern and the second semiconductor pattern each include a first active layer. Fig.11 In FIG. 1 , the first active layer in the first semiconductor pattern P1 is labeled as P1 - 7 , and the first active layer in the second semiconductor pattern P2 is labeled as P2 - 7 .

[0091] The first active layers in the first circuit column 21 and the second circuit column 22 are connected to each other. For example, in the semiconductor layer, the first active layer P1-7 and the first active layer P2-7 in the first circuit column 21 and the second circuit column 22 are connected to each other through semiconductor wiring, and the first active layer P1-7 and the first active layer P2-7 in the first circuit column 21 and the second circuit column 22 are an integrated structure.

[0092] For example, the first active layer P1-7 and the first active layer P2-7 in the first circuit column 21 and the second circuit column 22 are connected to a node N7, and can be connected to the same reset signal line Vref through a via at the node N7. In this way, the reset signal can be transmitted to different light-emitting elements through the same reset signal line, which can reduce the number of reset signal lines, thereby simplifying the layout structure, which is more conducive to achieving high resolution.

[0093] In some embodiments, please refer to Figure 5 and Fig.11, the pixel circuits of the display panel all include a second transistor M5 and a driving transistor M3, and the second transistor M5 is used to reset the gate of the driving transistor M3. Exemplarily, the first electrode of the second transistor M5 is connected to the reset signal line Vref, and the second electrode of the second transistor M5 is connected to the gate of the driving transistor M3. The first pixel circuit, the second pixel circuit, and the third pixel circuit all include a second transistor and a driving transistor, and the second transistor in each pixel circuit is used to reset the gate of the driving transistor in each pixel circuit.

[0094] The second transistor includes a second active layer. The first semiconductor pattern and the second semiconductor pattern each include a second active layer. Fig.11 In FIG. 1 , the second active layer in the first semiconductor pattern P1 is labeled as P1 - 5 , and the second active layer in the second semiconductor pattern P2 is labeled as P2 - 5 .

[0095] The second active layers in the third circuit column 23 and the fourth circuit column 24 are connected to each other. For example, in the semiconductor layer, the second active layers P1-5 and the second active layers P2-5 in the third circuit column 23 and the fourth circuit column 24 are connected to each other through semiconductor wiring, and the second active layers P1-5 and the second active layers P2-5 in the third circuit column 23 and the fourth circuit column 24 are an integrated structure.

[0096] For example, the second active layer P1-5 and the second active layer P2-5 in the third circuit column 23 and the fourth circuit column 24 are connected to a node N5, and can be connected to the same reset signal line Vref through a via at the node N5. In this way, the reset signal can be transmitted to the gates of different driving transistors through the same reset signal line, which can reduce the number of reset signal lines, thereby simplifying the layout structure, which is more conducive to achieving high resolution.

[0097] Exemplarily, in the pixel circuits in the same row, the node N7 and the node N5 may be connected to the same reset signal line Vref.

[0098] In some embodiments, please refer to Figure 5 and Fig.11 , the pixel circuits of the display panel all include a third transistor M1 and a driving transistor M3, and the third transistor M1 is used to provide a power signal PVDD to the driving transistor M3. The first electrode of the third transistor M1 is connected to a power signal line that transmits the power signal PVDD, and the second electrode of the third transistor M1 is connected to a first electrode of the driving transistor M3 (the first electrode of the driving transistor is, for example, a source electrode). The first pixel circuit, the second pixel circuit, and the third pixel circuit all include a third transistor and a driving transistor, and the third transistor in each pixel circuit is used to reset the driving transistor of each pixel circuit and provide a power signal.

[0099] The third transistor M1 includes a third active layer, and the first semiconductor pattern and the second semiconductor pattern each include a third active layer. Fig.11 In FIG. 1 , the third active layer in the first semiconductor pattern P1 is labeled as P1 - 1 , and the third active layer in the second semiconductor pattern P2 is labeled as P2 - 1 .

[0100] The third active layers in the third circuit column 23 and the fourth circuit column 24 are connected to each other. For example, in the semiconductor layer, the third active layer P1-1 and the third active layer P2-1 in the third circuit column 23 and the fourth circuit column 24 are connected to each other through semiconductor wiring, and the third active layer P1-1 and the third active layer P2-1 in the third circuit column 23 and the fourth circuit column 24 are an integrated structure.

[0101] For example, the third active layer P1-1 and the third active layer P2-1 in the third circuit column 23 and the fourth circuit column 24 are connected to the node N11, and can be connected to the same power signal line transmitting the power signal PVDD through a via at the node N11. In this way, the power signal can be transmitted to the gates of different driving transistors through the same power signal line, which can reduce the number of power signal lines, thereby simplifying the layout structure, which is more conducive to achieving high resolution.

[0102] It should be noted that the reset signal lines Vref of sub-pixels of different luminous colors may be independent, in which case the first active layers in the first circuit column 21 and the second circuit column 22 may be independent of each other. That is, in this case, the semiconductor layer is disconnected between the first active layer P1-7 and the first active layer P2-7 in the first circuit column 21 and the second circuit column 22, and the first active layer P1-7 and the first active layer P2-7 in the first circuit column 21 and the second circuit column 22 are independent structures.

[0103] In addition, the reset signal lines Vref of the sub-pixels of different luminous colors may be independent, in which case the second active layers in the third circuit column 23 and the fourth circuit column 24 may be independent of each other. That is, in the semiconductor layer, the second active layers P1-5 and the second active layers P2-5 in the third circuit column 23 and the fourth circuit column 24 are disconnected, and the second active layers P1-5 and the second active layers P2-5 in the third circuit column 23 and the fourth circuit column 24 are independent of each other.

[0104] And / or, the power signal PVDD connected to the sub-pixels of different luminous colors may be independent, in which case, the third active layers in the third circuit column 23 and the fourth circuit column 24 may be independent. That is, at the semiconductor layer, the third active layer P1-1 and the third active layer P2-1 in the third circuit column 23 and the fourth circuit column 24 are disconnected, and the third active layer P1-1 and the third active layer P2-1 in the third circuit column 23 and the fourth circuit column 24 are independent structures.

[0105] In some embodiments, please refer to Figures 7 to 10 In any one of the above, the second direction Y is the column direction, the layout structure of the first pixel circuits in the same column is the same, and in two adjacent columns of the first pixel circuits, the layout structure of the first pixel circuits in one column is the first pattern structure, and the layout structure of the first pixel circuits in the other column is the second pattern structure.

[0106] As an example, Figure 7 As shown, the first circuit column 21 and the third circuit column 23 include the first sub-pixel 11 and the second sub-pixel 12, and the second circuit column 22 and the fourth circuit column 24 include the third sub-pixel 13. It can be understood that the first circuit column 21 and the third circuit column 23 include the first pixel circuit and the second pixel circuit, and the second circuit column 22 and the fourth circuit column 24 include the third pixel circuit.

[0107] In the first circuit column 21 , the layout structures of the first pixel circuit and the second pixel circuit of the first sub-pixel 11 are both the first type pattern structure A.

[0108] In the second circuit column 22 , the layout structure of the third pixel circuits of the third sub-pixels 13 are all the second type pattern structure B.

[0109] In the third circuit row 23 , the layout structures of the first pixel circuit and the second pixel circuit of the first sub-pixel 11 are both the second type pattern structure B.

[0110] In the fourth circuit column 24 , the layout structures of the third pixel circuits of the third sub-pixels 13 are all the first type pattern structure A.

[0111] The first circuit column 21 and the third circuit column 23 are two adjacent columns of first pixel circuits. In the first circuit column 21 and the third circuit column 23, the first pixel circuit of the first circuit column 21 is a first type of pattern structure A, and the first pixel circuit of the third circuit column 23 is a second type of pattern structure B. In this way, the positions of the first pixel circuits of the two adjacent columns are relatively close, and the bright and dark effects of the sub-pixels to which they belong can be better offset.

[0112] In addition, the first circuit column 21 and the third circuit column 23 are two adjacent columns of second pixel circuits. In the first circuit column 21 and the third circuit column 23, the second pixel circuit of the first circuit column 21 is a first type of pattern structure A, and the second pixel circuit of the third circuit column 23 is a second type of pattern structure B. In this way, the positions of the second pixel circuits of the two adjacent columns are relatively close, and the bright and dark effects of the sub-pixels to which they belong can also be better offset.

[0113] For example, Fig.12 A schematic diagram of a layout structure of a gate metal layer in a display panel provided in an embodiment of the present application is shown. Figure 5 and Fig.12 , exemplarily, the first scan line S1, the second scan line S2, and the light emitting control signal line Emit are arranged in the gate metal layer. In addition, the gate g3 of the driving transistor and the first plate of the storage capacitor Cst are reused and arranged in the gate metal layer.

[0114] For example, Fig.13 A schematic diagram of a layout structure of a capacitor metal layer in a display panel provided by an embodiment of the present application is shown. Figure 5 and Fig.13 The reset signal line Vref and the second electrode plate c12 of the storage capacitor Cst are arranged on the capacitor metal layer. In addition, the capacitor metal layer may also be provided with other structures, such as a structure 31 for shading and / or shielding interference signals.

[0115] It should be noted that the layout structure shown in the drawings of the present application is merely an exemplary structure shown in the technical solution of the present application for the purpose of facilitating understanding, and the layout structure may include but is not limited to the layout structure shown in the drawings of the present application.

[0116] Based on the same inventive concept, the present application also provides a display device, including the display panel provided by the present application. Fig.14 , Fig.14 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.14 The provided display device 1000 includes a display panel 100 , and the display panel 100 includes the display panel provided by any of the above embodiments of the present application. Fig.14 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0117] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: Multiple first sub-pixels, each of which includes a first pixel circuit, a layout structure of a portion of the first pixel circuit is a first pattern structure, and a layout structure of another portion of the first pixel circuit is a second pattern structure, and the first pattern structure and the second pattern structure are mirror images of each other.

2. The display panel according to claim 1, characterized in that: The display panel further includes: A plurality of second sub-pixels, wherein the second sub-pixels include a second pixel circuit, a layout structure of a portion of the second pixel circuit is a third pattern structure, and a layout structure of another portion of the second pixel circuit is a fourth pattern structure, and the third pattern structure and the fourth pattern structure are mirror images of each other; A plurality of third sub-pixels, wherein the third sub-pixels include a third pixel circuit, a layout structure of a portion of the third pixel circuit is a fifth pattern structure, and a layout structure of another portion of the second pixel circuit is a sixth pattern structure, and the fifth pattern structure and the sixth pattern structure are mirror images of each other; The first sub-pixel, the second sub-pixel and the third sub-pixel emit different colors of light.

3. The display panel according to claim 2, characterized in that: The third pattern structure and the fifth pattern structure are the same as the first pattern structure, and the fourth pattern structure and the sixth pattern structure are the same as the second pattern structure.

4. The display panel according to claim 3, characterized in that: The display panel includes a plurality of circuit column groups arranged in a first direction, the circuit column groups include a first circuit column, a second circuit column, a third circuit column and a fourth circuit column sequentially arranged in the first direction, the first circuit column includes the first pixel circuits and the second pixel circuits alternately arranged in the second direction, the second circuit column includes a plurality of the third pixel circuits arranged in the second direction, the third circuit column includes the first pixel circuits and the second pixel circuits alternately arranged in the second direction, and the fourth circuit column includes a plurality of the third pixel circuits arranged in the second direction; The layout structure of the pixel circuits in the first circuit column is one of the first pattern structure and the second pattern structure, and the layout structure of the pixel circuits in the third circuit column is the other of the first pattern structure and the second pattern structure; The layout structure of the pixel circuits in the second circuit column is one of the first pattern structure and the second pattern structure, and the layout structure of the pixel circuits in the fourth circuit column is the other of the first pattern structure and the second pattern structure.

5. The display panel according to claim 4, characterized in that: The layout structure of the pixel circuits in the first circuit column is the first pattern structure, and the layout structure of the pixel circuits in the third circuit column is the second pattern structure; The layout structure of the pixel circuits in the second circuit column is the second pattern structure, and the layout structure of the pixel circuits in the fourth circuit column is the first pattern structure.

6. The display panel according to claim 5, characterized in that: The first pattern structure includes a first semiconductor pattern, and the second pattern structure includes a second semiconductor pattern; In the first direction, adjacent first semiconductor patterns and second semiconductor patterns are connected to each other. In the first direction, adjacent two first semiconductor patterns are disconnected from each other, and adjacent two second semiconductor patterns are disconnected from each other.

7. The display panel according to claim 6, characterized in that: The pixel circuits of the display panel each include a first transistor, and the first transistor is used to reset the light-emitting element of the display panel; The first transistor includes a first active layer, and the first semiconductor pattern and the second semiconductor pattern each include the first active layer; The first active layers in the first circuit column and the second circuit column are connected to each other.

8. The display panel according to claim 6, characterized in that: The pixel circuits of the display panel each include a second transistor and a driving transistor, wherein the second transistor is used to reset the gate of the driving transistor; The second transistor includes a second active layer; the first semiconductor pattern and the second semiconductor pattern each include the second active layer; The second active layers in the third circuit column and the fourth circuit column are connected to each other.

9. The display panel according to claim 6, characterized in that: The pixel circuits of the display panel each include a third transistor and a driving transistor, wherein the third transistor is used to provide a power signal to the driving transistor; The third transistor includes a third active layer, and the first semiconductor pattern and the second semiconductor pattern each include the third active layer; The third active layers in the third circuit column and the fourth circuit column are connected to each other.

10. The display panel according to claim 1, characterized in that: The layout structures of the first pixel circuits in the same column are the same. In two adjacent columns of the first pixel circuits, the layout structure of the first pixel circuits in one column is the first pattern structure, and the layout structure of the first pixel circuits in the other column is the second pattern structure.

11. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 10.

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