Display device

Abstract

A display device includes a substrate, a circuit layer, and an element layer. The element layer includes a light emitting element disposed in an emission region of the display region of the substrate and a light sensing element disposed in a light sensing region of the display region. The circuit layer includes a light emitting pixel driver electrically connected to the light emitting element, a light sensing pixel driver electrically connected to the light sensing element, a data line electrically connected to the light emitting pixel driver, a first dummy line extending in a first direction, a second dummy line extending parallel to the data line, and a reset control line, the reset control line is electrically connected to the light sensing pixel driver, extends in the first direction, transmits a reset control signal for resetting the light sensing pixel driver, and overlaps at least one of the first dummy lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0097137 filed in the Korean Intellectual Property Office on July 26, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As society becomes increasingly information-oriented, higher requirements are placed on display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0005] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro light-emitting display device including a micro light-emitting element.

[0006] Organic light-emitting display devices use light-emitting elements each including a light-emitting layer made of an organic light-emitting material to display images. As described above, organic light-emitting display devices use self-luminous elements to achieve image display, and therefore can have relatively excellent performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other display devices.

[0007] One surface of the display device may be a display surface including a display area in which an image is displayed and a non-display area as a periphery of the display area. Emission areas emitting light having corresponding brightness and color may be arranged in the display area. Summary of the invention

[0008] The display device may include a data supply line that is arranged in the non-display area and electrically connects the data line to the display driving circuit.

[0009] To overcome limitations in reducing the width of the non-display area due to arrangement of the data supply lines, the display device may further include a transmission bypass line arranged in the display area and electrically connecting some of the data supply lines to some of the data lines.

[0010] The transmission bypass line may include a first transmission bypass line extending in a first direction crossing the data line and a second transmission bypass line extending in parallel with the data line.

[0011] However, the first transmission bypass line in the first direction may be arranged adjacent to other lines extending in the first direction. As a result, there is a problem that the data signal of the first transmission bypass line may be easily distorted due to coupling with the variable voltage level of other lines arranged around the first transmission bypass line.

[0012] In view of the foregoing, aspects of the present disclosure provide a display device capable of reducing distortion of a data signal of a first transmission bypass line.

[0013] According to one aspect of the present disclosure, a display device is provided, the display device including a substrate, a circuit layer arranged on the substrate, and an element layer arranged on the circuit layer. The substrate includes a display area in which an emission area is arranged and a non-display area arranged around the display area. The display area includes a non-emission area between the emission areas and a light sensing area arranged in the non-emission area. The element layer includes a light emitting element arranged in the emission area and a light sensing element respectively arranged in the light sensing area. The circuit layer includes a light emitting pixel driver, a light sensing pixel driver, a data line, a first dummy line, a second dummy line and a reset control line, the light emitting pixel driver is electrically connected to the light emitting element, the light sensing pixel driver is electrically connected to the light sensing element, the data line is electrically connected to the light emitting pixel driver, the first dummy line extends in a first direction intersecting the data line, the second dummy line extends parallel to the data line, each of the second dummy lines is paired with one of the data lines, the reset control line is electrically connected to the light sensing pixel driver, the reset control line extends in the first direction, the reset control line transmits a reset control signal for resetting the light sensing pixel driver and overlaps with at least one of the first dummy lines.

[0014] The display device may further include a display driving circuit that outputs a data signal to the data line. The circuit layer may further include a data supply line arranged in the non-display area and electrically connected between the data line and the display driving circuit. The bypass area on one side of the display area may include a bypass middle area at the center of the bypass area, a first bypass side area between the bypass middle area and the non-display area, and a second bypass side area arranged between the bypass middle area and the first bypass side area. The data line may include a first data line arranged in the first bypass side area and a second data line arranged in the second bypass side area. The first dummy line may include a first transmission bypass line electrically connected to the first data line. The second dummy line may include a second transmission bypass line that is paired with the second data line and electrically connected to the first transmission bypass line. Among the data supply lines, the first data supply line that transmits the data signal to the first data line may be electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line. Among the data supply lines, the second data supply line that transmits the data signal to the second data line may be directly electrically connected to the second data line. Among the first dummy lines, the first transmission bypass line may overlap with the reset control line.

[0015] The circuit layer may also include a first power supply line and a second power supply line arranged in the non-display area and transmitting a first power supply and a second power supply for driving the light-emitting element, respectively, and a first power supply line electrically connected between the light-emitting pixel driver and the first power supply line. One of the light-emitting elements may be electrically connected between one of the light-emitting pixel drivers and a second power supply line for transmitting the second power supply and electrically connected to the second power supply line. One light-emitting pixel driver may include a first transistor for generating a driving current for driving one light-emitting element, a second transistor electrically connected between one of the data lines and the first electrode of the first transistor, a third transistor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor, a fourth transistor electrically connected between the first initialization power line for transmitting the first initialization power and the gate electrode of the first transistor, a fifth transistor electrically connected between the first power line and the first electrode of the first transistor, a sixth transistor electrically connected between the second electrode of the first transistor and one light-emitting element, a seventh transistor electrically connected between the second initialization power line for transmitting the second initialization power and one light-emitting element, and an eighth transistor electrically connected between the bias power line for transmitting the bias power and the first electrode of the first transistor.

[0016] The circuit layer may further include a readout line electrically connected to the light sensing pixel driver. One of the light sensing elements may be electrically connected between an element output node of one of the light sensing pixel drivers and a second power supply line. One light sensing pixel driver may include a ninth transistor configured to be turned on in response to a voltage level of the element output node, a tenth transistor electrically connected between a reset voltage line for transmitting a reset voltage and the element output node and configured to be turned on in response to a reset control signal of a reset control line, and an eleventh transistor electrically connected between the readout line and the ninth transistor.

[0017] The second transistor and the eleventh transistor may be turned on in response to a scan write signal of the scan write line. The scan write signal may be transmitted to the light emitting pixel driver and the light sensing pixel driver during each image frame period. A blanking period in which a voltage level of the scan write line is maintained at an off level is arranged between consecutive image frame periods. The voltage level of the reset control line may vary during the blanking period.

[0018] A reset control signal of the reset control line may be transmitted to the light-sensing pixel driver during the blanking period.

[0019] The voltage level of the reset control line may change in a first form during a first blanking period, and change in a second form opposite to the first form during a second blanking period after the first blanking period. At least one image frame period may be arranged between the first blanking period and the second blanking period.

[0020] The third transistor may be turned on in response to a gate control signal of a gate control line. The fourth transistor may be turned on in response to a scan initialization signal of a scan initialization line. The gate control signal and the scan initialization signal may be transmitted to the light emitting pixel driver during each image frame period.

[0021] The reset control line may include an extending portion extending in the first direction, and a protrusion branched from the extending portion and overlapping with a channel portion of the tenth transistor.

[0022] The protrusion may form a loop with the extension portion having two connection points.

[0023] The first dummy line may further include a first auxiliary line electrically connected to the second power supply line. The second dummy line may further include a second auxiliary line electrically connected to the first auxiliary line and the second power supply line.

[0024] Two of the first auxiliary lines may extend from both sides of the first transmission bypass line to the non-display area. One of the second auxiliary lines may extend from one side of the second transmission bypass line to the non-display area.

[0025] According to one aspect of the present disclosure, a display device is provided, the display device including a substrate, a circuit layer arranged on the substrate, and an element layer arranged on the circuit layer. The substrate includes a display area in which emission areas are arranged and a non-display area arranged around the display area. The display area includes a non-emission area between the emission areas and a light sensing area arranged in the non-emission area. The element layer includes a light emitting element arranged in the emission area and light sensing elements respectively arranged in the light sensing area. The bypass area on one side of the display area includes a bypass middle area at the center of the bypass area, a first bypass side area between the bypass middle area and the non-display area, and a second bypass side area arranged between the bypass middle area and the first bypass side area. The circuit layer includes a light-emitting pixel driver, a light-sensing pixel driver, a data line, a first transmission bypass line, a second transmission bypass line and a reset control line. The light-emitting pixel drivers are respectively electrically connected to the light-emitting elements, the light-sensing pixel drivers are respectively electrically connected to the light-sensing elements, the data line is electrically connected to the light-emitting pixel driver, the first transmission bypass line extends in a first direction crossing the data line and is electrically connected to a first data line arranged in a first bypass side region among the data lines, the second transmission bypass line extends in parallel with the data line, the second transmission bypass line is paired with a second data line arranged in a second bypass side region among the data lines and is electrically connected to the first transmission bypass line, and the reset control line is electrically connected to the light-sensing pixel driver, the reset control line extends in the first direction, the reset control line transmits a reset control signal for resetting an element output node of each of the light-sensing pixel drivers and overlaps with the first transmission bypass line.

[0026] The display device may further include a display driving circuit that outputs a data signal to the data line. The circuit layer may further include a data supply line arranged in the non-display area and electrically connected between the data line and the display driving circuit. Among the data supply lines, a first data supply line that transmits a data signal to a first data line is electrically connected to the first data line through a first transmission bypass line and a second transmission bypass line. Among the data supply lines, a second data supply line that transmits a data signal to a second data line is directly electrically connected to the second data line.

[0027] The circuit layer may also include a readout line electrically connected to the light sensing pixel driver. One of the light emitting elements may be electrically connected between one of the light emitting pixel drivers and a second power line for transmitting a second power supply. One of the light sensing elements may be electrically connected between an element output node of one of the light sensing pixel drivers and the second power line. A light emitting pixel driver may include a first transistor for generating a driving current for driving a light emitting element, a second transistor electrically connected between one of the data lines and a first electrode of the first transistor, a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor, a fourth transistor electrically connected between a first initialization power line for transmitting a first initialization power supply and a gate electrode of the first transistor, a fifth transistor electrically connected between a first power line for transmitting a first power supply and a first electrode of the first transistor, a sixth transistor electrically connected between the second electrode of the first transistor and a light emitting element, a seventh transistor electrically connected between a second initialization power line for transmitting a second initialization power supply and a light emitting element, and an eighth transistor electrically connected between a bias power line for transmitting a bias power supply and a first electrode of the first transistor. A light-sensing pixel driver may include a ninth transistor configured to be turned on in response to a voltage level of an element output node, a tenth transistor electrically connected between a reset voltage line for transmitting a reset voltage and the element output node and configured to be turned on in response to a reset control signal of a reset control line, and an eleventh transistor electrically connected between a readout line and the ninth transistor.

[0028] The second transistor and the eleventh transistor may be turned on in response to a scan write signal of the scan write line. The scan write signal is transmitted to the light emitting pixel driver and the light sensing pixel driver during each image frame period. A blanking period in which the voltage level of the scan write line is maintained at an off level may be arranged between consecutive image frame periods. The voltage level of the reset control line may vary during the blanking period.

[0029] The voltage level of the reset control line may change in a first form during a first blanking period, and change in a second form opposite to the first form during a second blanking period after the first blanking period. At least one image frame period is arranged between the first blanking period and the second blanking period.

[0030] The reset control line may include an extending portion extending in the first direction, and a protrusion branched from the extending portion and overlapping with a channel portion of the tenth transistor.

[0031] The protrusion may form a loop with the extension portion having two connection points.

[0032] The display device according to the embodiment includes a substrate, a circuit layer arranged on the substrate, and an element layer arranged on the circuit layer. The substrate includes a display area in which an emission area is arranged and a non-display area arranged around the display area. The display area includes a non-emission area as a separation area between the emission areas and a light sensing area arranged in a portion of the non-emission area.

[0033] The element layer includes light emitting elements respectively arranged in the emission regions and light sensing elements respectively arranged in the light sensing regions.

[0034] The circuit layer includes a light-emitting pixel driver, a light-sensing pixel driver, a data line, a first dummy line, a second dummy line and a reset control line. The light-emitting pixel drivers are electrically connected to the light-emitting elements, the light-sensing pixel drivers are electrically connected to the light-sensing elements, the data lines are electrically connected to the light-emitting pixel drivers, the first dummy lines extend in a first direction crossing the data lines, the second dummy lines extend parallel to the data lines and are paired with the data lines, respectively, and the reset control lines are electrically connected to the light-sensing pixel drivers. The reset control lines extend in the first direction and transmit a reset control signal for resetting the light-sensing pixel drivers.

[0035] The bypass area on one side of the display area includes a bypass middle area at the center, a first bypass side area parallel to the bypass middle area in a first direction and in contact with the non-display area, and a second bypass side area arranged between the bypass middle area and the first bypass side area.

[0036] The data lines include a first data line arranged in a first bypass side region and a second data line arranged in a second bypass side region.

[0037] The first dummy line includes a first transmission bypass line electrically connected to the first data line.

[0038] The second dummy line includes a second transmission bypass line paired with the second data line and electrically connected to the first transmission bypass line.

[0039] The first transmission bypass line overlaps the reset control line.

[0040] In addition, according to an embodiment, the voltage level of the reset control line may vary during a blanking period between consecutive image frame periods. That is, a reset control signal of the reset control line may be output during at least one blanking period.

[0041] For example, a reset control signal of the reset control line may be output during one blanking period. In this case, a voltage level of the reset control line may be maintained at an off level during each image frame period.

[0042] Alternatively, a reset control signal of the reset control line may be output during two or more blanking periods arranged before and after at least one image frame period. In this case, a voltage level of the reset control line may be maintained at an on-level of the reset control signal during at least one image frame period arranged between the two or more blanking periods, and a voltage level of the reset control line may be maintained at an off-level during other image frame periods except for at least one image frame period arranged between the two or more blanking periods.

[0043] Thus, according to an embodiment, a voltage level of a reset control line transmitting a reset control signal for resetting the light-sensing pixel driver during each image frame period may not vary but be maintained at a constant voltage. In addition, the first transmission bypass line overlaps the reset control line.

[0044] Accordingly, although a constant voltage line for stably maintaining the data signal of the first transmission bypass line is not separately arranged, the data signal of the first transmission bypass line overlapping the reset control line can be relatively stably maintained because the reset control line is maintained at a constant voltage during each image frame period. Accordingly, the distortion of the data signal can be reduced without adding a separate constant voltage line to reduce the coupling distortion of the first transmission bypass line.

[0045] In addition, since the spot defect caused by the distortion of the data signal of the first transmission bypass line can be reduced, the display quality of the display device can be improved.

[0046] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0048] Figure 1 is a perspective view showing a display device according to an embodiment;

[0049] Figure 2 It is shown Figure 1 A plan view of a display device;

[0050] Figure 3 is along Figure 2 A cross-sectional view taken along line A-A';

[0051] Figure 4It is shown Figure 2 a layout diagram of part B;

[0052] Figure 5 It is shown Figure 4 A diagram of the scanning function of the light sensing area shown in FIG.

[0053] Figure 6 It is shown Figure 3 The block diagram of the circuit layer;

[0054] Figure 7 yes Figure 6 An equivalent circuit diagram of a light emitting pixel driver and a light sensing pixel driver;

[0055] Figure 8 It is shown Figure 7 A cross-sectional view of a light emitting element, a first transistor, a second transistor, a fourth transistor and a sixth transistor;

[0056] Fig. 9 It is shown Figure 2 A plan view of a main region and a sub-region of a substrate;

[0057] Fig.10 It is shown Fig. 9 a layout diagram of part C;

[0058] Fig.11 It is shown that the arrangement Fig.10 A layout diagram of the lines in section D;

[0059] Fig.12 It is shown Fig.11 A layout diagram of lines extending in a first direction;

[0060] Fig.13 is along Fig.10 A cross-sectional view taken along line E-E';

[0061] Fig.14 and Fig.15 is a diagram showing a method according to an embodiment Figure 7 A waveform diagram of the voltage level of each of the scan initialization line, the gate control line, the scan write line and the reset control line;

[0062] Fig.16 and Fig.17 is a plan view showing a reset control line, a first dummy line, and a tenth transistor according to one embodiment; and

[0063] Fig.18 is along Fig.17 A cross-sectional view taken along line F-F'. DETAILED DESCRIPTION

[0064] Now, the embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. However, these embodiments can be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals indicate the same parts. In the accompanying drawings, for clarity, the thickness of the layers and regions may be magnified.

[0065] For describing the embodiments of the present disclosure, some of parts that are not associated with the description may not be provided.

[0066] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0067] Coordinates are provided in the figure. The phrase "in a plan view" means observing the object portion from the top on the third direction DR3 as will be explained below. The phrase "in a schematic cross-sectional view" means observing the object portion from the side, as if the product is cut in a plane partially defined by the third direction DR3. The term "overlap" or "overlapping" means that the first object may be located above or below the second object. Additionally, the term "overlap" may include stacking, stacking, facing or facing, extending on ..., covering or partially covering or any other suitable term understood and understood by a person of ordinary skill in the art. The statement "non-overlapping" may include the meaning of any other suitable corresponding words such as "separated from ... "or "keeping a distance from ... "or "offset from ... "and understood and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although still facing each other, the first object and the second object may be understood to be indirectly opposite to each other.

[0068] Spatially relative terms "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It should be understood that in addition to the orientations depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, in the case where the device shown in the accompanying drawings is turned over, a device located "below" or "below" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0069] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element via one or more intervening elements. It should also be understood that when the terms “comprise,” “comprising,” “has,” “have,” “having,” “include,” and / or “including,” are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0070] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or for the convenience of its description and explanation. For example, when discussing a "first element" in the description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0071] The terms "about" or "approximately" as used herein include the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0072] For the purpose of its meaning and interpretation, in the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or". For the purpose of its meaning and interpretation, in the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0073] Unless otherwise defined or implied, the terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly rigid sense unless explicitly defined in the specification.

[0074] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0075] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 A plan view of a display device. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'. Figure 4 It is shown Figure 2 Layout diagram of part B.

[0076] Reference Figure 1 and Figure 2 The display device 100 is a device for displaying moving images or still images. The display device 100 can be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0077] The display device 100 may be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micro or nano light-emitting diode (LED). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, the present disclosure is not limited thereto, and may be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

[0078] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include a bent portion formed at the left and right ends and having a constant curvature or a variable curvature. In addition, the display device 100 may be formed to be flexible so that it can be bent, curved, folded, or rolled.

[0079] like Figure 1 , Figure 2 and Figure 3 As shown in , the display device 100 includes a substrate 110 .

[0080] The substrate 110 may include a main area MA corresponding to a display surface of the display device 100 and a sub area SBA protruding from one side of the main area MA.

[0081] like Figure 2 As shown in , the main area MA may include a display area DA arranged to occupy most of a surface including the center of the display area DA, and a non-display area NDA arranged around the display area DA.

[0082] In a plan view, the display area DA may be formed in a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 crossing the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be rounded to have a predetermined curvature or may be a right angle. The planar shape of the display area DA is not limited to a rectangular shape and may be formed in other polygonal shapes, a circular shape, or an elliptical shape.

[0083] The non-display area NDA may be arranged at an edge of the main area MA to surround the display area DA.

[0084] The sub-area SBA may be an area protruding from the non-display area NDA of the main area MA to one side in the second direction DR2.

[0085] Since a portion of the sub-area SBA is deformed to be curved, another portion of the sub-area SBA may be disposed on the rear surface of the display device 100 .

[0086] Figure 2 and Figure 3 The display device 100 is shown with a portion of the sub-area SBA in a bent state.

[0087] Reference Figure 3 , the display device 100 according to the embodiment includes a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and an element layer 130 disposed on the circuit layer 120 .

[0088] The display device 100 according to the embodiment may further include an encapsulation layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the encapsulation layer 140 .

[0089] In addition, the display device 100 according to the embodiment may further include a polarizing layer 160 disposed on the touch sensor layer 150 to reduce reflection of external light.

[0090] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled.

[0091] Alternatively, the substrate 110 may be formed of an insulating material such as glass.

[0092] The substrate 110 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NDA.

[0093] Reference Figure 4 , the display area DA includes the emission areas EA, the non-emission areas NEA as regions between the emission areas EA, and the light sensing areas ODA arranged in portions of the non-emission areas NEA.

[0094] Each of the emission areas EA may be a unit that emits light having brightness corresponding to an image signal in a wavelength band corresponding to one of two or more different colors.

[0095] Each of the emission areas EA may have a rhombus planar shape or a rectangular planar shape. However, this is only an example, and the planar shapes of the plurality of emission areas EA according to one embodiment are not limited to Figure 4 That is, the plurality of emission areas EA may have a polygonal shape such as a hexagonal shape, a circular shape, or an elliptical shape in addition to the diamond shape or the rectangular shape in a plan view.

[0096] The emission area EA may include a first emission area EA1 that emits light of a first color having a predetermined wavelength band, a second emission area EA2 that emits light of a second color having a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color having a wavelength band lower than the wavelength band of the second color.

[0097] For example, the first color may be red having a wavelength band of about 600 nm to about 750 nm, the second color may be green having a wavelength band of about 480 nm to about 560 nm, and the third color may be blue having a wavelength band of about 370 nm to about 460 nm. However, this is only an example, and the wavelength bands of the first color, the second color, and the third color according to one embodiment of the present specification are not limited thereto.

[0098] Since the emission area EA includes a first emission area EA1, a second emission area EA2 and a third emission area EA3, each of the unit pixels UPX can be provided by a combination of one or more first emission areas EA1, one or more second emission areas EA2 and one or more third emission areas EA3 adjacent to each other in the emission area EA.

[0099] Each of the unit pixels UPX may be a unit for displaying various colors including white. That is, various colors of light displayed by the unit pixel UPX may be realized as a mixture of light emitted from two or more emission areas EA included in each unit pixel UPX.

[0100] In the case where the first color of the first emission area EA1, the second color of the second emission area EA2, and the third color of the third emission area EA3 are red, green, and blue, respectively, the third emission area EA3 may be larger than the first emission area EA1, and the second emission area EA2 may be smaller than the first emission area EA1. Figure 4 In the embodiment of the present invention, the third emission area EA3 has the longest size in the second direction DR2, and the second emission area EA2 has the shortest size in the second direction DR2. However, this is only an example, and the size of each of the emission areas EA is not limited to Figure 4 Sizes shown in .

[0101] In addition, the first emission area EA1 and the third emission area EA3 may be alternately arranged in the first direction DR1 or the second direction DR2. In addition, the second emission area EA2 may be arranged side by side in the first direction DR1 or the second direction DR2. The second emission area EA2 may be arranged between the first emission area EA1 and the third emission area EA3 in the first direction DR1 or in a fifth direction between the first direction DR1 and the second direction DR2.

[0102] In this case, each of the unit pixels UPX may include one first emission area EA1 and one third emission area EA3 adjacent to each other in the first direction DR1 or the second direction DR2, and two second emission areas EA2 adjacent to them in the second direction DR2 or the first direction DR1. However, this is only an example, and the arrangement pattern of the emission areas EA and the components of the unit pixels UPX according to one embodiment are not limited to Figure 4 Those shown in .

[0103] According to one embodiment, the display area DA includes a light sensing area ODA disposed in a portion of the non-emission area NEA.

[0104] For example, the light sensing area ODA may be arranged between the second emission areas EA2 having a relatively small length in the second direction DR2. One or more emission areas EA may be arranged between the light sensing areas ODA in each of the first direction DR1 and the second direction DR2.

[0105] Reference Figure 5 The element layer 130 includes light emitting elements LE respectively arranged in the emission areas EA (see Figure 7) and light sensing elements PD respectively arranged in the light sensing area ODA (see Figure 7 ).

[0106] According to an embodiment, the circuit layer 120 includes light emitting pixel drivers EPD (see FIG. 1 ) electrically connected to the light emitting elements LE of the element layer 130, respectively. Figure 6 ), respectively electrically connected to the light sensing element PD of the element layer 130 of the light sensing pixel driver DPD (see Figure 6 ), and a data line DL electrically connected to the light-emitting pixel driver EPD (see Figure 6 The circuit layer 120 may further include a readout line ROL electrically connected to the light sensing pixel driver DPD (see Figure 6 ).

[0107] The encapsulation layer 140 may cover the element layer 130 and extend into the non-display area NDA to contact the circuit layer 120. The encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked.

[0108] Reference Figure 3 , the touch sensor layer 150 may be disposed on the encapsulation layer 140 in the main area MA. The touch sensor layer 150 may include a touch electrode for sensing a touch of a person or an object.

[0109] The polarizing layer 160 blocks external light reflected from the touch sensor layer 150 , the encapsulation layer 140 , the element layer 130 , and the circuit layer 120 , and interfaces thereof, and this is to prevent degradation of visibility of an image due to external light reflection.

[0110] The display driving circuit 200 may be mounted on the sub-area SBA of the substrate 110 , and the display circuit board 300 may be attached to the sub-area SBA of the substrate 110 .

[0111] The display driving circuit 200 may be electrically connected to the data line DL of the circuit layer 120 (see Figure 6 The display driving circuit 200 may output a data signal based on a control signal and a power supply voltage supplied from the display circuit board 300 .

[0112] The display driving circuit 200 may be provided as an integrated circuit (IC) and mounted on the sub-area SBA of the display device 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic method. However, this is only an example, and one embodiment is not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0113] One end of the display circuit board 300 may be attached to a pad disposed on one edge of the sub-area SBA of the display device 100 by using an anisotropic conductive film.

[0114] The display circuit board 300 may be a bendable flexible printed circuit board (FPCB), a rigid printed circuit board (PCB) maintaining a flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0115] The touch driving circuit 400 and the scan driving circuit 500 may be mounted on the display circuit board 300 .

[0116] The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 of the display device 100 .

[0117] The touch drive circuit 400 can determine whether the user has touched the display area DA or otherwise transmit input by applying a touch drive signal to the drive line of the touch sensor layer 150 and detecting a change in capacitance based on the touch sensing signal received from the sensing line. In one embodiment, the user's "touch" means that an object such as a pen or a user's finger is in direct contact with the top surface of the cover window arranged on the touch sensor layer. In addition to "touch", the user can also transmit input through "approach", which is intended to mean that an object such as a pen or a user's finger hovers above the top surface of the cover window without direct contact. For simplicity, "touch" will be used in this disclosure to indicate user input, and it should be understood that the inventive concept can be adapted to other types of user input. The touch drive circuit 400 can output touch data including the user's touch coordinates to the main processor.

[0118] The scan driving circuit 500 may be electrically connected to the readout line ROL of the circuit layer 120 (see Figure 6 ).

[0119] The scanning driving circuit 500 can be driven by a light sensing pixel driver DPD (see Figure 6 ) and the readout line ROL periodically from the light sensing area ODA (see Figure 4 ) in the light sensing element PD (see Figure 7 ) receives the light sensing signal. In addition, based on the collected light sensing signal, the scan driving circuit 500 can output scan data about the shape of the object in contact with the screen to the main processor by detecting the difference in the amount of light reflected by the object in contact with the screen.

[0120] Figure 5 It is shown Figure 4 The scanning function of the light sensing area is shown in the diagram.

[0121] Reference Figure 5 , the display device 100 may further include a cover window CVW disposed above the encapsulation layer 140 .

[0122] For example, the cover window CVW may be attached to the polarizing layer 160 (see FIG. 1 ) by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). Figure 3 ).

[0123] The cover window CVW may be made of an inorganic material such as glass or an organic material such as plastic or polymer material.

[0124] Due to the cover window CVW, the touch sensor layer 150 can be protected (see Figure 3 ), packaging layer 140, component layer 130 and circuit layer 120 (see Figure 3 ) from electrical and physical shocks on the display surface.

[0125] The display device 100 according to the embodiment may include a light sensing element PD arranged in the light sensing area ODA (see Figure 7 ), and thus can provide a scanning function to detect the shape of an object in contact with the screen.

[0126] The fingerprint of the user's finger FG in contact with the cover window CVW includes ridges RID and valleys VAL located between the ridges RID. The ridges RID in the fingerprint are in contact with the cover window CVW. However, the valleys VAL in the fingerprint are spaced apart from the cover window CVW. That is, the top surface of the cover window CVW below the valleys VAL is in contact with the air.

[0127] The light emitted from the emission area EA may be reflected by the user's finger FG in contact with the cover window CVW and detected by the light sensing element PD of the light sensing area ODA. However, since the refractive index of the finger FG is different from that of air, the amount of light reflected from the ridge RID may be different from the amount of light reflected from the valley VAL.

[0128] Accordingly, based on the difference in the amount of light incident on the light sensing element PD, the positions and shapes of the ridges RID and valleys VAL of the fingerprint can be determined, thereby allowing the fingerprint pattern of the finger FG to be read.

[0129] Figure 6 It is shown Figure 3 Block diagram of the circuit layer.

[0130] Reference Figure 6 , the circuit layer 120 of the display device 100 according to the embodiment (see Figure 3 ) may include light-emitting pixel drivers EPD corresponding to emission areas EA of the display area DA, light-sensing pixel drivers DPD corresponding to light-sensing areas ODA of the display area DA, data lines DL electrically connected to the light-emitting pixel drivers EPD, and readout lines ROL electrically connected to the light-sensing pixel drivers DPD.

[0131] The display device 100 according to the embodiment may include outputting a data signal Vdata (see FIG. 1 ) to each of the light emitting pixel drivers EPD. Figure 7 ), a display driving circuit 200 for collecting light sensing signals of a light sensing pixel driver DPD, a scanning driving circuit 500 for supplying one or more gate signals to a light emitting pixel driver EPD and a light sensing pixel driver DPD, a gate driving circuit 101 for transmitting an emission control signal EC (see Figure 7 ) is supplied to the emission control circuit 102 of the light-emitting pixel driver EPD, a power supply unit 700 that supplies various power supplies and voltages to the light-emitting pixel driver EPD and the light-sensing pixel driver DPD, and a timing controller 800 that controls the driving timing.

[0132] The timing controller 800 receives an image signal supplied from the outside of the display device 100. The timing controller 800 may output the image data DATA and the data control signal DCS to the display driving circuit 200. In addition, the timing controller 800 may generate a scan control signal SCS for controlling the operation timing of the gate driving circuit 101, and an emission control driving signal ECS for controlling the operation timing of the emission control circuit 102. For example, the timing controller 800 may generate the scan control signal SCS and the emission control driving signal ECS, output the scan control signal SCS to the gate driving circuit 101 through the scan control line, and output the emission control driving signal ECS to the emission control circuit 102 through the emission control driving line.

[0133] The display driving circuit 200 may convert the image data DATA into analog data voltages and output them to the data lines DL.

[0134] The gate driving circuit 101 may generate a gate signal in response to the scan control signal SCS and sequentially output the gate signal to the gate lines GL. The gate lines GL may include a gate line for transmitting a scan write signal GW (see Figure 7 ) of the scan write line GWL (see Figure 7 ), used to transmit the scan initialization signal GI (see Figure 7 ) of the scan initialization line GIL (see Figure 7 ), used to transmit the gate control signal GC (see Figure 7 ) of the gate control line GCL (see Figure 7 ), used to transmit the bias control signal GB (see Figure 7 ) of the bias control line GBL (see Figure 7 ), and for transmitting a reset control signal GR (see Figure 7 ) of the reset control line GRL (see Figure 7 ).like Figure 7As drawn in , the reset control line GRL is electrically connected to the light sensing pixel driver DPD.

[0135] The emission control circuit 102 may respond to the emission control driving signal ECS by converting the emission control signal EC (see Figure 7 ) are sequentially output to the emission control line ECL. The emission control signal EC of the emission control circuit 102 may have a pulse of a first level voltage or a second level voltage. In some embodiments, the emission control circuit 102 may not be provided separately from the gate driving circuit 101, but may be incorporated into the gate driving circuit 101.

[0136] The power supply unit 700 may supply various types of power required to drive the light emitting pixel driver EPD and the light sensing pixel driver DPD.

[0137] For example, the power provided by the power supply unit 700 may include a power source for driving the light emitting element LE (see Figure 7 ) of the first power supply ELVDD (see Figure 7 ) and the second power supply ELVSS (see Figure 7 ), and a first initialization power source VINT (see Figure 7 ) and the second initialization power VAINT (see Figure 7 ).

[0138] In addition, the power provided by the power supply unit 700 may further include a reset voltage VRST (see Figure 7 ).

[0139] The scanning driving circuit 500 can be electrically connected to the light sensing element PD through the readout line ROL and the light sensing pixel driver DPD (see Figure 7 ).

[0140] Each of the light sensing elements PD may generate a photocurrent corresponding to the amount of light incident on the light sensing element PD, and the scan driving circuit 500 may read the fingerprint of the user based on the photocurrent of each of the light sensing elements PD.

[0141] The scan driving circuit 500 may generate scan data according to the magnitude of the photocurrent detected by the photo sensing element PD and transmit it to the main processor, and the main processor may compare the scan data with the reference data and execute an application based on whether the scan data matches the user's fingerprint.

[0142] Figure 7 yes Figure 6 Equivalent circuit diagram of the light-emitting pixel driver and the light-sensing pixel driver.

[0143] Reference Figure 7, component layer 130 (see Figure 3 ) can be electrically connected to the circuit layer 120 (see Figure 3 ) between one of the light-emitting pixel drivers EPD and a second power line VSL for transmitting the second power ELVSS.

[0144] The anode 131 of the light emitting element LE (see Figure 8 ) can be electrically connected to the light emitting pixel driver EPD, and the cathode 134 of the light emitting element LE (see Figure 8 ) may be applied with a second power source ELVSS having a voltage level lower than that of the first power source ELVDD.

[0145] The capacitor Cel connected in parallel with the light emitting element LE indicates a parasitic capacitance between the anode 131 and the cathode 134 .

[0146] The circuit layer 120 may further include a first power line VDL for transmitting a first power ELVDD, a first initialization power line VIL for transmitting a first initialization power VINT, a second initialization power line VAIL for transmitting a second initialization power VAINT, and a bias power line VBL for transmitting a bias power VBS.

[0147] The circuit layer 120 may also include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0148] One light emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving the light emitting element LE, two or more transistors T2 to T8 electrically connected to the first transistor T1 , and at least one capacitor PC1 .

[0149] The first transistor T1 and the light emitting element LE are connected in series between the first power source ELVDD and the second power source ELVSS.

[0150] That is, the first electrode (eg, source electrode) of the first transistor T1 may be electrically connected to the first power line VDL through the fifth transistor T5. In addition, the second electrode (eg, drain electrode) of the first transistor T1 may be electrically connected to the anode 131 of the light emitting element LE through the sixth transistor T6.

[0151] The first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0152] The gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first capacitor PC1. That is, the first capacitor PC1 may be electrically connected between the gate electrode of the first transistor T1 and the first power line VDL.

[0153] Accordingly, the potential of the gate electrode of the first transistor T1 may be maintained by the first power source ELVDD of the first power source line VDL.

[0154] In addition, when the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, a voltage difference corresponding to the data signal Vdata and the first power source ELVDD may be generated between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1.

[0155] In this case, when a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (i.e., a gate-to-source voltage difference) becomes equal to or greater than a threshold voltage, the first transistor T1 may be turned on, thereby generating a source-to-drain current of the first transistor T1 corresponding to the data signal Vdata.

[0156] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Accordingly, the source-to-drain current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0157] Accordingly, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0158] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by a scan write signal GW of the scan write line GWL.

[0159] The third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by a gate control signal GC of the gate control line GCL.

[0160] The fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the first initialization power line VIL. The fourth transistor T4 may be turned on by a scan initialization signal GI of the scan initialization line GIL.

[0161] The third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs.

[0162] The fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0163] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode 131 of the light emitting element LE.

[0164] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0165] The seventh transistor T7 may be electrically connected between the anode of the light emitting element LE and the second initialization power line VAIL. The seventh transistor T7 may be turned on by a bias control signal GB of a bias control line GBL.

[0166] The eighth transistor T8 may be connected between the first electrode of the first transistor T1 and the bias power line VBL.

[0167] The eighth transistor T8 may be turned on by a bias control signal GB of a bias control line GBL.

[0168] Among the first to eighth transistors T1 to T8 , the transistors T1 , T2 , and T5 to T8 excluding the third and fourth transistors T3 and T4 may be provided as P-type MOSFETs.

[0169] In addition, one of the light sensing elements PD of the element layer 130 may be electrically connected between the element output node NOP of one of the light sensing pixel drivers DPD of the circuit layer 120 and the second power source ELVSS.

[0170] The circuit layer 120 may further include a reset control line GRL for transmitting a reset control signal GR for starting the reset of the light sensing pixel driver DPD, a reset voltage line VRL for transmitting a reset voltage VRST for resetting the light sensing pixel driver DPD, and a reset line VRL for electrically connecting the light sensing pixel driver DPD to the scan driving circuit 500 (see Figure 6 )’s readout line ROL.

[0171] Each of the light-sensing pixel drivers DPD may include at least one transistor T9 , T10 , T11 .

[0172] The light sensing element PD may be a photoelectric conversion element that converts incident light into an electrical signal by generating a photocurrent corresponding to the amount of incident light and outputs a light sensing signal.

[0173] The light sensing element PD may be a photodiode including a sensing anode, a sensing cathode, and a photoelectric conversion layer disposed between the sensing anode and the sensing cathode.

[0174] The light sensing element PD may be a phototransistor or an inorganic photodiode formed of a pn-type or pin-type inorganic material. Alternatively, the light sensing element PD may also be an organic photodiode including an electron donating material that generates donor ions and an electron accepting material that generates acceptor ions.

[0175] When light is incident on the light sensing element PD, the photoelectric conversion layer may react to the incident light to generate photocharges, and the photocharges generated in the photoelectric conversion layer may move, thereby generating a photocurrent between a sensing anode and a sensing cathode.

[0176] As an example, photocharges generated in the photoelectric conversion layer by light incident on the photo sensing element PD may be accumulated in the sensing anode. In addition, the potential of the element output node NOP electrically connected to the sensing anode may be raised by the photocharges accumulated in the sensing anode. When the readout line ROL is connected to the element output node NOP by the conduction of the ninth transistor T9 and the eleventh transistor T11, the sensing voltage may be accumulated at the third node N3 between the readout line ROL and the eleventh transistor T11 in proportion to the voltage at the element output node NOP of the accumulated charge.

[0177] The ninth transistor T9 may include a gate electrode electrically connected to the element output node NOP, and may be electrically connected between the second initialization power line VAIL and the eleventh transistor T11 .

[0178] The ninth transistor T9 may be a source follower amplifier that generates a source-drain current in proportion to the amount of charge input to the element output node NOP of the gate electrode thereof.

[0179] When the potential of the element output node NOP is increased by the photocharge accumulated in the light sensing element PD and the difference voltage between the second initialization power supply VAINT and the potential of the element output node NOP becomes equal to or greater than the threshold voltage of the ninth transistor T9, the ninth transistor T9 may be turned on. In this case, a light sensing signal corresponding to the difference voltage between the second initialization power supply VAINT and the potential of the element output node NOP may be generated by the turned-on ninth transistor T9.

[0180] although Figure 7 The first electrode of the ninth transistor T9 is shown to be connected to the second initialization power line VAIL, but the embodiment is not limited to Figure 7 That is, the first electrode of the ninth transistor T9 may be connected to one of the first power line VDL and the first initialization power line VIL, instead of being connected to the second initialization power line VAIL.

[0181] The tenth transistor T10 may be electrically connected between the element output node NOP and the reset voltage line VRL, and may be turned on by the reset control signal GR of the reset control line GRL. Accordingly, when the tenth transistor T10 is turned on by the reset control signal GR, the potential of the element output node NOP may be reset to the reset voltage VRST of the reset voltage line VRL.

[0182] The eleventh transistor T11 may be electrically connected between the second electrode of the ninth transistor T9 and the readout line ROL, and may be turned on by the scan write signal GW of the scan write line GWL. Accordingly, the source-drain current of the ninth transistor T9 (i.e., the light sensing signal) may be transmitted to the readout line ROL through the eleventh transistor T11 turned on by the scan write signal GW.

[0183] The ninth transistor T9 and the eleventh transistor T11 may be provided as P-type MOSFETs, and the tenth transistor T10 may be provided as an N-type MOSFET.

[0184] Figure 8 It is shown Figure 7 A cross-sectional view of a light emitting element, a first transistor, a second transistor, a fourth transistor and a sixth transistor.

[0185] Reference Figure 8 The circuit layer 120 may include a buffer layer 121 covering the first light blocking layer LB1 on the substrate 110, a first semiconductor layer arranged on the buffer layer 121, a first gate insulating layer 122 covering the first semiconductor layer, a first gate conductive layer arranged on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer, a second gate conductive layer arranged on the second gate insulating layer 123, a first interlayer insulating layer 124 covering the second gate conductive layer, a second semiconductor layer arranged on the first interlayer insulating layer 124, and a second gate conductive layer covering the second gate conductive layer. A third gate insulating layer 125 of the semiconductor layer, a third gate conductive layer arranged on the third gate insulating layer 125, a second interlayer insulating layer 126 covering the third gate conductive layer, a first source-drain conductive layer arranged on the second interlayer insulating layer 126, a first planarizing layer 127 covering the first source-drain conductive layer, a second source-drain conductive layer arranged on the first planarizing layer 127, a second planarizing layer 128 covering the second source-drain conductive layer, a third source-drain conductive layer arranged on the second planarizing layer 128, and a third planarizing layer 129 covering the third source-drain conductive layer.

[0186] The first transistor T1 may include a channel portion CH1 formed of a first semiconductor layer on the buffer layer 121 , a source portion S1 and a drain portion D1 , and a gate electrode G1 disposed on the first gate insulating layer 122 and overlapping the channel portion CH1 .

[0187] A channel portion CH1 of the first transistor T1 may overlap the first light blocking layer LB1 on the substrate 110 .

[0188] The second transistor T2 may include a channel portion CH2 formed of the first semiconductor layer on the buffer layer 121 , a source portion S2 and a drain portion D2 , and a gate electrode G2 disposed on the first gate insulating layer 122 and overlapping the channel portion CH2 .

[0189] The sixth transistor T6 may include a channel portion CH6 formed of the first semiconductor layer on the buffer layer 121 , a source portion S6 and a drain portion D6 , and a gate electrode G6 disposed on the first gate insulating layer 122 and overlapping the channel portion CH6 .

[0190] The source portion S2 of the second transistor T2 may be electrically connected to the data line DL through the first data link electrode DCE1 and the second data link electrode DCE2.

[0191] The first data link electrode DCE1 may be disposed on the second interlayer insulating layer 126 and may be electrically connected to the source portion S2 of the second transistor T2 through a first data connection hole DCH1 extending through the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0192] The second data link electrode DCE2 may be disposed on the first planarization layer 127 and may be electrically connected to the first data link electrode DCE1 through a second data connection hole DCH2 extending through the first planarization layer 127 .

[0193] The data line DL may be disposed on the second planarization layer 128 and may be electrically connected to the second data link electrode DCE2 through a third data connection hole DCH3 extending through the second planarization layer 128 .

[0194] The drain portion D2 of the second transistor T2 may be connected to the source portion S1 of the first transistor T1 .

[0195] The drain portion D1 of the first transistor T1 may be connected to the source portion S6 of the sixth transistor T6 .

[0196] The drain portion D6 of the sixth transistor T6 may be electrically connected to the anode 131 through the first, second, and third anode connection electrodes ANCE1, ANCE2, and ANCE3.

[0197] The first anode connection electrode ANCE1 may be disposed on the second interlayer insulating layer 126 and may be electrically connected to the drain portion D6 of the sixth transistor T6 through a first anode connection hole ANCH1 extending through the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0198] The second anode connection electrode ANCE2 may be disposed on the first planarization layer 127 and may be electrically connected to the first anode connection electrode ANCE1 through a second anode connection hole ANCH2 extending through the first planarization layer 127 .

[0199] The third anode connection electrode ANCE3 may be disposed on the second planarization layer 128 and may be electrically connected to the second anode connection electrode ANCE2 through a third anode connection hole ANCH3 extending through the second planarization layer 128 .

[0200] The anode 131 may be disposed on the third planarization layer 129 , and may be electrically connected to the third anode connection electrode ANCE3 through a fourth anode connection hole ANCH4 extending through the third planarization layer 129 .

[0201] The first capacitor PC1 (see Figure 7 ) may be provided by an overlapping region between the capacitor electrode CPE disposed on the second gate insulating layer 123 and the gate electrode G1 of the first transistor T1.

[0202] The fourth transistor T4 may include a channel portion CH4 formed of the second semiconductor layer on the first interlayer insulating layer 124 , a source portion S4 and a drain portion D4 , and a gate electrode G4 disposed on the third gate insulating layer 125 and overlapping the channel portion CH4 .

[0203] A channel portion CH4 of the fourth transistor T4 may overlap the second light blocking layer LB2 on the second gate insulating layer 123 .

[0204] The source portion S4 of the fourth transistor T4 may be electrically connected to the first initialization power line VIL on the second interlayer insulating layer 126 through a hole VICH extending through the second interlayer insulating layer 126 and the third gate insulating layer 125 .

[0205] The drain portion D4 of the fourth transistor T4 may be electrically connected to the gate electrode G1 of the first transistor T1 through the gate connection electrode GCNE on the second interlayer insulating layer 126 .

[0206] The gate connection electrode GCNE may be electrically connected to the drain portion D4 of the fourth transistor T4 through a first gate connection hole GCH1 extending through the second interlayer insulating layer 126 and the third gate insulating layer 125 .

[0207] The gate connection electrode GCNE may be electrically connected to the gate electrode G1 of the first transistor T1 through a second gate connection hole GCH2 extending through the second interlayer insulating layer 126 , the third gate insulating layer 125 , the first interlayer insulating layer 124 , and the second gate insulating layer 123 .

[0208] The third transistor T3 and the tenth transistor T10 (see Figure 7 ) is similar in structure to the fourth transistor T4, and the fifth transistor T5, the seventh transistor T7, the ninth transistor T9 and the eleventh transistor T11 (see Figure 7 ) is similar in structure to the second transistor T2 and the sixth transistor T6. Therefore, redundant description of the transistor structure is omitted below.

[0209] The element layer 130 may include a light emitting element and a pixel defining layer 132. The light emitting element may include an anode 131, a cathode 134, and a light emitting layer 133 disposed between the anode 131 and the cathode 134.

[0210] In order to reduce the non-display area NDA (see Figure 1 ) width, the display device 100 according to the embodiment (see Figure 1 ) may include electrical connection to the data line DL (see Figure 6 ) and some of the non-display area NDA adjacent to the display driving circuit 200 (see Figure 1 ) and arranged in the display area DA (see Figure 1 ) in the transmission bypass line.

[0211] Fig. 9 It is shown Figure 2 A plan view of the main area and sub-areas of a substrate.

[0212] Reference Fig. 9 , the display device 100 (see Figure 2 ) includes a main area MA corresponding to a display surface and a sub area SBA protruding from one side of the main area MA.

[0213] The main area MA may include a display area DA arranged at a central area of ​​the polygonal shape and at most areas except for an area near the periphery, and a non-display area NDA arranged at the periphery to surround the display area DA.

[0214] The display area DA may include a bypass area DEA disposed on one side adjacent to the sub-area SBA and a general area GA disposed in a remaining area except the bypass area DEA.

[0215] The bypass area DEA includes a bypass middle area MDDA arranged at the center of an imaginary line extending across the display area DA in the first direction DR1, a first bypass side area SDA1 parallel to the bypass middle area MDDA in the first direction DR1 and in contact with the non-display area NDA, and a second bypass side area SDA2 arranged between the bypass middle area MDDA and the first bypass side area SDA1.

[0216] Unlike the bypass middle area MDDA and the second bypass side area SDA2 , the first bypass side area SDA1 may be disposed adjacent to a bent corner of the substrate 110 .

[0217] The first and second bypass side areas SDA1 and SDA2 may be disposed between the bypass middle area MDDA and the non-display area NDA located on both sides of the bypass middle area MDDA in the first direction DR1 .

[0218] The general area GA may include a general middle area GMA of a bypass middle area MDDA connected to the bypass area DEA in the second direction DR2, a first general side area GSA1 of a first bypass side area SDA1 connected to the bypass area DEA in the second direction DR2, and a second general side area GSA2 of a second bypass side area SDA2 connected to the bypass area DEA in the second direction DR2.

[0219] The non-display area NDA may include a gate driving circuit 101 and an emission control circuit 102 (see FIG. Figure 6 )'s gate drive circuit area GDRA.

[0220] The gate driving circuit area GDRA may be disposed in a portion of the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1.

[0221] The sub-area SBA may include a bendable bending area BA, a first sub-area SB1 disposed between one side of the bending area BA and the main area MA, and a second sub-area SB2 adjacent to the other side of the bending area BA. The second sub-area SB2 may be adjacent to one side of the bending area BA on the opposite side to the one side adjacent to the first sub-area SB1.

[0222] When the bending area BA is deformed as Figure 3 In the depicted curved shape, the second sub-region SB2 is arranged below the substrate 110 and overlaps the main region MA.

[0223] The display driving circuit 200 may be disposed in the second sub-region SB2 .

[0224] A signal pad SPD bonded to the display circuit board 300 may be arranged at one edge of the second sub-region SB2 .

[0225] Fig.10 It is shown Fig. 9 Layout diagram of part C.

[0226] Reference Fig.10 , the circuit layer 120 of the display device 100 according to the embodiment (see Figure 3 ) include electrically connected to the element layer 130 (see Figure 3 ) of the light emitting element LE (see Figure 7 ) of the light emitting pixel driver EPD, and the light sensing element PD electrically connected to the element layer 130 (see Figure 7 ) is electrically connected to the light-emitting pixel driver EPD and transmits a data signal Vdata (see Figure 7 ), first dummy lines DML1 extending in a first direction DR1 crossing the data lines DL, and second dummy lines DML2 extending parallel to the data lines DL and forming pairs with the data lines DL, respectively.

[0227] The data line DL and the second dummy line DML2 may extend in the second direction DR2.

[0228] According to an embodiment, the circuit layer 120 may further include a data supply line DSPL disposed in the non-display area NDA and electrically connected to the display driving circuit 200 and the data line DL.

[0229] The data lines DL may include a first data line DL1 arranged in the first bypass side area SDA1 and a second data line DL2 arranged in the second bypass side area SDA2.

[0230] The first dummy line DML1 may include a first transmission bypass line TDEL1 electrically connected to the first data line DL1 of the first bypass side area SDA1.

[0231] The second dummy line DML2 may include a second transmission bypass line TDEL2 paired with the second data line DL2 of the second bypass side area SDA2 and electrically connected to the first transmission bypass line TDEL1 .

[0232] The data supply lines DSPL may include a first data supply line DSPL1 transmitting a data signal of the first data line DL1 and a second data supply line DSPL2 transmitting a data signal of the second data line DL2 .

[0233] The first data supply line DSPL1 may be electrically connected to the second transmission bypass line TDEL2 .

[0234] The first transmission bypass line TDEL1 may be electrically connected to the second transmission bypass line TDEL2 through the first bypass connection hole DECH1 , and may be electrically connected to the first data line DL1 through the second bypass connection hole DECH2 .

[0235] As described above, according to an embodiment, the first data line DL1 of the first bypass side area SDA1 may be electrically connected to the first data supply line DSPL1 extending to the second bypass side area SDA2 through the first and second transmission bypass lines TDEL1 and TDEL2 arranged in the bypass area DEA of the display area DA.

[0236] On the other hand, the second data supply line DSPL2 may extend toward the second bypass side area SDA2 and may be directly electrically connected to the second data line DL2.

[0237] In other words, even if the first data supply line DSPL1 extends only to the second bypass side area SDA2 relatively adjacent to the sub-area SBA like the second data supply line DSPL2, the electrical connection between the first data line DL1 and the first data supply line DSPL1 can be achieved through the first transmission bypass line TDEL1 and the second transmission bypass line TDEL2.

[0238] Therefore, since the first data supply line DSPL1 does not extend relatively long from the sub-area SBA to the first bypass side area SDA1 adjacent to the curved edge of the substrate 110, and the first data supply line DSPL1 is not arranged at a portion of the non-display area NDA located between the curved edge of the substrate 110 and the first bypass side area SDA1, the width of the non-display area NDA can be reduced.

[0239] The data lines DL may further include a third data line DL3 disposed in the bypass middle area MDDA. In addition, the data supply line DSPL may further include a third data supply line DSPL3 transmitting a data signal of the third data line DL3.

[0240] The third data supply line DSPL3 may extend toward the bypass middle area MDDA and may be directly electrically connected to the third data line DL3 .

[0241] The first transmission bypass line TDEL1 extends from the second transmission bypass line TDEL2 to the first data line DL1 .

[0242] The second transmission bypass line TDEL2 extends from the first data supply line DSPL1 of the non-display area NDA to the first transmission bypass line TDEL1.

[0243] In this way, since the first transmission bypass line TDEL1 and the second transmission bypass line TDEL2 are restrictively arranged in the bypass area DEA, the ends of the first transmission bypass line TDEL1 and the ends of the second transmission bypass line TDEL2 are regularly arranged. Accordingly, it is possible to increase the visibility of the first transmission bypass line TDEL1 and the second transmission bypass line TDEL2.

[0244] To prevent this, the first dummy line DML1 may further include a first auxiliary line ASL1 in addition to the first transmission bypass line TDEL1 .

[0245] In addition, the second dummy line DML2 may further include a second auxiliary line ASL2 in addition to the second transmission bypass line TDEL2 .

[0246] Two of the first auxiliary lines ASL1 may extend to the non-display area NDA at both ends of the first transmission bypass line TDEL1 .

[0247] One of the second auxiliary lines ASL2 may extend from one end of the second transmission bypass line TDEL2 to the non-display area NDA in a direction away from the sub-area SBA.

[0248] Accordingly, a portion of the second data line DL2 may be paired with the second transmission bypass line TDEL2 , and another portion thereof may be paired with one second auxiliary line ASL2 extending from one end of the second transmission bypass line TDEL2 .

[0249] Since the second transmission bypass line TDEL2 is arranged only in the second bypass side area SDA2 , the first data line DL1 of the first bypass side area SDA1 may be paired with the second auxiliary line ASL2 as a whole.

[0250] In addition, the third data line DL3 bypassing the middle area MDDA may be paired with the second auxiliary line ASL2 as a whole.

[0251] The circuit layer 120 may further include a first power source ELVDD and a second power source ELVSS (see Figure 7 )'s first power supply line VDSPL and second power supply line VSSPL.

[0252] The first and second power supply lines VDSPL and VSSPL may be disposed in the non-display area NDA and may extend to the sub-area SBA.

[0253] The first power supply line VDSPL may be electrically connected to a signal pad SPD (see FIG. Fig. 9 ) is used to transmit the first power supply ELVDD.

[0254] The second power supply line VSSPL may be electrically connected to a second power pad for transmitting the second power ELVSS among the signal pads SPD arranged in the second sub-region SB2 .

[0255] The first auxiliary line ASL1 may be electrically connected to the second power supply line VSSPL.

[0256] The second auxiliary line ASL2 may be electrically connected to the first auxiliary line ASL1 and the second power supply line VSSPL.

[0257] According to an embodiment, the circuit layer 120 may further include a second power auxiliary line VSAL disposed at the same layer as the data line DL and the second dummy line DML2 and electrically connected to the second power supply line VSSPL.

[0258] According to an embodiment, the display device 100 may have a scanning function for detecting the curvature of an object in contact with the screen based on a difference in the amount of light reflected from the screen.

[0259] To this end, the display device 100 may further include light sensing elements PD distributed in at least a portion of the display area DA, and a scanning driving circuit 500 (see FIG. 5 ) that periodically collects light sensing signals of the light sensing elements PD. Figure 6 ).

[0260] The light sensing element PD may be arranged in the non-emitting area NEA (see Figure 4 ) of the optical sensing area ODA (see Figure 4 )middle.

[0261] The circuit layer 120 of the display device 100 according to the embodiment further includes light sensing pixel drivers DPD electrically connected to the light sensing elements PD, and a reset control signal GR (see Figure 7 ) of the reset control line GRL (see Figure 7 ).

[0262] In addition, the circuit layer 120 may further include a reset voltage VRST (see Figure 7 ) is transmitted to the reset voltage line VRL of the light sensing pixel driver DPD (see Figure 7 ), and a readout line ROL electrically connected between the light sensing pixel driver DPD and the scan driving circuit 500.

[0263] Like the first dummy line DML1 , the reset control line GRL may extend in the first direction DR1 .

[0264] The readout lines ROL may extend in the second direction DR2 in parallel with the data lines DL.

[0265] Fig.11It is shown that the arrangement Fig.10 Layout diagram of the lines in section D. Fig.12 It is shown Fig.11 A layout diagram of lines extending in a first direction in FIG.

[0266] Reference Fig.11 , the circuit layer 120 of the display device 100 according to the embodiment (see Figure 3 ) may extend in the second direction DR2.

[0267] The second dummy lines DML2 respectively paired with the data lines DL may extend in the second direction DR2 in parallel with the data lines DL.

[0268] In addition, the readout line ROL, the second power auxiliary line VSAL, and the first power line VDL may also extend in the second direction DR2.

[0269] The data line DL, the second dummy line DML2, and the second power auxiliary line VSAL may be arranged in the same layer. That is, the data line DL, the second dummy line DML2, and the second power auxiliary line VSAL may be arranged as the second planarization layer 128 (see Figure 8 ) on a third source / drain conductive layer.

[0270] For example, four light-emitting pixel drivers EPD (see Fig.10 ) can be arranged at any two adjacent light sensing pixel drivers DPD in the first direction DR1 (see Fig.10 )between.

[0271] Here, two second dummy lines DML2 respectively paired with two data lines DL may be arranged between two data lines DL respectively electrically connected to any two adjacent light-emitting pixel drivers EPDs adjacent to the light-sensing pixel driver DPD among the four light-emitting pixel drivers EPD. In addition, the second power auxiliary line VSAL may be arranged between the two second dummy lines DML2. In addition, two data lines DL respectively electrically connected to any two adjacent light-emitting pixel drivers EPDs relatively spaced apart from the light-sensing pixel driver DPD among the four light-emitting pixel drivers EPD may be adjacent to each other.

[0272] The readout line ROL may include a readout lower line ROBL and a readout upper line ROTL overlapping each other.

[0273] The readout upper line ROTL may be disposed at the same layer as the data line DL, the second dummy line DML2 , and the second power auxiliary line VSAL.

[0274] The readout lower line ROBL may be arranged at the same layer as the first power line VDL. As an example, the readout lower line ROBL and the first power line VDL may be arranged as a first planarization layer 127 (see Figure 8 ) on a second source / drain conductive layer.

[0275] Reference Fig.12 , in the circuit layer 120 of the display device 100 according to the embodiment, the reset control line GRL and the first dummy line DML1 may extend in the first direction DR1 intersecting the data line DL.

[0276] Furthermore, the scan write line GWL, the scan initialization line GIL, the emission control line ECL, the gate control line GCL, the bias power line VBL, the bias control line GBL, the first initialization power line VIL, the second initialization power line VAIL, and the reset voltage line VRL may extend in the first direction DR1.

[0277] The third transistor T3, the fourth transistor T4 and the tenth transistor T10 are provided as N-type MOSFETs (see Figure 7 ) may be provided by a structure including a bottom gate electrode arranged below a channel portion and a top gate electrode arranged above the channel portion.

[0278] To this end, the gate control line GCL electrically connected to the gate electrode of the third transistor T3 may include a gate control lower line GCBL and a gate control upper line GCTL overlapping each other.

[0279] The scan initialization line GIL electrically connected to the gate electrode of the fourth transistor T4 may include a scan initialization lower line GIBL and a scan initialization upper line GITL overlapping each other.

[0280] The reset control line GRL electrically connected to the gate electrode of the tenth transistor T10 may include a reset control lower line GRBL and a reset control upper line GRTL overlapping each other.

[0281] The light emitting element LE of the first emission area EA1 (see Figure 7 ) may be initialized to a voltage level different from the voltage levels of the light emitting elements LE of the second emission area EA2 emitting light of the second color and the light emitting elements LE of the third emission area EA3 emitting light of the third color.

[0282] To this end, the second initialization power line VAIL may include a red second initialization power line VAIL_R for transmitting a red second initialization power for the red first emission area EA1, and a cyan second initialization power line VAIL_GB for transmitting a cyan second initialization power for the green second emission area EA2 and the blue third emission area EA3.

[0283] For example, the scan write line GWL, the emission control line ECL, and the bias control line GBL may be arranged as the first gate insulating layer 122 (see Figure 8 ) on a first gate conductive layer.

[0284] The gate control lower line GCBL, the scan initialization lower line GIBL, and the reset control lower line GRBL may be arranged as the second gate insulating layer 123 (see Figure 8 ) on a second gate conductive layer.

[0285] The gate control upper line GCTL, the scan initialization upper line GITL, the reset control upper line GRTL and the second initialization power supply line VAIL (VAIL_R and VAIL_GB) may be arranged as a third gate insulating layer 125 (see Figure 8 ) on a third gate conductive layer.

[0286] The first dummy line DML1, the first initialization power line VIL, the reset voltage line VRL, and the bias power line VBL may be arranged as a second interlayer insulating layer 126 (see Figure 8 ) on a first source / drain conductive layer.

[0287] According to an embodiment, the reset control line GRL overlaps at least some of the first dummy lines DML1 among the first dummy lines DML1. That is, the reset control line GRL overlaps at least some of the first transmission bypass lines TDEL1 (see Fig.10 )overlapping.

[0288] Fig.13 is along Fig.10 A cross-sectional view taken along line EE'.

[0289] Reference Fig.13 , the second dummy line DML2 including the second transmission bypass line TDEL2 and the second auxiliary line ASL2 may be arranged as a third source-drain conductive layer on the second planarization layer 128 in the same manner as the data line DL.

[0290] The first dummy line DML1 including the first transmission bypass line TDEL1 may be disposed as a conductive layer under the second planarization layer 128 .

[0291] For example, the first dummy line DML1 including the first transmission bypass line TDEL1 may be disposed as a first source-drain conductive layer on the second interlayer insulating layer 126 , and may be covered with the first planarization layer 127 .

[0292] In this case, the first and second bypass connection holes DECH1 and DECH2 may extend through the second planarization layer 128 and the first planarization layer 127 .

[0293] In addition, according to the embodiment, at least the first transmission bypass line TDEL1 among the first dummy lines DML1 overlaps the reset control line GRL.

[0294] The reset control lines GRL may include a reset control lower line GRBL and a reset control upper line GRTL overlapping each other.

[0295] In this case, at least a portion of the first transmission bypass line TDEL1 on the second interlayer insulating layer 126 may overlap the reset control upper line GRTL on the third gate insulating layer 125 .

[0296] Alternatively, at least a portion of the first transmission bypass line TDEL1 on the second interlayer insulating layer 126 may overlap not only the reset control upper line GRTL on the third gate insulating layer 125 but also the reset control lower line GRBL on the second gate insulating layer 123 .

[0297] Thus, according to the embodiment, the first dummy line DML1 including the first transmission bypass line TDEL1 is not connected to the scan write line GWL, the scan initialization line GIL, the emission control line ECL, the gate control line GCL, and the bias control line GBL (see Fig.12 ) Similarly, during each image frame period, a plurality of pulse signals are applied in the first direction DR1 (see Fig.12 ) overlap.

[0298] Accordingly, the data signal of the first transmission bypass line TDEL1 may be prevented from being distorted by the influence of the pulse signal applied a plurality of times during each image frame period.

[0299] In addition, according to an embodiment, the first dummy line DML1 including the first transmission bypass line TDEL1 is not connected to the first dummy line DML1 for initializing the light emitting pixel driver EPD (see Figure 7 ) of the first initialization power line VIL and the second initialization power line VAIL (see Fig.12 ) and for resetting the light sensing pixel driver DPD (see Figure 7 ) reset voltage line VRL (see Fig.12 )overlapping.

[0300] Accordingly, the first initialization power supply VINT, the second initialization power supply VAINT and the reset voltage VRST (see Figure 7 ) varies with the data signal of the first transmission bypass line TDEL1. Accordingly, the initialization of the light emitting pixel driver EPD and the reset of the light sensing pixel driver DPD can be prevented from being performed differently, thereby preventing image quality degradation caused by spot defects, etc.

[0301] According to an embodiment, in order to prevent the data signal of the first transmission bypass line TDEL1 from being distorted by the voltage level of the reset control line GRL overlapping the first transmission bypass line TDEL1 , the voltage level of the reset control line GRL may be maintained at a constant voltage during each image frame period.

[0302] Fig.14 and Fig.15 is a diagram showing a method according to an embodiment Figure 7 1 is a waveform diagram of the voltage level of each of the scan initialization line, the gate control line, the scan write line and the reset control line.

[0303] Reference Fig.14 and Fig.15 During each of the image frame periods i-th Frame and (i+1)-th Frame, the scan write signal GW may be transmitted to the light emitting pixel driver EPD and the light sensing pixel driver DPD via the scan write line GWL (see Figure 7 ).

[0304] In addition, during each of the image frame periods i-th Frame and (i+1)-th Frame, the gate control signal GC may be transmitted to the luminescent pixel driver EPD through the gate control line GCL, and the scan initialization signal GI may be transmitted to the luminescent pixel driver EPD through the scan initialization line GIL.

[0305] The blank period BLK may be arranged between consecutive image frame periods i-th Frame and (i+1)-th Frame.

[0306] During the blank period BLK, the voltage level of the scan write line GWL may be maintained at a turn-off level.

[0307] According to some embodiments, the voltage level of the reset control line GRL may vary during the blank period BLK.

[0308] For example, Fig.14 As shown in , the reset control signal GR of the reset control line GRL may be transmitted to the light sensing pixel driver DPD during a blanking period BLK located between consecutive image frame periods i-th Frame and (i+1)-th Frame (where i is a natural number greater than or equal to 1).

[0309] That is, during the blank period BLK between the consecutive image frame periods i-th Frame and (i+1)-th Frame, the voltage level of the reset control line GRL may be changed twice into a rising form and a falling form by the reset control signal GR.

[0310] In this case, during each of the image frame periods i-th Frame and (i+1)-th Frame, the voltage level of the reset control line GRL may be maintained at an off level after the falling form.

[0311] For example, Fig.15 As shown in , the voltage level of the reset control line GRL may change to a rising form during the first blanking period j-th BLK, and may change to a falling form during the second blanking period (j+m)-th BLK (wherein each of i, j, and m is a natural number greater than or equal to 1) after the first blanking period j-th BLK. In addition, between the first blanking period j-th BLK and the second blanking period (j+m)-th BLK, at least one image frame period mFrames may be arranged.

[0312] In this case, during at least one image frame period m Frames between the first blank period j-th BLK and the second blank period (j+m)-th BLK, the voltage level of the reset control line GRL may be maintained at a turn-on level after the rising form.

[0313] On the other hand, during the image frame period i-th Frame before the first blank period j-th BLK and the image frame period (i+m)-th Frame after the second blank period (j+m)-th BLK, the voltage level of the reset control line GRL may be maintained at the off level.

[0314] As described above, according to an embodiment, the voltage level of the reset control line GRL changes only during the blanking period BLK, so that during each of the image frame periods i-th Frame, (i+1)-th Frame, m Frames and (i+m)-th Frame, the voltage level of the reset control line GRL can be maintained at a constant voltage of the on level or a constant voltage of the off level.

[0315] Accordingly, the reset control line GRL (see Fig.13 ) overlaps the first transmission bypass line TDEL1 (see Fig.13 ) is distorted due to the influence of the voltage level of the reset control line GRL.

[0316] on the other hand, Fig.14 and Fig.15 10. The scanning initialization signal GI, the gate control signal GC and the reset control signal GR are shown to be at a high level and their off levels are at a low level, but this is the case where the third transistor T3, the fourth transistor T4 and the tenth transistor T10 (see Figure 7That is, when the third transistor T3, the fourth transistor T4 and the tenth transistor T10 are provided as P-type MOSFETs, the scan initialization signal GI, the gate control signal GC and the reset control signal GR may be at a low level.

[0317] in addition, Fig.14 and Fig.15 1 shows that the scanning write signal GW is at a low level and the off level of the scanning write signal GW is at a high level, but this is in which the second transistor T2 and the eleventh transistor T11 (see Figure 7 ) is an example of a case where the second transistor T2 and the eleventh transistor T11 are provided as N-type MOSFETs. That is, when the second transistor T2 and the eleventh transistor T11 are provided as N-type MOSFETs, the scan write signal GW may be at a high level.

[0318] Fig.16 and Fig.17 is a plan view showing a reset control line, a first dummy line, and a tenth transistor according to an embodiment. Fig.18 is along Fig.17 A cross-sectional view taken along line F-F'.

[0319] Reference Fig.16 and Fig.17 , the reset control line GRL according to one embodiment may include an extension portion EXT extending in the first direction DR1 , and protrusions PRJ and PRJ′ branched from the extension portion EXT and overlapping the channel portion of the tenth transistor T10 .

[0320] The first dummy line DML1 including the first transmission bypass line TDEL1 may overlap the extending portion EXT of the reset control line GRL.

[0321] In this way, the malfunction of the tenth transistor T10 due to the influence of the data signal of the first transmission bypass line TDEL1 can be reduced.

[0322] The reset control line GRL may include a reset control lower line GRBL and a reset control upper line GRTL overlapping each other. In this case, each of the reset control lower line GRBL and the reset control upper line GRTL may include an extension portion EXT and protrusions PRJ and PRJ′.

[0323] For example, Fig.16 As shown in , the protrusion PRJ of the reset control line GRL may be arranged such that one side thereof is connected to the extension portion EXT.

[0324] In another embodiment, if Fig.17As shown in , the protrusion PRJ' of the reset control line GRL may be arranged so that there are two connection points to the extension portion EXT. That is, the protrusion PRJ' of the reset control line GRL may form a loop with a portion of the extension portion EXT. In this way, the connection between the extension portion EXT and the protrusion PRJ' may be more stably ensured, and the voltage level of the protrusion PRJ' may be easily maintained to be the same as the voltage level of the extension portion EXT.

[0325] like Fig.18 As shown in , the tenth transistor T10 may include a channel portion CH10 made of a second semiconductor layer on the first interlayer insulating layer 124, a source portion S10 and a drain portion D10, a top gate electrode G101 arranged above the channel portion CH10, and a bottom gate electrode G102 arranged below the channel portion CH10.

[0326] A channel portion CH10 of the tenth transistor T10 may overlap the top gate electrode G101 and the bottom gate electrode G102 .

[0327] The bottom gate electrode G102 of the tenth transistor T10 may be provided as a protrusion GRBL_PRJ′ of the reset control lower line GRBL disposed as a second gate conductive layer on the second gate insulating layer 123 .

[0328] The top gate electrode G101 of the tenth transistor T10 may be provided as a protrusion GRTL_PRJ′ of the reset control upper line GRTL disposed as a third gate conductive layer on the third gate insulating layer 125 .

[0329] The source portion S10 of the tenth transistor T10 may be electrically connected to the reset voltage line VRL through the reset voltage connection hole VRCH.

[0330] The drain portion D10 of the tenth transistor T10 may be electrically connected to the output node connection electrode NOPE through the output node connection hole NOPCH.

[0331] The extended portion GRTL_EXT of the reset control upper line GRTL can be connected to the first transmission bypass line TDEL1 (see Fig.13 An extension portion GRBL_EXT of the reset control lower line GRBL may overlap the first dummy line DML1 including the first transmission bypass line TDEL1.

[0332] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims.

Claims

1. A display device, comprising: substrate; A circuit layer, wherein the circuit layer is arranged on the substrate; as well as a component layer, the component layer being arranged on the circuit layer, The substrate includes a display area where a plurality of emission areas are arranged and a non-display area arranged around the display area. The display area includes a non-emitting area between the emitting areas and a plurality of light sensing areas arranged in the non-emitting area. The element layer includes a plurality of light emitting elements arranged in the plurality of emission regions and a plurality of light sensing elements respectively arranged in the plurality of light sensing regions, and The circuit layer comprises: a plurality of light-emitting pixel drivers, the plurality of light-emitting pixel drivers being electrically connected to the plurality of light-emitting elements; a plurality of light sensing pixel drivers, the plurality of light sensing pixel drivers being electrically connected to the plurality of light sensing elements; a plurality of data lines electrically connected to the plurality of light-emitting pixel drivers; a plurality of first dummy lines extending in a first direction crossing the data lines; a plurality of second dummy lines extending in parallel with the data lines, each of the plurality of second dummy lines forming a pair with one of the plurality of data lines; and A reset control line is electrically connected to the light sensing pixel driver, extends in the first direction, transmits a reset control signal for resetting the light sensing pixel driver, and overlaps at least one of the plurality of first dummy lines.

2. The display device according to claim 1, further comprising: a display driving circuit, wherein the display driving circuit outputs data signals to the plurality of data lines; The circuit layer further includes a plurality of data supply lines arranged in the non-display area and electrically connected between the plurality of data lines and the display driving circuit. The bypass area on one side of the display area includes a bypass middle area located at the center of the bypass area, a first bypass side area located between the bypass middle area and the non-display area, and a second bypass side area arranged between the bypass middle area and the first bypass side area, The plurality of data lines include a first data line arranged in the first bypass side region and a second data line arranged in the second bypass side region, The plurality of first dummy lines include a first transmission bypass line electrically connected to the first data line, The plurality of second dummy lines include a second transmission bypass line that is paired with the second data line and is electrically connected to the first transmission bypass line, Among the plurality of data supply lines, a first data supply line that transmits the data signal to the first data line is electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line, Among the plurality of data supply lines, a second data supply line that transmits the data signal to the second data line is directly electrically connected to the second data line, and Among the plurality of first dummy lines, the first transmission bypass line overlaps with the reset control line.

3. The display device according to claim 2, wherein: The circuit layer also includes: a first power supply line and a second power supply line, which are arranged in the non-display area and transmit first power and second power for driving the light emitting element, respectively; and a first power supply line, the first power supply line being electrically connected between the light-emitting pixel driver and the first power supply line, One of the plurality of light emitting elements is electrically connected between one of the plurality of light emitting pixel drivers and a second power supply line for transmitting the second power and electrically connected to the second power supply line, and The one light-emitting pixel driver comprises: a first transistor that generates a drive current for driving the one light emitting element; a second transistor electrically connected between one of the plurality of data lines and a first electrode of the first transistor; a third transistor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; a fourth transistor electrically connected between a first initialization power line for transmitting a first initialization power and the gate electrode of the first transistor; a fifth transistor electrically connected between the first power line and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and the one light emitting element; a seventh transistor electrically connected between a second initialization power line for transmitting a second initialization power and the one light emitting element; and An eighth transistor is electrically connected between a bias power line for transmitting a bias power and the first electrode of the first transistor.

4. The display device according to claim 3, wherein: The circuit layer further includes a readout line electrically connected to the light sensing pixel driver, One of the plurality of light sensing elements is electrically connected between an element output node of one of the plurality of light sensing pixel drivers and the second power line, and The light sensing pixel driver comprises: a ninth transistor configured to be turned on in response to a voltage level of an output node of the element; a tenth transistor electrically connected between a reset voltage line for transmitting a reset voltage and the element output node and configured to be turned on in response to the reset control signal of the reset control line; and An eleventh transistor, the eleventh transistor is electrically connected between the readout line and the ninth transistor.

5. The display device according to claim 4, wherein: The second transistor and the eleventh transistor are turned on in response to a scan write signal of a scan write line, The scanning write signal is transmitted to the light emitting pixel driver and the light sensing pixel driver during each image frame period, A blanking period in which the voltage level of the scan write line is maintained at an off level is arranged between consecutive image frame periods, and The voltage level of the reset control line changes during the blanking period.

6. The display device according to claim 5, wherein: The reset control signal of the reset control line is transmitted to the light-sensing pixel driver during the blanking period.

7. The display device according to claim 5, wherein: The voltage level of the reset control line changes in a first form during a first blanking period, and changes in a second form opposite to the first form during a second blanking period following the first blanking period, and At least one image frame period is arranged between the first blanking period and the second blanking period.

8. The display device according to claim 5, wherein: The third transistor is turned on in response to a gate control signal of a gate control line, The fourth transistor is turned on in response to a scan initialization signal of the scan initialization line, and The gate control signal and the scan initialization signal are transmitted to all the light-emitting pixel drivers during each image frame period.

9. The display device according to claim 5, wherein: The reset control line includes: an extending portion extending in the first direction; and A protrusion branched from the extending portion and overlapping with a channel portion of the tenth transistor.

10. The display device according to claim 9, wherein: The protrusion and the extension form a loop having two connection points.

11. The display device according to claim 2, wherein: The circuit layer also includes: a first power supply line and a second power supply line, which are arranged in the non-display area and transmit a first power supply and a second power supply for driving the light emitting element, respectively; and wherein the plurality of first dummy lines further include a plurality of first auxiliary lines electrically connected to the second power supply line, and The plurality of second dummy lines further include a plurality of second auxiliary lines electrically connected to the first auxiliary line and the second power supply line.

12. The display device according to claim 11, wherein: Two first auxiliary lines among the plurality of first auxiliary lines extend from both sides of the first transmission bypass line to the non-display area, and One of the plurality of second auxiliary lines extends from one side of the second transmission bypass line to the non-display area.

13. A display device, comprising: substrate; A circuit layer, wherein the circuit layer is arranged on the substrate; as well as a component layer, the component layer being arranged on the circuit layer, The substrate includes a display area where a plurality of emission areas are arranged and a non-display area arranged around the display area. The display area includes a non-emitting area between the emitting areas and a plurality of light sensing areas arranged in the non-emitting area. The element layer includes a plurality of light emitting elements arranged in the plurality of emission regions and a plurality of light sensing elements respectively arranged in the plurality of light sensing regions. The bypass area on one side of the display area includes a bypass middle area located at the center of the bypass area, a first bypass side area located between the bypass middle area and the non-display area, and a second bypass side area arranged between the bypass middle area and the first bypass side area, and The circuit layer comprises: a plurality of light-emitting pixel drivers, wherein the plurality of light-emitting pixel drivers are electrically connected to the plurality of light-emitting elements respectively; a plurality of light sensing pixel drivers, the plurality of light sensing pixel drivers being electrically connected to the plurality of light sensing elements respectively; a plurality of data lines electrically connected to the plurality of light-emitting pixel drivers; a first transmission bypass line extending in a first direction crossing the data line and electrically connected to a first data line arranged in the first bypass side region among the plurality of data lines; a second transmission bypass line extending in parallel with the data line, forming a pair with a second data line arranged in the second bypass side region among the plurality of data lines, and electrically connected to the first transmission bypass line; and a reset control line electrically connected to the light sensing pixel driver, extending in the first direction, transmitting a reset control signal for resetting an element output node of each light sensing pixel driver in the plurality of light sensing pixel drivers, and Overlapping with the first transmission bypass line.

14. The display device according to claim 13, further comprising: a display driving circuit, wherein the display driving circuit outputs data signals to the plurality of data lines; The circuit layer further includes a plurality of data supply lines arranged in the non-display area and electrically connected between the plurality of data lines and the display driving circuit. Among the plurality of data supply lines, a first data supply line that transmits the data signal to the first data line is electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line, and Among the plurality of data supply lines, a second data supply line transmitting the data signal to the second data line is directly electrically connected to the second data line.

15. The display device according to claim 14, wherein: The circuit layer also includes a readout line electrically connected to the light sensing pixel driver, One of the plurality of light emitting elements is electrically connected between one of the plurality of light emitting pixel drivers and a second power line for transmitting a second power source, One of the plurality of light sensing elements is electrically connected between the element output node of one of the plurality of light sensing pixel drivers and the second power line. The one light-emitting pixel driver comprises: a first transistor that generates a drive current for driving the one light emitting element; a second transistor electrically connected between one of the plurality of data lines and a first electrode of the first transistor; a third transistor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; a fourth transistor electrically connected between a first initialization power line for transmitting a first initialization power and the gate electrode of the first transistor; a fifth transistor electrically connected between a first power line for transmitting a first power source and the first electrode of the first transistor; a sixth transistor electrically connected between the second electrode of the first transistor and the one light emitting element; a seventh transistor electrically connected between a second initialization power line for transmitting a second initialization power and the one light emitting element; and an eighth transistor electrically connected between a bias power line for transmitting a bias power and the first electrode of the first transistor, and The light sensing pixel driver comprises: a ninth transistor configured to be turned on in response to a voltage level of an output node of the element; a tenth transistor electrically connected between a reset voltage line for transmitting a reset voltage and the element output node and configured to be turned on in response to the reset control signal of the reset control line; and An eleventh transistor, the eleventh transistor is electrically connected between the readout line and the ninth transistor.

16. The display device according to claim 15, wherein: The second transistor and the eleventh transistor are turned on in response to a scan write signal of a scan write line, The scanning write signal is transmitted to the light emitting pixel driver and the light sensing pixel driver during each image frame period, A blanking period in which the voltage level of the scan write line is maintained at an off level is arranged between consecutive image frame periods, and The voltage level of the reset control line changes during the blanking period.

17. The display device according to claim 16, wherein: The voltage level of the reset control line changes in a first form during a first blanking period, and changes in a second form opposite to the first form during a second blanking period following the first blanking period, and At least one image frame period is arranged between the first blanking period and the second blanking period.

18. The display device according to claim 16, wherein: The reset control line includes: an extending portion extending in the first direction; and A protrusion branched from the extending portion and overlapping with a channel portion of the tenth transistor.

19. The display device according to claim 18, wherein: The protrusion and the extension form a loop having two connection points.

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