Data processing apparatus and data processing method

Abstract

The present technology relates to a data processing device and a data processing method capable of outputting an appropriate multi-level signal having a desired multi-level with a simple configuration in data transmission using a multi-level signal. In the present technique, first to M-th drivers (each of which receives an input of a control signal and outputs a voltage corresponding to the control signal) are provided to a transmission line for transmitting a multi-level signal, in which transmission data is represented by a number of voltage levels corresponding to a state number N, the state number N represents a value that is an integer of 3 or more and is different from the power of 2 and a value that is the smallest integer of the result of the power of 2 and is not less than N, and represents the control number M. The first to M-th drivers have first to M-th output resistors, respectively. When a given integer not smaller than 1 and not larger than M is represented by m, a resistance value of an mth output resistor where m is not larger than M-1 is a value obtained by dividing a predetermined resistance value by a power of (m-1) of 2, and a resistance value of an Mth output resistor where m is M is a value obtained by dividing the predetermined resistance value by a power of (M-1) subtracting 2 from N.

Description

Technical Field

[0001] The present technology relates to a data processing device and a data processing method, and more particularly, to a data processing device and a data processing method capable of outputting an appropriate multilevel signal of a desired multilevel with a simple configuration in data transmission based on a multilevel signal. Background Art

[0002] Patent Documents 1 to 4 disclose technologies for realizing a single-phase N-level output driver.

[0003] Reference List

[0004] Patent Literature

[0005] Patent document 1: JP 05-336174A.

[0006] Patent document 2: WO 2011 / 045830 A.

[0007] Patent document 3: JP 10-303994A.

[0008] Patent document 4: JP 11-154859A. Summary of the invention

[0009] Problems to be solved by the present invention

[0010] Improvement of transmission speed based on multi-level has been proposed, and it is desired to output an appropriate multi-level signal of a desired level with a simple configuration.

[0011] The present technology has been made in view of such circumstances, and can output an appropriate multi-level signal of a desired multi-level with a simple configuration.

[0012] Solution to the problem

[0013] According to the first aspect of the present technology, a data processing device includes a plurality of drivers, each driver including a driver input terminal for inputting a control signal and a driver output terminal for outputting a voltage corresponding to the control signal input from the driver input terminal, and when the corresponding driver output terminal is in an open state, each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal, the plurality of drivers are a first driver to an Mth driver, wherein an integer greater than or equal to 3 and different from a power of 2 is the number of states N, the power of the smallest integer greater than or equal to N being a power of 2 is a control value M, and the driver output terminals are connected in parallel to a transmission line, through which a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted. The first driver to the Mth driver respectively include a first output resistor to an Mth output resistor, and in a case where any integer greater than or equal to 1 and less than or equal to M is represented by m, the resistance value of the mth output resistor where m is less than or equal to M-1 is a value obtained by dividing a predetermined resistance value by 2 to the (m-1) power, and the resistance value of the Mth output resistor where m is M is a value obtained by dividing a predetermined resistance value by a value obtained by subtracting 2 to the (M-1) power from N.

[0014] In a data processing device according to the first aspect of the present technology, a plurality of drivers are provided, each driver including a driver input terminal for inputting a control signal and a driver output terminal for outputting a voltage corresponding to the control signal input from the driver input terminal, and when the corresponding driver output terminal is in an open state, the driver output terminal outputs a high voltage or a low voltage corresponding to the control signal, the plurality of drivers are a first driver to an Mth driver, wherein an integer greater than or equal to 3 and different from a power of 2 is the number of states N, the power of the smallest integer greater than or equal to N being a power of 2 is a control value M, and the driver output terminals are connected in parallel to a transmission line, through which a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted. The first driver to the Mth driver respectively include a first output resistor to an Mth output resistor, and in a case where any integer greater than or equal to 1 and less than or equal to M is represented by m, the resistance value of the mth output resistor where m is less than or equal to M-1 is a value obtained by dividing a predetermined resistance value by 2 to the (m-1) power, and the resistance value of the Mth output resistor where m is M is a value obtained by dividing a predetermined resistance value by a value obtained by subtracting 2 to the (M-1) power from N.

[0015] A data processing device according to a second aspect of the present technology includes a plurality of drivers, each driver including a driver input terminal to which a control signal is input and a driver output terminal to which a voltage corresponding to the control signal input from the driver input terminal is output, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are first to M-th drivers, wherein an integer greater than or equal to 3 is the number of states N, a power of the smallest integer greater than or equal to the power of 2 of N is a control value M, and the driver output terminals are connected in parallel to a transmission line through which a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted, and a selection circuit to select a control signal to be input to the driver input terminal of each of the first to M-th drivers from among the plurality of control signals. The selection circuit changes the number of voltage levels of the multi-level signal to a value different from the number of states N by changing the control signal input to each of the first to M-th drivers.

[0016] The data processing method according to the second aspect of the present technology is a data processing method used by a data processing device, the data processing device including: a plurality of drivers, each driver including a driver input terminal for inputting a control signal and a driver output terminal for outputting a voltage corresponding to the control signal input from the driver input terminal, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are first to M-th drivers, wherein an integer greater than or equal to 3 is the number of states N, a power of the smallest integer greater than or equal to the power of 2 of N is a control value M, and the driver output terminals are connected in parallel to a transmission line, through which a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted, and a selection circuit, which selects a control signal to be input to the driver input terminal of each of the first to M-th drivers from a plurality of control signals. The data processing method includes: using the selection circuit, by changing the control signal input to each of the first to M-th drivers, the number of voltage levels of the multi-level signal is changed to a value different from the number of states N.

[0017] In a data processing device and a data processing method according to a second aspect of the present technology, a plurality of drivers are provided, each driver including a driver input terminal to which a control signal is input and a driver output terminal to which a voltage corresponding to the control signal input from the driver input terminal is output, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are first to M-th drivers, wherein an integer greater than or equal to 3 is the number of states N, a power of the smallest integer greater than or equal to the power of 2 of N is a control value M, and the driver output terminals are connected in parallel to a transmission line through which a multilevel signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted, and a selection circuit to select a control signal to be input to the driver input terminal of each of the first to M-th drivers from among the plurality of control signals. The selection circuit changes the number of voltage levels of the multilevel signal to a value different from the number of states N by changing the control signal input to each of the first to M-th drivers. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram showing an example of the configuration of a data transmission system according to an embodiment to which the present technology is applied.

[0019] Figure 2 It is shown Figure 1 Schematic diagram of an example of a configuration of a first mode of a transmitter in FIG.

[0020] Figure 3 is a table showing the number of states applied to the transmitter and the resistance value of the output resistor.

[0021] Figure 4 is shown in the case where the number of states is 7 Figure 2 Schematic diagram of the specific configuration of the transmitter.

[0022] Figure 5 It is shown Figure 4 Schematic diagram of the operation of the transmitter in.

[0023] Figure 6 is a graph showing changes in normalized output voltage with respect to a signal number in a case where the number of states is 7.

[0024] Figure 7 The number of states is shown in the case where the number of states is 27. Figure 2 Schematic diagram of the specific configuration of the transmitter.

[0025] Figure 8 It shows Figure 7 Schematic diagram of the operation of the transmitter in.

[0026] Fig. 9 is a graph showing changes in normalized output voltage with respect to a signal number in a case where the number of states is 27.

[0027] Fig.10 It is shown Figure 4 Configuration diagram of the first example of the transmitter in (case of N=7).

[0028] Fig.11 It is shown Figure 4 Configuration diagram of the second example of the transmitter in (case of N=7).

[0029] Fig.12 It is shown Figure 4 Configuration diagram of the third example of the transmitter in (case of N=7).

[0030] Fig.13 It is shown Figure 4 Configuration diagram of the fourth example of the transmitter in (case of N=7).

[0031] Fig.14 It is shown Figure 4 Configuration diagram of the fifth example of the transmitter in (case of N=7).

[0032] Fig.15 is a diagram showing another example of the circuit configuration of a unit.

[0033] Fig.16 is a diagram showing another example of the circuit configuration of another unit.

[0034] Fig.17 is a diagram showing another example of the circuit configuration of another unit.

[0035] Fig.18 is a diagram showing another example of the circuit configuration of another unit.

[0036] Fig.19 It is shown Figure 1 Schematic diagram of an example of a configuration of a first mode of a receiver in.

[0037] Fig. 20 It is shown Figure 1 Schematic diagram of an example of a configuration of a second mode of a receiver in.

[0038] Fig.21 It is shown Figure 1 Schematic diagram of an example of a configuration of a third mode of a receiver in.

[0039] Fig. 22 is a list showing comparison results between the transmitter to which the present technology is applied and comparison technologies 1 and 2.

[0040] Fig.23 is a schematic diagram of a transmitter in comparison technology 1.

[0041] Fig.24 is a schematic diagram of a transmitter in comparison technique 2.

[0042] Fig.25 is a diagram showing the configuration of the transmitter in Comparative Technology 2 in a case where the number of states is 7.

[0043] Fig.26 It is shown Fig.25 Schematic diagram of the operation of the transmitter in.

[0044] Fig. 27 It is shown Fig.25 FIG. 5 is a graph showing the time variation of the output voltage of the transmitter.

[0045] Fig.28 It is shown Figure 1 Schematic diagram of an example of a configuration of a second mode of a transmitter in FIG.

[0046] Fig.29 It is shown Fig.28 Schematic diagram of the operation of the transmitter in the second mode.

[0047] Fig.30 It is shown Fig.28 Another illustration of the operation of the transmitter in the second mode of operation.

[0048] Fig.31 It is shown Fig.28 Another illustration of the operation of the transmitter in the second mode of operation.

[0049] Fig.32 It is shown Figure 1 Schematic diagram of an example of a configuration of a third mode of a transmitter in FIG.

[0050] Fig.33 It is shown Fig.32 A configuration diagram of a first example of a configuration of a transmitter in FIG.

[0051] Fig.34 : is a table showing the relationship between the mode value corresponding to the number N of states and the control signal output from the multiplexer MUX of each unit.

[0052] Fig.35 It is shown Fig.34 Schematic diagram of case 1 (case where the number of states N=7).

[0053] Fig.36 Is used to describe Fig.34 Illustration of case 1 in .

[0054] Fig.37 Is used to describe Fig.34 Another illustration of Case 1 in FIG.

[0055] Fig.38 Is used to describe Fig.34 Another illustration of Case 1 in FIG.

[0056] Fig.39 It is shown Fig.34 Schematic diagram of case 2 (case where the number of states N=4).

[0057] Fig.40 Is used to describe Fig.34 Schematic diagram of case 2 in .

[0058] Fig.41 Is used to describe Fig.34 Another illustration of Case 2 in FIG.

[0059] Fig.42 Is used to describe Fig.34 Another illustration of Case 2 in FIG.

[0060] Fig.43 It is shown Fig.34 Schematic diagram of case 3 (case where the number of states N=3).

[0061] Fig.44 Is used to describe Fig.34 Schematic diagram of case 3 in .

[0062] Fig.45 Is used to describe Fig.34 Another illustration of Case 3 in FIG.

[0063] Fig.46 Is used to describe Fig.34 Another illustration of Case 3 in FIG.

[0064] Fig.47 It is shown Fig.34 Schematic diagram of case 4 (case where the number of states N=2).

[0065] Fig.48 Is used to describe Fig.34 Illustration of case 4 in .

[0066] Fig.49 Is used to describe Fig.34 Another illustration of Case 4 in FIG.

[0067] Fig.50 Is used to describe Fig.34 Another illustration of Case 4 in FIG.

[0068] Fig.51 It is shown Fig.32 A configuration diagram of a second example of the configuration of the transmitter in FIG.

[0069] Fig.52 It is shown Fig.51 Schematic diagram of the operation of the transmitter in.

[0070] Fig.53 It is shown Fig.51 Another illustration of the operation of the transmitter in .

[0071] Fig.54 is a diagram showing the operation of the transmitter in Comparative Technology 2 in a case where the number of states is 7.

[0072] Fig.55 is another diagram showing the operation of the transmitter in Comparative Technology 2.

[0073] Fig.56 It is shown Fig.32 Configuration diagram of a first example of a transmitter in FIG.

[0074] Fig.57 It is shown Fig.32 Configuration diagram of a second example of a transmitter in FIG.

[0075] Fig.58 It is shown Fig.32 Configuration diagram of a third example of a transmitter in FIG.

[0076] Fig.59 is a diagram showing an example of a circuit configuration of a multiplexer MUX.

[0077] Fig.60 is a diagram showing another example of the circuit configuration of the multiplexer MUX.

[0078] Fig.61 is a diagram showing a first example of application of a transmitter to which the present technology is applied. DETAILED DESCRIPTION

[0079] An embodiment of the present technology (this embodiment) will be described below with reference to the drawings.

[0080] <<Data transmission system 1 according to present embodiment>>

[0081] Figure 1 : is a block diagram showing an example of the configuration of a data transmission system according to an embodiment to which the present technology is applied. Figure 1 In the embodiment, the data transmission system 1 includes a transmitter 11, a receiver 12 and a transmission path 13. The transmitter 11 generates a control signal corresponding to N (N is less than or equal to 2) based on M-bit (M is a natural number) digital data (control signal) input in parallel. MA transmitting signal (also called a multi-level signal or a signal to be transmitted) having a voltage level (multiple levels) corresponding to a natural number) value is output, and the signal is transmitted to a receiver 12 via a single-wire transmission path 13 (transmission line) connected to an output terminal.

[0082] The receiver 12 receives the transmission signal (multi-level signal) transmitted from the transmitter 11 via the transmission path 13, and detects which level of the voltage level of the received multi-level signal is N multi-level. Note that the number of multiple levels (number of levels) N of the multi-level signal transmitted by the transmitter 11 will also be referred to as the number of states. In addition, in the case where multiple types of digital data or digital data with a large number of bits (bit depth) are converted into serial data and transmitted at high speed, it is effective to reduce the bit depth of the transmission data transmitted simultaneously. The M-bit digital data input to the transmitter 11 can be a combination of multiple types of data, or can be partial data obtained by dividing the data represented by multiple bits. Note that in order to increase the communication speed, it is necessary to increase the number of conversions per unit time (bit / second), but there are manufacturing restrictions. Therefore, by adopting the multi-level of the transmission signal, the amount of data converted each time can be increased, and faster data communication can be achieved. Specifically, due to the bit efficiency in single-phase communication (for example, the bit efficiency is higher in the case of outputting eight values ​​than in the case of outputting seven values ​​using three bits), the encoding of the number of multiple levels (the number of states) other than the power of 2 is generally inefficient. In a communication standard that performs special encoding in three-wire communication, etc., there is a case where the output of the number of multiple levels other than the power of 2 is required due to the requirements of characteristics related to electrical specifications and high-speed signal quality other than the bit efficiency, and the present technology is particularly effective in such a case. As the transmission path 13, wiring in a printed circuit board (PCB), a package of each chip, a connector, a cable, etc. can be assumed.

[0083] <<First Mode of Transmitter 11>>

[0084] Figure 2 It is shown Figure 1 FIG. 1 is a diagram showing an example of a configuration of a first mode of the transmitter 11 in FIG. Figure 2 , the transmitter 11-1 is Figure 1 The first mode of the transmitter 11 includes drivers D0 to D M-1 and output resistors R0 to R M-1 The control signals cont(0) to cont(M-1) are input to drivers D0 to D1 respectively. M-1 In addition, the low voltage V L and high voltage V H (>V L ) is applied to drivers D0 to DM-1 Each of the low voltage V L For example, the ground potential (GND potential), the high voltage V H It is a constant voltage generated by a constant voltage generating circuit, but the low voltage V L and high voltage V H The control signals cont(0) to cont(M-1) correspond to the input signals to Figure 1 0 to M-1 (the first bit to the Mth bit, i.e., the first bit to the second bit) of the M-bit digital data of the transmitter 11 in M-1 For example, each of the control signals cont(0) to cont(M-1) is a binary signal indicating whether the corresponding bit is 0 or 1, and indicates 0 or 1 depending on whether the voltage of the control signal is at a high level or a low level. In the following description, it is assumed that the control signals cont(0) to cont(M-1) are applied to the drivers D0 to D1 when the voltage of the control signal is at a high level or a low level. M-1 A value of 0 or 1 is input without specifying whether the control signal is 0 or 1. In addition, the control signals cont(0) to cont(M-1) which are M-bit digital data are not necessarily the transmission data (data to be transmitted) themselves, and may be for controlling the drivers D0 to D1. M-1 The output of drivers D0 to D1 is used to make the transmission data as a multi-level signal transmitted from the transmitter 11-1. M-1 are M ideal voltage drivers. Drivers D0 to D M-1 When the value of the input control signal cont(0) to cont(M-1) is 0, a low voltage V is output. L , and outputs a high voltage V when the value is 1 H . Output resistors R0 to R M-1 is connected between driver D0 to D M-1 The output terminal V of the transmitter 11-1 is out (transmission line). Note that the output terminal V out The sign of is also used as a parameter indicating the output voltage output from the output terminal. In addition, drivers D0 to D M-1 and the output resistors R0 to R connected with it M-1 can be considered as an equivalent circuit in which the actual driver is represented by an ideal voltage driver and an output resistor, and the configuration of the actual driver need not be separable into the driver and the output resistor. Therefore, in the case where m is any value from 0 to M-1, the driver D m and the output resistor R m represents a driver, and the output terminal of the driver (driver output terminal) is connected to the output terminal V out(Transmission line). The driver can be considered to output a low voltage V from the driver output terminal when the driver output terminal is disconnected (assuming that no voltage drop occurs in the output resistor). L Or high voltage V H Assuming that Figure 2 While all of the following embodiments will be described with the configuration shown in which the driver and its output resistor are detachably connected to each other, in any case, the driver and its output resistor are not necessarily separable, and the driver and its output resistor may be regarded as constituting one driver.

[0085] Output resistors R0 to R M-1 The resistance value of the output resistor R0 to R M-1 The symbol is used as a parameter indicating the resistance value, and in the following expression (1), the resistance value R m The value of m is any value between 0 and M-1.

[0086] [Mathematical formula 1]

[0087]

[0088] Note that M is also referred to as a control value hereinafter, and m is also referred to as a control number hereinafter. The control value M corresponds to the number of control signals for controlling the driver. The control number m is used as a number for specifying a control signal, a number for specifying a driver to be controlled by the specified control signal, and a number for specifying an output resistor connected to the specified driver. N is the number of multiple levels (voltage levels) of a multi-level signal, which is output from the transmitter 11-1 to the output terminal V out The output transmission signal. Hereinafter, N will also be referred to as the number of states. The number N of states of the multi-level signal output from the transmitter 11 will also be referred to as the number N of states of the transmitter 11, or simply the number N of states.

[0089] Here, the resistance value R term Indicates that all output resistors R0 to R M-1 The resistance value R in the case of connecting in parallel with each other according to the following expression (2) os .

[0090] [Mathematical formula 2]

[0091]

[0092] In addition, the output voltage V nis the voltage level outputted by the transmitter 11-1 as a multi-level signal, represented by the following expression (3). Note that n represents each of the numbers 0 to N-1 assigned to the voltage level of N levels in ascending order. Hereinafter, n is also referred to as a state number.

[0093] [Mathematical formula 3]

[0094]

[0095] Accordingly, the transmitter 11-1 uses output resistors R0 to R1 having resistance values ​​defined in the above expression (1). M-1 As drivers D0 to D1 of control numbers 0 to M-1 M-1 The output resistors R0 to R M-1 , from the output terminal V out Outputs N (N level) output voltage V corresponding to control signals cont(0) to cont(M-1) n . Output voltage V n The low voltage V L After the state number n is set to 0, the low voltage V L With high voltage V H The difference is divided equally (divided into N-1 equal parts) into N-1 parts to obtain N voltage levels (including voltage V L and voltage V H ) The voltages of state number n are assigned in ascending order.

[0096] Incidentally, the value in the case where the M-bit digital data indicated by the control signals cont(0) to cont(M-1) input to the transmitter 11-1 is expressed in decimal will be referred to as a signal number X (0 to 2 M-1 That is, the value in the case where the control signal cont(0) is a 1-bit (first bit) value, the control signal cont(1) is a 2-bit (second bit) value, and the control signal cont(2) is a 4-bit (third bit) value expressed as a decimal number is defined as the signal number X. M -1 -1, drive D M-1 The output voltage is low voltage V L , and from drivers D0 to D M-2 One of the output high voltage V H At this time, the output resistor R0 to R M-2 In the case of connecting to the output high voltage V H The resistance value of the case where the output resistors of the driver are connected in parallel with each other is the resistance value R shown in the lower part of the above expression (1) m The expression is proportional to the inverse of the signal number X. That is, when connected to the output high voltage VH The admittance of the driver when the output resistors are connected in parallel is proportional to the signal X. The admittance at this time is calculated by using the proportional constant C (C is 1 / {(N-1)·R term}) is represented by C·X. Therefore, when the signal number X is 0 to 2 M-1 -1 case, from the output terminal V out Output voltage V out As the signal number X increases from 0 to 1. More specifically, when the signal number X is 0 to 2 M-1 -1, the state number n output in the above expression (3) is 0 to 2 M-1 -1 output voltage V n .

[0097] On the other hand, when signal number X is 2 M-1 to 2 M -1 case, drive D M-1 The output voltage is a high voltage V H , and is connected to the output high voltage V H The admittance of the driver in the case where the output resistors are connected in parallel with each other is the same as the output resistor R shown in the above expression (1) M-1 The resistance value R m N-2 in (m=M-1) M-1 and signal number X and 2 M-1 The difference between (X-2 M-1 ) and (N+X-2 M ) is proportional. The admittance at this time is calculated using the proportional constant C by C·(N+X-2 M ) indicates. In the admittance C·(N+X-2 M ) and signal number X is 0 to 2 M-1 -1 maximum admittance C·(2 M-1 -1) compared to C·(N+X-2 M ) is less than or equal to C·(2 M-1 -1) the admittance of signal number X and signal number X is 0 to 2 M-1 -1. That is, (N+X-2 M )-(2 M-1 -1) = (N + X-3·2 M-1 +1) is less than or equal to 0 and the signal number X is 0 to 2 M-1 -1. M-1 ≤X≤3·2 M-1 -1-N The admittance of the signal number X is 0 to 2 when the signal number X is M-1-1 in the case of admittance overlap, the output voltage V out With the signal number X ranging from 0 to 2 M-1 -1 output voltage V n overlap (in state number n is 0 to 2 M-1 -1 output voltage V n ). Due to 2 M-1 ≤X≤3·2 M-1 -1-N can be converted to 0≤X-2 M-1 ≤2 M -1-N, so in 2 M-1 to 2 M -1 signal number X is replaced by 2 M-1 In the case of +ΔX, ΔX is from 0 to the maximum value of the signal number X (2 M-1 ) minus the number of states N to obtain the value of the integer range, the output voltage V out With the signal number X being 0 to 2 M-1 -1 output voltage V n part (in state number n is 0 to 2 M-1 -1 output voltage V n )overlapping.

[0098] The number N of states in the transmitter 11-1 and the output resistors R0 to R M-1 The relationship between>

[0099] Figure 3 1 and 2 are diagrams showing the number N of states applied to the transmitter 11 - 1 and the output resistors R0 to R1 in the case of the number N of states. M-1 The resistance value R0 to R M-1 (with resistance value R term In the leftmost column, 2 to 32 are described as examples of the number N of states applied to the transmitter 11-1. In each row of the plurality of states, the output resistors R0 to R1 of the control numbers 0 to M-1 calculated according to the above expression (1) are M-1 The resistance value R0 to R M-1 is represented as the resistance value R term It should be noted that as the output resistor R0 to R M-1 The value of the control value M of the number, that is, as the driver D0 to D M-1 The number and the number of drivers used to control D0 to D M-1 The value of the control value M of the number of control signals cont(0) to cont(M-1) is the value that satisfies (N-2 M-1) (which is the denominator in the upper expression of the above expression (1)) is greater than 0. In other words, the control value M is a value greater than or equal to the smallest power (integer) of 2 of N.

[0100] exist Figure 3 When the number of states N is 3, for example, the control value M is 2, the resistance value R0 of control number 0 / resistance value R term is 2, and the resistance value of control number 1 is R1 / resistance value R term is 2. When the number of states N is 5, the control value M is 3, and the resistance value R0 of the control number 0 / the resistance value R term is 4, the resistance value of control number 1 is R1 / resistance value R term is 2, and the resistance value of control number 2 is R2 / resistance value R term is 4. When the number of states N is 7, the control value M is 3, and the resistance value R0 of the control number 0 / the resistance value R term is 6, the resistance value of control number 1 is R1 / resistance value R term is 3, and the resistance value of control number 2 is R2 / resistance value R term is 2. When the number of states N is 27, the control value M is 5, and the resistance value R0 of the control number 0 / the resistance value R term is 26, the resistance value of control number 1 is R1 / resistance value R term =13, the resistance value of control number 2 is R2 / resistance value R term is 6.5 (26 / 4), the resistance value of control number 3 is R3 / resistance value R term is 3.25 (26 / 8), the resistance value of control number 4 is R4 / resistance value R term It is 2.364 (26 / 11).

[0101] It should be noted that if Figure 3 In the table of, in the case where the transmitter 11 is set to the number N of states, the above expression (1) limits the output resistors R0 to R1 of the control numbers 0 to M-1. M-1 The resistance value R0 to R M-1 ratio, and the resistance value R0 to R M-1 Not limited to specific values.

[0102] <Specific Configuration of Transmitter 11-1 When the State Number N1 is 7>

[0103] Figure 4 It is shown that when the number of states N is 7 Figure 2 FIG. 1 is a diagram showing a specific configuration of the transmitter 11-1 in FIG. Figure 3 As shown, when the number of states N is 7, the control value M is 3, and the resistance value R0 of the control number 0 / the resistance value R termis 6, the resistance value of control number 1 is R1 / resistance value R term is 3, and the resistance value of control number 2 is R2 / resistance value R term Yes 2. Figure 4 In the example, since the control value M is 3, the transmitter 11-1 includes three drivers D0 to D2 of control numbers 0 to 2 and a resistor 6R term , resistance value 3R term And the resistance value is 2R term The three output resistors R0 to R2 of the control numbers 0 to 2 are represented. The control signals cont(0) to cont(2) are input to the drivers D0 to D2, respectively, and are output from the output terminals V out Output voltage V of state number n corresponding to the value of control signal cont(0) to cont(2) n multi-level signal.

[0104] Figure 5 It is shown Figure 4 1 is a diagram showing the operation of the transmitter 11-1 in FIG. Figure 5 , signal numbers X of 0 to 7 are shown in the leftmost column. Signal number X is a value obtained by expressing 3-bit digital data indicated by control signals cont(0) to cont(2) in decimal. In each row of signal number X of 0 to 7, the value (0 or 1) of control signals cont(0) to cont(2) and the value of the control signals cont(0) to cont(2) and the value of the control signals from the output terminal V out Normalized output voltage V of output state number n n . Normalized output voltage V n is achieved by using a low voltage V L and high voltage V H The voltage range between 0 and 1 is defined as the normalized output voltage V n The obtained value is used (V n -V L ) / (V H -V L ) is normalized. Note that by n Normalization (V n -V L ) / (V H -V L ) The value obtained will be called the normalized output voltage V n , and the value obtained by normalizing the value of an arbitrary output voltage by a similar expression will be referred to as a normalized output voltage hereinafter. Figure 6 The normalized output voltage V n The change with respect to the signal number X is shown as a graph, in which the horizontal axis represents the signal number X and the vertical axis represents the normalized output voltage.

[0105] according to Figure 5 and Figure 6 , when the signal number X is 0, the output voltage V0 (=V L ), and the normalized output voltage V0 of state number 0 is the minimum value 0. When the signal number X is 1 to 3, the output voltages V1 to V3 of state numbers n 1 to 3 are output, and the normalized output voltages V1 to V3 of state numbers 1 to 3 are 0.167, 0.333, 0.667 and 0.500 respectively. At this time, the normalized output voltage V n The value in the case of the previous signal number X is increased by 1 / 6. When the signal number X is 4, the output voltage V3 of the state number n is 3 is output as in the case of the signal number X is 3. The normalized output voltage V3 of the state number 3 is 0.500, which overlaps with the normalized output voltage V3 of the case of the signal number X is 3. When the signal number X is 5 to 7, the output voltages V4 to V6 of the state numbers n 4 to 6 are output, and the normalized output voltages V4 to V6 of the state numbers 4 to 6 are 0.667, 0.833 and 1.000, respectively. At this time, the normalized output voltage V n The value of the previous signal number X is increased by 1 / 6. The output voltage V6 of state number 6 when signal number X is 7 is V H , so the maximum value of the normalized output voltage V6 is 1.

[0106] <Specific Configuration of Transmitter 11-1 When the Number of States N is 27>

[0107] Figure 7 It is shown that when the number of states N is 27 Figure 2 FIG. 1 is a diagram showing a specific configuration of the transmitter 11-1 in FIG. Figure 3 As shown, when the number of states N is 27, the control value M is 5, and the resistance value R0 of the control number 0 / the resistance value R term is 26, the resistance value of control number 1 is R1 / resistance value R term =13, the resistance value of control number 2 is R2 / resistance value R term is 6.5 (26 / 4), the resistance value of control number 3 is R3 / resistance value R term is 3.25 (26 / 8), the resistance value of control number 4 is R4 / resistance value R term is 2.364 (26 / 11). Figure 7 In FIG. 1 , since the control value M is 5, the transmitter 11 - 1 includes five drivers D0 to D4 of control numbers 0 to 4 and a resistor 26R term , resistance value 3.25R term , resistance value 2.364R term , resistance value 3.25R termAnd the resistance value (26 / 11)R term The five output resistors R0 to R4 of the control numbers 0 to 4 are represented by . The control signals cont(0) to cont(4) of the control numbers 0 to 4 are input to the drivers D0 to D4, respectively, and are output from the output terminals V out Output voltage V of state number n corresponding to the value of control signal cont(0) to cont(4) n multi-level signal.

[0108] Figure 8 It shows Figure 7 1 is a diagram showing the operation of the transmitter 11-1 in FIG. Figure 8 , the signal numbers X of 0 to 31 are shown in the leftmost column. The signal number X is a value obtained by expressing the 5-bit digital data indicated by the control signals cont(0) to cont(4) in decimal. In each row of the signal number X of 0 to 31, the value (0 or 1) of the control signal cont(0) to cont(4) and the value of the control signal cont(0) to cont(4) from the output terminal V out Normalized output voltage V of output state number n n .exist Fig. 9 The normalized output voltage V n The change with respect to the signal number X is shown as a graph, in which the horizontal axis represents the signal number X and the vertical axis represents the normalized output voltage.

[0109] according to Figure 8 and Fig. 9 , when the signal number X is 0, the output voltage V0 (=V L ), and the normalized output voltage V0 of state number 0 is the minimum value 0. When the signal number X is 1 to 15, the output voltages V1 to V 15 , and the normalized output voltages V1 to V 15 Increased from 0.038 to 0.577. At this time, the normalized output voltage V n The value is increased by 1 / 26 from the value in the previous case of signal number X. In the case where signal number X is 16 to 20, the output voltage V of the state number n of 11 to 15 is output as in the case where signal number X is 11 to 15. 11 To V 15 The normalized output voltage V with state numbers 11 to 15 11 To V 15 It is a value increased by 1 / 26 from 0.423 to 0.577, and overlaps with the value in the case where the signal number X is 11 to 15. When the signal number X is 21 to 31, the output voltage V of the output state number n is 16 to 26 16 To V 26, and the normalized output voltage V for state numbers 16 to 26 16 To V 26 Increases from 0.617 to 1.000. At this time, the normalized output voltage V n Increased by 1 / 26 from the value in the previous case of signal number X. Since the output voltage V with state number 26 in the case of signal number X being 31 25 V H , so the normalized output voltage V 26 Has a maximum value of 1.

[0110] <First Example of Transmitter 11-1>

[0111] Fig.10 It is shown Figure 4 FIG. 1 is a configuration diagram of a first example (case of N=7) of the transmitter 11-1. Fig.10 In the embodiment, the transmitter 11-1 includes unit drivers 31-1 to 31-3. Each of the unit drivers 31-0 to 31-2 includes one or more units 41 having the same circuit configuration and circuit characteristics. Each unit 41 includes a circuit having the same circuit configuration and circuit characteristics as in Figure 4 A driver (referred to as a unit driver D) having characteristics similar to the characteristics of the drivers D0 to D2 shown in FIG. 1 and an output resistor (corresponding to a unit resistor L·R described later) connected to an output terminal of the unit driver D term , although it will be referred to here as the unit resistor R out ). Each unit 41 is mounted on, for example, an IC chip or a substrate. Fig.10 In the embodiment, the cell driver D in each cell 41 has a circuit configuration of a complementary MOS (CMOS) including a combination of a p-type MOSFET and an n-type MOSFET, but the circuit configuration of the driver D is an example and is not limited thereto. The cell resistor R in each cell 41 out The resistance value can be expressed as 12·R term Since the resistance value R term The unit resistance R in each cell 41 is not limited to a specific value. out Each cell 41 need not include a cell resistor R out As a resistance element, and as a unit resistor R of the resistance element out The resistance value can be 0Ω. In this case, again, assuming a unit resistor R of 0Ω out Connected to driver D. It should be noted that when a plurality of units 41 are used to configure the required number (control value M) of drivers D0 to D1 with control numbers 0 to M-1, M-1 and output resistors R0 to R M-1In the case of one or more cells 41, the cell driver D and the cell resistor R out Configure drivers D0 to D M-1 and output resistors R0 to R M-1 , each unit 41 is a unit driver D and a unit resistor R having the same characteristics out That is, a plurality of unit drivers D controlled by a control signal of the same control number is equivalent to one driver of the control number, and is equivalent to a plurality of unit resistors R connected to the unit drivers D connected in parallel with each other. out Therefore, through the unit driver D and unit resistor R of one or more units 41 having the same characteristics out Capable of implementing drivers D0 to D M-1 Each of the output resistors R0 to R M-1 As described above, as drivers D0 to D1 respectively constitute control numbers 0 to M-1, M-1 and output resistors R0 to R M-1 The cell driver D and the cell resistor R out will be referred to as a cell driver and a cell resistor so as to distinguish the cell driver and the cell resistor from the drivers D0 to D M-1 and output resistors R0 to R M-1 In addition, as described above, the unit driver D and the unit resistor R as its output resistor out It can be regarded as an equivalent circuit representing one unit driver D, and in this case, unit 41 represents the unit driver D.

[0112] exist Fig.10 In the embodiment, in the cell drivers 31-0 to 31-2, two cells 41, four cells 41, and six cells 41 are connected in parallel to each other, respectively. Connecting the cells 41 in parallel means that the same type of terminals in the plurality of cells 41 are connected to the same line. Each cell 41 includes an input terminal for a control signal input to the cell driver D, a cell resistor R out The output terminal of the output voltage is applied to the output side (the side opposite to the contact of the unit driver D) of the H The high voltage terminal and the low voltage V L Low voltage terminal.

[0113] With respect to the two cells 41 of the cell driver 31-0, the input terminal of the cell 41 is connected to the output terminal (supply line through which the control signal cont(0) is supplied) of the high-speed control logic (logic circuit) 32 that outputs the control signal Cont(0). The output terminal of the cell 41 is connected to the output terminal V out(Transmission line for transmitting a multi-level signal) The high voltage terminal of the unit 41 is connected to the output of the high voltage V generated by the constant voltage generating circuit 33. H The low voltage terminal is connected to the GND terminal. Therefore, the two units 41 are connected in parallel to each other and always perform the same operation, thereby constituting an equivalent Figure 4 The control number in the driver is 0, D0, and the output resistor is 6R term circuit.

[0114] With respect to the four cells 41 of the cell driver 31-1, the input terminal of the cell 41 is connected to the output terminal (supply line through which the control signal cont(1) is supplied) of the high-speed control logic 32 that outputs the control signal control t(1). The output terminal of the cell 41 is connected to the output terminal V out The high voltage terminal of the cell 41 is connected to the output of the high voltage V generated by the constant voltage generating circuit 33. H The low voltage terminal of the unit 41 is connected to the GND terminal. Therefore, the four units 41 are connected in parallel to each other and always perform the same operation, thereby constituting an equivalent Figure 4 The control number in the driver D1 is 1 and the output resistor 3R term circuit.

[0115] With respect to the six cells 41 of the cell driver 31-2, the input terminal of the cell 41 is connected to the output terminal (supply line through which the control signal cont(2) is supplied) of the high-speed control logic 32 that outputs the control signal Cont(2). The output terminal of the cell 41 is connected to the output terminal V out The high voltage terminal of the cell 41 is connected to the output of the high voltage V generated by the constant voltage generating circuit 33. H The low voltage terminal of the unit 41 is connected to the GND terminal. Therefore, the six units 41 are connected in parallel to each other and always perform the same operation, thereby constituting an equivalent Figure 4 The control number in the driver D2 is 2 and the output resistor 2R term circuit.

[0116] according to Fig.10 In the first example, the unit drivers 31-0 to 31-2 constitute Figure 4 In addition, the potential of GND (0V) is used as the low voltage V Lis applied to the cell drivers 31-0 to 31-2. Since the cell drivers 31-0 to 31-2 can be configured using the cell 41 having the same configuration, the transmitter 11-1 can be easily manufactured and space saving can be achieved. It should be noted that the cell drivers 31-0 to 31-2 can include one cell 41, two cells 41, and three cells 41, respectively, wherein the cell resistor R of each cell 41 is out The resistance value is 6·R term In addition, the ratio of the number of cells 41 constituting each of the cell drivers 31-0 to 31-2 matches the ratio of the reciprocal numbers of the output resistors R0 to R2 of the control numbers 0 to 2 constituted by the cell drivers 31-0 to 31-2. Figure 3 As shown in FIG. 1 , the above expression (1) limits the ratio of the resistance values ​​R0 to R2 of the output resistors R0 to R2 and does not limit the resistance values ​​of the output resistors R0 to R2. Fig.10 In the first example, when the number of states N is 7, the ratio of the resistance values ​​R0 to R2 needs to be 6:3:2, as shown in Figure 3 At this time, since the ratio of the reciprocal of the resistance value R0 to R2 is 1:2:3, the unit 41 of the unit drivers 31-0 to 31-2 constituting the drivers D0 to D2 of the control numbers 0 to 2 and the output resistor 02 The ratio of the number of R0 to R2 may be 1:2:3. The number of cells 41 constituting the cell drivers 31-0 to 31-2 may be a value obtained by multiplying 1, 2, and 3 by any natural number, respectively. Similarly, the number of cells 41 is not limited to the following reference number. Figures 11 to 14 The second example to the fourth example and so on described.

[0117] <Second Example of Transmitter 11-1>

[0118] Fig.11 It is shown Figure 4 FIG. 1 is a configuration diagram of a second example (case of N=7) of the transmitter 11-1 in FIG. Fig.10 Those identical parts in the drawings are given the same figure marks, and their description is omitted. Fig.11 The second example in Fig.10 The first example in FIG. 1 is different in that a constant voltage generating circuit 34 (depicted as a constant voltage generating circuit 2 in the figure) is included. Note that a constant voltage generating circuit 33 that generates and outputs a high voltage terminal is shown as a constant voltage generating circuit 1.

[0119] The low voltage terminal of the cell 41 in each cell driver 31 - 0 to 31 - 2 is connected to the output of the low voltage V generated by the constant voltage generating circuit 34. L According to the terminal. Fig.11In the second example, the unit drivers 31-0 to 31-2 constitute Figure 4 The circuit of the transmitter 11-1 in Fig.10 In addition, the low voltage V generated by the constant voltage generating circuit 34 is L Instead of GND potential as low voltage V L is applied to the unit drivers 31 - 0 to 31 - 2 .

[0120] <Third Example of Transmitter 11-1>

[0121] Fig.12 It is shown Figure 4 FIG. 1 is a configuration diagram of a third example (case of N=7) of the transmitter 11-1 in FIG. Fig.10 Those identical parts in the drawings are given the same figure marks, and their description is omitted. Fig.12 The third example in Fig.10 The first example in FIG. 1 is different in that the constant voltage generating circuit 33 is not provided. The high voltage terminal of the cell 41 in each cell driver 31-0 to 31-2 is connected to the power supply terminal. The high voltage V from the external voltage source H is supplied to the power supply terminal.

[0122] according to Fig.12 In the third example, the unit drivers 31-0 to 31-2 constitute Figure 4 The circuit of the transmitter 11-1 in Fig.10 In addition, the high voltage V can be supplied from any external power supply H , without accompanying the unit drivers 31-0 to 31-2 and generating the high voltage V H The constant voltage generating circuit 33, such as Fig.10 shown.

[0123] <Fourth Example of Transmitter 11-1>

[0124] Fig.13 It is shown Figure 4 FIG. 1 is a configuration diagram of a fourth example (case of N=7) of the transmitter 11-1 in FIG. Fig.10 The same parts in FIG. 1 are given the same reference numerals, and their description is omitted. Fig.13 In the fourth example in FIG. 1 , the configuration of the unit 42 in each of the unit drivers 31 - 0 to 31 - 2 is the same as Fig.10 The configuration of the unit 41 is different, and the unit drivers 31-0 to 31-2 each include a unit 42. A resistor MOSFET is connected in each unit 42, instead of Fig.10 The unit resistor R of each unit 41 outThe DC voltage from the DC control logic (logic circuit) 35 is applied to the gate of the resistance MOSFET, and the resistance value of the on-resistance between the source and the drain of the resistance MOSFET changes according to the voltage value of the DC voltage. The resistance values ​​of the on-resistance of the resistance MOSFET in the cells 42 of the cell drivers 31-0 to 31-2 are adjusted to 6R term 、3R term and 2R term , i.e., adjusted in such a way as to achieve a ratio of 6:3:2. Therefore, the unit driver 31-0 configuration is equivalent to Figure 4 The control number in the driver is 0, D0, and the output resistor is 6R term The circuit of the unit driver 31-1 is configured equivalent to Figure 4 The control number in the driver D1 is 1 and the output resistor 3R term The circuit of the unit driver 31-2 is equivalent to Figure 4 The control number in the driver D2 is 2 and the output resistor 2R term circuit.

[0125] according to Fig.13 In the fourth example, the unit drivers 31-0 to 31-2 constitute Figure 4 The circuit of the transmitter 11-1 in Fig.10 Same as in.

[0126] <Fifth Example of Transmitter 11-1>

[0127] Fig.14 It is shown Figure 4 FIG. 1 is a configuration diagram of a fifth example (case of N=7) of the transmitter 11-1 in FIG. Fig.10 Those identical parts in the drawings are given the same figure marks, and their description is omitted. Fig.14 The fifth example is by applying Figure 4 An example of a case where the transmitter 11-1 is configured to output a multi-level signal for differential transmission. Fig.14 In the example, the unit drivers 31-0 to 31-2 have Fig.10 The same configuration as in FIG. 1 is used, and its output terminal is connected to the output terminal V for the p output (forward output) of the transmitter 11-1. out (Indicated as output terminal P in the figure).

[0128] The unit drivers 51-0 to 51-2 have the same configuration as the unit drivers 31-0 to 31-2, respectively. However, for the two units 41 in the unit driver 51-0, the input terminal of the unit 41 is connected to the output terminal of the high-speed control logic (logic circuit) 32 that outputs the control signal Cont(0) via the NOT circuit. Therefore, the inverted value of the control signal cont(0) is input to the input terminal of the unit 41. The output terminal of the unit 41 is connected to the output terminal V out (represented as output terminal N in the figure), the output terminal V out The high voltage terminal of the unit 41 is connected to the output terminal of the constant voltage generating circuit 33 to output the high voltage V H The low voltage terminal of the unit 41 is connected to the GND terminal. Therefore, the two units 41 are connected in parallel to each other and always perform the same operation, thereby constituting an equivalent Figure 4 The control number in the driver is 0, D0, and the output resistor is 6R term circuit.

[0129] For the four cells 41 in the cell driver 51-1, the input terminal of the cell 41 is connected to the output terminal of the high-speed control logic (logic circuit) 32 that outputs the control signal Cont(1) via the NOT circuit. Therefore, the inverted value of the control signal cont(1) is input to the input terminal of the cell 41. The output terminal of the cell 41 is connected to the output terminal V out , the output terminal V out The high voltage terminal of the unit 41 is connected to the output terminal of the constant voltage generating circuit 33 to output the high voltage V H The low voltage terminal of the unit 41 is connected to the GND terminal. Therefore, the four units 41 are connected in parallel to each other and always perform the same operation, thereby constituting an equivalent Figure 4 The control number in the driver D1 is 1 and the output resistor 3R term circuit.

[0130] For the six cells 41 in the cell driver 51-2, the input terminal of the cell 41 is connected to the output end of the high-speed control logic (logic circuit) 32 that outputs the control signal Cont(2) via a NOT circuit. Therefore, the inverted value of the control signal cont(2) is input to the input terminal of the cell 41. The output terminal of the cell 41 is connected to the output terminal V out , the output terminal V out The high voltage terminal of the unit 41 is connected to the output terminal of the constant voltage generating circuit 33 to output the high voltage VH The low voltage terminal of the unit 41 is connected to the GND terminal. Therefore, the six units 41 are connected in parallel to each other and always perform the same operation, thereby constituting an equivalent Figure 4 The control number in the driver D2 is 2 and the output resistor 2R term circuit.

[0131] according to Fig.14 In the fifth embodiment, the unit drivers 31-0 to 31-2 constitute Figure 4 The transmitter 11-1 circuit in FIG. 1 is a circuit in which a forward transmission signal is transmitted from an output terminal V for p output (for forward output) out The unit drivers 51-0 to 51-2 also constitute Figure 4 The circuit of the transmitter 11-1 in FIG. 1 is configured to control the inverted values ​​of the control signals cont(0) to cont(2) to be input to the unit drivers 51-0 to 51-2, respectively. Therefore, the inverted transmission signal is transmitted from the output terminal V of the negative sign for n output (for inverted output) to the output terminal V of the negative sign for n output (for inverted output). out Note that in the fifth example, the configurations in the second example to the fourth example can also be applied.

[0132] <Example of Circuit Configuration of Unit 41 in Unit Drivers 31 - 0 to 31 - 2 >

[0133] exist Fig.10 In the first example of the transmitter 11-1 in FIG. 1 , the circuit configuration of the unit 41 constituting each of the unit drivers 31-0 to 31-2 is not limited to that in Fig.10 The situation shown in . Fig.15 4 is a diagram showing another example of the circuit configuration of the unit 41. Fig.15 Unit 42 is Fig.13 In the fourth example, the cell 42 is connected with a resistor MOSFET instead of Fig.10 The unit resistor R of unit 41 out . Note that already in Fig.13 Unit 42 is described in the fourth example of , and its description is omitted here.

[0134] Fig.16 4 is a diagram showing another example of the circuit configuration of the unit 41. Fig.16 In the embodiment, the cell 43 is configured by only a pair of n-type MOSFETs in the cell driver D instead of Fig.10 An example of a circuit configuration in the case of a CMOS configuration constituting a unit driver D in the unit 41 shown in FIG. A forward control signal cont is input to the gate of one n-type MOSFET, and a reverse control signal cont (an inverted value of the control signal cont) is input to the gate of another n-type MOSFET. Fig.17 4 is a diagram showing another example of the circuit configuration of the unit 41. Fig.17 In the embodiment, the cell 44 is configured by only a pair of p-type MOSFETs in the cell driver D instead of Fig.10 An example of a circuit configuration in the case where the unit 41 shown in FIG. is configured by a CMOS constituting the unit driver D. A forward control signal cont is input to the gate of one p-type MOSFET, and a reverse control signal cont (an inverted value of the control signal cont) is input to the gate of another p-type MOSFET. Fig.18 4 is a diagram showing another example of the circuit configuration of the unit 41. Fig.18 , the cell 45 is an example of a circuit configuration including a cell driver D (eg, a current mode logic (CML) driver) having a general configuration using an n-type MOSFET.

[0135] <First Mode of Receiver 12>

[0136] Fig.19 It is shown Figure 1 Schematic diagram of a configuration example of a first mode of the receiver 12 in FIG. Fig.19 The data transmission system in is a single-line single-phase communication system, and the transmitter 11 is in Figure 2 In the first mode in the embodiment, a multi-level output driver is used to output a transmission signal (a multi-level signal with N states) of N multi-levels (voltage levels) using a transmitter 11-1, etc. Note that it is assumed that the number of states N is 4. The encoder 71 generates M-bit (control value M) control signals cont(0) to cont(M-1) for converting data to be transmitted to the receiver 12 into a multi-level signal, and provides the generated control signal to the transmitter 11. The transmitter 11 generates a multi-level signal based on the control signals cont(0) to cont(M-1) from the encoder 71, and transmits the multi-level signal to the receiver 12 via the transmission path 13. Since the number of states N is 4 in this specification, the control value M is 2.

[0137] The receiver 12 includes a plurality of samplers (comparators) 72A to 72C. Since the number of samplers 72A to 72C is equal to the number of states N-1 and the number of states N is 4, the receiver 12 includes three samplers 72A to 72C. The multilevel signal transmitted from the transmitter 11 is input to the positive input terminal of each of the samplers 72A to 72C. Reference voltages 1 to 3 are input to the negative input terminal of each of the samplers 72A to 72C. Each of the samplers 72A to 72C compares the voltage of the multilevel signal input to the positive input terminal with the reference voltage input to the negative input terminal, and outputs 0 or 1 according to the amplitude relationship therebetween. For example, the samplers 72A-72C output 1 when the former is less than or equal to the latter, and output 0 when the former is greater than the latter. The reference voltage 1 input to the negative input terminal of the sampler 72A is set to a voltage greater than the voltage V0 of the state number 0 of the multilevel signal and less than the voltage V1 of the state number 1. As a result, in the case where the multilevel signal has the voltage V0 of the state number 0, 1 is output from the sampler 72A. In the case where the multilevel signal has the voltage V1 of the state number 1, the voltage V2 of the state number 2, or the voltage V3 of the state number 3, 0 is output from the sampler 72A. The reference voltage 2 input to the negative input terminal of the sampler 72B is set to a voltage greater than the voltage V1 of the state number 1 of the multilevel signal and less than the voltage V2 of the state number 2. As a result, in the case where the multilevel signal has the voltage V0 of the state number 0 or the voltage V1 of the state number 1, 1 is output from the sampler 72B. In the case where the multilevel signal has the voltage V2 of the state number 2 or the voltage V3 of the state number 3, 0 is output from the sampler 72B. The reference voltage 3 input to the negative input terminal of the sampler 72C is set to a voltage greater than the voltage V2 of the state number 2 of the multilevel signal and less than the voltage V3 of the state number 3. As a result, when the multilevel signal has voltage V0 of state number 0, voltage V1 of state number 1, or voltage V2 of state number 2, 1 is output from sampler 72C. When the multilevel signal has voltage V3 of state number 3, 0 is output from sampler 72C.

[0138] The decoder 73 detects multiple levels (voltage levels) of the multilevel signal based on the output values ​​of the samplers 72A- 72C, and decodes the multiple levels into data based on the detected multiple levels before conversion into the multilevel signal performed by the encoder 71 and the transmitter 11 .

[0139] <Second Mode of Receiver 12>

[0140] Fig. 20 It is shown Figure 1 Schematic diagram of a configuration example of a second mode of the receiver 12 in FIG. Fig. 20The data transmission system in the embodiment is a two-wire differential communication system, and the transmitter 11 is a multi-level output driver, using the Fig.14 The transmitter 11-1 of the fifth example in the embodiment outputs N multi-level (voltage level) forward transmission signals (multi-level signals of multiple states N) and reverse transmission signals (multi-level signals of multiple states N). The transmitter 11 includes a transmitter 11A that outputs N multi-level forward transmission signals and a transmitter 11B that outputs N multi-level reverse transmission signals. Note that it is assumed that the number of states N is 4. The encoder 71 generates M-bit (control value M) control signals cont(0) to cont(M-1) for converting data to be transmitted to the receiver 12 into multi-level signals, and provides the generated control signals to each transmitter 11A and 11B. Because the number of states N is 4 in this specification, the control value M is 2. The transmitter 11 includes a transmitter 11A for P output (forward output) and a transmitter 11B for n output (reverse output). The transmitters 11A and 11B generate and output a forward multilevel signal and a reverse multilevel signal, respectively, based on control signals cont(0) to cont(M-1) from the encoder 71. The transmission path 13 includes transmission paths 13A and 13B, and the transmission path 13A transmits the forward multilevel signal output from the transmitter 11A to the receiver 12. The transmission path 13B transmits the inverted multilevel signal output from the transmitter 11B to the receiver 12.

[0141] Receiver 12 includes a plurality of samplers (comparators) 82A to 82C. Since the number of samplers 82A to 82C is equal to the number of states N-1 and the number of states N is 4, receiver 12 includes three samplers 82A to 82C. The forward multi-level signal sent from transmitter 11A is input to the positive input terminal of each of samplers 82A to 82C. The forward multi-level signal sent from transmitter 11B is input to the negative input terminal of each of samplers 82A to 82C. In addition, reference voltages 1 to 3 are input to the reference voltage input terminal of each of samplers 82A to 82C. Samplers 82A to 82C each generate a differential signal (differential signal), and the differential signal is compared with the reference voltage input to the reference voltage input terminal, and the differential signal is the difference between the voltage of the forward multi-level signal input to the positive input terminal and the voltage of the reverse multi-level signal input to the negative input terminal. The samplers 82A to 82C each output 0 or 1 according to the amplitude relationship between the differential signal and the reference voltage. For example, the samplers 82A-82C output 1 when the former is less than or equal to the latter, and output 0 when the former is greater than the latter. The differential signal can take one of four voltage levels corresponding to state numbers 0 to 3. Therefore, the reference voltages 1 to 3 input to the reference voltage input terminals of the samplers 82A to 82C are set to voltages between the four voltage levels of state numbers 0 to 3 that can be taken by the differential signal, as in Fig.19 The details of the case where the samplers 82A to 82C output 0 or 1 are the same as Fig.19 The situation in the first example in is similar, and its description is omitted. The decoder 83 detects multiple levels (voltage levels) of the multi-level signal based on the output values ​​of the samplers 72A-72C, and based on the detected multiple levels, decodes the multiple levels into data before conversion into a multi-level signal performed by the encoder 81 and the transmitter 11.

[0142] <Third Mode of Receiver 12>

[0143] Fig.21 It is shown Figure 1 Schematic diagram of an example of a configuration of a third mode of receiver 12 in FIG. Fig.21The data transmission system in is a three-wire differential communication system adopted in a data transmission standard such as MIPI C-PHY, and the transmitter 11 is a multi-level output driver that outputs a transmission signal of N multiple levels (voltage levels) (multi-level signals of multiple states N). Note that it is assumed that the number of states N is 4. The transmitter 11 includes three transmitters 11A to 11C that output N multi-level transmission signals, and based on a difference signal (differential signal) between a transmission signal output from the transmitter 11A and a transmission signal output from the transmitter 11B, a difference signal between a transmission signal output from the transmitter 11B and a transmission signal output from the transmitter 11C, and a difference signal between a transmission signal output from the transmitter 11C and a transmission signal output from the transmitter 11A, the receiver 12 recognizes the N multi-levels. The encoder 91 generates M-bit (control value M) control signals cont(0) to cont(M-1) for converting data to be transmitted to the receiver 12 into a multi-level signal, and provides the generated control signal to each of the transmitters 11A to 11C. Since the number of states N is 4 in this specification, the control value M is 2. The transmitters 11A to 11C of the transmitter 11 generate and output multilevel signals based on the control signals cont(0) to cont(M-1) from the encoder 71, respectively. The transmission path 13 includes transmission paths 13A to 13C, and the transmission path 13A transmits the multilevel signal output from the transmitter 11A to the receiver 12. The transmission path 13B transmits the multilevel signal output from the transmitter 11B to the receiver 12. The transmission path 13C transmits the multilevel signal output from the transmitter 11C to the receiver 12.

[0144] The receiver 12 includes three differential multi-level samplers 12A to 12C. The differential multi-level samplers 12A to 12C each have a Fig. 20 82A to 82C in the receiver 12. The transmission signal (multi-level signal) from the transmitter 11A and 11B is input to the differential multi-level sampler 12A, and multiple levels (voltage levels) of the differential signal are detected based on the differential signal. The transmission signal (multi-level signal) from the transmitter 11B and 11C is input to the differential multi-level sampler 12B, and multiple levels (voltage levels) of the differential signal are detected based on the differential signal. The transmission signal (multi-level signal) from the transmitter 11C and 11A is input to the differential multi-level sampler 12C, and multiple levels (voltage levels) of the differential signal are detected based on the differential signal. The decoder 92 detects multiple levels (voltage levels) based on the output values ​​of the samplers 12A to 12C, and based on the detected multiple levels, the multiple levels are decoded into data before being converted into a multi-level signal performed by the encoder 91 and the transmitter 11.

[0145] <Comparison between transmitter 11 applying the present technology and comparative technologies 1 and 2>

[0146] Fig. 22 is a diagram showing a transmitter 11 ( Figure 2 1) and comparison techniques 1 and 2. Comparison technique 1 is the technique of the transmitter disclosed in JP5-336174A and WO 2011 / 045830 A of Patent Documents 1 and 2. Comparison technique 2 is the technique of the transmitter disclosed in JP 10-303994A and JP 11-154859A.

[0147] Fig.23 is a schematic diagram of the transmitter in Comparative Technology 1. Fig.23 In the embodiment, the transmitter 401 outputs N multi-level transmission signals (a multi-level signal with N states). The transmitter 401 includes multiplexers (selectors) MUX(0) to MUX(N-1) and an output resistor R term . Each of the multiplexers MUX(0) to MUX(N-1) includes a first input terminal, a second input terminal, an output terminal, and a selection terminal. In the first input terminal and the second input terminal of each of the multiplexers MUX(0) to MUX(N-1), the terminal internally connected to the output terminal is switched according to the value (0 or 1) of the control signal cont(0) to cont(N-1) input to the selection terminal. Note that it is assumed that when the value of the control signal Cont is 0, the first input terminal is connected to the output terminal, and when the value of the control signal cont is 1, the second input terminal is connected to the output terminal. The voltages V0 to V N-1 The voltage V of the state number n is output from the transmitter 401. n In the case of a multi-level signal, the value of the control signal cont(n) input to the selection terminal of the multiplexer MUX(n) is set to 0, and the voltage V applied to the first input terminal is n The output terminal of the multiplexer MUX(n) is output. For multiplexers other than the multiplexer MUX(n), the value of the control signal is set to 1, and a high impedance element is connected to the output terminal. As a result, the output terminal V of the transmitter 401 is output. out Output voltage V with state number n n The multi-level signal is used as the transmission signal.

[0148] Fig.24 is a schematic diagram of the transmitter in Comparative Technology 2. Fig.24In the transmitter 411, the Figure 2 The same circuit configuration as the transmitter 11-1 in the first mode shown in FIG. Figure 2 The components of the transmitter 11-1 in FIG. 4 are provided with the same reference numerals. However, the output resistors R0 to R1 in the transmitter 411 are M-1 Different from the transmitter 11 - 1 in the first mode, and is determined by the following expression (4).

[0149] [Formula 4]

[0150]

[0151] The transmitter 401 of the above-mentioned comparative technique 1 and the transmitter 411 of the comparative technique 2 are compared with the transmitter 11 applying the present technique. Fig. 22 As shown in the first row of FIG. 1 , the transmitter 401 of the comparative technique 1 needs to provide the transmitter 401 with as many voltages V0 to V1 as the number N of the multiple levels of the multi-level signal (the number N of states). N-1 In addition, it is necessary to supply the transmitter 401 with as many control signals cont(0) to cont(N-1) as the number of states N. The circuit area is therefore increased.

[0152] on the other hand, Figure 2 The transmitter 11 (11-1) of the present technology shown in FIG. 1 only needs to include a low voltage V L and high voltage V H Two power supplies are supplied to the transmitter 11 regardless of the number of states N. In addition, since the transmitter 11 of the present technology does not require a multiplexer, a control signal for controlling the multiplexer is also unnecessary. Therefore, the circuit area can be reduced.

[0153] like Fig. 22 As shown in the sixth row of FIG. , in the transmitter 411 of the comparative technique 2, the low voltage V L and high voltage V H The voltage range of cannot be used as the maximum of multiple levels of a multi-level signal. For example, Fig.25 FIG. 4 shows a configuration of a transmitter 411 for outputting a multi-level signal whose number of output states N is 7. The control value M is 3. The resistor value 7R term , 3.5R term and 1.75R term The resistance values ​​of the output resistors R0 to R2 of the control numbers 0 to 2 indicated are the values ​​calculated by the above expression (4).

[0154] Fig.26 It is shown Fig.25 FIG. 4 is a diagram of the operation of transmitter 411 in FIG. Fig.26, signal numbers X of 0 to 7 are shown in the leftmost column. Signal number X is a value obtained by expressing 3-bit digital data indicated by control signals cont(0) to cont(2) in decimal. In each row of signal number X, the value (0 or 1) of control signals cont(0) to cont(2) and the value of the control signals cont(0) to cont(2) are shown. out Normalized output voltage V of output state number n n According to this, every time the signal number X increases from 0 to 1, the state number n increases by 1, and the normalized output voltage V n Increase by 1 / 7 at equal intervals. In the case where the number of states N is 7, output voltages V0 to V6 of state number n in the case where signal number X is 0 to 6 are used as voltage levels of the multi-level signal, and output voltage V7 of state number n in the case where signal number X is 7 is not used, so as to maintain a constant interval between possible voltage levels of the multi-level signal. Fig. 27 shows the output voltage V at any control number n (0 to 6) n Change to another control number n (0 to 6) output voltage V n The normalized output voltage V out The horizontal axis represents time and the vertical axis represents the normalized output voltage V out .also, Fig. 27 FIG. 1 shows a graph in which the normalized output voltage V is obtained within a specific time period after the control signals cont(0) to cont(2) are changed by 0.1 (ns) and 1.1 (ns). out The state has been changed to the normalized output voltages V0 to V6 of control numbers 0 to 6.

[0155] Under the assumption that the state number N is a power of 2 (Mth power) and by not using the output voltage of one of the state numbers 0 to N-1, by determining the output resistors R0 to R1 for each control number m M-1 The transmitter 411 of the prior art 2 corresponds to the case where the number of states N is a value different from a power of 2. Fig.25 In the example of the configuration in , under the assumption that the number of states N is 8 (the cube of 2), the output resistors R0 to R1 with control numbers 0 to 2 are determined. M-1 The resistance value of Fig.26 and Fig. 27 It can be seen that the transmitter 411 with the state number N being 7 is obtained by using only the output voltages V0 to V6 of the state numbers 0 to 6 among the state numbers 0 to 7. The normalized output voltages V0 to V6 of the state numbers 0 to 6 represent values ​​at regular intervals, but since the normalized output voltage V7 of the state number 7 is not used, 1, which is the original maximum value of the normalized output voltage, is not used for the multi-level signal. Lis 0 (volts) and the high voltage V H When V (volts), for example, the difference between the minimum voltage and the maximum voltage of the multi-level signal output from the transmitter 411 is (6 / 7)·V (volts). Fig. 22 As suggested by the seventh row in , a voltage loss of about 14% is involved. The signal amplitude is a parameter directly associated with the reception availability on the receiver side, and even if the signal amplitude is increased by raising the voltage V, for example, it is disadvantageous in terms of power.

[0156] On the other hand, the circuit configuration and operation in the case where the number of states N in the transmitter 11 of the present technology is 7 are as shown in FIG. Figures 4 to 6 described, and the low voltage V L With high voltage V H The voltage range between is used as the multi-level level of the multi-level signal to the greatest extent. For example, at the low voltage V L is 0 (volts) and the high voltage V H When the voltage is V (volts), when the signal number X is 3 and 4, the output voltage V3 of the state number 3 overlaps at (3 / 6)·V, as shown in Figure 5 and Figure 6 In addition, the output resistors R0 to R2 of control numbers 0 to 2 M-1 The resistance value of is set so that the output voltages V0 to V6 of the state numbers 0 to 6 become six voltage levels obtained by equally dividing (dividing into five equal parts) the voltage range from 0 (volt) to V (volt). Therefore, even in the case where the state number N is a value different from 2, the transmitter 11 of the present technology can output a multi-level signal using the entire voltage range between 0 (volt) and V (volt), and there is no disadvantage such as voltage loss in the transmitter 411 of the prior art 2.

[0157] In addition, in the transmitter 401 of the comparative technique 1, as Fig. 22 As shown in the eighth row in , it is necessary to prepare a control signal to be supplied to the transmitter 401 according to the number N of states of the multilevel signal (the number N of multiple levels), which is disadvantageous in terms of AC power and is not suitable for acceleration due to wiring capacitance.

[0158] On the other hand, in the transmitter 11 of the present technology, as Fig. 22As shown in the eighth and ninth rows of , the number of high-speed signal lines for providing control signals to the transmitter 11 can be equal to the control value M, which is advantageous in terms of high speed and AC power for the transmitter 401 of the comparative technique 1. In addition, in the case of differential transmission using the transmitter 11 of the present technique, the control signal for the inversion driver can be easily implemented by inversion of the control signal cont, and the control logic can be simplified. In this regard, the transmitter 11 of the present technique is more advantageous than the transmitter 411 of the comparative technique 2 in terms of AC power.

[0159] It should be noted that the above-mentioned comparison between the transmitter 11 of the present technology and the comparative technologies 1 and 2 is not limited to the first mode of the transmitter 11 , and is also applicable to other modes such as the second mode and the third mode, which will be described below.

[0160] <<Second Mode of Transmitter 11>>

[0161] Fig.28 It is shown in Figure 1 FIG. 1 is a diagram showing an example of a configuration of a second mode of the transmitter 11 in FIG. Fig.28 The transmitter 11-2 in the second mode has a configuration that can set or change the number N of states to any one of 7, 3, and 2. The transmitter 11-2 includes drivers D0 to D2, a resistor of 6R term 、3R term and 2R term denoted by output resistors R0 to R2, and multiplexers MUX(0) and MUX(1). The output terminal of multiplexer MUX(1) is connected to the input terminal of driver D0, and the output terminal of multiplexer MUX(0) is connected to the input terminal of driver D0. Control signal cont(2) is input to the input terminal of driver D2. Low voltage V is applied to drivers D0 to D2 respectively. L and high voltage V H In this mode, it is assumed that the low voltage V L is the GND potential (0), the high voltage V H Yes V REG The output terminals of the drivers D0 to D2 are connected to the output terminal V of the transmitter 11-2 via the output resistors R0 to R2, respectively. out(Transmission line for transmitting multi-level signals). Multiplexers MUX(0) and MUX(1) each include a first input terminal, a second input terminal, an output terminal, and a selection terminal. In each of the first input terminal and the second input terminal of multiplexers MUX(0) and MUX(1), a selection signal (mode value) Mode is input to the selection terminal. <0> and Mode <1> The value (0 or 1) of the mode value switches the terminal connected to the output terminal internally. <0> When the first input terminal represented by "0" is connected to the output terminal, and the mode value Mode <0> When it is 1, the second input terminal represented by "1" is connected to the output terminal. The control signal cont(2) is input to the first input terminal of the multiplexer MUX(0), and the control signal cont(1) is input to the second input terminal. The output terminal of the multiplexer MUX(0) is connected to the input terminal of the driver D1 and to the first input terminal of the multiplexer MUX(1). The control signal cont(0) is input to the second input terminal of the multiplexer MUX(1), and the output terminal of the multiplexer MUX(1) is connected to the input terminal of the driver D0.

[0162] Here, the mode values ​​Mode<0> and Mode<1> are set to 0 or 1, respectively. In addition, the bit in the 1st bit (the first bit) of the two bits is set to the mode value Mode <0> The value of , and the bit in bit 2 (the second bit) is set to the mode value Mode <1> At this time, the mode value of the two-digit binary number is represented as Mode<1:0> and is mainly represented as a decimal number. <0> and mode value Mode <1> When both are 1 and the mode values ​​Mode<1:0> are 3, control signals cont(0) to cont(2) are input to drivers D0 to D2, respectively. Figure 4 The transmitter 11 - 1 shown in FIG. 1 operates similarly, and outputs a multi-level signal whose state number N is 7. Fig.29 is a diagram showing the operation of the transmitter 11 - 2 in a case where the mode value Mode<1:0> is 3. Fig.29 The value of each of the control signals cont(0) to cont(2) and the output voltage V of the transmitter 11-2 are shown. out The relationship between Fig.29 In each row, the signal number X at the values ​​of the control signals cont(0) to cont(2) increases by 1 from the top from 0 to 7. When the signal number X is 0 to 3, the output voltage V out Increase from 0 to (1 / 6) V REG When the signal number X is 3 and 4, since the output voltage V out In (3 / 6) VREG The state number n does not change. When the signal number X is 4 to 7, the output voltage V out From (3 / 6) · V REG Increase to (1 / 6) V REG Therefore, in the case where the mode value Mode<1:0> is 3, the transmitter 11 - 2 outputs a multi-level signal whose state number N is 7.

[0163] In the mode value Mode <0> is 1 and the mode value is Mode <1> When it is 0, the mode value Mode<1:0> is 1. In this case, the control signals cont(1) and cont(2) are input to the drivers D1 and D2, respectively. On the other hand, the control signal cont(1) is input to the driver D0. Fig.30 is a diagram showing the operation of the transmitter 11 - 2 in a case where the mode value Mode<1:0> is 1. Fig.30 The value of each of the control signals cont(0) to cont(2) and the output voltage V of the transmitter 11-2 are shown. out When the mode value Mode<1:0> is 1, the same value (the value of the control signal cont(1)) is always input to the drivers D0 to D1 regardless of the value of the control signal cont(0), and it can be considered that when the mode value <1:0> is 3, Fig.29 One of the values ​​of control signals cont(0) to cont(2) in which the signal number X is 0, 3, 4, and 7 is input to drivers D0 to D2. Fig.30 The rows in FIG. 1 represent, in order from the top, the values ​​of the control signals cont(1) and cont(2) and the output voltage V of the transmitter 11-2 when the signal number X is 0, 3, 4, and 7. out When the signal number X is 3 and 4, since the output voltage V out In (3 / 6) V REG Therefore, when the mode value Mode<1:0> is 1, the transmitter 11 - 2 outputs a multi-level signal with a state number N of 3.

[0164] In the mode value Mode <0> is 0 and the mode value is Mode <1> When it is 0, the mode value Mode<1:0> is 0. In this case, the control signal cont(2) is input to all drivers D0 to D2. Fig.31 is a diagram showing the operation of the transmitter 11 - 2 in a case where the mode value Mode<1:0> is 0. Fig.31 The value of the control signal cont(2) and the output voltage V of the transmitter 11-2 are shown. nWhen the mode value Mode<1:0> is 0, the same value (the value of the control signal cont(2)) is always input to the drivers D0 to D2 regardless of the values ​​of the control signals cont(0) and cont(1), and it can be considered that when the mode value <1:0> is 3, Fig.29 One of the values ​​of control signals cont(0) to cont(2) in which the signal number X is 0 and 7 is input to drivers D0 to D2. Fig.31 The rows in FIG. 1 indicate the values ​​of the control signal cont(2) and the output voltage V of the transmitter 11-2 when the control number X is 0 and 7. out Start from the top in order. Since the output voltage V is 0 and 7 respectively when the signal number X is out is 0 and V REG Therefore, when the mode value Mode<1:0> is 0, the transmitter 11 - 2 outputs a multi-level signal whose state number N is 2.

[0165] When the transmitter 11 - 2 is in the second mode, since the mode value Mode<1:0> is 3, the resistor value 6R term 、3R term and 2R term The output resistors R0 to R2 correspond to Figure 3 The output resistors R0 to R2 of control numbers 0 to 2 in the control value 7 in the transmitter 11-2 are set to 7. In the case where the mode value Mode<1:0> is 1, since the output resistors R0 and R1 are connected in parallel to each other and the resistance value thereof becomes 2R term , so the output resistors R0 and R1 correspond to Figure 3 The output resistor R0 in the control value 3 in the control number 0. The output resistor R2 corresponds to Figure 3 The control value in 3 is the output resistance R1 of control number 1. Assuming Fig.28 The control signals cont(1) and cont(2) in Figure 3 The control signal cont(0) and the control signal cont(1) of the control numbers 0 and 1 in FIG. 11 are respectively set. Therefore, the number N of states of the transmitter 11-2 is set to 3. It should be noted that the output resistors R0 and R1 may correspond to Figure 3 The output resistor R1 of the control value 3 in the control number 1, and the output resistor R2 may correspond to Figure 3 In the case where the mode value Mode<1:0> is 0, since the output resistors R0 to R2 are connected in parallel to each other and their resistance values ​​become R term , so the output resistors R0 to R2 correspond to Figure 3The output resistor R0 of the control number 0 in the control value 2 in the transmitter 11-2 is thus set to 2. Assuming Fig.28 The control signal cont(2) in Figure 3 0 in the control signal cont(0). As described above, by setting the control signals to be input to the plurality of drivers to control signals of different control numbers (control numbers whose values ​​are independently determined), or by setting a subset or all of the control signals to control signals of the same control number, the resistance value of the output resistor of each control number can be changed, or the control value can be changed. As a result, the number N of states can be changed.

[0166] <<Third Mode of Transmitter>>

[0167] Fig.32 It is shown in Figure 1 Schematic diagram of an example of a configuration of a third mode of the transmitter 11 in FIG. Fig.32 The transmitter 11-3 in the third mode has a configuration in which Fig.28 The transmitter 11-2 in the second mode in FIG. 1 can change the number of states N. In addition, in the third mode, the transmitter 11-2 in the second mode in FIG. 1 can change the number of states N. Fig.10 The cell driver D and the cell resistor L·R are installed in the same manner as in the cell 41 of the first example of the transmitter 11-1 in the first mode. term A plurality of (L) units U of the same circuit configuration and circuit characteristics are connected in parallel to each other. It should be noted that, as described above, the unit driver D and the unit resistor L·R as the output resistor of the unit driver D term It can be regarded as an equivalent circuit representing one unit driver D. The multiplexer MUX is installed on each unit U, and the units U performing the same operation are set or changed by the multiplexer MUX based on the control signal of the same control number. Therefore, the unit driver including one or more units U is configured to Fig.10 The unit drivers 31-0 to 31-2 in the same manner can be changed, and the number of unit drivers and the number of units U constituting the unit drivers can be changed. Since the control signal based on the different control number m and the output resistor R of the control number m can be changed m The resistance value R m The number of unit drivers (referred to as unit drivers of control number m) of the unit driver D can be controlled so that the number of states N of the multi-level signal output by the transmitter 11-3 can be changed, wherein the output resistor R of the control number m m The output resistors L·R connected in parallel to each other in the unit driver of each control number m term constitute.

[0168] exist Fig.32In the embodiment, the transmitter 11-3 includes a plurality of (L) units U. The units U have the same circuit configuration and circuit characteristics, and are connected by a unit driver D, a resistor value L·R term The unit resistor L·R term , and a multiplexer MUX are mounted on one IC chip or one substrate to configure each unit U. Each unit U includes: an input terminal (first input terminal to Mth input terminal) that inputs control signals cont(0) to cont(M-1) to a unit driver D via the multiplexer MUX; an output terminal, from a unit resistor L·R term Output voltage on the output side (the side opposite to the contact of the unit driver D); high voltage terminal, high voltage V H applied to the high voltage terminal; and the low voltage terminal, the low voltage V L Applied to the low voltage terminal. Connecting the units U in parallel means that the terminals of the same type except the selection terminal are connected to the same line. The first input terminal to the Mth input terminal of each unit U are respectively connected to the terminals of the logic circuit that outputs the control signals cont(0) to cont(M-1) (the power supply line that transmits the control signal). The output terminal of each unit U is connected to the output terminal V of the transmitter 11-3. out (Transmission line for transmitting multi-level signals). The high voltage terminal of each unit U is connected to the output high voltage V H The low voltage terminal of each unit U is connected to the output low voltage V L The selection terminal of each unit U is connected to one of a plurality of terminals of a logic circuit that outputs a plurality of types of selection signals (mode values).

[0169] (Relationship between the number of states N and L)

[0170] Here, the relationship between the number of states N and L will be described. Hereinafter, each of the plurality of control signals supplied by the plurality of power supply lines will be represented by a different control number m, and in the case where the control signal cont(m) is connected between one or more unit drivers D to which the control signal cont(m) is input and the output terminal V out In the case where the output resistors are connected in parallel with each other, the combined resistor will be referred to as the output resistor R of control number m. m Furthermore, the unit driver D to which the control signal cont(m) is supplied and the unit U including the unit driver D will also be referred to as the unit driver D of control number m and the unit U of control number m, respectively.

[0171] As shown in the above expressions (1) and Figure 3It can be seen that, in the case of the transmitter 11-3 that outputs a multilevel signal having a number of states N (the transmitter 11-3 having a number of states N), the control value M is determined to satisfy 2 M-1 <N ≤ 2 M (or log2N ≤ M < log2N + 1). That is, the control value M is determined to be the smallest power of 2 greater than or equal to the number of states N. In the case of an integer number of output resistors having a resistance value of (N - 1)·R term (hereinafter referred to as the unit resistor (N - 1)·R term ) being connected in parallel with each other, the output resistor R of the control number m m has a resistance value. More specifically, regarding the control value M, the output resistors R of the control numbers m (0 to M - 2) other than the control number M - 1 m have a resistance value in the case where 2m (1, 2, 4, 8,...) unit resistors (N - 1)·R term are connected in parallel with each other. Note that the total number of unit resistors (N - 1) - R m constituting the output resistor R of the control number m from 0 to M - 2 term is (2 M-1 - 1).

[0172] The output resistor R of the control number M - 1 m has a resistance value in the case where (N - 2 M-1 ) unit resistors (N - 1) - R term are connected in parallel with each other, and the number of unit resistors (N - 1) - R m constituting the output resistor R of the control number M - 1 term also increases by 1 each time the number of states N increases by 1 from 2 M-1 + 1 to 2M. The total number of unit resistors (N - 1) - R term required in the case of the number of states N is (2 M-1 - 1)+(N - 2 M-1 ) = (N - 1), which matches the coefficient of R term of the unit resistor (N - 1) - R term .

[0173] Therefore, in the case of setting N - 1 to L, by using a total of L units U including the unit resistor L·R term as the output resistor of the unit driver D, the transmitter 11-3 having a number of states N (= L + 1) can be configured. Since the resistance value R term is not limited to the specific value as described above, however, the unit resistor L·R termTherefore, the transmitter 11-3 of the state number N (= L+1) can be configured by using L units U including unit resistors having arbitrary resistance values ​​as output resistors of the unit driver D. That is, in the case of configuring the transmitter 11-3 of the state number N, N-1 units U are required.

[0174] By the way, if the output resistor R of each control number m m The resistance value R m The ratio of Figure 3 If the ratio of any number of states N in the transmitter 11-3 is matched, the transmitter 11-3 having a plurality of states N is configured. By using the multiplexer MUX, the predetermined L unit resistors L·R of the transmitter 11-3 are term The total number of (unit U) changes the output resistor R that constitutes each control number m m Unit resistor L·R term The number of states N of the transmitter 11-3 can be changed to a state number other than L+1.

[0175] For example, the transmitter 11-3 whose state number N is 7 has a control value M of 3, an L of 6, and includes a total of six unit resistors 6·R term (Unit U). In this case, the total number of unit resistors is 6·R term Including 1 unit resistor 6·R of control number 0 term 、2 unit resistors of control number 1 6·R term 、3 unit resistors of control number 2 6·R term As a result, the output resistor R of control number m from 0 to 2 m The resistance value R m They are set to 6·R term 3.R term and 2·R term .

[0176] On the other hand, the transmitter 11-3 whose state number N is 7 can be controlled by changing the unit resistor 6·R for each control number m. term The number of states N is set to 4, 3 or 2 without changing the total number of units U.

[0177] When the state number N of the transmitter 11-3 is set to 4, a total of 6 unit resistors 6·R term Including 2 unit resistors 6·R of control number 0 term 、4 unit resistors of control number 1 6·R term , 0 unit resistor 6·R of control number 2 term As a result, the output resistor R of control number m from 0 to 2 m The resistance value Rm are set to 3·R term , 1.5·R term and ∞.

[0178] When the state number N of the transmitter 11 is set to 3, there are 6 unit resistors 6·R in total. term Including 3 unit resistors 6·R of control number 0 term 、3 unit resistors of control number 1 6·R term , 0 unit resistor 6·R of control number 2 term As a result, the output resistor R of control number m from 0 to 2 m The resistance value R m are set to 2·R term , 2·R term and ∞.

[0179] When the state number N of the transmitter 11 is set to 2, a total of 6 unit resistors 6·R term Including 6 unit resistors 6·R of control number 0 term 、0 unit resistor 6·R of control number 1 term , 0 unit resistor 6·R of control number 2 term As a result, the output resistor R of control number m from 0 to 2 m The resistance value R m are set to 1·R term , ∞, and ∞.

[0180] In addition, by setting the L / Ld unit resistor L·R term connected in parallel with each other, including a total of L unit resistors L·R term can be considered as equivalent to including a total of Ld unit resistors Ld·R term , where an arbitrary divisor of L is represented by Ld. Therefore, the number of states N of the transmitter 11-3 (the number of states N is L+1) can be set to Ld+1. As described above, in the case where the number of states N is 7, since L is 6, the number of states N can be changed to 2, 3, or 4, which is obtained by adding 1, which is a divisor of 6, to 1, 2, or 3. As an example of a case where the number of states N is not 7, for example, in the case where the number of states N is 31, L is 30, and the divisor Ld of 30 is 1, 2, 3, 5, 6, 10, or 15. Therefore, the number of states N can be changed to 2, 3, 4, 6, 7, 11, or 16. In the case where the number of states N is 31, for example, a total of 30 unit resistors 30·R term Including a unit resistor 30·R of control number 0 term 、Two unit resistors of control number 1 30·R term 、The four unit resistors of control number 2 are 30·Rterm 、Eight unit resistors of control number 3 30·R term 、The fifteenth unit resistor of control number 4 is 30·R term As a result, the output resistor R of control number m from 0 to 4 m The resistance value R m They are set to 30·R term 、15·R term , 7.5·R term , 3.75·R term and 2·R term On the other hand, when the number of states N is set to 11, a total of 30 unit resistors 30·R term Including 3 unit resistors 30·R of control number 0 term 、6 unit resistors of control number 1 30·R term 、12 unit resistors of control number 2 30·R term 、9 unit resistors of control number 3 30·R term , 0 unit resistor 30·R of control number 4 term As a result, the output resistor R of control number m from 0 to 4 m The resistance value R m are set to 10·R term 5.R term , 2.5·R term , 3.33·R term and ∞.

[0181] It should be noted that in the case of configuring the transmitter 11-3 in which the number of settable states N is N1 to NK (K is a natural number greater than or equal to 2), a total of L unit resistors L·R are used. term (unit U), where L represents a positive common multiple of N1-1 to NK-1. When L represents the least common multiple of N1-1 to NK-1, the number of unit U can be minimized, but a value obtained by multiplying L representing the least common multiple by any positive integer (natural number) a can be set as the number of unit U. In this case, if a unit U is always regarded as a unit U having the same control number and regarded as one unit U, the resistance value of the unit resistor of the unit U can be set to 1 / a, and the resistance value of the unit resistor can be adjusted by the number of unit U. For example, although in Fig.10The example of the configuration of the transmitter 11-1 in the first mode shown in FIG. 1 is an example in which the number of states N is not changed and is fixed to 7, but the minimum number of required cells 41 is 6. On the other hand, in the case of using twelve cells 42 which is twice the minimum number of required cells 41, two cells 42 are regarded as one cell, and the resistance value of the cell resistor of the cell is set to the cell resistor R of each cell 42. out As a result, the output resistor for each control number is set to 1 / 2 of the case where six units 42 are used.

[0182] (Change in the number of states N)

[0183] In order to change the L unit resistors L·R according to the number of states N term A multiplexer MUX is provided at the front stage of the unit driver D of each unit U, with a control number m of each of the sums of . A control signal cont(m) having a control number m of 0 to M-1 is input to a plurality of input terminals of each unit U. The control value M represents the maximum value (referred to as the maximum control value M) among the desired control values ​​of a plurality of states N that can be set (changed). A selection signal (mode value) for selecting an input terminal to be internally connected to an output terminal of the multiplexer MUX is input to a selection terminal of the multiplexer MUX of each unit U.

[0184] The multiplexer MUX outputs one of the control signals cont(m) (m is 0 to M-1) input to the input terminal from the output terminal to the unit driver D in response to the selection signal. For example, in the case where the state number N is set to Nk, based on the state number N and Figure 3 The output resistor R m (R0 to R M-1 ) resistance value R m The control value Mk required for the state number Nk is determined by the relationship between and, and the unit resistor L·R for each of the control numbers m from 0 to Mk-1 is determined. term The number of L(m). The coefficient L and the number of unit resistors LL·R term is the sum of the number L(m). Note that in the case where the control value Mk is less than the maximum control value M, it is assumed that the unit resistor L·R of the control number m is Mk to M-1 term The number L(m) is 0. In this case, by explaining that the control signal cont(m) with the control number m being Mk to M-1 is not used, the control value Mk can be regarded as the maximum control value M. The unit resistor L·R with each control number m of 0 to M-1 termThe number L(m) corresponds to the number of multiplexers MUX that output the control signal cont(m) of the control number m among the multiplexers MUX of the L units U. Therefore, the selection signal controls the L(m) multiplexers MUX so that for each control number m from 0 to M-1, the L(m) multiplexers MUX output the control signal cont(m) input from the input terminal to the unit driver D from the output terminal. In the transmitter 11-3 in which the number of settable states N is 7 and 4, for example, L is 6, and a total of six units U (unit resistor 6·R term ). The maximum control value M is 3. In the case where the state number N of the transmitter 11-3 is set to 7, the control value is 3, which is equivalent to the maximum control value M, and the unit resistor 6·R whose control number m is 0 to 2 term The number L(m) of the signal control unit U is 1 to 3. Therefore, the multiplexers MUX of the signal control unit U are selected so that one multiplexer MUX outputs the control signal cont(0), two multiplexers MUX output the control signal cont(1), and three multiplexers MUX output the control signal cont(2). In addition, in the case where the number N of states of the transmitter 11-3 is set to 4, the control value is 2, which is smaller than 3 as the maximum control value M, and the unit resistor 6·R whose control number m is 0 and 1 term The number L(m) is 2 and 4 respectively. The unit resistor 6·R term The number L(m) is 0. Therefore, the selection signal controls the multiplexers MUX so that two multiplexers MUX output the control signal cont(0), four multiplexers MUX output the control signal cont(1), and zero multiplexers MUX output the control signal cont(2).

[0185] In addition, each unit U (multiplexer MUX) of the transmitter 11-3 includes M input terminals, which input control signals cont(0) to cont(M-1) of control numbers 0 to M-1 that are at least the same as the maximum control value M. By the circuit (logic circuit) at the previous stage that outputs the control signals cont(0) to cont(M-1), the distribution of the control signals cont(0) to cont(M-1) input to the M input terminals (which control signal is to be input) can be appropriately changed. In addition, Figure 3 In the example, control numbers m from 0 to M-1 are sequentially assigned to the output resistors R m , but the control number m is used to control the multiple drivers (drivers D0 to D1) input from the input terminal of the unit U. M-1 ) and the output resistor R of the driver controlled by the control signals cont(0) to cont(M-1)m is associated, and can be any number. Figure 3 The number of unit resistors L·R for each of the control numbers 0 to M-1 identified in term For the case of L(0) to L(M-1), therefore, Figure 3 Differently, the numbers L(0) to L(M-1) can be rearranged as the numbers of control numbers 0 to M-1. In the case where the number of states N of the transmitter 11-3 is set to 7 in the transmitter 11-3 in which the number of states N that can be set is 7 and 4 in the example described above, for example, according to Figure 3 , control number 0 to 2 unit resistor 6·R term The numbers L(0) to L(2) are 1 to 3, respectively. On the other hand, the unit resistors 6·R of control numbers 0 to 2 term The numbers L(0) to L(2) can be 1, 3, and 2, respectively. That is, Figure 3 Control numbers 1 and 2 in can be changed to control numbers 2 and 1, and Figure 3 The control signals cont(1) and cont(2) of the control numbers 1 and 2 assumed in the above may be provided to each unit U as the control signals cont(2) and cont(1) of the control numbers 2 and 1. In addition, in the case where the number N of states of the transmitter 11-3 is set to 4, the unit resistors 6·R of the control numbers 0 to 2 term The numbers L(0) to L(2) are 2, 4, and 0, respectively. On the other hand, the unit resistors 6·R of control numbers 0 to 2 term The numbers L(0) to L(2) may be 0, 2, and 4, respectively. Therefore, in this case, the selection signal controls the multiplexers so that two multiplexers MUX output the control signal cont(1), four multiplexers MUX output the control signal cont(2), and zero multiplexers MUX output the control signal cont(0).

[0186] Here, in the case of individually controlling the multiplexers MUX, it is necessary to provide as many selection signals as the number (L) of the multiplexers MUX. Since the number of selection signals and signal lines increases in this case, the number of selection signals and signal lines can be reduced as follows. Assuming that a total of L unit resistors L·R are included term The maximum control value of the transmitter 11-3 is M, and the transmitter 11-3 is set to the state number N, and the unit resistor L·R of the control number m termIn the case where the number L(m) is arranged in descending order, the value of the number L(m) is L(1, N), L(2, N), ..., L(p, N), ..., L(P, N) (P is a natural number and 1≤P≤M), and the number p is used (p is a natural number). At this time, in the case where the settable number of states N of the transmitter 11 is N1 to NK, the minimum value other than 0 among the numbers L(p, N1) to L(p, NK) of the same number p is assumed to be the minimum number Lmin(p). In the case where the settable number of states N is 7, 4, 3, and 2, for example, in the case where the number of states N is 7, when the number p is 2, the numbers L(2, 7), L(2, 4), and L(2, 3) are not 0, 4, or 3, but in the case where the number of states N is 2, since the number L(2, 2) is 0 when the number p is 2, the minimum number Lmin(2) when the number p is 2 is the minimum value among the numbers L(2, 7), L(2, 4), and L(2, 3). More specifically, in the case where the settable number of states N of the transmitter 11 is 7, 4, 3, and 2 and the number N of states is 7, the numbers L(1, 7), L(2, 7), and L(3, 7) are 3, 2, and 1, respectively. In the case where the number N of states is 4, the numbers L(1, 4), L(2, 4), and L(3, 4) are 4, 2, and 0, respectively. In the case where the number N of states is 3, the numbers L(1,3), L(2,3) and L(3,3) are 3, 3 and 0 respectively. In the case where the number N of states is 2, the numbers L(1,2), L(2,3) and L(3,3) are 6, 0 and 0 respectively. Therefore, the minimum number Lmin(1) when the value p is 1 is 3, which is the minimum value among the values ​​L(1,7), L(1,4), L(1,3) and L(1,2). The minimum number Lmin(2) when the value p is 2 is 2, which is the minimum value among the values ​​L(2,7), L(2,4) and L(2,3). The minimum number Lmin(3) when the value p is 3 is 1, which is the minimum value among the values ​​L(3,7), L(3,4) and L(3,3). As described above, regardless of the number N of states, since a set of unit resistors L·R of Lmin(p) (1≤p≤M) is used term As the unit resistor L·R of the same control number m term, so the same selection signal is input to the minimum number Lmin(p) of the multiplexers MUX. Therefore, by short-circuiting the selection terminals of the minimum number Lmin(p) of the multiplexers MUX and connecting the selection terminals to the signal lines (power supply lines) of the same selection signal, the number of selection signals and signal lines can be reduced. In addition, since the minimum number Lmin(p) of units U operates as a unit regardless of the set value of the state number N, in the case where the unit is configured by one unit driver and one output resistor, the configuration of the unit U can be regarded as one. That is, the minimum number Lmin(p) of units U can be regarded as being composed of one unit driver D and one unit resistor (L· / Lmin(p))·R term Configuration. Fig.28 The example of the configuration of the transmitter 11 - 2 in the second mode shown in etc. corresponds to this case.

[0187] <First Example of Configuration of Transmitter 11-3>

[0188] Fig.33 It is shown in Fig.32 A configuration diagram of a first example of the configuration of transmitter 11-3 in the third mode. Fig.33 Shown in Fig.32 An example of a configuration in which the settable number of states N of the transmitter 11-3 in is 7, 4, 3, and 2. Fig.33 In FIG. 1 , the transmitter 11 - 3 includes three units U (units L0 to L2) connected in parallel to each other, two units U (units L3 and L4) connected in parallel to each other, and one unit U (unit L5). Fig.33 middle, Fig.32 The number L of units U in is 6, and the unit resistor L·R term (Resistance value L·R term )(which is the output resistor R of the cell driver D of each of the cells L0 to L5 out ) by 6·R termIndicates. In the case where the settable number N of states is 7, 4, 3, and 2, the maximum control value M is 3, the minimum number Lmin(1) is 3, the minimum number Lmin(2) is 2, and the minimum number Lmin(3) is 1. Therefore, the same selection signal is input to the selection terminals of the three units L0 to L2 (the selection terminals of the multiplexer MUX), the same selection signal is input to the selection terminals of the two units L3 and L4 (the selection terminals of the multiplexer MUX), and the same selection signal is input to one unit L5 (the selection terminal of the multiplexer MUX). It should be noted that the multiplexer MUX of the units L0 to L5 may include, for example, three or more input terminals for inputting control signals cont(0) to cont(2), and a selection terminal for inputting a selection signal for selecting a control signal input from one of the input terminals as a selection signal for a signal to be output from the output terminal. In Fig.33 In the transmitter 11 - 3 , the configurations of the multiplexer MUX of the units L0 to L2 and L5 and the multiplexer MUX of the units L3 and L4 are different from each other, but the difference is used to describe the operation of the multiplexer MUX, and actually the configurations may be the same.

[0189] The control signals cont(0) to cont(2) are respectively input to the three input terminals of the units L0 to L2, and the control signals cont(0) to cont(2) are respectively input to the three input terminals of the multiplexer MUX. A selection signal of a mode value 0 is input as a fixed value to the selection terminal of the multiplexer MUX of the units L0 to L2. In this case, the multiplexer MUX outputs the control signal cont(2) input to the input terminal from the output terminal, and supplies the control signal cont(2) to the unit driver D.

[0190] The control signals cont(0) to cont(2) are input to the three input terminals of the units L3 and L4, respectively, and the control signals cont(0) to cont(2) are input to the four input terminals of the multiplexer MUX, respectively. The selection signal of the mode value MODE<1:0> is input to the selection terminal of the multiplexer MUX of the units L3 and L4. The mode value MODE<1:0 and the operation of the multiplexer MUX based on the mode value MODE<1:0 will be described later.

[0191] The control signals cont(0) to cont(2) are input to the three input terminals of the unit L5, and are input to the three input terminals of the multiplexer MUX. The selection signal of the mode value MODE<0> is input to the selection terminal of the multiplexer MUX of the unit L5. <0> and based on the mode value MODE <0> The operation of the multiplexer MUX will be described later.

[0192] Here, unlike Fig.33 The multiplexer MUX of each of the units L0 to L5 in the example of the configuration of the transmitter 11-3 in FIG. 1 is based on the multiplexer MUX of each of the units L0 to L5 to be described later. Fig.33 The multiplexer MUX will be described as follows: Figure 3 The number N of states identified in each control number m of the unit resistor L·R term In the case where the number of states L(m) is set to perform an operation. In the case where the number of states N is set to 7, the selection signal is input to the multiplexers MUX of the units L0 to L2, so that the control signal cont(2) is output from the multiplexer MUX to the unit driver D. The selection signal is input to the multiplexers MUX of the units L3 and L4, so that the control signal cont(1) is output from the multiplexer MUX to the unit driver D. The selection signal is input to the multiplexer MUX of the unit L5, so that the control signal cont(0) is output from the multiplexer MUX to the unit driver D. As a result, the number L(2) of the control number 2 is set to 3, the number L(1) of the control number 1 is set to 2, and the number L(0) of the control number 0 is set to 1.

[0193] In the case where the number of states N is set to 4, the selection signal is input to the multiplexers MUX of the cells L0 to L2, so that the control signal cont(1) is output from the multiplexers MUX to the cell driver D. The selection signal is input to the multiplexers MUX of the cells L3 and L4, so that the control signal cont(0) is output from the multiplexers MUX to the cell driver D. The selection signal is input to the multiplexer MUX of the cell L5, so that the control signal cont(1) is output from the multiplexer MUX to the cell driver D. As a result, the number L(2) of the control number 2 is set to 0, the number L(1) of the control number 1 is set to 4, and the number L(0) of the control number 0 is set to 2.

[0194] In the case where the state number N of the transmitter 11-3 is set to 3, the selection signal is input to the multiplexers MUX of the units L0 to L2, so that the control signal cont(1) is output from the multiplexers MUX to the unit driver D. The selection signal is input to the multiplexers MUX of the units L3 and L4, so that the control signal cont(0) is output from the multiplexers MUX to the unit driver D. The selection signal is input to the multiplexer MUX of the unit L5, so that the control signal cont(0) is output from the multiplexer MUX to the unit driver D. As a result, the number L(2) of the control number 2 is set to 0, the number L(1) of the control number 1 is set to 3, and the number L(0) of the control number 0 is set to 3.

[0195] In the case where the state number N of the transmitter 11-3 is set to 2, the selection signal is input to the multiplexers MUX of the units L0 to L2, so that the control signal cont(0) is output from the multiplexers MUX to the unit driver D. The selection signal is input to the multiplexers MUX of the units L3 and L4, so that the control signal cont(0) is output from the multiplexers MUX to the unit driver D. The selection signal is input to the multiplexer MUX of the unit L5, so that the control signal cont(0) is output from the multiplexer MUX to the unit driver D. As a result, the number L(2) of the control number 2 is set to 0, the number L(1) of the control number 1 is set to 0, and the number L(0) of the control number 0 is set to 6.

[0196] Fig.33 The transmitter 11-3 in sets a mode value corresponding to the state number N, and uses the set mode value as a selection signal of the multiplexer MUX. Fig.33 In the transmitter 11-3, relative to the Figure 3 The number of states N in which the control number 0 to 2 of the unit resistor 6·R is determined term The number L(0) to L(M-1), the number L(0) to L(M-1) are rearranged to be Figure 3 Different control numbers 0 to 2 unit resistor 6·R term The number of

[0197] Fig.34 is a graph showing the mode value corresponding to the number of states N and the Fig.33 FIG. 1 is a table showing the relationship between the control signals output by the multiplexer MUX of each of the units L0 to L5 in the transmitter 11-3. Fig.34 , cases 1 to 4 represent cases where the number N of states of the transmitter 11-3 is set to 7, 4, 3, and 2, respectively, and the number N of states set in cases 1 to 4 is represented as the number of output levels. In addition, the mode value is represented by MODE <1> and MODE <0> The combination of means that each mode is set to 0 or 1. Case 1 is that the number of states N is set to 7, and Mode <1> and Mode <0> is set to 0. Case 2 is when the number of states N is set to 4 and Mode <1> and Mode <0> are set to 0 and 1 respectively. Case 3 is when the number of states N is set to 3 and Mode <1> and Mode <0> are set to 1 and 0 respectively. Case 4 is when the number of states N is set to 2 and Mode <1> and Mode <0> The case where 1 is set to 1 and 1. The output of the multiplexer MUX in each of the cases 1 to 4 will be described separately later.

[0198] (Case 1)

[0199] Fig.35 It is shown in Fig.34 In case 1 (when the number of states N is 7), Fig.33 11 - 3 , and Fig.36 It is shown from Fig.34 Extract the table for case 1 from . Fig.35 and Fig.36 In the mode value MODE <1> and mode value MODE <0> is set to 0. <1> and mode value MODE <0> In the case where the two-digit binary number obtained by the combination is set to the mode value MODE<1:0>, the mode value MODE<1:0> is set to 00. In case 1, 0 as a fixed value is input to the multiplexer MUX of the units L0 to L2 as a selection signal, 00 is input to the multiplexer MUX of the units L3 and L4 as the mode value MODE<1:0 (i.e., the selection signal), and 0 is input to the multiplexer MUX of the unit L5 as the mode value MODE<0 (i.e., the selection signal). Therefore, in the units L0 to L2, the control signal cont(2) is provided from the multiplexer MUX to the unit driver D. In the units L3 and L4, the control signal cont(1) is provided from the multiplexer MUX to the unit driver D. In the unit L5, the control signal cont(0) is provided from the multiplexer MUX to the unit driver D. As a result, the three unit resistors 6·R of the units L0 to L2 are term The output resistor R2 of the control number 2, the two unit resistors 6·R of the units L3 and L4 term The output resistor R1 of the control number 1 is constituted, and a unit resistor 6·R of the unit L5 is term The output resistor R0 constitutes the control number 0. Therefore, the number N of states of the transmitter 11 - 3 is set to seven.

[0200] Fig.37 1 is a graph showing the output terminal V of the slave transmitter 11 - 3 for each combination of the values ​​of the control signals cont( 0 ) to cont( 2 ). out The normalized output voltage V n In Fig.37 In FIG. 1 , the signal numbers X from 0 to 7 are shown in the leftmost column, such as Figure 5 The signal number X is a value obtained by expressing the 3-bit digital data indicated by the control signals cont(0) to cont(2) in decimal. In the signal number X of each row 0 to 7, the value (0 or 1) of the control signals cont(0) to cont(2) input to the transmitter 11-3 and the value (0 or 1) of the control signals cont(0) to cont(2) output from the output terminal V out Normalized output voltage V of output state number n n . Because in Fig.37The contents and references shown in Figure 5 and Figure 6 The contents described are similar, so the reference is omitted Fig.37 In the case where the signal number X is 3 and 4, the output voltage V3 of the state number 3 is output. For the eight combinations of the values ​​of the control signals cont(0) to cont(2) where the signal number X is 0 to 7, the normalized output voltage V n Is one of seven levels obtained by dividing the range from 0 to 1 equally (into six equal parts). Fig.38 shows the output voltage V at any control number n (0 to 6) n Change to another control number n (0 to 6) output voltage V n The normalized output voltage V out The horizontal axis represents time and the vertical axis represents the normalized output voltage V out Based on this, the normalized output voltage V out Normalized output voltages V0 to V6 that have been switched to control numbers 0 to 6 over a certain period of time after the control signals cont(0) to cont(2) are changed at 0.1 (ns) and 1.1 (ns).

[0201] (Case 2)

[0202] Fig.39 It is shown in Fig.34 In case 2 (when the number of states N is 4), Fig.33 11 - 3 , and Fig.40 It is shown from Fig.34 The table for case 2 is extracted from . Fig.39 and Fig.40 In the mode value MODE <1> and mode value MODE <0> are set to 0 and 1, respectively, and the mode value MODE<1:0> is set to 01. In case 2, 0 as a fixed value is input to the multiplexers MUX of the units L0 to L2 as a selection signal, 01 is input to the multiplexers MUX of the units L3 and L4 as the mode value MODE<1:0> (i.e., the selection signal), and 1 is input to the multiplexer MUX of the unit L5 as the mode value MODE <0> (i.e., selection signal). Therefore, in the cells L0 to L2, the control signal cont(2) is supplied from the multiplexer MUX to the cell driver D. In the cells L3 and L4, the control signal cont(1) is supplied from the multiplexer MUX to the cell driver D. In the cell L5, the control signal cont(2) is supplied from the multiplexer MUX to the cell driver D. As a result, the four cell resistors 6·R of the cells L0 to L2 and L5 are termThe output resistor R2 of the control number 2, the two unit resistors 6·R of the units L3 and L4 term The output resistor R1 of the control number 1 is configured, and the output resistor R0 of the control number 0 is not configured. Therefore, the number N of states of the transmitter 11 - 3 is set to four.

[0203] Fig.41 1 is a graph showing the output terminal V of the slave transmitter 11 - 3 for each combination of the values ​​of the control signals cont( 0 ) to cont( 2 ). out The normalized output voltage V n In Fig.41 , signal numbers X of 0 to 3 are shown in the leftmost column. Signal number X is a value obtained by expressing 2-bit digital data in a decimal number, where control signals cont(1) and cont(2) are values ​​of 1 bit (first bit) and 2 bits (second bit), respectively. In each row of signal number X of 0 to 3, the values ​​(0 or 1) of control signals cont(0) to cont(2) input to transmitter 11-3 and the values ​​output from output terminal V out Normalized output voltage V of output state number n n Note that since there is no output resistor R0 of control number 0, the control signal cont(0) is not used.

[0204] according to Fig.41 , the state number n is 0 to 3, and the normalized output voltages V0 to V3 of the state numbers 0 to 3 are 0.000, 0.333, 0.667 and 1.000 respectively. Whenever the signal number X increases by 1 from 0 to 3, the normalized output voltage V n Increase by 1 / 3 in the range of 0 to 1. For the four combinations of the values ​​of the control signals cont(1) and cont(2) where the signal number X is 0 to 3, the normalized output voltage V n is one of four levels obtained by dividing the range from 0 to 1 equally (into three equal parts). Note that for the four output voltages V0 to V3, Fig.37 The output voltages V0 , V2 , V4 , and V6 of control numbers 0 , 2 , 4 , and 6 of equivalent voltages among the output voltages V0 to V6 in case 1 are shown in the remark field. Fig.42 shows the output voltage V at any control number n (0 to 3) n Change to another control number n (0 to 3) output voltage V n Normalized output voltage V out The horizontal axis represents time and the vertical axis represents the normalized output voltage V out Based on this, the normalized output voltage V outThe normalized output voltages V0 to V3 of control numbers 0 to 3 have been converted at a specific time period after the control signals cont(0) to cont(2) are changed at 0.1 (ns) and 1.1 (ns). Fig.42 , the normalized output voltages V0 to V3 of control numbers 0 to 3 are indicated as output voltages V0, V2, V4, and V6 in case 1, respectively.

[0205] (Case 3)

[0206] Fig.43 It is shown in Fig.34 In case 3 (when the number of states N is 3), Fig.33 11 - 3 , and Fig.44 It is shown from Fig.34 The table for case 3 is extracted from . Fig.43 and Fig.44 In the mode value MODE <1> and mode value MODE <0> are set to 1 and 0, respectively, and the mode value MODE<1:0> is set to 10. In case 3, 0 as a fixed value is input to the multiplexer MUX of the cells L0 to L2 as a selection signal, 10 is input to the multiplexers MUX of the cells L3 and L4 as the mode value MODE<1:0 (i.e., the selection signal), and 0 is input to the multiplexer MUX of the cell L5 as the mode value MODE<0 (i.e., the selection signal). Therefore, in the cells L0 to L2, the control signal cont(2) is provided from the multiplexer MUX to the cell driver D. In the cells L3 and L4, the control signal cont(0) is provided from the multiplexer MUX to the cell driver D. In the cell L5, the control signal cont(0) is provided from the multiplexer MUX to the cell driver D. As a result, the three cell resistors 6·R of the cells L0 to L2 are term The output resistor R2 constituting the control number 2, the three unit resistors 6·R of the units L3 to L5 term The output resistor R0 of the control number 0 is configured, and the output resistor R1 of the control number 1 is not configured. Therefore, the number N of states of the transmitter 11 - 3 is set to three.

[0207] Fig.45 1 is a graph showing the output terminal V of the slave transmitter 11 - 3 for each combination of the values ​​of the control signals cont( 0 ) to cont( 2 ). out The normalized output voltage V n In Fig.45, signal numbers X of 0 to 3 are shown in the leftmost column. Signal number X is a value obtained by expressing 2-bit digital data in a decimal number, where control signals cont(0) and cont(2) are values ​​of 1 bit (first bit) and 2 bits (second bit), respectively. In each row of signal number X of 0 to 3, the values ​​(0 or 1) of control signals cont(0) to cont(2) input to transmitter 11-3 and the values ​​of control signals output from output terminal V out Normalized output voltage V of output state number n n Note that since there is no output resistor R1 of control number 1, the control signal cont(1) is not used.

[0208] according to Fig.45 , the state number n is 0 to 2, and the normalized output voltages V0 to V2 of the state numbers 0 to 2 are 0.000, 0.500, and 1.000, respectively. In the case where the signal number X is 1 and 2, the output voltage V1 of the state number 1 is output. In the case where the signal number X increases from 0 to 1 or from 2 to 3, the state number n increases by 1, and the normalized output voltage V n Increase by 1 / 2 in the range of 0 to 1. For the four combinations of the values ​​of the control signals cont(0) to cont(2) where the signal number X is 0 to 3, the normalized output voltage V n is one of three levels obtained by dividing the range from 0 to 1 equally (into two equal parts). Note that for the three output voltages V0 to V2, Fig.37 The output voltages V0 , V3 , and V6 of control numbers 0 , 3 , and 6 of equivalent voltages among the output voltages V0 to V6 of case 1 are shown in the remark field. Fig.46 shows the output voltage V at any control number n (0 to 2) n Change to another control number n (0 to 2) output voltage V n The normalized output voltage V out The horizontal axis represents time and the vertical axis represents the normalized output voltage V out Based on this, the normalized output voltage V out The normalized output voltages V0 to V2 of control numbers 0 to 2 have been converted over a specific period of time after the control signals cont(0) to cont(2) are changed at 0.1 (ns) and 1.1 (ns). Fig.46 , the normalized output voltages V0 to V2 of control numbers 0 to 2 are indicated as output voltages V0, V3, and V6 in case 1, respectively.

[0209] (Case 4)

[0210] Fig.47 It is shown Fig.33The transmitter 11-3 in Fig.34 is a diagram of the operation in case 4 (the case where the number of states N is 2), and Fig.48 It is shown from Fig.34 Extract the table for case 4. Fig.47 and Fig.48 In the mode value MODE <1> and mode value MODE <0> is set to 1, and the mode value MODE<1:0> is set to 11. In case 4, 0 as a fixed value is input to the multiplexers MUX of the units L0 to L2 as a selection signal, 11 is input to the multiplexers MUX of the units L3 and L4 as the mode value MODE<1:0> (i.e., the selection signal), and 1 is input to the multiplexer MUX of the unit L5 as the mode value MODE <0> (i.e., selection signal). Therefore, in cells L0 to L2, control signal cont(2) is supplied from multiplexer MUX to cell driver D. In cells L3 and L4, control signal cont(2) is supplied from multiplexer MUX to cell driver D. In cell L5, control signal cont(2) is supplied from multiplexer MUX to cell driver D. As a result, six cell resistors 6·R of cells L0 to L5 are term The output resistor R2 of the control number 2 is configured, and the output resistors R0 and R1 of the control numbers 0 and 1 are not configured. Therefore, the number N of states of the transmitter 11 - 3 is set to two.

[0211] Fig.49 1 is a graph showing the output terminal V of the slave transmitter 11 - 3 for each combination of the values ​​of the control signals cont( 0 ) to cont( 2 ). out The normalized output voltage V n In Fig.49 , the signal number X of 0 and 1 is shown in the leftmost column. The signal number X is a value obtained by expressing the 2-bit digital data of the control signal cont(2) in decimal. In each row where the signal number X is 0 and 1, the values ​​(0 or 1) of the control signals cont(0) to cont(2) input to the transmitter 11-3 and the values ​​(0 or 1) of the control signals cont(0) to cont(2) output from the output terminal V out Normalized output voltage V of output state number n n Note that since there are no output resistors R0 and R1 for control numbers 0 and 1, the control signals cont(0) and cont(1) are not used.

[0212] according to Fig.49 , the state number n is 0 and 1, and the normalized output voltages V0 and V1 of the state numbers 0 and 1 are 0.000 and 1.000, respectively. When the signal number X increases from 0 to 1, the normalized output voltage V n Increases from 0 to 1. The normalized output voltage Vn The two values ​​of the control signal cont(2) corresponding to the signal number X being 0 and 1 become one of the two levels of 0 and 1. Note that for the two output voltages V0 and V1, Fig.37 The output voltages V0 and V6 of control numbers 0 and 6 of equivalent voltages among the output voltages V0 to V6 of case 1 are shown in the marked fields. Fig.50 shows the output voltage V at any control number n (0 and 1) n Change to another control number n (0 and 1) output voltage V n The normalized output voltage V out The horizontal axis represents time and the vertical axis represents the normalized output voltage V out Based on this, the normalized output voltage V out The normalized output voltages V0 and V1 of the control numbers 0 to 1 have been converted at a specific time period after the control signals cont(0) to cont(2) are changed at 0.1 (ns) and 1.1 (ns). Fig.50 , the normalized output voltages V0 and V1 of the control numbers 0 and 1 are indicated as output voltages V0 and V6 in case 1, respectively.

[0213] <Second Example of Configuration of Transmitter 11-3>

[0214] Fig.51 It is shown Fig.32 A configuration diagram of a second example of the configuration of transmitter 11-3. Fig.51 Shown in Fig.32 An example of a configuration in which the settable number of states N of the transmitter 11-3 in is 5, 3, and 2. It should be noted that Fig.51 The second example of the configuration of the transmitter 11-3 in the reference is similar in configuration and operation to the reference Figures 33 to 50 The first example described is similar, and its description is simplified.

[0215] exist Fig.51 In FIG. 1 , the transmitter 11-3 includes two units U (units L0 and L1) and one unit U (units L2 and L3) connected in parallel to each other. Fig.51 middle, Fig.32 The number L of units U in is 4, and the unit resistor L·R term (Resistance value L·R term )(which is the output resistor R of the cell driver D of each of the cells L0 to L3 out ) by 4·R termIndicates. In the case where the settable number N of states is 5, 3, and 2, the maximum control value M is 3, the minimum number Lmin(1) is 2, the minimum number Lmin(2) is 1, and the minimum number Lmin(3) is 1. Therefore, the same selection signal is input to the selection terminals of the two units L0 and L1 (the selection terminals of the multiplexer MUX), and a separate single selection signal is input to the selection terminals of the units L3 and L4 (the selection terminals of the multiplexer MUX). It should be noted that the multiplexer MUX of the units L0 to L3 may include, for example, three or more input terminals for inputting control signals cont(0) to cont(2), and a selection terminal for inputting a selection signal for selecting a control signal input from one of the input terminals as a selection signal for a signal to be output from the output terminal. In Fig.51 In the transmitter 11-3, the configurations of the multiplexer MUX of the units L0, L1, and L3 and the multiplexer MUX of the unit L2 are different from each other, but the difference is used to describe the operation of the multiplexer MUX, and actually the configurations may be the same.

[0216] The control signals cont(0) to cont(2) are respectively input to the three input terminals of the units L0 and L1, and the control signals cont(0) to cont(2) are respectively input to the three input terminals of the multiplexer MUX. The selection signal of the mode value 0 is input as a fixed value to the selection terminal of the multiplexer MUX of the units L0 and L1. In this case, the multiplexer MUX outputs the control signal cont(2) input to the input terminal from the output terminal, and supplies the control signal cont(2) to the unit driver D.

[0217] The control signals cont(0) to cont(2) are respectively input to the three input terminals of the unit L2, and the control signals cont(0) to cont(2) are respectively input to the four input terminals of the multiplexer MUX. The selection signal of the mode value MODE<1:0> is input to the selection terminal of the multiplexer MUX of the unit L2.

[0218] Control signals cont(0) to cont(2) are input to three input terminals of the unit L3, respectively, and are input to three input terminals of the multiplexer MUX. A selection signal of a mode value MODE<0> is input to a selection terminal of the multiplexer MUX of the unit L3.

[0219] When the state number N is set to 5, the mode value MODE<1> and the mode value MODE<0> are both set to 0, and the mode value MODE<1:0> is set to 00. In this case, 0 as a fixed value is input to the multiplexers MUX of the cells L0 and L1 as a selection signal, 00 is input to the multiplexer MUX of the cell L2 as the mode value MODE<1:0 (i.e., the selection signal), and 0 is input to the multiplexing multiplexer MUX of the cell L3 as the mode value MODE<0 (i.e., the selection signal). Therefore, in the cells L0 and L1, the control signal cont(2) is provided from the multiplexer MUX to the cell driver D. In the cell L2, the control signal cont(1) is provided from the multiplexer MUX to the cell driver D. In the cell L3, the control signal cont(0) is provided from the multiplexer MUX to the cell driver D. As a result, the two cell resistors 4·R of the cells L0 and L1 are connected. term The output resistor R2 of the control number 2, a unit resistor 4·R of the unit L2 term The output resistor R1 of the control number 1 is constituted, and a unit resistor 4·R of the unit L3 is term The output resistor R0 constitutes the control number 0. Therefore, the number N of states of the transmitter 11 - 3 is set to five.

[0220] When the state number N is set to 3, the mode value MODE<1> and the mode value MODE<0> are set to 1 and 0, respectively, and the mode value MODE<1:0> is set to 10. In this case, 0 as a fixed value is input to the multiplexers MUX of the units L0 and L1 as a selection signal, 10 is input to the multiplexer MUX of the unit L2 as the mode value MODE<1:0> (i.e., the selection signal), and 0 is input to the multiplexing multiplexer MUX of the unit L3 as the mode value MODE<1:0>. <0> (i.e., selection signal). Therefore, in cells L0 and L1, control signal cont(2) is supplied from multiplexer MUX to cell driver D. In cell L2, control signal cont(0) is supplied from multiplexer MUX to cell driver D. In cell L3, control signal cont(0) is supplied from multiplexer MUX to cell driver D. As a result, two cell resistors 4·R of cells L0 and L1 are connected. term The output resistor R2 of the control number 2, the two unit resistors 4·R of the units L2 and L3 term The output resistor R0 of the control number 0 is configured, and the output resistor R1 of the control number 1 is not configured. Therefore, the number N of states of the transmitter 11 - 3 is set to three.

[0221] When the state number N is set to 2, the mode value MODE<1> and the mode value MODE<0> are each set to 1, and the mode value MODE<1:0> is set to 11. In this case, 0 as a fixed value is input to the multiplexers MUX of the units L0 and L1 as a selection signal, 11 is input to the multiplexer MUX of the unit L2 as the mode value MODE<1:0> (i.e., the selection signal), and 1 is input to the multiplexing multiplexer MUX of the unit L3 as the mode value MODE<1:0>. <0> (i.e., selection signal). Therefore, in cells L0 and L1, control signal cont(2) is supplied from multiplexer MUX to cell driver D. In cell L2, control signal cont(2) is supplied from multiplexer MUX to cell driver D. In cell L3, control signal cont(2) is supplied from multiplexer MUX to cell driver D. As a result, four cell resistors 4·R of cells L0 and L3 are term The output resistor R2 of the control number 2 is configured, and the output resistors R0 and R1 of the control numbers 0 and 1 are not configured. Therefore, the number N of states of the transmitter 11 - 3 is set to two.

[0222] Fig.52 is a graph showing the state of the transmitter 11-3 output from the output terminal V for each combination of the values ​​of the control signals cont(0) to cont(2) when the number of states N is set to 5. out The normalized output voltage V n In Fig.52 In the leftmost column, signal numbers X from 0 to 7 are shown, which are the same as those in Figure 5 The signal number X is a value obtained by expressing the 3-bit digital data indicated by the control signals cont(0) to cont(2) in decimal. However, in the case where the state number N is set to 5 in the second example of the configuration, the control signals cont(1) and cont(2) of the control numbers 1 and 2 are used as Figure 3 The control signal of control number 2 and the control signal of control number 1. Therefore, in Fig.52 In the signal condition X, the value obtained by expressing a 3-bit binary number in decimal, where 1 bit is the value of the control signal cont(0), 2 bits are the value of the control signal cont(2), and 3 bits are the value of the control signal cont(1). In the signal condition X of each row 0 to 7, the values ​​(0 or 1) of the control signals cont(0) to cont(2) input to the transmitter 11-3 and the values ​​output from the output terminal V out Normalized output voltage V of output state number n n .

[0223] according to Fig.52, state number n is 0 to 4, and the normalized output voltages V0 to V4 of state numbers 0 to 4 are 0.000, 0.250, 0.500, 0.750, and 1.000, respectively. In the case where the signal number X is 1 to 3 and 4 to 6, the output voltages V1 to V3 of state numbers 1 to 3 are output. In the case where the signal number X increases by 1 from any of 0 to 2 and 6, the state number n increases by 1, and the normalized output voltage V n Increase by 1 / 4 in the range of 0 to 1. For eight combinations of the values ​​of the control signals cont(0) to cont(2) with signal numbers X ranging from 0 to 7, the normalized output voltage V n Is one of four levels obtained by dividing the range from 0 to 1 equally (into three equal parts). Fig.53 shows the output voltage V at any control number n (0 to 4) n Change to another control number n (0 to 4) output voltage V n Normalized output voltage V out The horizontal axis represents time and the vertical axis represents the normalized output voltage V out Based on this, the normalized output voltage V out The normalized output voltages V0 to V2 of control numbers 0 to 4 have been converted over a certain period of time after the control signals cont(0) to cont(2) are changed at 0.1 (ns) and 1.1 (ns). Note that the description of the case where the number N of states is set to 3 or 2 is omitted.

[0224] <Comparison between the Third Mode of Transmitter 11 and Comparative Technique 2>

[0225] Here, the transmitter 11-3 as the third mode of the transmitter 11 to which the present technology is applied is compared with the comparative technology 2. It should be noted that in this comparison, reference is made to Figures 51 to 53 The second example of the configuration of the transmitter 11 - 3 is described as serving as the third mode of the transmitter 11 to which the present technology is applied. Fig.54 It is shown Fig.25 When the number of states N of the transmitter 411 in the comparison technique 2 is set to 5, the output terminal V of the transmitter 411 for each combination of the values ​​of the control signals cont(0) and cont(2) is out The normalized output voltage V n of table.

[0226] exist Fig.54 In Fig.26As shown in FIG. 1 , signal numbers X of 0 to 7 are shown in the leftmost column. Signal number X is a value obtained by expressing 3-bit digital data indicated by control signals cont(0) to cont(2) in decimal. In each row of signal number X of 0 to 7, the value (0 or 1) of control signals cont(0) to cont(2) input to transmitter 411 and the value (0 or 1) of control signals cont(0) to cont(2) output from output terminal V out Normalized output voltage V of output state number n n .

[0227] Fig.55 The output voltage V of any control number n (0 to 4) in the transmitter 411 of the comparison technique 2 is shown. n Change to another control number n (0 to 4) output voltage V n Normalized output voltage V out The time variation of the state number 5 is shown in FIG. 1 , where the horizontal axis represents time and the vertical axis represents the normalized output voltage V out .

[0228] like Fig.54 and Fig.55 As shown, in the case where the number N of states of the transmitter 411 is set to 5 (which is a value different from the power of 2), the combination of the values ​​of the control signal input to the transmitter 411 is limited in the configuration where the number N of states is 2 so that the output voltage V n The number of states N becomes 5.

[0229] according to Fig.54 and Fig.55 , the control signals cont(0) to cont(2) input to the transmitter 411 are limited to combinations of five consecutive control signals cont(0) to cont(2) with signal numbers 0 to 4 among the signal numbers X from 0 to 7. As a result, the transmitter 411 outputs the normalized output voltage V with state numbers 0 to 7. n The five state numbers in the output voltage V0 to V4 are 0 to 4. The reason why the signal number X is limited to the combination of the control signals cont(0) to cont(2) from 0 to 4 is to make the output voltage V out The normalized output voltage V n The five levels are output at equal intervals, and the output voltage V of five consecutive state numbers n is n Therefore, when the output voltage V0 of the output state number 0 is output, the output voltages V of the state numbers 5 to 7 are not used. n Therefore, the output voltage V output from the transmitter 411 is out is limited to a low voltage V L With high voltage V HThe range is between 4 / 7 and is accompanied by a voltage loss of approximately 42%.

[0230] On the other hand, in reference Figure 51 to Figure 53 In the second example of the configuration of the transmitter 11-3 described above, for example, in the case where the number of states N is set to 5, the output is at the low voltage V L With high voltage V H The output voltage V0 to V4 changes state number between 0 to 4 over the entire range, making the low voltage V L With high voltage V H The voltage range between can be effectively maximized.

[0231] It should be noted that in the first and second examples of the configuration of the transmitter 11-3 described above, the unit driver D and the unit resistor L·R in the unit U term is set as a combinational circuit, and the number of states of the plurality of combinational circuits is configured to be changed by the multiplexer MUX according to the number of states N. On the other hand, regardless of the number of states N, the number of drivers for each state number can be fixed to 1, and the plurality of unit resistors L·R term The driver connected to can be changed by a multiplexer etc. according to the number of states N, and each unit resistor L·R term The state number can be changed (the resistance value of the output resistor of each control number can be changed).

[0232] <First Embodiment of Transmitter 11-3>

[0233] Fig.56 It is shown Fig.32 A configuration diagram of a first example of the transmitter 11-3 in FIG. Fig.56 In the example, the transmitter 11-3 includes L units U. Each unit U is configured such that Fig.32 The multiplexer MUX, the unit driver D and the output resistor L·R shown in term2 mounted on an IC chip or a substrate. Fig.56 In the embodiment, the unit driver D in each unit U has a circuit configuration of a complementary MOS (CMOS) including a combination of a p-type MOSFET and an n-type MOSFET, but the circuit configuration of the driver D is an example and is not limited thereto. The output resistor L·R in each unit U term Not limited to specific values. Fig.56In the embodiment, the multiplexer MUX has a circuit configuration including a plurality of transmission gates, each transmission gate including a combination of a p-type MOSFET and an n-type MOSFET, but the circuit configuration of the multiplexer MUX is an example and is not limited thereto. The L units U are connected in parallel with each other. In addition, connecting the units U in parallel means that terminals of the same type (except for certain types) of a plurality of units U are connected to the same line. Each unit U includes an input terminal for a control signal input to the multiplexer MUX, a selection terminal for a selection signal input to the multiplexer MUX, an output resistor L·R term2 The output side (the side opposite to the contact of the unit driver D) outputs the output voltage, and a high voltage V is applied to the output terminal. H The high voltage end and the low voltage V L It should be noted that Fig.56 A case where three control signals cont(0) to cont(2) are input to the input terminal of each unit U is shown, but the number of control signals (control value M) is not limited thereto.

[0234] The input terminal of the unit U is connected to the output terminal (power line for transmitting the control signal) of the high-speed control logic (logic circuit) 101 which outputs the control signals cont(0) to cont(2). Here, the configuration of the multiplexer MUX of the units L0 to L5 and the configuration of the input terminal to which the control signals cont(0) to cont(2) are input need not be the same. In this case, the wiring between the input terminal of each unit U to which the control signal is input and the input terminal of the multiplexer MUX may be different depending on the unit U. The selection terminal of the unit U is connected to the output terminal of the DC control logic (logic circuit) 102 which outputs the selection signal to the multiplexer MUX. Since the selection signal is different for each or some units U, the DC control logic 102 includes an output terminal that outputs a plurality of types of selection signals, and the selection terminal is connected to different output terminals of the DC control logic 102 for each or some units U. The output terminal of the unit U is connected to the output terminal V as the transmitter 11-3. out The high voltage terminal of the unit U is connected to the output of the high voltage V generated by the constant voltage generating circuit 103. H The low voltage terminal of unit U is connected to the GND terminal.

[0235] <Second Example of Transmitter 11-3>

[0236] Fig.57 It is shown Fig.32 FIG. 1 is a configuration diagram of a second example of the transmitter 11-3 in FIG. Fig.56 The same components as those in FIG. 1 have the same reference numerals, and description thereof is omitted. Fig.57 The second example in Fig.56 The first example in FIG. 1 is different in that a constant voltage generating circuit 104 is included (described as a constant voltage generating circuit 2 in the figure). Note that the constant voltage generating circuit 103 that generates and outputs a high voltage terminal is shown as a constant voltage generating circuit 1. The low voltage terminal of each unit U is connected to the output of the low voltage V generated by the constant voltage generating circuit 104. L According to the terminal. Fig.57 The second example, as in Fig.56 The low voltage V generated by the constant voltage generating circuit 104 is L As low voltage V L Instead of GND potential (0 V), the unit driver D of each unit U is applied.

[0237] <Third Example of Transmitter 11-1>

[0238] Fig.58 It is shown Fig.32 FIG. 1 is a configuration diagram of a third example of the transmitter 11-3 in FIG. Fig.56 The same components as those in FIG. 1 have the same reference numerals, and description thereof is omitted. Fig.58 The third example in Fig.56 The first example in FIG. 1 is different in that the constant voltage generating circuit 103 is not provided. The high voltage terminal of each unit U is connected to the power supply terminal. The high voltage V from the external voltage source H is supplied to the power supply terminal.

[0239] according to Fig.58 In the third example, a high voltage V can be supplied from any external power source H , without the need to accompany each unit U and generate a high voltage V H The constant voltage generating circuit 103, such as Fig.56 shown.

[0240] <Example of Circuit Configuration of Multiplexer MUX of Each Unit U>

[0241] exist Fig.32 The circuit configuration of the multiplexer MUX of each unit U in the transmitter 11-3 as the third mode of the transmitter 11 shown in FIG. 1 is not limited to that in Fig.56 The configuration including the transmission gate shown in FIG. For example, the multiplexer MUX may have a configuration as shown in FIG. Fig.59 The NAND configuration shown in , or may have a Fig.60 The configuration of the inverter with switches shown in FIG.

[0242] <Application example of transmitter 11 to which the present technology is applied>

[0243] Fig.61: is a diagram showing an application example of the transmitter 11 to which the present technology is applied. Fig.61 shows the internal configuration of a device having a camera function (such as a smart phone), and Fig.61 The device in includes an image sensor 121 and an application processor 122. The image (video data) obtained by the image sensor 121 is transmitted to the application processor 122 at high speed via a high-speed interface and is used for processing in the application processor 122. The image sensor 121 is configured by, for example, stacking an upper chip and a lower chip, and an image sensor unit 141 is formed on the upper chip, in which pixels including a light receiving element that performs photoelectric conversion are arranged two-dimensionally. The image analog signal obtained by the image sensor unit 141 is transmitted to an analog-to-digital (AD) converter 142 formed on the lower chip and converted into a multi-bit digital signal (digital multi-bit signal). The digital multi-bit signal is sent from the AD converter 142 to the logic circuit 143 of the lower chip and is subjected to predetermined processing, and then sent to the serializer 144 of the lower chip. In the serializer 144, the digital multi-bit signal is converted from a parallel signal to a serial signal and sent at high speed to the transmitter (driver) 11 of the lower chip to which the present technology is applied. It should be noted that the transmitter 11 may be mounted on a substrate (a mounting substrate such as a PCB) on which the image sensor 121 is mounted, rather than being formed on a lower chip of the image sensor 121. The transmitter 11 generates a multi-level signal based on the serial signal from the serializer 144, and transmits the multi-level signal to the receiver 12 of the application processor 12 on the mounting substrate via the transmission path 13 on the mounting substrate.

[0244] <Example of configuration combination>

[0245] Note that the present technology may also have the following configurations. (1)

[0247] A data processing device, comprising:

[0248] A plurality of drivers, each driver including a driver input terminal for inputting a control signal and a driver output terminal for outputting a voltage corresponding to the control signal input from the driver input terminal, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are a first driver to an M-th driver, wherein an integer greater than or equal to 3 and different from a power of 2 is the number of states N, a power of the smallest integer greater than or equal to N being a power of 2 is a control value M, and the driver output terminals are connected in parallel to a transmission line, through which a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted, wherein

[0249] The first driver to the Mth driver respectively include a first output resistor to an Mth output resistor, and in a case where any integer greater than or equal to 1 and less than or equal to M is represented by m, the resistance value of the mth output resistor where m is less than or equal to M-1 is a value obtained by dividing a predetermined resistance value by 2 to the (m-1) power, and the resistance value of the Mth output resistor where m is M is a value obtained by dividing a predetermined resistance value by a value obtained by subtracting 2 to the (M-1) power from N. (2)

[0251] The data processing device according to (1) further comprises:

[0252] A selection circuit selects a control signal to be input to a driver input terminal of each of the first to M-th drivers from a plurality of control signals, wherein:

[0253] The selection circuit changes the number of voltage levels of the multi-level signal to a value different from the number N of states by changing a control signal input to each of the first to M-th drivers. (3)

[0255] The data processing device according to (1) or (2), wherein:

[0256] The first to M-th drivers are unit drivers each including a unit resistor of a predetermined resistance value as an output resistor and are configured by connecting one or more unit drivers in parallel to each other,

[0257] The m-th driver having m less than or equal to M-1 is configured by connecting as many unit drivers as the m-th constituent value in parallel to each other, the m-th constituent value being a value obtained by multiplying 2 to the (m-1)th power by a natural number a, and

[0258] The Mth driver where m is M is configured by connecting as many unit drivers in parallel to each other as the Mth constituent value, which is a value obtained by multiplying a value obtained by subtracting 2 raised to the power of (M-1) from N by a natural number a. (4)

[0260] The data processing device according to (3), wherein:

[0261] Assuming that the control signal input to the mth driver is the mth control signal, the mth driver is configured by connecting as many unit drivers as the mth constituent value in parallel to one another between the mth power supply line supplying the mth control signal and the transmission line. (5)

[0263] The data processing device according to (3) or (4), further comprising:

[0264] A selection circuit selects a unit driver constituting each of the first to M-th drivers from a plurality of unit drivers, wherein:

[0265] The selection circuit changes the number of voltage levels of the multi-level signal to a value different from the number N of states by respectively changing first to M-th constituent values ​​of unit drivers constituting the first to M-th drivers. (6)

[0267] The data processing device according to (5), wherein:

[0268] The selection circuit changes the number of voltage levels of the multi-level signal to the number of states as many as a value obtained by adding 1 to any divisor of N-1. (7)

[0270] The data processing device according to (5), wherein:

[0271] A value obtained by adding 1 to any divisor of N-1 is set as the number of states N1, and a power of the smallest integer that is greater than or equal to the power of 2 of N1 is set as the control value M1,

[0272] In the case where any integer greater than or equal to 1 and less than or equal to M1 is represented by m1, a value obtained by multiplying 2 raised to the power of (m1-1) by (N-1) / (N1-1) is set as the m1-th constituent value where m1 is less than or equal to M1-1, and a value obtained by subtracting a value obtained by multiplying 2 raised to the power of (M1-1) by (N-1) / (N1-1) from N1 is set as the M1 constituent value where m1 is M1,

[0273] M1 power lines among the first to M-th power lines are set as the first to M1-th power lines, and

[0274] The selection circuit changes the number of voltage levels of the multi-level signal from the number of states N to the number of states N1 by switching the cell drivers as many as the m1-th constituent value to be connected to the m1-th power supply line. (8)

[0276] The data processing device according to (7), wherein:

[0277] In a case where the smaller of the constituent values ​​L(m) of the same rank m and the constituent value L1(m) between the constituent values ​​L(1) to the constituent value L(M) in which the first to Mth constituent values ​​are arranged in descending order when the number of voltage levels of the multi-level signal is set to the number of states N and the constituent values ​​L1(1) to L1(M) in which the first to M1th constituent values ​​are arranged in descending order when the number of voltage levels of the multi-level signal is set to the number of states N1 and the M1th constituent value and subsequent constituent values ​​are set to 0 when the control value M1 is less than the control value M is set to the constituent value Lmin(m), regardless of setting the number of states N or the number of states N1, the selection circuit always connects as many predetermined unit drivers as the constituent value Lmin(m) greater than or equal to 2 to the same power supply line (where m is an integer greater than or equal to 1 and less than or equal to M). (9)

[0279] The data processing device according to (8), wherein:

[0280] The selection circuit is provided for each unit driver and includes an input terminal to which first to M-th control signals are respectively input, a control signal output terminal connected to a driver input terminal of the unit driver, and a selection terminal to which a selection signal is input for selecting a control signal output from the control signal output terminal among the first to M-th control signals input from the input terminal, and

[0281] For as many predetermined unit drivers as the configuration value Lmin(m) greater than or equal to 2, the same selection signal is input to the selection terminal of the selection circuit. (10)

[0283] The data processing device according to any one of (3) to (9), wherein:

[0284] Each unit driver is mounted as a unit on an IC chip or a substrate. (11)

[0286] The data processing device according to any one of (5) to (10), wherein:

[0287] Each of the unit driver and the selection circuit for the unit driver is mounted as a unit on one IC chip or one substrate. (12)

[0289] The data processing device according to any one of (3) to (11), wherein:

[0290] The predetermined resistance value of the unit resistor of the unit driver is N-1 times the resistance value in a case where all of the first to M-th output resistors are connected in parallel to each other. (13)

[0292] A data processing device, comprising:

[0293] a plurality of drivers, each driver including a driver input terminal to which a control signal is input and a driver output terminal to which a voltage corresponding to the control signal input from the driver input terminal is output, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are a first driver to an M-th driver, wherein an integer greater than or equal to 3 is the number of states N, a power of the smallest integer which is a power of 2 greater than or equal to N is a control value M, and the driver output terminals are connected in parallel to a transmission line through which a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted; and

[0294] A selection circuit selects a control signal to be input to a driver input terminal of each of the first to M-th drivers from a plurality of control signals, wherein:

[0295] The selection circuit changes the number of voltage levels of the multi-level signal to a value different from the number N of states by changing a control signal input to each of the first to M-th drivers. (14)

[0297] A data processing method used by a data processing device, the data processing device comprising:

[0298] a plurality of drivers, each driver including a driver input terminal to which a control signal is input and a driver output terminal to which a voltage corresponding to the control signal input from the driver input terminal is output, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are a first driver to an M-th driver, wherein an integer greater than or equal to 3 is the number of states N, a power of the smallest integer which is a power of 2 greater than or equal to N is a control value M, and the driver output terminals are connected in parallel to a transmission line through which a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted; and

[0299] a selection circuit that selects a control signal to be input to a driver input terminal of each of the first to M-th drivers from a plurality of control signals,

[0300] The data processing method includes:

[0301] Using the selection circuit, the number of voltage levels of the multi-level signal is changed to a value different from the number N of states by changing a control signal input to each of the first to M-th drivers. (15)

[0303] The data processing method according to (14), wherein:

[0304] The first driver to the Mth driver respectively include a first output resistor to an Mth output resistor, and in a case where any integer greater than or equal to 1 and less than or equal to M is represented by m, the resistance value of the mth output resistor where m is less than or equal to M-1 is a value obtained by dividing a predetermined resistance value by 2 to the (m-1) power, and the resistance value of the Mth output resistor where m is M is a value obtained by dividing a predetermined resistance value by a value obtained by subtracting 2 to the (M-1) power from N.

[0305] Reference Mark List

[0306] 1Data transmission system

[0307] 11, 11-1, 11-2, 11-3 transmitter

[0308] 12 Receivers

[0309] 13Transmission Path

[0310] Unit 41

[0311] D Unit Driver

[0312] D0 to D M-1 Drive

[0313] M control value

[0314] MUX Multiplexer

[0315] N The number of states

[0316] R0 to R M-1 , R m Output resistor.

Claims

1. A data processing device, comprising: A plurality of drivers, each driver including a driver input terminal for inputting a control signal and a driver output terminal for outputting a voltage corresponding to the control signal input from the driver input terminal, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are a first driver to an M-th driver, wherein an integer greater than or equal to 3 and different from a power of 2 is the number of states N, a power of the smallest integer greater than or equal to N being a power of 2 is a control value M, and the driver output terminals are connected in parallel to a transmission line, and a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted through the transmission line as a signal to be transmitted, wherein The first driver to the Mth driver respectively include a first output resistor to an Mth output resistor, and in a case where any integer greater than or equal to 1 and less than or equal to M is represented by m, the resistance value of the mth output resistor where m is less than or equal to M-1 is a value obtained by dividing a predetermined resistance value by 2 to the power of (m-1), and the resistance value of the Mth output resistor where m is M is a value obtained by dividing the predetermined resistance value by a value obtained by subtracting 2 to the power of (M-1) from N.

2. The data processing device according to claim 1, further comprising: a selection circuit that selects a control signal to be input to the driver input terminal of each of the first driver to the Mth driver from the plurality of control signals, wherein: The selection circuit changes the number of voltage levels of the multi-level signal to a value different from the number N of the states by changing the control signal input to each of the first to M-th drivers.

3. The data processing device according to claim 1, wherein: The first to M-th drivers are unit drivers each including a unit resistor of a predetermined resistance value as an output resistor and are configured by connecting one or more of the unit drivers in parallel with each other, The m-th driver having m less than or equal to M-1 is configured by connecting as many of the unit drivers as an m-th constituent value, which is a value obtained by multiplying 2 to the (m-1)th power by a natural number a, in parallel with each other, and The Mth driver where m is M is configured by connecting as many unit drivers as the Mth constituent value obtained by multiplying a value obtained by subtracting 2 raised to the power of (M-1) from N by the natural number a in parallel with each other.

4. The data processing device according to claim 3, wherein: Assuming that the control signal input to the mth driver is an mth control signal, the mth driver is configured by connecting as many unit drivers as the mth constituent value in parallel to one another between an mth power supply line providing the mth control signal and the transmission line.

5. The data processing device according to claim 3, further comprising: A selection circuit selects a unit driver constituting each of the first to M-th drivers from a plurality of the unit drivers, wherein: The selection circuit changes the number of voltage levels of the multi-level signal to a value different from the number N of states by respectively changing first to M-th constituent values ​​of the unit drivers constituting the first to M-th drivers.

6. The data processing device according to claim 5, wherein: The selection circuit changes the number of voltage levels of the multi-level signal to the number of states which is as many as a value obtained by adding 1 to any divisor of N-1.

7. The data processing device according to claim 5, wherein: A value obtained by adding 1 to any divisor of N-1 is set as the number of states N1, and a power of the smallest integer that is greater than or equal to the power of 2 of N1 is set as the control value M1, In the case where any integer greater than or equal to 1 and less than or equal to M1 is represented by m1, a value obtained by multiplying 2 raised to the power of (m1-1) by (N-1) / (N1-1) is set as the m1-th constituent value where m1 is less than or equal to M1-1, and a value obtained by subtracting a value obtained by multiplying 2 raised to the power of (M1-1) by (N-1) / (N1-1) from N1 is set as the M1 constituent value where m1 is M1, M1 power lines among the first to M-th power lines are set as the first to M1-th power lines, and The selection circuit changes the number of voltage levels of the multi-level signal from the number N of states to the number N1 of states by switching the unit drivers as many as the m1-th constituent value to be connected to the m1-th power supply line.

8. The data processing device according to claim 7, wherein: In a case where the smaller of the constituent values ​​L(m) of the same rank m and the constituent value L1(m) between the constituent values ​​L(1) to the constituent value L(M) in which the first to Mth constituent values ​​are arranged in descending order when the number of voltage levels of the multilevel signal is set to the number of states N and the constituent values ​​L1(1) to L1(M) in which the first to M1th constituent values ​​are arranged in descending order when the number of voltage levels of the multilevel signal is set to the number of states N1 and the M1th constituent value and subsequent constituent values ​​are set to 0 when the control value M1 is less than the control value M is set to the constituent value Lmin(m), regardless of setting the number of states N or the number of states N1, the selection circuit always connects as many predetermined unit drivers as the constituent value Lmin(m) greater than or equal to 2 to the same power supply line (wherein m is an integer greater than or equal to 1 and less than or equal to M).

9. The data processing device according to claim 8, wherein: The selection circuit is provided for each of the unit drivers and includes an input terminal to which first to M-th control signals are respectively input, a control signal output terminal connected to the driver input terminal of the unit driver, and a selection terminal to which a selection signal is input for selecting a control signal output from the control signal output terminal from among the first to M-th control signals input from the input terminals, and For as many predetermined unit drivers as the configuration value Lmin(m) greater than or equal to 2, the same selection signal is input to the selection terminal of the selection circuit.

10. The data processing device according to claim 3, wherein: Each of the unit drivers is mounted as a unit on an IC chip or a substrate.

11. The data processing device according to claim 5, wherein: Each of the unit driver and the selection circuit for the unit driver is mounted as a unit on one IC chip or one substrate.

12. The data processing device according to claim 3, wherein: The predetermined resistance value of the unit resistor of the unit driver is N-1 times a resistance value in a case where all of the first to M-th output resistors are connected in parallel to each other.

13. A data processing device, comprising: a plurality of drivers, each driver including a driver input terminal to which a control signal is input and a driver output terminal to which a voltage corresponding to the control signal input from the driver input terminal is output, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are a first driver to an M-th driver, wherein an integer greater than or equal to 3 is the number of states N, a power of the smallest integer greater than or equal to N to the power of 2 is a control value M, and the driver output terminals are connected in parallel to a transmission line, and a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted through the transmission line; and a selection circuit that selects a control signal to be input to the driver input terminal of each of the first driver to the Mth driver from the plurality of control signals, wherein: The selection circuit changes the number of voltage levels of the multi-level signal to a value different from the number N of the states by changing the control signal input to each of the first to M-th drivers.

14. A data processing method used by a data processing device, the data processing device comprising: a plurality of drivers, each driver including a driver input terminal to which a control signal is input and a driver output terminal to which a voltage corresponding to the control signal input from the driver input terminal is output, and each driver output terminal outputs a high voltage or a low voltage corresponding to the control signal when the corresponding driver output terminal is in an open state, the plurality of drivers are a first driver to an M-th driver, wherein an integer greater than or equal to 3 is the number of states N, a power of the smallest integer greater than or equal to N to the power of 2 is a control value M, and the driver output terminals are connected in parallel to a transmission line, and a multi-level signal representing transmission data having as many voltage levels as the number of states N is transmitted as a signal to be transmitted through the transmission line; and a selection circuit that selects a control signal to be input to the driver input terminal of each of the first driver to the Mth driver from the plurality of control signals, The data processing method comprises: Using the selection circuit, the number of voltage levels of the multi-level signal is changed to a value different from the number N of states by changing the control signal input to each of the first to M-th drivers.

15. The data processing method according to claim 14, wherein: The first driver to the Mth driver respectively include a first output resistor to an Mth output resistor, and in a case where any integer greater than or equal to 1 and less than or equal to M is represented by m, the resistance value of the mth output resistor where m is less than or equal to M-1 is a value obtained by dividing a predetermined resistance value by 2 to the power of (m-1), and the resistance value of the Mth output resistor where m is M is a value obtained by dividing the predetermined resistance value by a value obtained by subtracting 2 to the power of (M-1) from N.

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