Array substrate and liquid crystal display device

Abstract

The present disclosure provides an array substrate and a liquid crystal display device, and belongs to the technical field of display. The array substrate comprises a plurality of sub-pixel units, each of which comprises a substrate, a thin film transistor, a pixel electrode and a common electrode. The thin film transistor comprises an active layer, and the active layer comprises a channel region. The pixel electrode is connected with a first electrode of the thin film transistor and comprises a plurality of electrode strips. At least one end of each electrode strip comprises at least one first corner. The common electrode is located on a side of the pixel electrode close to the substrate, and the orthogonal projection of the common electrode on the substrate overlaps with the orthogonal projection of the pixel electrode on the substrate. The common electrode in at least one sub-pixel unit comprises at least one second corner, and the orthogonal projection of the second corner on the substrate is located within the orthogonal projection of the region where the first corner of the electrode strip is located on the substrate. In addition, at least one sub-pixel unit further comprises a shielding layer, and the orthogonal projection of the shielding layer on the substrate covers the orthogonal projection of the channel region on the substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate and a liquid crystal display device. BACKGROUND

[0002] Liquid crystal display, or LCD (Liquid Crystal Display), is a flat, thin display device. The liquid crystal display generally includes a backlight plate, an array substrate (also known as a TFT substrate), a color film substrate, and liquid crystal between the color film substrate and the array substrate. The brightness of the liquid crystal display has always been an important display indicator of the product. However, when the brightness of the liquid crystal display is improved, Crosstalk (cross talk) defects often occur in the product. SUMMARY

[0003] Based on the background technology, the present disclosure provides an array substrate and a liquid crystal display device.

[0004] In a first aspect, the present disclosure provides an array substrate, comprising a plurality of sub-pixel units, each of the sub-pixel units comprising:

[0005] a substrate;

[0006] a thin film transistor on the substrate, comprising an active layer, the active layer comprising a channel region;

[0007] a pixel electrode comprising a plurality of electrode strips, at least one end of each of the electrode strips comprising at least one first corner; and

[0008] a common electrode on a side of the pixel electrode close to the substrate, a normal projection of the common electrode on the substrate overlapping a normal projection of the pixel electrode on the substrate;

[0009] wherein the common electrode in at least one of the sub-pixel units comprises at least one second corner, a normal projection of the second corner on the substrate being located within a normal projection on the substrate of a region of the electrode strip in which the first corner is located;

[0010] and at least one of the sub-pixel units further comprises a shielding layer, a normal projection of the shielding layer on the substrate covering at least a normal projection on the substrate of the channel region.

[0011] Exemplarily, the first corner has the same angle as the second corner.

[0012] Exemplarily, each of the electrode strips comprises opposite first and second ends, and the first corner is located at the first end.

[0013] The first vertical distance between the orthographic projection of the vertex of the first corner on the substrate to the orthographic projection of the second end on the substrate is greater than or equal to a second vertical distance between the orthographic projection of the vertex of the second corner on the substrate to the orthographic projection of the second end on the substrate.

[0014] The first vertical distance is greater than the second vertical distance, and the vertex of the second corner is located on the reverse extension line of the vertex of the first corner.

[0015] The electrode strip includes opposite first and second ends, and the first corner is located at the first end. A plurality of electrode strips include edge electrode strips located at edges and intermediate electrode strips adjacent to the edge electrode strips. The orthographic projection of the second corner on the substrate is located within the orthographic projection of the area where the first corner is located in the edge electrode strips on the substrate.

[0016] The common electrode is adjacent to the target end point of the first end point on the substrate, and has a lateral distance between the orthographic projection of the intermediate electrode strip on the substrate. The lateral distance increases as the vertical distance between the second corner and the second end decreases.

[0017] The end of the electrode strip includes at least one first corner.

[0018] The orthographic projection of the electrode strips in adjacent two sub-pixel units on the substrate is centrosymmetric.

[0019] The shielding layer includes a first shielding layer located on the side of the channel region close to the substrate, and / or a second shielding layer located on the side of the channel region away from the substrate.

[0020] The shielding layer includes the first shielding layer, and the thin film transistor includes:

[0021] A gate layer located on the side of the channel region close to the substrate.

[0022] Part or all of the area of the first shielding layer is the gate layer, and the orthographic projection of the first shielding layer on the substrate covers the orthographic projection of the active layer on the substrate.

[0023] The side of the substrate includes a plurality of gate lines, the active layer includes source and drain regions located on opposite sides of the channel region, and the source region, the channel region and the drain region are arranged in the extension direction of the gate lines.

[0024] The third vertical distance is greater than the fourth vertical distance.

[0025] The third vertical distance is greater than the fourth vertical distance.

[0026] Exemplarily, the third vertical distance is 4-5 μm, and the fourth vertical distance is 2.7-3 μm.

[0027] Exemplarily, one side of the substrate includes a plurality of data lines, the active layer includes a source region and a drain region located on opposite sides of the channel region, and the source region, the channel region and the drain region are arranged in the extension direction of the data lines.

[0028] The vertical distance between the outer contour of the projection of the first shielding layer on the substrate and the outer contour of the projection of the active layer on the substrate is 2.7-3 μm.

[0029] Exemplarily, the shielding layer includes the first shielding layer and the second shielding layer, and the thin film transistor includes:

[0030] A first gate layer is located on one side of the substrate.

[0031] A first gate insulating layer is located on the side of the first gate layer away from the substrate, and the active layer is located on the side of the first gate insulating layer away from the substrate.

[0032] A second gate insulating layer is located on the side of the active layer away from the substrate.

[0033] A second gate layer is located on the side of the second gate insulating layer away from the substrate.

[0034] Part or all of the first shielding layer is the first gate layer, and part or all of the second shielding layer is the second gate layer.

[0035] Exemplarily, the shielding layer includes the second shielding layer, and the second shielding layer includes:

[0036] An organic insulating layer, the projection of the organic insulating layer on the substrate covers the projection of the channel region on the substrate.

[0037] The refractive index of the organic insulating layer is less than the refractive index of liquid crystal.

[0038] Exemplarily, a preset relationship is satisfied between a size of the organic insulating layer in a normal line direction of the substrate, a size of the channel region in a plane direction of the substrate, a refractive index of the organic insulating layer, and a refractive index of the liquid crystal.

[0039] Exemplarily, the array substrate comprises a display area, and a plurality of the sub-pixel units are located in the display area, and the display area comprises a plurality of sub-display areas.

[0040] The shielding layer in the sub-pixel units in the plurality of sub-display areas has different spatial positions and / or shielding sizes.

[0041] The spatial position represents the relative positions of the shielding layer and the channel layer in the up-down direction of the substrate, and the shielding size comprises a vertical distance between the outer contour of the normal projection of the shielding layer on the substrate and the outer contour of the normal projection of the channel region on the substrate.

[0042] In a second aspect of the present disclosure, a liquid crystal display device is provided, comprising:

[0043] a color film substrate, and the array substrate as described in any of the exemplary embodiments of the first aspect.

[0044] The color film substrate and the array substrate are arranged in a cell-to-cell manner, and the color film substrate and the array substrate are filled with liquid crystal.

[0045] Exemplarily, a spacer is further arranged between the color film substrate and the array substrate.

[0046] The array substrate comprises an organic insulating layer, and the spacer is located on a side of the organic insulating layer away from the substrate, and the normal projection of the spacer on the substrate overlaps the normal projection of the organic insulating layer on the substrate.

[0047] Exemplarily, the organic insulating layer comprises a plurality of first grooves, the spacer comprises a plurality of first protruding portions respectively matched with the plurality of first grooves, and the plurality of first protruding portions are respectively embedded in the first grooves.

[0048] Alternatively, the spacer comprises a plurality of second grooves, and the organic insulating layer comprises a plurality of second protruding portions respectively matched with the plurality of second grooves, and the plurality of second protruding portions are respectively embedded in the second grooves.

[0049] The array substrate provided by the present disclosure comprises a plurality of sub-pixel units, and each sub-pixel unit comprises a substrate, a thin film transistor, a pixel electrode and a common electrode. The thin film transistor comprises an active layer, and the active layer comprises a channel region. The pixel electrode is connected with a first electrode of the thin film transistor and comprises a plurality of electrode strips. At least one end of each electrode strip comprises at least one first corner. The common electrode is located on a side of the pixel electrode close to the substrate, and a normal projection of the common electrode on the substrate overlaps a normal projection of the pixel electrode on the substrate. The common electrode in at least one sub-pixel unit comprises at least one second corner, and a normal projection of the second corner on the substrate is located within a normal projection of a region where the first corner of the electrode strip is located on the substrate. In addition, the at least one sub-pixel unit further comprises a shielding layer, and a normal projection of the shielding layer on the substrate covers a normal projection of the channel region on the substrate. By adding the second corner to the common electrode, an electric field can be formed between the second corner and the first corner, so that the electric field at the end of the pixel electrode is improved, thereby increasing the light output of the sub-pixel unit, and thus the light efficiency of the product is improved. By adding the shielding layer to shield the channel region, the characteristics of the thin film transistor can be prevented from changing when the channel region is irradiated by high-brightness backlight, such as improving the phenomenon of increasing Ioff of the thin film transistor, so that the product does not have the Crosstalk defect. In summary, by using the shielding layer and the second corner, the product can have high display brightness while avoiding the Crosstalk defect caused by using high-brightness backlight.

[0050] The above description is only a summary of the technical solutions of the present disclosure. In order to more clearly understand the technical means of the present disclosure, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described below. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0052] Figure 1 A top view schematic diagram of an array substrate is shown;

[0053] Figure 2 A cross-sectional structure schematic diagram of a sub-pixel unit of Figure 1 in the A-A direction is shown;

[0054] Figure 3 A cross-sectional structure schematic diagram of a sub-pixel unit ofFigure 1 An enlarged schematic diagram of the S1 region of the sub-pixel unit;

[0055] Figure 4 It shows Figure 1 A schematic diagram illustrating the working principle of the shielding layer present in the image;

[0056] Figures 5-9 Enlarged schematic diagrams of partial regions S1 of several sub-pixel units are shown respectively;

[0057] Figure 10 It shows Figure 9 An enlarged schematic diagram of the defined region H in the diagram;

[0058] Figure 11 A planar schematic diagram of yet another array substrate is shown;

[0059] Figure 12 It shows Figure 11 A schematic diagram of the layout of the common electrodes in the diagram;

[0060] Figure 13 It shows Figure 1 Enlarged schematic diagram of region S2 in the middle;

[0061] Figure 14 A schematic diagram showing the coverage relationship between the first shielding layer and the active layer is shown;

[0062] Figure 15 and Figure 18 Schematic diagrams of the layouts of the two array substrates are shown respectively;

[0063] Figure 16 It shows Figure 15 Enlarged schematic diagram of region S2 in the middle;

[0064] Figure 17 A cross-sectional schematic diagram of a thin-film transistor in yet another embodiment is shown;

[0065] Figure 19 yes Figure 18 Enlarged schematic diagram of region S2 in the middle;

[0066] Figure 20 A schematic diagram of the optical path between the backlight reflected by the cover plate and the organic insulating layer is shown;

[0067] Figure 21 The diagram illustrates several different ways of dividing the display area;

[0068] Figure 22 A cross-sectional structural schematic diagram of a liquid crystal display device is shown;

[0069] Figure 23 The diagram shows the shapes of various complementary designs of organic insulating layers and spacer pillars.

[0070] BRIEF DESCRIPTION OF DRAWINGS

[0071] 100, array substrate; 200, color film substrate; 300, spacer; 11, substrate; 12, thin film transistor; 13, electrode strip; 14, common electrode; 121, gate layer; 122, gate insulating layer; 123, active layer; 124, drain electrode; 125, source electrode; 15, shielding layer; 16, planarization layer; 17, data line; 18, gate line; 131, first corner; 141, second corner; 20, opening area; 13a, first end of electrode strip; 13b, second end of electrode strip; 132, middle electrode strip; 133, edge electrode strip; 1231, channel area; 1233, source area; 1232, drain area; 151, sub-shielding layer; 1211, first gate layer; 1212, second gate layer; 1221, first gate insulating layer; 1222, second gate insulating layer; 1213, via hole; 110, sub-display area; 21, black matrix layer; 22, color film layer; 23, OC layer; 24, transparent substrate. DETAILED DESCRIPTION

[0072] In order to make the above objectives, features and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0073] With the increasing demand for liquid crystal display products, it is necessary to improve the brightness of liquid crystal display products. For example, in products such as smart phones, outdoor billboards, automobile instruments, navigation devices and outdoor signboards, display brightness is an important quality index. The brightness improvement scheme of the liquid crystal display product includes the following:

[0074] 1. Optimizing pixel design, increasing the number of pixel electrode strips, and improving light efficiency; 2. Increasing pixel aperture ratio; 3. Replacing CF color resistance raw material; 4. Replacing liquid crystal raw material; 5. Using high-brightness backlight plate;

[0075] Generally, according to the use environment of the liquid crystal display product, the above-mentioned five solutions can be appropriately adopted, such as using a high-brightness backlight panel in outdoor display. However, each of the above-mentioned solutions has disadvantages. For example, although increasing the number of pixel electrode strips can improve the transmittance of the product, under the condition of a certain aperture ratio, it needs to greatly improve the process capacity, and the VOP of the product will also be increased accordingly, and the actual capacity demand of the IC is also increased. Secondly, to increase the pixel aperture ratio, the commonly used method is to reduce the wrapping distance of the black matrix to the structure that needs to be shielded on the array substrate. In this way, for high-brightness / high-transmittance products, the strong light incident from the backlight panel will be reflected to the active layer (mainly the channel region) of the thin film transistor, and the active layer will be affected by the strong light to generate charge drift, so that the Ioff is increased, and serious cross-talk (CT) failure occurs. Similarly, for high-brightness backlight panels, the direction of the backlight after the birefringence effect of the liquid crystal is deflected, and after the deflection, it also irradiates the active layer (mainly the channel region) in the thin film transistor TFT, thereby causing CT failure (referred to as CT failure).

[0076] Thirdly, for replacing the liquid crystal raw material, it is limited by the development and verification of new materials by the supplier, and generally not applied in actual production.

[0077] As can be seen, in the related art, if the display brightness is to be improved, either high-brightness backlight or increasing the pixel aperture ratio will cause CT failure of the product. If CT failure is to be avoided, the wrapping of the active layer needs to be increased, such as increasing the wrapping distance of the black matrix to the active layer. In this way, the aperture ratio is also reduced, which affects the display brightness. Therefore, how to avoid CT failure and improve the display brightness has become a very difficult problem in actual production.

[0078] Therefore, the inventors propose an optimization scheme for a sub-pixel structure, which optimizes the pixel electrode and the common electrode in the sub-pixel structure, so as to start from the structural characteristics of the pixel electrode and the common electrode, to optimize the display light efficiency and improve the transmittance and brightness of the product without increasing the actual production demand. On this basis, the channel region of the active layer can also be shielded by the shielding layer to improve the CT failure. In this way, the wrapping distance of the black matrix to the active layer can be reduced, the aperture ratio is improved, and the overall display brightness of the product is improved.

[0079] First, before formally introducing the embodiments of the array substrate proposed in the present disclosure, the technical terms used in the embodiments are explained as follows:

[0080] Corner: refers to a point and a figure formed between two non-parallel line segments connected by the point, the point is also called the intersection point of the two straight lines, and the point is also called the vertex of the corner; the degree of the corner refers to the angle formed at the intersection point of the two line segments. In the embodiment, the two line segments constituting the corner can both be straight line segments, both be circular arc segments, or one of the two line segments is a straight line segment and the other is a circular arc segment.

[0081] Parallel: refers to the case that the included angle between two straight lines is 0-5°, the included angle between the two straight lines is 0°, and the included angle between the two straight lines is 5°, that is, the included angle between the two straight lines is within the range of 0-5°, which can be called as the two straight lines being orthogonal.

[0082] Please refer to Figures 1-4 , Figure 1 a schematic view of the top plane of the array substrate is shown, Figure 2 a schematic view of the cross-sectional structure of the sub-pixel unit in the A-A direction of Figure 1 a schematic view of the S1 region of the sub-pixel unit in Figure 3 a schematic view of the S1 region of the sub-pixel unit in Figure 1 a schematic view of the S1 region of the sub-pixel unit in Figure 4 a schematic view of the S1 region of the sub-pixel unit in Figure 1 the principle of the shielding layer in Figures 1-4 As shown in the embodiment, the array substrate includes a plurality of sub-pixel units, wherein each sub-pixel unit can include the following structure:

[0083] a substrate 11;

[0084] a thin film transistor 12 located on the substrate 11 and including an active layer 123, the active layer 123 including a channel region 1231;

[0085] a pixel electrode including a plurality of electrode strips 13, at least one end of the electrode strip 13 including at least one first corner 131; and

[0086] a common electrode 14 located on the side of the pixel electrode close to the substrate, the orthogonal projection of the common electrode 14 on the substrate 11 overlapping the orthogonal projection of the pixel electrode on the substrate 11;

[0087] wherein the common electrode 14 in at least one sub-pixel unit includes at least one second corner 141, the orthogonal projection of the second corner on the substrate 11 being located within the orthogonal projection of the region where the first corner 131 of the electrode strip 13 is located on the substrate 11;

[0088] and at least one sub-pixel unit further includes a shielding layer 15, the orthogonal projection of the shielding layer on the substrate covering the orthogonal projection of the channel region 1231 on the substrate.

[0089] In this embodiment, the substrate of the sub-pixel unit can be a flexible substrate or a non-flexible substrate, specifically, the substrate can be a transparent substrate such as a glass substrate or a silicon-based substrate; for example, it can be a Corning or Asahi glass with a thickness of 50-1000 μm and other quartz glass and the like. Among them, the substrate can be divided into a display area and a non-display area, the non-display area can enclose the display area, or partially enclose the display area, and a plurality of sub-pixel units can be located in the display area.

[0090] Among them, a plurality of sub-pixel units can be arranged in an array in the display area, for example, arranged in an array in the row direction and the column direction, and the area occupied by the orthogonal projection of each sub-pixel unit on the substrate can be referred to as a sub-pixel area.

[0091] Among them, the thin film transistor can be a bottom-gate type thin film transistor, so that the light of the backlight irradiating the array substrate can be shielded by the gate layer, and the irradiation of the active layer by the backlight can be reduced. Specifically, as shown in Figure 2 The bottom-gate type thin film transistor can include a gate layer 121, a gate insulating layer 122, an active layer 123, and a first electrode 124 and a second electrode 125 connected to the active layer 123. Specifically, the gate layer is located on one side of the substrate, the gate insulating layer is located on the side of the gate layer away from the substrate, the active layer is located on the side of the gate insulating layer away from the substrate, the active layer includes a channel region 1231, one side of the opposite two regions of the channel region 1231 is a source region 1232, the first electrode is connected to the source region 1232, the other side is a drain region 1233, and the second electrode is connected to the drain region 1233. The first electrode can be the source electrode of the thin film transistor, and the second electrode can be the drain electrode of the thin film transistor.

[0092] Among them, the active layer can be a low-temperature polycrystalline silicon material, such as an A-Si material, and the process of forming the active layer is: forming a pattern of A-Si layer on the substrate, and then using excimer laser annealing to crystallize the A-Si layer to form the active layer.

[0093] Among them, the pixel electrode can be connected to the first electrode or the second electrode of the thin film transistor, and the pixel electrode can include a plurality of electrode strips arranged at intervals, and the orthogonal projection of the plurality of electrode strips on the substrate can be located in the sub-pixel area. Specifically, as shown in Figure 1 and Figure 2 The pixel electrode includes a connection portion and a plurality of electrode strips connected to the connection portion, and the connection portion is connected to the first electrode or the second electrode of the thin film transistor through a via.

[0094] The first corner can be formed by a straight line segment and a circular arc segment, or by two straight line segments. Figure 3 As shown in FIG. 2A, the first corner can be formed by a straight line segment and a circular arc segment.

[0095] As shown in FIG. 2B, the first corner can be formed by two straight line segments.

[0096] The common electrode can be arranged in the same layer as the active layer of the thin film transistor, or in the same layer as the first electrode and the second electrode. The common electrode is arranged on the side of the pixel electrode close to the substrate and overlaps the pixel electrode. The overlap can include that the projection of the common electrode on the substrate is located within the projection of the pixel electrode on the substrate, or the projection of the common electrode on the substrate is staggered with the projection of the pixel electrode on the substrate, for example, the projection of a part of the common electrode on the substrate is located within the projection of the pixel electrode on the substrate, and the projection of the rest of the common electrode on the substrate does not overlap the projection of the pixel electrode on the substrate. Figure 1 As shown in FIG. 3A, the projection of the common electrode on the substrate is located within the projection of the pixel electrode on the substrate. Figure 3 As shown in FIG. 3B, the projection of the common electrode on the substrate is staggered with the projection of the pixel electrode on the substrate.

[0097] As shown in FIG. 4A and FIG. 4B, the pixel electrode includes a plurality of electrode strips, which can include two edge electrode strips located at the edges and an intermediate electrode strip located between the two edge electrode strips. The outer contour of the projection of the common electrode on the substrate can overlap the projections of the two edge electrode strips on the substrate. Figure 1 As shown in FIG. 5A, the outer contour of the projection of the common electrode on the substrate overlaps the projections of the two edge electrode strips on the substrate. Figure 3 As shown in FIG. 5B, the outer contour of the projection of the common electrode on the substrate does not overlap the projections of the two edge electrode strips on the substrate.

[0098] In this embodiment, there is at least one sub-pixel unit, and the common electrode in the sub-pixel unit includes at least one second corner. The second corner can be formed by bending the edge of the common electrode, that is, the edge of the common electrode is bent at least once to form the second corner.

[0099] The orthographic projection of the second corner onto the substrate can lie within the orthographic projection of the region containing the first corner of the electrode strip onto the substrate. Specifically, the orthographic projections of the second corner and the first corner onto the substrate can lie at the same end of the electrode strip. For example, if the first end of the electrode strip has a first corner, then the orthographic projection of the second corner onto the substrate can also lie at the first end of the electrode strip. As described above, the outer contour of the orthographic projection of the second corner onto the substrate can overlap with the orthographic projections of the two edge electrode strips onto the substrate. Figure 3 As shown, the orthogonal projection of the second corner of the common electrode onto the substrate can be located within the orthogonal projection of the edge electrode strip onto the substrate.

[0100] The common electrode may include a second corner, the orthographic projection of which on the substrate may be located within the orthographic projection of an edge electrode strip on the substrate; or, the common electrode may include multiple second corners, the orthographic projections of which on the substrate may be located within the orthographic projection of the same edge electrode strip on the substrate; or, the common electrode may include multiple second corners, the orthographic projections of which on the substrate may be located within the orthographic projections of two edge electrode strips on the substrate respectively. In this case, the common electrode may form second corners on opposite side edges.

[0101] In this embodiment, the first corner and the second corner can have the same orientation, for example, as shown below. Figure 3 As shown, both the first and second corners can face the direction of the middle electrode strip. The degree of the first corner can be 10 to 90°, and the degree of the second corner can be 10 to 90°; or, the degree of the first corner can be 90 to 170°, and the degree of the second corner can be 0 to 170°; or, the first corner can be an acute angle, and the second corner can be an obtuse angle, or, the first corner can be an obtuse angle, and the second corner can be an acute angle.

[0102] The region where the first corner of the electrode strip is located, within its orthographic projection onto the substrate, may include multiple second corners, or may include only one first corner. Specifically, the number of second corners may be the same as the number of first corners included at one end of the electrode strip. For example, if one end of the electrode strip includes a first corner, then the common electrode includes a second corner at the corresponding position of the first corner of the electrode strip. Alternatively, the number of second corners may differ from the number of first corners included at one end of the electrode strip. For example, ... Figure 3 As shown, one end of the electrode strip includes multiple first corners, and the common electrode includes a second corner at the corresponding position of the first corner of the electrode strip.

[0103] Since the second corner on the common electrode and the first corner on the electrode strip are located at the same end of the electrode strip, the common electrode and the pixel electrode can form a relatively complex electric field at the two corners (the first corner and the second corner). Under the action of this electric field, the light transmittance at this location can be increased, thereby improving the display brightness.

[0104] In this embodiment, at least one sub-pixel unit exists, and the sub-pixel unit may further include a masking layer 15, the orthographic projection of which on the substrate at least covers the orthographic projection of the channel region 1231 on the substrate. For example... Figure 4 As shown, the shielding layer can be disposed on the side of the active layer near the substrate, that is, the shielding layer can be located between the active layer and the backlight; or, the shielding layer can be disposed on the side of the active layer away from the substrate, that is, the shielding layer can be located between the active layer and the light-emitting surface; or, the shielding layer can be disposed on both the side of the active layer away from the substrate and the side of the active layer near the substrate.

[0105] The shielding layer can be formed of an opaque material, specifically, it can be a metallic material or a non-metallic material. When it is a non-metallic material, it can be an organic material or an inorganic material.

[0106] like Figure 4 As shown in (a), when the shielding layer is disposed on the side of the active layer near the substrate, the shielding layer can block the backlight from directly illuminating the channel region. Furthermore, as the area of ​​the channel region covered by the shielding layer increases, it can further reduce the brightness of the reflected light reflected from the light-emitting surface to the array substrate, thereby further reducing the risk of TFT characteristic changes and improving CT defects.

[0107] like Figure 4 As shown in (b), when the shielding layer is disposed on the side of the active layer away from the substrate, the shielding layer can block the reflected light reflected from the plate on the light-side of the substrate to the array substrate from illuminating the channel area. In this way, with the shielding layer above the channel area, while increasing the aperture ratio of the sub-pixels, the reflected light reflected from the plate on the light-side of the substrate to the array substrate can be completely blocked above the channel area. Thus, while ensuring the aperture ratio and improving the display brightness, CT defects can be further improved.

[0108] In one example, the common electrode of each sub-pixel unit may include a second corner, and the channel region of each sub-pixel unit may have a masking layer.

[0109] The array substrate used in this embodiment has the following advantages:

[0110] In one aspect, the second corner included in the common electrode in the sub-pixel unit can cooperate with the first corner to improve light transmittance and increase display brightness of the product, so that the sub-pixel unit can also improve display brightness under the same aperture ratio, and in practice, the wrapping distance of the black matrix to the active layer can be increased to protect the active layer from being irradiated and avoid CT defects. Therefore, the display brightness can be improved while the CT defects are improved.

[0111] In another aspect, the shielding layer including the shielding channel region in the sub-pixel unit can avoid irradiation of the channel region by high-brightness backlight or reflected backlight through the shielding layer, thereby avoiding CT defects, so that the wrapping distance of the black matrix to the active layer can be reduced to increase the aperture ratio of the sub-pixel, and the aperture ratio is increased, so that the light transmittance can be improved to increase the display brightness. Therefore, the display brightness can be improved while the CT defects are improved.

[0112] In still another aspect, the shielding layer including the shielding channel region in the sub-pixel unit can allow the wrapping distance of the black matrix to the active layer to be reduced and the aperture ratio of the sub-pixel to be increased, and the second corner of the common electrode in the sub-pixel unit can further increase the light transmittance and improve the display brightness under the condition of increased aperture ratio, so that the display brightness is doubled, thereby improving the display brightness while improving the CT defects.

[0113] In one example of the embodiment, the degree of the first corner can be the same as the degree of the second corner, which can include a case where the difference between the degree of the first corner and the degree of the second corner is 1-2°.

[0114] For example, reference can be made to Figure 5 , Figure 5 An enlarged schematic view of a partial region S1 of still another sub-pixel unit is shown, as Figure 5 shown, the second corner and the first corner have the same orientation, and the first corner and the second corner are both obtuse angles, and the degree of the first corner is the same as the degree of the second corner.

[0115] When this embodiment is adopted, the first corner and the second corner at the edge of the electrode strip are designed in parallel, which can reduce the dark area of the edge of the sub-pixel, thereby improving the brightness of the edge, and thus the display brightness can be further improved.

[0116] In still another example in the embodiment, the relative position between the second corner and the first corner can be adjusted to further improve the display brightness, for example, the second corner can be closer to the opening region of the sub-pixel than the first corner to improve the display brightness. The opening region refers to a region in the sub-pixel unit that is not shielded by the black matrix (black matrix on the color filter substrate).

[0117] In this example, the first corner at the first end of the electrode strip is used as an example. The electrode strip includes a first end and a second end opposite to each other, and the first corner is located at the first end; wherein, the first vertical distance between the orthographic projection of the vertex of the first corner onto the substrate and the orthographic projection of the second end onto the substrate is greater than or equal to the second vertical distance between the orthographic projection of the vertex of the second corner onto the substrate and the orthographic projection of the second end onto the substrate.

[0118] In this embodiment, please refer to Figure 6 and Figure 7 As shown, Figure 6 and Figure 7 Two layout diagrams of a portion of the pixel unit S1 are shown respectively, as follows: Figure 6 and Figure 7 As shown, the electrode strip includes a first end 13a and a second end 13b opposite to each other. Taking the first corner located at the first end as an example, the first vertical distance between the first corner and the second end can be greater than the second vertical distance between the second corner and the second end. The first vertical distance can be the straight-line distance D1 between the focus of the perpendicular line between the vertex of the first corner and the horizontal line L where the second end is located and the vertex of the first corner. Similarly, the second vertical distance can be the straight-line distance D2 between the focus of the perpendicular line between the vertex of the second corner and the horizontal line L where the second end is located and the vertex of the second corner.

[0119] The first vertical distance can be the same as the second vertical distance, for example, such as... Figure 6 As shown, the line connecting the vertices of the first and second corners can be parallel to the horizontal line L containing the second end. Figure 6 As shown, the vertex of the first corner can be located at the edge of the opening area of ​​the sub-pixel, and the vertex of the second corner can also be located at the edge of the opening area of ​​the sub-pixel, and is on the same edge of the opening area of ​​the sub-pixel as the vertex of the first corner.

[0120] The first vertical distance can be greater than the second vertical distance, for example, such as... Figure 7 As shown, the line connecting the vertex of the first corner and the vertex of the second corner may not be parallel to the horizontal line L where the second end is located, and the vertex of the second corner is closer to the second end of the electrode strip, that is, the vertex of the second corner is further away from the edge of the opening area of ​​the sub-pixel.

[0121] In one example, such as Figure 7As shown, in the case that the first vertical distance is greater than the second vertical distance, the orthographic projection of the first corner on the substrate does not overlap with the opening region of the sub-pixel, and the orthographic projection of the second corner on the substrate can be located within the opening region of the sub-pixel. For example, the first corner can be located outside the opening region of the sub-pixel, and the second corner can be located within the opening region of the sub-pixel. For another example, as shown in Figure 7 As shown, the vertex of the first corner can be located on the edge of the opening region of the sub-pixel, and the second corner can be located within the opening region of the sub-pixel.

[0122] In some other examples, in the case that the first vertical distance is greater than or equal to the second vertical distance, the first corner and the second corner can both be located outside or within the opening region of the sub-pixel (not shown in the figure).

[0123] With such an embodiment, the degrees of the first corner and the second corner can be the same or different. In the case of the same, the second corner is closer to the opening region of the sub-pixel than the first corner, and thus the second corner does not only form an electric field with the first corner parallel thereto, but also forms a complex electric field with the edge of the electrode strip, thereby further increasing the light transmittance and light efficiency.

[0124] Of course, in some other embodiments, the first vertical distance corresponding to the first corner can also be less than the second vertical distance corresponding to the second corner. For example, as shown in Figure 5 As shown, in this case, the first corner is arranged closer to the opening region of the sub-pixel than the second corner. The orthographic projection of the first corner and the orthographic projection of the second corner on the substrate do not overlap with the opening region of the sub-pixel. For example, the first corner and the second corner are located outside the opening region of the sub-pixel. For another example, as shown in Figure 5 As shown, the vertex of the first corner is located on the edge of the opening region of the sub-pixel, and the second corner is located outside the opening region of the sub-pixel.

[0125] In yet some other embodiments, in the case that the second vertical distance between the vertex of the second corner and the second end continuously decreases, the target end point of the common electrode connected with the second corner can continuously approach the electrode strip of the edge.

[0126] Specifically, the first corner and the second corner can be located on the same side of the edge of the common electrode. Figure 8 As shown, Figure 8 Fig. 6 shows a comparison diagram of the second corner design of two common electrodes, and Fig. 7 shows a comparison diagram of the second corner design of two common electrodes. Figure 8 As shown, the plurality of electrode strips include an edge electrode strip located on the edge and an intermediate electrode strip adjacent to the edge electrode strip, and the orthographic projection of the second corner on the substrate is located within the area on the substrate where the first corner of the edge electrode strip is located. Specifically, the target end point of the common electrode connected with the second corner and close to the first end point has a horizontal distance with the orthographic projection of the intermediate electrode strip on the substrate, and the horizontal distance increases with the decrease of the second vertical distance.

[0127] As Figure 8 shown, the transverse distance can refer to the vertical distance D3 between the target end point and the middle electrode strip; wherein the target end point can refer to an end point A in the common electrode adjacent to the second corner and close to the second end of the edge electrode strip, in the case that the vertex of the second corner is constantly close to the opening area of the sub-pixel, that is, the second vertical distance is constantly decreasing, the target end point is constantly away from the middle electrode strip.

[0128] As Figure 8 shown, Figure 8 the second vertical distance corresponding to the second corner of the common electrode 14 shown by the solid line is greater than the second vertical distance corresponding to the second corner of the common electrode 14' shown by the dashed line, that is, the second corner of the common electrode shown by the dashed line is closer to the opening area; and the transverse distance between the target end point A of the common electrode 14 and the middle electrode strip is less than the transverse distance between the target end point A' of the common electrode 14' and the middle electrode strip. As Figure 8 can be seen, the target end point A' is more to the right. In this way, as the target end point is constantly away from the middle electrode strip, it can form a more complex electric field with the peripheral edge of the pixel electrode, thereby increasing the light efficiency.

[0129] In a further example of the example, the position of the vertex of the second corner and the angle size of the second corner can be set with the limit position of the target end point as the maximum limit, and the limit position of the target end point can be the position of the first electrode or the second electrode of the thin film transistor.

[0130] Specifically, the thin film transistor further includes a second electrode, and the first electrode and the second electrode are connected to the regions on the opposite sides of the channel region of the active layer; wherein the orthographic projection of the target end point on the substrate can intersect with the orthographic projection of the first electrode or the second electrode on the substrate. As Figure 8 shown, when the target end point is constantly moved to the right to the junction of the first electrode and the second electrode, the light efficiency can reach the maximum.

[0131] In a further example of the embodiment, in the case that the second vertical distance corresponding to the second corner is less than the first vertical distance corresponding to the first corner, the target structure feature between the second corner and the first corner can make the sub-pixel achieve the maximum light efficiency under the same aperture ratio. Specifically, as Figure 9 and Figure 10 shown, Figure 9 a schematic diagram of a partial region S1 of another sub-pixel unit is shown, Figure 10 an enlarged schematic diagram of the circled region H in Figure 9 is shown, as Figure 9 and Figure 10As shown, the vertex of the second corner is located at the reverse extension line of the vertex of the first corner.

[0132] In the case where the common electrode includes only one second corner, the electrode strip includes a first corner corresponding to the position of the second corner, and the vertex of the second corner is located on the reverse extension line of the vertex of the first corner. In this case, the right-angled triangle is formed by the perpendicular line from the vertex of the second corner to the common electrode, the straight line segment between the vertex of the second corner and the vertex of the first corner, and the line segment between the intersection of the perpendicular line from the vertex of the first corner to the common electrode and the vertex of the second corner.

[0133] For example, as shown in FIG. 1A, the first end of the electrode strip includes a plurality of first corners, and the common electrode includes a plurality of second corners. In the direction from the first end to the second end, the target first corner is located at the end position among the plurality of first corners, and the target second corner is located at the start position among the plurality of second corners. The vertex of the target second corner is located on the reverse extension line of the vertex of the target first corner. Figure 9 Figure 10 For example, as shown in FIG. 1A, the first end of the electrode strip includes a plurality of first corners, and the common electrode includes a plurality of second corners. In the direction from the first end to the second end, the target first corner is located at the end position among the plurality of first corners, and the target second corner is located at the start position among the plurality of second corners. The vertex of the target second corner is located on the reverse extension line of the vertex of the target first corner.

[0134] For example, as shown in FIG. 1A, the first end of the electrode strip includes a plurality of first corners, and the common electrode includes a plurality of second corners. In the direction from the first end to the second end, the target first corner is located at the end position among the plurality of first corners, and the target second corner is located at the start position among the plurality of second corners. The vertex of the target second corner is located on the reverse extension line of the vertex of the target first corner.

[0135] For example, as shown in FIG. 1A, the first end of the electrode strip includes a plurality of first corners, and the common electrode includes a plurality of second corners. In the direction from the first end to the second end, the target first corner is located at the end position among the plurality of first corners, and the target second corner is located at the start position among the plurality of second corners. The vertex of the target second corner is located on the reverse extension line of the vertex of the target first corner. Figure 9 For example, as shown in FIG. 1A, the first end of the electrode strip includes a plurality of first corners, and the common electrode includes a plurality of second corners. In the direction from the first end to the second end, the target first corner is located at the end position among the plurality of first corners, and the target second corner is located at the start position among the plurality of second corners. The vertex of the target second corner is located on the reverse extension line of the vertex of the target first corner.

[0136] For example, as shown in FIG. 1A, the first end of the electrode strip includes a plurality of first corners, and the common electrode includes a plurality of second corners. In the direction from the first end to the second end, the target first corner is located at the end position among the plurality of first corners, and the target second corner is located at the start position among the plurality of second corners. The vertex of the target second corner is located on the reverse extension line of the vertex of the target first corner. Figure 9 For example, as shown in FIG. 1A, the first end of the electrode strip includes a plurality of first corners, and the common electrode includes a plurality of second corners. In the direction from the first end to the second end, the target first corner is located at the end position among the plurality of first corners, and the target second corner is located at the start position among the plurality of second corners. The vertex of the target second corner is located on the reverse extension line of the vertex of the target first corner.

[0137] For example, as shown in FIG. 1A, the first end of the electrode strip includes a plurality of first corners, and the common electrode includes a plurality of second corners. In the direction from the first end to the second end, the target first corner is located at the end position among the plurality of first corners, and the target second corner is located at the start position among the plurality of second corners. The vertex of the target second corner is located on the reverse extension line of the vertex of the target first corner. Figure 9 ​As shown, the plurality of second corners are all located within the opening region of the sub-pixel, and the plurality of first corners can all be located outside the opening region of the sub-pixel. Alternatively, in some other examples, the plurality of second corners are all located within the opening region of the sub-pixel, and the plurality of first corners can include corners located outside the opening region of the sub-pixel, and corners located within the opening region of the sub-pixel. Alternatively, the plurality of second corners can include corners located within the opening region of the sub-pixel and corners located outside the opening region, and the plurality of first corners can include corners located outside the opening region of the sub-pixel and corners located within the opening region of the sub-pixel.

[0138] In the embodiment, the plurality of first corners include a target first corner located at the end position, and the plurality of second corners include a target second corner located at the start position, wherein the vertex D of the target first corner is perpendicular to the common electrode, the perpendicular line has an intersection G with the edge of the common electrode, the target second corner has a vertex E, and the perpendicular distance D4 from the vertex D of the target first corner to the common electrode, the straight line distance D5 between the vertex E of the target second corner and the vertex D of the target first corner, and the straight line distance D6 between the vertex E of the target second corner and the intersection G satisfy the Pythagorean theorem.

[0139] It should be noted that the straight line segment D6 between the vertex E of the target second corner and the intersection G coincides with the edge of the common electrode, so that the vertex D of the target first corner, the vertex E of the target second corner and the intersection G form a right triangle; wherein the straight line segment between the vertex E of the target second corner and the vertex D of the target first corner is the hypotenuse of the right triangle.

[0140] With such a configuration, the light efficiency of the product can be maximized.

[0141] It should be noted that, Figures 5-9 For the convenience of illustration, the electrode strips and the common electrode strips are not pattern filled.

[0142] In some other embodiments, the electrode strip can include at least one first corner only at one end; wherein the pattern of the orthogonal projection of the electrode strip on the substrate in the adjacent two sub-pixel units is center-symmetric.

[0143] Referring to Figure 11 As shown, Figure 11 A plan view of another array substrate is shown, as Figure 11 As shown, the electrode strip in each sub-pixel unit on the array substrate is provided with a first corner only at one end, and the positions of the second corners on the common electrode correspond to the positions of the first corners of the electrode strips. For example, as Figure 12 As shown, Figure 12 A layout diagram of the common electrode in Figure 11 is shown, as Figure 12As shown, the common electrode sets the second corner at the corresponding position of the first corner of the edge electrode strip, and the second corners in different sub-pixel units are located at different positions of the common electrode.

[0144] The pattern of the orthogonal projection of the electrode strips in the two adjacent sub-pixel units on the substrate is centrally symmetric, which can mean that one electrode strip is mirror-symmetric to another electrode strip, for example, one electrode strip is obtained by vertically flipping another electrode strip. The two adjacent sub-pixel units can mean the sub-pixel units adjacent in the horizontal direction (the extension direction of the gate line), or can mean the sub-pixel units adjacent in the vertical direction (the extension direction of the data line); or, as shown, can mean every two adjacent sub-pixel units. Figure 12 The pattern of the orthogonal projection of the electrode strips in the two adjacent sub-pixel units on the substrate is centrally symmetric, which can mean that one electrode strip is mirror-symmetric to another electrode strip, for example, one electrode strip is obtained by vertically flipping another electrode strip. The two adjacent sub-pixel units can mean the sub-pixel units adjacent in the horizontal direction (the extension direction of the gate line), or can mean the sub-pixel units adjacent in the vertical direction (the extension direction of the data line); or, as shown, can mean every two adjacent sub-pixel units.

[0145] With this embodiment, one end of the electrode strip has the first corner and the other end of the electrode strip has no first corner, thereby increasing the aperture ratio of the sub-pixel, improving the transmittance, and increasing the overall brightness of the product, and the electrode strip adopts the single-side corner design, which can also avoid trace mura (trace mark).

[0146] The above describes the design of the electrode strips of the common electrode and the pixel electrode of the present disclosure, and the following introduces the shielding layer shielding the channel region.

[0147] In some embodiments, the shielding layer can include a first shielding layer located on one side of the channel region close to the substrate, and / or a second shielding layer located on the side of the channel region away from the substrate.

[0148] Specifically, the shielding layer can be the first shielding layer, or the shielding layer can be the second shielding layer, or the shielding layer can include the first shielding layer and the second shielding layer. In the case of including the first shielding layer and the second shielding layer, the first shielding layer can block the direct illumination of the backlight to the channel region, and the second shielding layer can shield the reflected light reflected by the panel on the light surface side of the channel region, thereby avoiding strong light from the upper and lower sides of the channel region to irradiate the TFT, thereby reducing the risk of changing the characteristics of the TFT and improving the CT defect.

[0149] Specifically, in an example, the shielding layer can include a first shielding layer, which can be disposed in the same layer as the gate layer and connected with the gate layer. Specifically, it can be combined with Figure 2 As shown, in this example, the thin film transistor can include a gate layer located on one side of the channel region close to the substrate; wherein part or all of the region of the first shielding layer is the gate layer, and the orthogonal projection of the first shielding layer on the substrate covers the orthogonal projection of the active layer on the substrate.

[0150] In the example, the entire region of the first shielding layer can be the gate layer, that is, the gate layer can act as a shielding layer for shielding the channel region. The orthogonal projection of the gate layer on the substrate can cover the channel region, specifically, as shown in Figure 2 and Figure 1 , the orthogonal projection of the gate layer on the substrate can cover the active layer, thereby avoiding the entire active layer being irradiated.

[0151] In the case where the first shielding layer covers the active layer, the distance of the first shielding layer wrapping the active layer can be determined according to the positional relationship between the active layer, the first electrode and the second electrode, wherein the positional relationship between the active layer, the first electrode and the second electrode can be understood as the placement direction of the thin film transistor on the substrate.

[0152] Exemplarily, in an example, the placement direction of the thin film transistor on the substrate can be referenced to the gate lines 18 and the data lines 17 on the substrate.

[0153] In an exemplary embodiment, one side of the substrate includes a plurality of gate lines, the active layer includes a source region and a drain region located on opposite sides of the channel region, and the source region, the channel region and the drain region are arranged in the extension direction of the gate lines. Then, in the extension direction of the data lines, the outer contour of the orthogonal projection of the first shielding layer on the substrate and the outer contour of the orthogonal projection of the active layer on the substrate have a third vertical distance, and in the extension direction of the gate lines, the outer contour of the orthogonal projection of the first shielding layer on the substrate and the outer contour of the orthogonal projection of the active layer on the substrate have a fourth vertical distance; wherein the third vertical distance is greater than the fourth vertical distance.

[0154] Please refer to Figure 1 and Figure 13 , it is shown that Figure 13 shows an enlarged schematic view of the S2 region in Figure 1 , as shown in Figure 13 and Figure 2 , the source region, the channel region and the drain region of the entire thin film transistor are arranged in the extension direction of the gate lines, so that the source region and the drain region are located on opposite sides of the channel region in the extension direction of the gate lines, that is, the source region and the drain region are located on opposite sides of the channel region in the lateral direction, so that the thin film transistor is arranged laterally on the array substrate, wherein the lateral direction is the extension direction of the gate lines, and the longitudinal direction can be the extension direction of the data lines.

[0155] Generally, when displaying, the highlight backlight mainly irradiates the active layer from the longitudinal two sides of the array substrate, that is, from the two sides of the extension direction of the data lines after liquid crystal birefringence, resulting in the change of the characteristics of the TFT. In order to eliminate the influence of the longitudinal direction, the wrapping of the active layer by the first shielding layer in the longitudinal direction can be increased, specifically, please refer to Figure 13As shown, in the transverse direction, the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate have a third vertical distance A; in the longitudinal direction, the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate have a fourth vertical distance B, wherein the third vertical distance A is greater than the fourth vertical distance B, thereby shielding the reflected light from the longitudinal two sides of the array substrate to the TFT.

[0156] In further examples of this embodiment, the third vertical distance can be 4-5 μm, and the fourth vertical distance can be 2.7-3 μm. Exemplarily, the third vertical distance can be 4 μm, 4.2 μm, 4.2 μm, 4.4 μm, 4.5 μm, 4.6 μm, 4.8 μm and 5 μm, and the fourth vertical distance can be 2.7 μm, 2.8 μm, 2.9 μm and 3 μm.

[0157] In this embodiment, the entire region of the first shielding layer can be the gate layer, or the first shielding layer comprises the gate layer and a shielding sub-layer connected with the gate layer, the orthographic projection of the shielding sub-layer on the substrate can be connected with the outer edge of the orthographic projection of the gate layer on the substrate, wherein the shielding sub-layer can be made of the same metal as the gate layer, or the shielding sub-layer is made of an organic insulating material or an inorganic insulating material.

[0158] In the case where the first shielding layer comprises the gate layer and the shielding sub-layer connected with the gate layer, the orthographic projection of the gate layer on the substrate covers the orthographic projection of the channel region on the substrate, and the orthographic projection of the shielding sub-layer on the substrate covers the region of the active layer other than the channel region. Exemplarily, reference can be made to Figure 14 As shown, Figure 14 A schematic diagram of the covering relationship between the first shielding layer and the active layer is shown, as Figure 14 As shown, the first shielding layer comprises the gate layer and the shielding sub-layer, the orthographic projection of the gate layer on the substrate covers the orthographic projection of the channel region on the substrate, and the orthographic projection of the shielding sub-layer on the substrate covers the region of the active layer other than the channel region and does not overlap with the channel region. Specifically, in the transverse direction, the outer contour of the orthographic projection of the shielding sub-layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate have a third vertical distance A; in the longitudinal direction, the outer contour of the orthographic projection of the shielding sub-layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate have a fourth vertical distance B, wherein the third vertical distance A is greater than the fourth vertical distance B.

[0159] In yet another embodiment, the thin film transistor can be placed longitudinally, in which case, the gate layer can shield in the lateral direction, and the first electrode and the second electrode can shield in the longitudinal direction. Specifically, the source region, the channel region and the drain region are arranged in the extension direction of the data line; and the vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the channel region on the substrate is 2.7 μm to 3 μm.

[0160] The present embodiment is described in conjunction with Figure 15 and Figure 16 , and Figure 15 shows a layout diagram of yet another array substrate, as Figure 16 shows a zoomed-in diagram of the S2 region in Figure 15 , and Figure 15 and Figure 16 , the source region, the channel region and the drain region of the entire thin film transistor are arranged in the extension direction of the data line, so that the source region and the drain region are located on opposite sides of the channel region in the extension direction of the data line, that is, the source region and the drain region are located on opposite sides of the channel region in the longitudinal direction of the channel region, so that the thin film transistor is longitudinally placed on the array substrate.

[0161] In this arrangement, the first electrode and the second electrode are in the longitudinal direction, that is, the source metal and the drain metal of the thin film transistor shield the channel region in the lateral direction, so that, compared with the lateral placement, the first shielding layer can adopt a smaller wrapping distance to the active layer. For example, the vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate is 2.7 μm to 3 μm.

[0162] In this arrangement, as shown in Figure 16 , in the lateral direction, the third vertical distance A between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate; in the longitudinal direction, the fourth vertical distance B between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate, wherein the third vertical distance A and the fourth vertical distance B can be the same, or the difference between the two is controlled within 1 μm. Specifically, the third vertical distance A and the fourth vertical distance B can be 2.7 μm to 3 μm.

[0163] Exemplarily, when the thin film transistor is longitudinally placed, the third vertical distance can be 2.7 μm, 2.8 μm, 2.9 μm and 3 μm, and the fourth vertical distance can be 2.7 μm, 2.8 μm, 2.9 μm and 3 μm.

[0164] In a specific implementation, the third vertical distance and the fourth vertical distance can be adjusted according to the size of the backlight brightness. Generally, the higher the backlight brightness, the greater the third vertical distance and the fourth vertical distance, that is, the third vertical distance and the fourth vertical distance are positively correlated with the backlight brightness.

[0165] In this embodiment, when the thin film transistor is placed longitudinally, the entire region of the first shielding layer can be the gate layer, that is, the gate layer acts as the shielding layer of the active layer, or the first shielding layer can include the gate layer and a shielding sub-layer enclosing the gate layer. The positional relationship between the shielding sub-layer and the gate layer can be combined with the description of the gate layer in the introduction, which will not be repeated here. Figure 14

[0166] In still some embodiments, the shielding layer can include a first shielding layer and a second shielding layer. In this case, the thin film transistor can be a gate-type thin film transistor. Please refer to FIG. 6A. Figure 17 Figure 17 FIG. 6B shows a cross-sectional structure schematic diagram of a thin film transistor in still another embodiment. As shown in FIG. 6B, the thin film transistor includes: Figure 17

[0167] a first gate layer 1211 located on one side of the substrate;

[0168] a first gate insulating layer 1221 located on the side of the first gate layer away from the substrate, and the active layer is located on the side of the first gate insulating layer away from the substrate;

[0169] a second gate insulating layer 1222 located on the side of the active layer away from the substrate;

[0170] a second gate layer 1212 located on the side of the second gate insulating layer away from the substrate;

[0171] Among them, part or all of the region of the first shielding layer is the first gate layer, and part or all of the region of the second shielding layer is the second gate layer.

[0172] Among them, the first gate layer and the second gate layer are connected through the via hole 1213 on the first gate insulating layer and the second gate insulating layer.

[0173] In this embodiment, the first gate layer can act as the first shielding layer, and the second gate layer can act as the second shielding layer, or the first shielding layer includes the first gate layer and a sub-shielding layer 151 enclosing the first gate layer 121, and the second shielding layer includes the second gate layer and a sub-shielding layer enclosing the second gate layer. The positional relationship between the sub-shielding layer and the gate layer can be combined with the description of the gate layer in the introduction, which will not be repeated here. Figure 14

[0174] In this example, when a double-gate thin film transistor is used, the planar schematic diagram of the array substrate can refer to FIG. 5A.​​​​Figure 18 and Figure 19 as shown, Figure 19 is Figure 18 an enlarged schematic view of the S2 region in the middle of the thin-film transistor, as Figure 18 and Figure 19 shown, both upper and lower sides of the thin-film transistor are shielded by metal layers, whereby the first shielding layer and the second shielding layer can directly use the corresponding first gate layer and the second gate layer.

[0175] The vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate can be 2.7 μm to 3 μm, and the vertical distance between the outer contour of the orthographic projection of the second shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate can be 2.7 μm to 3 μm.

[0176] In this embodiment, since the thin-film transistor adopts a double-gate structure, the Ioff of the double-gate structure thin-film transistor is smaller than that of a single-gate structure thin-film transistor, and is about half of that of the single-gate structure thin-film transistor, thus improving the CT defect. Further, the first shielding layer and the second shielding layer still wrap the active layer, which can block the irradiation of the high-brightness backlight, so that the CT defect does not occur.

[0177] In some embodiments, the second shielding layer can use an organic insulating layer material, for example, as shown in Figure 4 The second shielding layer includes an organic insulating layer, and the orthographic projection of the organic insulating layer on the substrate covers the orthographic projection of the active layer on the substrate; wherein the refractive index of the organic insulating layer is less than the refractive index of the liquid crystal.

[0178] In this embodiment, the refractive index of the liquid crystal is 1.4, and the refractive index of the organic insulating layer is less than 1.4, for example, the refractive index can be 1.3, 1.2, 1.1, etc. The organic insulating layer is located above the active layer and can block the reflection of the backlight by the cover plate on the light-emitting surface. In the case where the refractive index of the organic insulating layer is less than the refractive index of the liquid crystal, the organic insulating layer can refract the backlight refracted by the liquid crystal back to the liquid crystal, thereby avoiding the backlight refracted by the liquid crystal from irradiating the thin-film transistor.

[0179] The material of the organic insulating layer can be a resin material.

[0180] In this embodiment, the organic insulating layer can only cover the channel region, specifically, the orthographic projection of the organic insulating layer on the substrate can cover the orthographic projection of the channel region on the substrate, and be covered by the orthographic projection of the active layer on the substrate. Or, in some other examples, the orthographic projection of the organic insulating layer on the substrate can cover the orthographic projection of the active layer on the substrate.

[0181] In further examples of this embodiment, the thickness of the organic insulating layer is related to the case where the back light reflected by the cover plate irradiates the channel. Specifically, a preset relationship is satisfied between the size of the organic insulating layer in the normal line of the substrate, the size of the channel region in the plane of the substrate, the refractive index of the organic insulating layer, and the refractive index of the liquid crystal.

[0182] In this embodiment, the size of the organic insulating layer in the normal line of the substrate is the thickness of the organic insulating layer, which can also be referred to as the height of the organic insulating layer. The size of the channel region in the plane of the substrate can refer to the size of the channel region in the extension direction of the gate line, or the size of the channel region in the direction of the data line. Specifically, when the thin film transistor is arranged horizontally, the size of the channel region in the plane of the substrate can be the size of the channel region in the extension direction of the gate line; when the thin film transistor is arranged vertically, the size of the channel region in the plane of the substrate can be the size of the channel region in the extension direction of the data line.

[0183] In combination with FIG. 1, FIG. 2, and FIG. 3, the relationship between the back light reflected by the cover plate and the organic insulating layer is shown in FIG. 4, and FIG. 5. Figure 20 Figure 20 The optical path schematic diagram between the back light reflected by the cover plate and the organic insulating layer is shown in FIG. 4, and FIG. 5. Figure 20 As shown in FIG. 4 and FIG. 5, i is the incident angle of the back light reflected by the cover plate, n1 is the refractive index of the liquid crystal, n2 is the refractive index of the organic insulating layer, L is the channel length, and H is the height of the organic insulating layer; wherein, L≤L1+L2; L1 is the boundary of the back light reflected by the cover plate and incident to the organic insulating layer, and the light reflected by the organic insulating layer can avoid the channel region as far as possible, which is shown by the dashed line L’ in the figure.

[0184]

[0185] When H satisfies the following preset relationship, the protection of the thin film transistor can be improved, and the effect of CT is better:

[0186]

[0187] In this example, the back light reflected by the cover plate can deviate from the channel region, and the CT defect can be eliminated. In this example, the wrapping of the black matrix can be reduced, the aperture ratio of the sub-pixel can be increased, and the transmittance can be improved. Of course, when H does not satisfy the above preset relationship, the crosstalk defect can also be reduced to a certain extent.

[0188] In combination with the design of the shielding layer, in some embodiments, the display area can be divided into a plurality of sub-display areas 110 according to the back light brightness or according to the difference between the required display brightness and the actual display brightness, which is shown in FIG. 6, FIG. 7, and FIG. 8. Figure 21 Figure 21 Different division schematic diagrams for dividing the display area are shown in FIG. 6, FIG. 7, and FIG. 8, which are shown in combination with FIG. 1, FIG. 2, and FIG. 3.​​Figure 21 As shown, the division manner can be regular division such as four-square grid, nine-square grid, or irregular division. In practice, the display area can be divided according to the size of the simulated value of backlight brightness, and the number of sub-display areas is greater than or equal to 2.

[0189] Among them, the design of the shielding layer of the sub-pixel unit located in different sub-display areas is different, mainly reflected in: the shielding layer of the sub-pixel unit located in multiple sub-display areas has different spatial positions and / or shielding sizes.

[0190] Among them, the spatial position represents the up-down position of the shielding layer and the channel layer relative to the substrate, and the shielding size includes the vertical distance between the outer contour of the orthogonal projection of the shielding layer on the substrate and the outer contour of the orthogonal projection of the channel area on the substrate.

[0191] In this embodiment, the shielding layer of the sub-pixel unit in the same sub-display area can have the same setting manner. Among them, the shielding layer located in multiple sub-display areas can have different spatial positions, for example, the shielding layer of the sub-pixel unit in one sub-display area is located on the side of the channel area away from the substrate, that is, the shielding layer of all sub-pixel units in this sub-display area includes the second shielding layer; while the shielding layer of the sub-pixel unit in another sub-display area is located on the side of the channel area close to the substrate, that is, the shielding layer of all sub-pixel units in this sub-display area includes the first shielding layer.

[0192] Or, the shielding layer located in multiple sub-display areas can have different shielding sizes, for example, the shielding layer of the sub-pixel unit in one sub-display area has a wrapping distance of 4-5 μm to wrap the active layer; while the shielding layer of the sub-pixel unit in another sub-display area has a wrapping distance of 2.7-3 μm to wrap the active layer, which is the vertical distance between the outer contour of the orthogonal projection of the shielding layer on the substrate and the outer contour of the orthogonal projection of the active layer on the substrate.

[0193] Or, the shielding layer located in multiple sub-display areas can have different spatial positions and different shielding sizes. For example, the shielding layer of the sub-pixel unit in one sub-display area includes the first shielding layer, and the first shielding layer has a wrapping distance of 4-5 μm to wrap the active layer; while the shielding layer of the sub-pixel unit in another sub-display area includes the second shielding layer, but the second shielding layer has a wrapping distance of 2.7-3 μm to wrap the active layer. For another example, the shielding layer of the sub-pixel unit in one sub-display area includes the first shielding layer, and the first shielding layer is the gate layer, and the first shielding layer has a wrapping distance of 4-5 μm to wrap the active layer; while the shielding layer of the sub-pixel unit in another sub-display area includes the second shielding layer, and the second shielding layer is the organic insulating layer, but the second shielding layer only wraps the channel area, but not the active layer.

[0194] For example, taking the first masking layer in a sub-pixel unit as an example, the vertical distance between the outer contour of the orthographic projection of the first masking layer of the sub-pixel unit located in different sub-display areas on the substrate and the outer contour of the orthographic projection of the active layer on the substrate can vary within the range of 2.7 to 5 μm.

[0195] In this exemplary embodiment, the first blocking layer of the sub-pixel units located in different sub-display areas has different wrapping distances. For example, for a sub-display area with high backlight brightness, the third vertical distance of the first blocking layer in the vertical direction can be larger, such as a larger value between 4μm and 5μm, while the fourth vertical distance of the first blocking layer in the horizontal direction can also be larger; for a sub-display area with low backlight brightness, the third vertical distance of the first blocking layer in the vertical direction can be smaller, such as a smaller value between 4μm and 5μm, or even 2.7 to 3μm, while the fourth vertical distance of the first blocking layer in the horizontal direction can also be smaller.

[0196] Using this example, the thin-film transistors in each sub-display area of ​​the display area are wrapped to different degrees, with the wrapping adjustment range of 2.7 to 5 μm, which can solve the high-brightness CT problem and reduce the load at the same time.

[0197] Based on the same inventive concept, this disclosure also provides a liquid crystal display device. Please refer to... Figure 22 As shown, Figure 22 A cross-sectional structural schematic diagram of a liquid crystal display device is shown, such as... Figure 22 As shown, the liquid crystal display device may include a color filter substrate 200 and an array substrate 100 as described in any of the above array substrate embodiments; wherein the color filter substrate and the array substrate are arranged in a cell, and liquid crystal is filled between the color filter substrate and the array substrate.

[0198] The color filter substrate includes an OC layer 23, which can be a planarization layer made of organic or inorganic materials, a color filter layer 22 and a black matrix layer 21 located on the side of the OC layer away from the array substrate, and a transparent substrate 24 located on the side of the black matrix layer away from the array substrate.

[0199] In this embodiment, a black matrix layer can be disposed on the color filter substrate. The black matrix layer includes multiple opening regions 20, each opening region corresponding to a sub-pixel unit on the array substrate. A color filter layer is disposed in the opening region, which may include a red color filter layer, a blue color filter layer and a green color filter layer.

[0200] The aperture ratio of the sub-pixel described in the above embodiments can refer to the opening area of the opening area, and a plurality of spacers 300 are supported between the array substrate and the color film, and the orthogonal projection of the spacers 300 can overlap with the orthogonal projection of the active layer on the substrate in the array substrate, that is, the plurality of spacers 300 can be arranged at the position of the active layer of the thin film transistor, and the spacers 300 can also block the irradiation of the backlight reflected by the cover plate to the active layer.

[0201] In one example of the present embodiment, the shielding layer on the array substrate for shielding the active layer can be an organic insulating layer located on the side of the channel region away from the substrate, and the spacers can be located on the side of the organic insulating layer away from the substrate, wherein the orthogonal projection of the spacers on the substrate overlaps with the orthogonal projection of the organic insulating layer on the substrate.

[0202] Please continue to refer to Figure 22 It is shown that the spacer layer is stacked above the organic insulating layer, thereby the shielding effect on the active layer can be improved. The spacers can be made of a low refractive index material, for example, the refractive index of the spacers can be less than the refractive index of the liquid crystal.

[0203] In one example of the present embodiment, the fitting mode between the spacers and the organic insulating layer can include: the surface of the spacer away from the substrate is in contact with the surface of the organic insulating layer away from the substrate, and the spacers and the organic insulating layer are fitted.

[0204] In specific implementation, the organic insulating layer can include a plurality of first grooves, the spacers include a plurality of first protrusions respectively matched with the plurality of first grooves, and the plurality of first protrusions are respectively embedded in the first grooves; or the spacers can include a plurality of second grooves, and the organic insulating layer includes a plurality of second protrusions respectively matched with the plurality of second grooves, and the plurality of second protrusions are respectively embedded in the second grooves.

[0205] In the present embodiment, the shape of the first groove is adapted to the shape of the first protrusion, and the shape of the second groove is adapted to the shape of the second protrusion. Specifically, the adaptation can mean that the orthogonal projection of the first protrusion on the substrate is the same as the shape of the orthogonal projection of the first groove on the substrate. For example, the orthogonal projection of the first protrusion on the substrate is circular, and the orthogonal projection of the first groove on the substrate is also circular; for another example, the orthogonal projection of the first protrusion on the substrate is triangular, and the orthogonal projection of the first groove on the substrate is also triangular; for another example, the orthogonal projection of the first protrusion on the substrate is cross-shaped, and the orthogonal projection of the first groove on the substrate is also cross-shaped.

[0206] Referring to Figure 23 It is shown that Figure 23 The shape diagrams of various complementary designs of the organic insulating layer and the spacers are shown, wherein the shapes of the first protrusion and the second protrusion are not limited when the organic insulating layer and the spacers are complementarily fitted, such as Figure 23As shown, the shapes of the first and second protruding portions can be rectangular, trapezoidal, polygonal, cylindrical, triangular pyramid, etc.

[0207] With this example, the spacer column and the organic insulating layer are fixed by embedding, and the embedding design satisfies the complementary design of the spacer column and the organic insulating layer. When the array substrate and the color film substrate are aligned, the two can be embedded in each other. In this way, on the one hand, the alignment accuracy can be improved, and on the other hand, the connection stability between the two can be improved.

[0208] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0209] Finally, it should be noted that in this document, relationship terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, product or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, product or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, product or equipment including the element.

[0210] The above describes in detail a display method, device, system and medium provided by the present disclosure. The principles and implementation manners of the present disclosure are described by applying specific examples. The above description of the embodiments is only to help understand the method and core idea of the present disclosure; meanwhile, for those skilled in the art, according to the idea of the present disclosure, the specific implementation manner and application range can be changed. In summary, the content of the specification should not be understood as a limitation of the present disclosure.

[0211] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practice of the disclosed application. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following the general principles thereof and including the general knowledge and technical skills of those skilled in the art which are not disclosed in the present disclosure. The specification and examples are only considered as exemplary, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0212] It is to be understood that the present disclosure is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those of ordinary skill in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the appended claims.

[0213] As used herein, the term "one embodiment," "an embodiment," or "one or more embodiments," means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0214] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order not to obscure the understanding of this description.

[0215] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The disclosure can be implemented by means of both hardware and software, and any combination thereof. In a unit claim, several elements can be presented - the use of "each" before the first of these elements does not exclude the presence of a plurality of these elements. The usage of the words "first", "second" and "third" etc. do not limit the number of these elements. These words are only used to distinguish between alternative claims.

[0216] Finally, it should be noted that the above-mentioned embodiments are merely intended for describing and illustrating, not limiting, the technical solutions of the present disclosure; even though the present disclosure has been described in detail with reference to the above-mentioned embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the above-mentioned embodiments, or make equivalent replacements to some technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An array substrate, characterized in that, It includes multiple sub-pixel units, wherein the sub-pixel units include: Substrate; A thin-film transistor, located on the substrate, includes an active layer, the active layer including a channel region; A pixel electrode includes a plurality of electrode strips, at least one end of each electrode strip including at least one first corner; and, A common electrode is located on the side of the pixel electrode closer to the substrate, and the orthographic projection of the common electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate; Wherein, at least one of the common electrodes in the sub-pixel units includes at least one second corner, and the orthographic projection of the second corner on the substrate is located within the orthographic projection of the region where the first corner in the electrode strip is located on the substrate; In addition, at least one of the sub-pixel units further includes a masking layer, the orthographic projection of the masking layer on the substrate at least covering the orthographic projection of the channel region on the substrate; The angle of the first corner is the same as the angle of the second corner; The electrode strip includes a first end and a second end opposite to each other, with the first corner located at the first end; Wherein, the first vertical distance between the orthographic projection of the vertex of the first corner onto the substrate and the orthographic projection of the second end onto the substrate is greater than or equal to the second vertical distance between the orthographic projection of the vertex of the second corner onto the substrate and the orthographic projection of the second end onto the substrate; The first vertical distance is greater than the second vertical distance, wherein the vertex of the second corner is located on the reverse extension line of the vertex of the first corner.

2. The array substrate according to claim 1, characterized in that, The electrode strip includes a first end and a second end opposite to each other, and the first corner is located at the first end; the plurality of electrode strips include an edge electrode strip located at the edge and an intermediate electrode strip adjacent to the edge electrode strip, and the orthographic projection of the second corner on the substrate is located within the orthographic projection of the area where the first corner is located in the edge electrode strip on the substrate; The orthographic projection of the target endpoint of the common electrode that is connected to the second corner and close to the first endpoint on the substrate has a lateral distance between it and the orthographic projection of the intermediate electrode strip on the substrate. The lateral distance increases as the vertical distance between the second corner and the second end decreases.

3. The array substrate according to claim 1, characterized in that, One end of the electrode strip includes at least one of the first corners; The electrode strips in two adjacent sub-pixel units have a centrally symmetrical orthographic projection onto the substrate.

4. The array substrate according to claim 1, characterized in that, The shielding layer includes a first shielding layer located on the side of the channel region closer to the substrate, and / or includes a second shielding layer located on the side of the channel region away from the substrate.

5. The array substrate according to claim 4, characterized in that, The shielding layer includes the first shielding layer, and the thin-film transistor includes: A gate layer is located on the side of the channel region closest to the substrate; Wherein, part or all of the first shielding layer is the gate layer, and the orthogonal projection of the first shielding layer on the substrate covers the orthogonal projection of the active layer on the substrate.

6. The array substrate according to claim 5, characterized in that, The substrate includes multiple gate lines on one side, and the active layer includes a source region and a drain region located on opposite sides of the channel region. The source region, the channel region, and the drain region are arranged in the extension direction of the gate lines. In the direction of extension of the data line, there is a third vertical distance between the outer contour of the orthogonal projection of the first shielding layer on the substrate and the outer contour of the orthogonal projection of the active layer on the substrate; and in the direction of extension of the gate line, there is a fourth vertical distance between the outer contour of the orthogonal projection of the first shielding layer on the substrate and the outer contour of the orthogonal projection of the active layer on the substrate. The third vertical distance is greater than the fourth vertical distance.

7. The array substrate according to claim 6, characterized in that, The third vertical distance is 4μm~5μm, and the fourth vertical distance is 2.7~3μm.

8. The array substrate according to claim 5, characterized in that, One side of the substrate includes multiple data lines, and the active layer includes a source region and a drain region located on opposite sides of the channel region. The source region, the channel region, and the drain region are arranged in the extension direction of the data lines. The vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate is 2.7 μm to 3 μm.

9. The array substrate according to claim 5, characterized in that, The shielding layer includes a first shielding layer and a second shielding layer, and the thin-film transistor includes: The first gate layer is located on one side of the substrate; A first gate insulating layer is located on the side of the first gate layer opposite to the substrate, and the active layer is located on the side of the first gate insulating layer opposite to the substrate. The second gate insulating layer is located on the side of the active layer that is away from the substrate; The second gate layer is located on the side of the second gate insulating layer that faces away from the substrate; Wherein, part or all of the area of ​​the first shielding layer is the first gate layer, and part or all of the area of ​​the second shielding layer is the second gate layer.

10. The array substrate according to claim 5, characterized in that, The shielding layer includes the second shielding layer, and the second shielding layer includes: An organic insulating layer, wherein the orthographic projection of the organic insulating layer on the substrate covers the orthographic projection of the channel region on the substrate; The refractive index of the organic insulating layer is less than that of the liquid crystal.

11. The array substrate according to claim 10, characterized in that, The dimensions of the organic insulating layer on the normal to the substrate, the dimensions of the channel region on the plane of the substrate, the refractive index of the organic insulating layer, and the refractive index of the liquid crystal satisfy a preset relationship.

12. The array substrate according to any one of claims 1 or 5-11, characterized in that, The array substrate includes a display area, and a plurality of the sub-pixel units are located in the display area, the display area including a plurality of sub-display areas; The occlusion layers located in the sub-pixel units of the multiple sub-display areas have not exactly the same spatial positions and / or occlusion sizes; Wherein, the spatial position represents the vertical position of the shielding layer and the channel layer relative to the substrate, and the shielding size includes the outer contour of the orthographic projection of the shielding layer on the substrate and the vertical distance between the outer contour of the orthographic projection of the channel region on the substrate.

13. A liquid crystal display device, characterized in that, include: Color filter substrate, and array substrate as described in any one of claims 1-12; The color filter substrate and the array substrate are arranged in a cell, and liquid crystal is filled between the color filter substrate and the array substrate.

14. The liquid crystal display device according to claim 13, characterized in that, A spacer column is also provided between the color filter substrate and the array substrate; The array substrate includes an organic insulating layer, and the spacer pillars are located on the side of the organic insulating layer opposite to the substrate. The orthographic projection of the spacer pillars on the substrate overlaps with the orthographic projection of the organic insulating layer on the substrate.

15. The liquid crystal display device according to claim 14, characterized in that, The organic insulating layer includes a plurality of first grooves, and the spacer post includes a first protrusion that matches the plurality of first grooves respectively, and the plurality of first protrusions are respectively embedded in the first grooves; Alternatively, the spacer post includes a plurality of second grooves, and the organic insulating layer includes second protrusions that respectively match the plurality of second grooves, with the plurality of second protrusions respectively embedded in the second grooves.

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