Multi-frequency switching method, electronic equipment, medium and multi-frequency switching system

Abstract

The present application relates to the field of storage technology and provides a multi-frequency switching method, electronic device, medium and multi-frequency switching system. The multi-frequency switching method provided by the present application, in response to the demand for fast switching of multiple frequencies, utilizes the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module, while maintaining the communication between the interface module and the memory, realizes the sending of the trained interface parameters corresponding to the first working frequency to multiple frequency configuration registers, equivalently expanding the number of fast-switchable working frequencies that can be supported by the multiple frequency configuration registers on the memory, helping to save the time of retraining the memory and reconfiguring the mode register of the memory, and can flexibly adapt to various storage protocols and memory specifications, which is conducive to fast response and improving the overall performance of the system.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a multi-frequency switching method, electronic equipment, medium and multi-frequency switching system. Background Art

[0002] In the application fields of artificial intelligence, data centers, industrial control, smart cars, etc., various types of memories that comply with the storage technology specifications of Low Power Double Data Rate 5 (LPDDR5) and Low Power Double Data Rate 4 (LPDDR4) are widely used. In addition, based on power consumption requirements, communication protocol specifications, and user customization requirements, these memories may need to run at different operating frequencies, so they need to support multi-frequency switching. For example, the particles of dynamic random access memory (DRAM) based on LPDDR5 or LPDDR4 support data rates from 40 megabits per second (Mbps) to 8533Mbps. In the prior art, taking LPDDR5 and LPDDR4 as examples, the protocol stipulates that the particles of the memory support three registers for fast multi-frequency switching. However, when the application scenario requires the storage system to support switching between more than three frequencies, it is necessary to reconfigure the registers and retrain the interface parameters, which is not conducive to fast response and improving the overall system performance.

[0003] To this end, the present application provides a multi-frequency switching method, electronic device, medium and multi-frequency switching system, which can not only meet the needs of switching between more than three frequencies, but also can be conveniently promoted and applied to various existing storage systems, memories, and storage particles, which is conducive to rapid response and improving the overall performance of the system. Summary of the invention

[0004] In a first aspect, the present application provides a multi-frequency switching method. The multi-frequency switching method includes: providing a first frequency setting point configuration register and a second frequency setting point configuration register through an interface module, wherein the interface module is connected to a memory, the memory includes a plurality of frequency configuration registers defined by a storage protocol, the plurality of frequency configuration registers are respectively associated with different operating frequencies, and each of the plurality of frequency configuration registers is used to store the trained interface parameters of the memory defined by the storage protocol for the memory to operate at the operating frequency associated with the frequency configuration register; in response to a switching requirement for a first operating frequency, when the first operating frequency and the operating frequencies associated with the plurality of frequency configuration registers are not the same, using the first frequency setting point configuration register to maintain communication between the interface module and the memory, and using the second frequency setting point configuration register to send the trained interface parameters corresponding to the first operating frequency to the plurality of frequency configuration registers, and then switching the memory to the first operating frequency, and switching the interface module to using the second frequency setting point configuration register to maintain communication between the interface module and the memory.

[0005] Through the first aspect of the present application, in the face of the demand for fast switching of multiple frequency points, the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module are utilized to achieve the sending of the trained interface parameters corresponding to the first operating frequency to multiple frequency configuration registers while maintaining the communication between the interface module and the memory, which equivalently expands the number of fast-switchable operating frequencies that can be supported by the multiple frequency configuration registers on the memory, helps to save time for retraining the memory and reconfiguring the memory's mode register, can flexibly adapt to various storage protocols and memory specifications, and is conducive to rapid response and improving the overall performance of the system.

[0006] In a possible implementation of the first aspect of the present application, the multi-frequency switching method also includes: when the first operating frequency is the same as the operating frequency associated with the first frequency configuration register among the multiple frequency configuration registers, the memory is switched to the operating frequency associated with the first frequency configuration register, and the interface module is switched to using the second frequency setting point configuration register to maintain communication between the interface module and the memory.

[0007] In a possible implementation of the first aspect of the present application, the first frequency set point configuration register and the second frequency set point configuration register are used to alternately support the interface module to operate at the current operating frequency of the memory so as to maintain communication between the interface module and the memory.

[0008] In a possible implementation of the first aspect of the present application, the memory uses a second frequency configuration register among the multiple frequency configuration registers to maintain communication with the interface module, wherein the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers, including: using the second frequency setting point configuration register to store the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency stored in the second frequency setting point configuration register to update a third frequency configuration register among the multiple frequency configuration registers that is different from the second frequency configuration register, and so that the third frequency configuration register is associated with the first operating frequency.

[0009] In a possible implementation manner of the first aspect of the present application, enabling the memory to switch to the first operating frequency includes: enabling the memory to switch to using the third frequency configuration register to maintain communication with the interface module.

[0010] In a possible implementation of the first aspect of the present application, the interface module is connected to an external memory, and the external memory is used to store trained interface parameters corresponding to each of a plurality of preset frequencies, the trained interface parameters corresponding to each of the plurality of preset frequencies are used for the memory to operate at the preset frequency, and the trained interface parameters corresponding to a first preset frequency of the plurality of preset frequencies are stored in the second frequency set point configuration register.

[0011] In a possible implementation of the first aspect of the present application, the second frequency set point configuration register is used to store the trained interface parameters corresponding to the first operating frequency, including: when the first preset frequency is the same as the first operating frequency, calling the trained interface parameters corresponding to the first preset frequency stored in the second frequency set point configuration register; when the first preset frequency is different from the first operating frequency, and the second preset frequency among the multiple preset frequencies is the same as the first operating frequency, using the second frequency set point configuration register to obtain and store the trained interface parameters corresponding to the second preset frequency from the external memory; when the multiple preset frequencies are all different from the first operating frequency, training the memory to obtain the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency to update the external memory and the second frequency set point configuration register.

[0012] In a possible implementation of the first aspect of the present application, the multi-frequency switching method also includes: when the memory is idle, training the memory to obtain trained interface parameters corresponding to additional preset frequencies, and then using the trained interface parameters corresponding to the additional preset frequencies to update the external memory and the second frequency set point configuration register.

[0013] In a possible implementation of the first aspect of the present application, the multi-frequency switching method also includes: after the memory switches to the first operating frequency and the interface module switches to using the second frequency setting point configuration register to maintain communication between the interface module and the memory, in response to a switching requirement for the second operating frequency, when the second operating frequency and the operating frequencies associated with each of the multiple frequency configuration registers are different, using the second frequency setting point configuration register to maintain communication between the interface module and the memory, and using the first frequency setting point configuration register to send the trained interface parameters corresponding to the second operating frequency to the multiple frequency configuration registers, and then, switching the memory to the second operating frequency, and switching the interface module to using the first frequency setting point configuration register to maintain communication between the interface module and the memory.

[0014] In a possible implementation of the first aspect of the present application, the multi-frequency point switching method is based on a ping-pong operation between the first frequency setting point configuration register and the second frequency setting point configuration register to realize the communication between the interface module and the memory at the current operating frequency of the memory and to send the trained interface parameters corresponding to the new operating frequencies that are different from the operating frequencies associated with the multiple frequency point configuration registers to the multiple frequency point configuration registers.

[0015] In a possible implementation manner of the first aspect of the present application, the storage protocol is a low power fourth generation double rate protocol or a low power fifth generation double rate protocol.

[0016] In a possible implementation manner of the first aspect of the present application, the trained interface parameters of the memory defined by the storage protocol include a chip selection signal, a command address signal, a data selection signal, and a data signal.

[0017] In a possible implementation manner of the first aspect of the present application, the multiple frequency configuration registers are three frequency configuration registers.

[0018] In a possible implementation of the first aspect of the present application, the memory also includes a mode register, which is used to configure the write enable function, operation mode function, and command bus training function associated with the multiple frequency configuration registers so as to enable the memory to switch between the operating frequencies associated with each of the multiple frequency configuration registers.

[0019] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0020] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0021] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0022] In a fifth aspect, an embodiment of the present application further provides a multi-frequency switching system. The multi-frequency switching system includes: an interface module, the interface module provides a first frequency setting point configuration register and a second frequency setting point configuration register, wherein the interface module is connected to a memory, the memory includes a plurality of frequency configuration registers defined by a storage protocol, the plurality of frequency configuration registers are respectively associated with different operating frequencies, and each of the plurality of frequency configuration registers is used to store the trained interface parameters of the memory defined by the storage protocol for the memory to operate at the operating frequency associated with the frequency configuration register, and the interface module is used to: in response to the switching requirement of the first operating frequency, when the first operating frequency and the operating frequencies associated with the plurality of frequency configuration registers are not the same, use the first frequency setting point configuration register to maintain the communication between the interface module and the memory, and use the second frequency setting point configuration register to send the trained interface parameters corresponding to the first operating frequency to the plurality of frequency configuration registers, and then switch the memory to the first operating frequency, and switch the interface module to use the second frequency setting point configuration register to maintain the communication between the interface module and the memory.

[0023] Through the fifth aspect of the present application, in the face of the demand for fast switching of multiple frequency points, the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module are utilized to achieve the sending of the trained interface parameters corresponding to the first operating frequency to multiple frequency configuration registers while maintaining the communication between the interface module and the memory, which equivalently expands the number of fast-switchable operating frequencies that can be supported by the multiple frequency configuration registers on the memory, helps to save time for retraining the memory and reconfiguring the memory's mode register, can flexibly adapt to various storage protocols and memory specifications, and is conducive to rapid response and improving the overall performance of the system.

[0024] In a possible implementation of the fifth aspect of the present application, the memory uses a second frequency configuration register among the multiple frequency configuration registers to maintain communication with the interface module, wherein the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers, including: using the second frequency setting point configuration register to store the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency stored in the second frequency setting point configuration register to update a third frequency configuration register among the multiple frequency configuration registers that is different from the second frequency configuration register, and so that the third frequency configuration register is associated with the first operating frequency.

[0025] In a possible implementation of the fifth aspect of the present application, the multi-frequency switching system also includes an external memory, the interface module is connected to the external memory, the external memory is used to store trained interface parameters corresponding to each of a plurality of preset frequencies, the trained interface parameters corresponding to each of the plurality of preset frequencies are used for the memory to operate at the preset frequency, and the trained interface parameters corresponding to the first preset frequency of the plurality of preset frequencies are stored in the second frequency set point configuration register.

[0026] In a possible implementation of the fifth aspect of the present application, the second frequency set point configuration register is used to store the trained interface parameters corresponding to the first operating frequency, including: when the first preset frequency is the same as the first operating frequency, calling the trained interface parameters corresponding to the first preset frequency stored in the second frequency set point configuration register; when the first preset frequency is different from the first operating frequency, and the second preset frequency among the multiple preset frequencies is the same as the first operating frequency, using the second frequency set point configuration register to obtain and store the trained interface parameters corresponding to the second preset frequency from the external memory; when the multiple preset frequencies are all different from the first operating frequency, training the memory to obtain the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency to update the external memory and the second frequency set point configuration register. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 A schematic diagram of a flow chart of a multi-frequency switching method provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a multi-frequency switching system according to a first embodiment of the present application;

[0030] Figure 3 A schematic diagram of a multi-frequency switching system according to a second implementation mode provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0033] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0034] Figure 1A schematic diagram of a multi-frequency switching method provided in an embodiment of the present application. Figure 1 As shown, the multi-frequency switching method includes the following steps.

[0035] Step S101: providing a first frequency setting point configuration register and a second frequency setting point configuration register through an interface module, wherein the interface module is connected to a memory, the memory includes a plurality of frequency configuration registers defined by a storage protocol, the plurality of frequency configuration registers are respectively associated with different operating frequencies, and each of the plurality of frequency configuration registers is used to store trained interface parameters of the memory defined by the storage protocol for the memory to operate at the operating frequency associated with the frequency configuration register.

[0036] Step S103: In response to the switching demand of the first operating frequency, when the first operating frequency and the operating frequencies associated with the multiple frequency configuration registers are different, the first frequency setting point configuration register is used to maintain the communication between the interface module and the memory, and the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers, and then the memory is switched to the first operating frequency, and the interface module is switched to using the second frequency setting point configuration register to maintain the communication between the interface module and the memory.

[0037] Figure 1The multi-frequency switching method shown is applied to application fields such as artificial intelligence, data centers, industrial control, and smart cars. In these application fields, various types of memories that comply with the storage technology specifications of Low Power Double Data Rate 5 (LPDDR5) and Low Power Double Data Rate 4 (LPDDR4) are widely used. Based on power consumption requirements, communication protocol specifications, and user customization requirements, these memories may need to run at different operating frequencies, so they need to support multi-frequency switching. For example, the particles of dynamic random access memory (DRAM) based on LPDDR5 or LPDDR4 support data rates from 40 megabits per second (Mbps) to 8533Mbps. Storage protocols, such as LPDDR4 and LPDDR5, stipulate that the memory particles support three registers for multi-frequency fast switching, such as configuring the mode register (MR) to achieve fast frequency switching. However, when there is a need to switch between more than three frequencies, the three registers specified by the storage protocol cannot meet the storage requirements of interface parameters for more than three operating frequencies. If the registers are reconfigured and the interface parameters are retrained, including re-adapting the interface parameters of the memory, such as the DRAM chip select (Chip Select, CS) signal, command address (command / address, CA) signal, data strobe (Bi-directional Data Strobe, DQS) pulse signal, data (Data Strobe, DQ) signal, and updating the information related to command bus training (CBT). Considering the development of storage technology and the evolution of storage protocols, memories such as DRAM need to meet the needs of switching between more diverse operating frequencies in order to better adapt to the needs of various network devices and host servers. Therefore, it is necessary to try to avoid the loss of time and resources caused by re-adapting and retraining the interface parameters after each switch of the operating frequency. The following is combined with Figure 1 To elaborate further, Figure 1 The multi-frequency switching method shown realizes the demand for switching between more than three frequencies, and can be conveniently promoted and applied to various existing storage systems, memories, and storage particles, which is conducive to rapid response and improvement of overall system performance.

[0038] refer to Figure 1, in step S101, a first frequency setting point configuration register and a second frequency setting point configuration register are provided through an interface module, wherein the interface module is connected to a memory, the memory includes a plurality of frequency configuration registers defined by a storage protocol, the plurality of frequency configuration registers are respectively associated with different operating frequencies, and each of the plurality of frequency configuration registers is used to store the trained interface parameters of the memory defined by the storage protocol for the memory to operate at the operating frequency associated with the frequency configuration register. The memory refers to a storage device, equipment, device, etc. that has a requirement for fast switching of operating frequencies, such as various types of memory that conform to storage technical specifications such as low power fifth generation double rate and low power fourth generation double rate, such as LPDDR4 DRAM and LPDDR5 DRAM, etc., which needs to operate at different operating frequencies through multi-frequency switching. Each time the memory switches to a new operating frequency, various interface parameters corresponding to the new operating frequency are required to adapt to the new operating frequency to achieve correct data transmission and communication between devices, such as making adaptive adjustments to chip selection signals, command address signals, data selection signals, data signals, etc., and for example, locking the mode of the command address signal output by the data signal at the rising edge of the clock signal. Here, the memory includes multiple frequency configuration registers defined by the storage protocol, and the number of multiple frequency configuration registers and the internal field definition of the registers are determined by the storage protocol. Taking the low-power fifth-generation double-rate protocol and the low-power fourth-generation double-rate protocol as examples, that is, LPDDR4 and LPDDR5, it is stipulated that the memory particles support three registers for multi-frequency fast switching, and it is also stipulated that frequency switching is achieved by configuring the mode register. The multiple frequency configuration registers are respectively associated with different operating frequencies, and each of the multiple frequency configuration registers is used to store the trained interface parameters of the memory defined by the storage protocol for the memory to run at the operating frequency associated with the frequency configuration register. In this way, the memory can configure the corresponding interface parameters of the memory by calling the data in a given frequency configuration register among the multiple frequency configuration registers, that is, reading the stored trained interface parameters from the given frequency configuration register, so that the memory works at the working frequency associated with the given frequency configuration register, thereby achieving correct data communication and inter-device communication. For example, each frequency configuration register among the multiple frequency configuration registers is used to store the trained interface parameters of the memory defined by the storage protocol, indicating how to make adaptive adjustments to chip selection signals, command address signals, data selection signals, data signals, etc.

[0039] Continue to refer Figure 1, in step S103, in response to the switching demand of the first operating frequency, when the first operating frequency and the operating frequencies associated with the multiple frequency configuration registers are not the same, the first frequency setting point configuration register is used to maintain the communication between the interface module and the memory, and the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers, and then the memory is switched to the first operating frequency, and the interface module is switched to using the second frequency setting point configuration register to maintain the communication between the interface module and the memory. As described above, the number of multiple frequency configuration registers and the internal field definitions of the registers are determined by the storage protocol. For example, LPDDR4 and LPDDR5 stipulate that the memory particles support three registers for fast switching of multiple frequencies. Therefore, based on power consumption requirements, communication protocol specifications, and user customization requirements, the memory needs to meet the multi-frequency switching requirements, which may require the number of working frequencies for fast frequency switching of the memory to exceed the number of multiple frequency configuration registers specified by the storage protocol, which results in the interface parameters corresponding to the new working frequency not being stored by the multiple frequency configuration registers, that is, the first working frequency may be different from the working frequencies associated with the multiple frequency configuration registers. Therefore, in response to the switching requirements of the first working frequency, when the first working frequency is different from the working frequencies associated with the multiple frequency configuration registers, the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module are used to maintain the communication between the interface module and the memory, and the trained interface parameters corresponding to the first working frequency are sent to the multiple frequency configuration registers. In this way, the first frequency setting point configuration register and the second frequency setting point configuration register are used to equivalently expand the number of fast-switchable working frequencies that can be supported by the multiple frequency configuration registers on the memory. For example, LPDDR4 and LPDDR5 stipulate that the memory particles support three registers for fast switching of multiple frequency points. By using the first frequency setting point configuration register and the second frequency setting point configuration register, fast switching of more than three operating frequencies can be provided.Assuming that the first operating frequency is not among the operating frequencies associated with the three frequency configuration registers of the memory, the communication between the interface module and the memory is maintained through the first frequency setting point configuration register. At the same time, the mode register of the memory is configured through the second frequency setting point configuration register, and the trained interface parameters corresponding to the first operating frequency are configured to an available frequency configuration register among the multiple frequency configuration registers of the memory (the interface parameters are sent to the memory without affecting the communication between the interface module and the memory). In this way, the memory can be switched to operate at the first operating frequency by configuring the mode register, and the interface parameters of the memory have also been adjusted to adapt to the first operating frequency. In addition, the interface module is switched to use the second frequency setting point configuration register to maintain the communication between the interface module and the memory. In this way, on the basis of the memory switching to operate at the first operating frequency, the interface module is also switched to the first operating frequency, that is, the communication between the interface module and the memory is maintained by using the second frequency setting point configuration register. Therefore, when the first operating frequency is not supported by the interface parameters currently stored in the frequency configuration register of the memory, the memory and the interface mode are switched to the first operating frequency, and it is helpful to avoid the loss of time and resources caused by re-adaptation and re-training of interface parameters. In addition, by following the training plan in advance, the memory can be trained according to the expected multiple frequency points and the corresponding interface parameters can be obtained. Then, in actual applications, the interface parameters corresponding to the corresponding operating frequency can be obtained and stored on the interface module through the interface module, so that the interface parameters corresponding to the new operating frequency can be sent to the frequency configuration register of the memory, thus saving the time of retraining the memory and reconfiguring the mode register of the memory. In this way, through time-division operation, by training in advance and using the interface module, the range of operating frequencies that support fast switching is equivalently expanded, so that in actual applications, reconfiguring the mode register and retraining can be avoided, so that the business can be switched to the new operating frequency while maintaining uninterrupted, which is conducive to fast response and improving the overall performance of the system. In addition, the multiple frequency configuration registers on the memory are defined by the storage protocol. Therefore, there is no need to occupy additional resources on the memory. Instead, the first frequency setting point configuration register and the second frequency setting point configuration register on the interface module connected to the memory are utilized, which equivalently expands the number of quickly switchable operating frequencies supported by the multiple frequency configuration registers on the memory. This not only meets the need to switch between more than three frequencies, but also can be conveniently promoted and applied to various existing storage systems, memories, and storage particles, which is conducive to rapid response and improving the overall performance of the system.

[0040] In conclusion, Figure 1The multi-frequency switching method shown in the figure, in response to the demand for fast switching of multiple frequencies, utilizes the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module, while maintaining the communication between the interface module and the memory, it realizes the sending of the trained interface parameters corresponding to the first operating frequency to multiple frequency configuration registers, and equivalently expands the number of fast-switchable operating frequencies that can be supported by the multiple frequency configuration registers on the memory, which helps to save the time of retraining the memory and reconfiguring the mode register of the memory, can flexibly adapt to various storage protocols and memory specifications, and is conducive to fast response and improving the overall performance of the system.

[0041] refer to Figure 1 In a possible implementation, the multi-frequency switching method further includes: when the first operating frequency is the same as the operating frequency associated with the first frequency configuration register in the multiple frequency configuration registers, the memory is switched to the operating frequency associated with the first frequency configuration register, and the interface module is switched to using the second frequency setting point configuration register to maintain communication between the interface module and the memory. In this way, when the new operating frequency, that is, the first operating frequency, falls within the operating frequency range supported by the current storage contents of the multiple frequency configuration registers, the corresponding frequency configuration register can be directly called to implement the memory switching to the first operating frequency, and the interface module is switched to the first operating frequency to maintain communication between the interface module and the memory. In this way, various storage protocols and memory specifications can be flexibly adapted, which is conducive to rapid response and improving the overall performance of the system.

[0042] In a possible implementation, the first frequency setting point configuration register and the second frequency setting point configuration register are used to alternately support the interface module to operate at the current operating frequency of the memory so as to maintain the communication between the interface module and the memory. In this way, by using the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module, while maintaining the communication between the interface module and the memory, it is possible to send the trained interface parameters corresponding to the first operating frequency to multiple frequency configuration registers, which is equivalent to expanding the number of fast-switchable operating frequencies that can be supported by the multiple frequency configuration registers on the memory, which helps to save the time of retraining the memory and reconfiguring the mode register of the memory, and can flexibly adapt to various storage protocols and memory specifications, which is conducive to fast response and improving the overall performance of the system.

[0043] In a possible implementation, the memory uses the second frequency configuration register among the multiple frequency configuration registers to maintain communication with the interface module, wherein the use of the second frequency setting point configuration register to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers includes: using the second frequency setting point configuration register to store the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency stored in the second frequency setting point configuration register to update a third frequency configuration register among the multiple frequency configuration registers that is different from the second frequency configuration register, and making the third frequency configuration register associated with the first operating frequency. In this way, the second frequency configuration register is used to maintain communication with the interface module, and by updating the third frequency configuration register among the multiple frequency configuration registers that is different from the second frequency configuration register, it is achieved that sending the interface parameters to the memory does not affect the communication between the interface module and the memory. By utilizing the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module, it is possible to send the trained interface parameters corresponding to the first operating frequency to multiple frequency configuration registers while maintaining the communication between the interface module and the memory, thereby equivalently expanding the number of quickly switchable operating frequencies supported by the multiple frequency configuration registers on the memory, helping to save time in retraining the memory and reconfiguring the memory's mode register, and being able to flexibly adapt to various storage protocols and memory specifications, which is conducive to rapid response and improving the overall performance of the system.

[0044] In some embodiments, making the memory switch to the first operating frequency includes: making the memory switch to using the third frequency configuration register to maintain communication with the interface module. In this way, by using the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module, while maintaining communication between the interface module and the memory, it is possible to send the trained interface parameters corresponding to the first operating frequency to multiple frequency configuration registers, which equivalently expands the number of rapidly switchable operating frequencies that can be supported by multiple frequency configuration registers on the memory, helps save time for retraining the memory and reconfiguring the memory's mode register, can flexibly adapt to various storage protocols and memory specifications, and is conducive to rapid response and improvement of overall system performance.

[0045] In some embodiments, the interface module is connected to an external memory, and the external memory is used to store trained interface parameters corresponding to each of the multiple preset frequencies. The trained interface parameters corresponding to each of the multiple preset frequencies are used for the memory to operate at the preset frequency, and the trained interface parameters corresponding to the first preset frequency of the multiple preset frequencies are stored in the second frequency setting point configuration register. In this way, by following the training scheme in advance, the memory can be trained according to the expected multiple frequency points and the corresponding interface parameters can be obtained. Then, in actual applications, the interface parameters corresponding to the corresponding working frequency can be obtained and stored on the interface module through the interface module, so that the interface parameters corresponding to the new working frequency can be sent to the frequency point configuration register of the memory, thus saving the time of retraining the memory and reconfiguring the mode register of the memory. In this way, through time-division operation, by training in advance and using the interface module, the range of working frequencies that support fast switching is equivalently expanded, so that in actual applications, reconfiguring the mode register and retraining can be avoided, so as to switch to the new working frequency while keeping the service uninterrupted, which is conducive to fast response and improving the overall performance of the system. In addition, the multiple frequency configuration registers on the memory are defined by the storage protocol. Therefore, there is no need to occupy additional resources on the memory. Instead, the first frequency setting point configuration register and the second frequency setting point configuration register on the interface module connected to the memory are utilized, which equivalently expands the number of quickly switchable operating frequencies supported by the multiple frequency configuration registers on the memory. This not only meets the need to switch between more than three frequencies, but also can be conveniently promoted and applied to various existing storage systems, memories, and storage particles, which is conducive to rapid response and improving the overall performance of the system.

[0046] In some examples, using the second frequency set point configuration register to store the trained interface parameters corresponding to the first operating frequency includes: when the first preset frequency is the same as the first operating frequency, calling the trained interface parameters corresponding to the first preset frequency stored in the second frequency set point configuration register; when the first preset frequency is different from the first operating frequency, and the second preset frequency among the multiple preset frequencies is the same as the first operating frequency, using the second frequency set point configuration register to obtain and store the trained interface parameters corresponding to the second preset frequency from the external memory; when the multiple preset frequencies are all different from the first operating frequency, training the memory to obtain the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency to update the external memory and the second frequency set point configuration register. In this way, full use of the resources of the external memory is achieved, and only when the multiple preset frequencies are all different from the first operating frequency, the memory will be trained to obtain the corresponding trained interface parameters. By following the training plan in advance, the memory can be trained according to the expected multiple frequency points and the corresponding interface parameters can be obtained. Then, in actual applications, the interface parameters corresponding to the corresponding working frequency can be obtained and stored on the interface module through the interface module, so that the interface parameters corresponding to the new working frequency can be sent to the frequency configuration register of the memory, thus saving the time of retraining the memory and reconfiguring the mode register of the memory. In this way, through time-division operation, by training in advance and using the interface module, the range of working frequencies that support fast switching is equivalently expanded, so that in actual applications, reconfiguring the mode register and retraining can be avoided, so that the business can be switched to the new working frequency while maintaining uninterrupted, which is conducive to rapid response and improving the overall performance of the system. In addition, the multiple frequency configuration registers on the memory are defined by the storage protocol. Therefore, there is no need to occupy additional resources on the memory. Instead, the first frequency setting point configuration register and the second frequency setting point configuration register on the interface module connected to the memory are utilized, which equivalently expands the number of quickly switchable operating frequencies supported by the multiple frequency configuration registers on the memory. This not only meets the need to switch between more than three frequencies, but also can be conveniently promoted and applied to various existing storage systems, memories, and storage particles, which is conducive to rapid response and improving the overall performance of the system.

[0047] In some examples, the multi-frequency switching method further includes: when the memory is idle, training the memory to obtain trained interface parameters corresponding to the additional preset frequency, and then using the trained interface parameters corresponding to the additional preset frequency to update the external memory and the second frequency setting point configuration register. In this way, the idle state of the memory and bus resources are utilized. When initializing the training, the interface parameters are trained using the default operating frequency. After the training is completed, the interface parameters can be trained using the trained current operating frequency, so that the new configuration can be obtained when the bus is idle, and used to update the configuration stored in the memory, which helps to improve the overall operating efficiency of the system.

[0048] In a possible implementation, the multi-frequency switching method further includes: after the memory switches to the first operating frequency and the interface module switches to using the second frequency setting point configuration register to maintain communication between the interface module and the memory, in response to a switching requirement for the second operating frequency, when the second operating frequency and the operating frequencies associated with each of the multiple frequency configuration registers are different, using the second frequency setting point configuration register to maintain communication between the interface module and the memory, and using the first frequency setting point configuration register to send the trained interface parameters corresponding to the second operating frequency to the multiple frequency configuration registers, and then, switching the memory to the second operating frequency, and switching the interface module to using the first frequency setting point configuration register to maintain communication between the interface module and the memory. In this way, after switching to the first operating frequency, in the face of the subsequent switching demand of the second operating frequency, the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module can be used to implement a ping-pong operation. When responding to the switching demand of the first operating frequency, the first frequency setting point configuration register is used to maintain the communication between the interface module and the memory, and the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency point configuration registers; conversely, when responding to the switching demand of the second operating frequency, the second frequency setting point configuration register is used to maintain the communication between the interface module and the memory, and the first frequency setting point configuration register is used to send the trained interface parameters corresponding to the second operating frequency to the multiple frequency point configuration registers. In this way, by utilizing the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module, it is possible to send the trained interface parameters corresponding to the first operating frequency to multiple frequency configuration registers while maintaining the communication between the interface module and the memory, thereby equivalently expanding the number of quickly switchable operating frequencies supported by the multiple frequency configuration registers on the memory, helping to save time in retraining the memory and reconfiguring the memory's mode registers, and being able to flexibly adapt to various storage protocols and memory specifications, which is conducive to rapid response and improving the overall performance of the system.

[0049] In a possible implementation, the multi-frequency switching method is based on the ping-pong operation between the first frequency setting point configuration register and the second frequency setting point configuration register to realize the communication between the interface module and the memory at the current working frequency of the memory and to send the trained interface parameters corresponding to the new working frequencies that are different from the working frequencies associated with the multiple frequency configuration registers to the multiple frequency configuration registers. In this way, by using the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module, while maintaining the communication between the interface module and the memory, it is realized to send the trained interface parameters corresponding to the first working frequency to the multiple frequency configuration registers, which is equivalent to expanding the number of fast-switchable working frequencies that can be supported by the multiple frequency configuration registers on the memory, which helps to save the time of retraining the memory and reconfiguring the mode register of the memory, and can flexibly adapt to various storage protocols and memory specifications, which is conducive to fast response and improving the overall performance of the system.

[0050] In a possible implementation, the storage protocol is a low-power fourth-generation double-rate protocol or a low-power fifth-generation double-rate protocol. In this way, flexible adaptation of the storage protocol is achieved, which helps to promote and apply it to various existing storage systems, memories, and storage particles, and is conducive to rapid response and improvement of overall system performance.

[0051] In a possible implementation, the trained interface parameters of the memory defined by the storage protocol include a chip selection signal, a command address signal, a data strobe signal, and a data signal. In this way, flexible adaptation of the storage protocol is achieved, which helps to promote and apply it to various existing storage systems, memories, and storage particles, and is conducive to rapid response and improvement of overall system performance.

[0052] In a possible implementation, the multiple frequency configuration registers are three frequency configuration registers. In this way, the need for switching between more than three frequencies is met, and it can be conveniently promoted and applied to various existing storage systems, memories, and storage particles, which is conducive to rapid response and improvement of overall system performance.

[0053] In a possible implementation, the memory further includes a mode register, and the mode register is used to configure the write enable function, the operation mode function, and the command bus training function associated with the multiple frequency configuration registers so as to realize the switching of the memory between the operating frequencies associated with the multiple frequency configuration registers. In this way, by utilizing the first frequency setting point configuration register and the second frequency setting point configuration register of the interface module, while maintaining the communication between the interface module and the memory, the trained interface parameters corresponding to the first operating frequency are sent to the multiple frequency configuration registers, which equivalently expands the number of rapidly switchable operating frequencies that can be supported by the multiple frequency configuration registers on the memory, helps to save the time of retraining the memory and reconfiguring the mode register of the memory, can flexibly adapt to various storage protocols and memory specifications, and is conducive to rapid response and improvement of overall system performance.

[0054] Figure 2 Schematic diagram of a multi-frequency switching system according to a first embodiment of the present application. Figure 2 As shown, the interface module A203 includes a first frequency setting point configuration register A220 and a second frequency setting point configuration register A222. The memory A201 includes a plurality of frequency point configuration registers, Figure 2 2 shows, by way of example, a frequency configuration register A 210 , a frequency configuration register B 212 , and a frequency configuration register C 214 . Figure 2The multi-frequency switching system shown includes: an interface module A203, the interface module A203 provides a first frequency setting point configuration register A220 and a second frequency setting point configuration register A222. The interface module A203 is connected to a memory A201, and the memory A201 includes a plurality of frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214) defined by a storage protocol. The plurality of frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214) are respectively associated with different operating frequencies, and each of the plurality of frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214) is used to store the trained interface parameters of the memory A201 defined by the storage protocol for the memory A201 to operate at the operating frequency associated with the frequency configuration register. The interface module A203 is used to: respond to the switching demand of the first operating frequency, when the first operating frequency and the operating frequencies associated with the multiple frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214) are all different, use the first frequency setting point configuration register A220 to maintain the communication between the interface module A203 and the memory A201, and use the second frequency setting point configuration register A222 to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214), then, make the memory A201 switch to the first operating frequency, and make the interface module A203 switch to using the second frequency setting point configuration register A222 to maintain the communication between the interface module A203 and the memory A201.

[0055] Figure 2The multi-frequency switching system shown in the figure, in response to the demand for fast switching of multiple frequencies, utilizes the first frequency setting point configuration register A220 and the second frequency setting point configuration register A222 of the interface module A203, while maintaining the communication between the interface module A203 and the memory A201, realizes the sending of the trained interface parameters corresponding to the first operating frequency to multiple frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214), equivalently expanding the number of fast-switchable operating frequencies supported by the multiple frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214) on the memory A201, helping to save the time of retraining the memory A201 and reconfiguring the mode register of the memory A201, and can flexibly adapt to various storage protocols and memory specifications, which is conducive to fast response and improving the overall performance of the system.

[0056] In a possible implementation, the memory A201 uses the second frequency configuration register in the multiple frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214) to maintain communication with the interface module A203, wherein the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214), including: using the second frequency setting point configuration register to store the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency stored in the second frequency setting point configuration register to update a third frequency configuration register in the multiple frequency configuration registers (frequency configuration register A210, frequency configuration register B212, frequency configuration register C214) that is different from the second frequency configuration register, and making the third frequency configuration register associated with the first operating frequency. In some embodiments, the second frequency setting point configuration register is Figure 2 The frequency configuration register B212 shown in FIG. 1 is the third frequency configuration register. Figure 2 The frequency configuration register C214 is shown.

[0057] Figure 3 This is a schematic diagram of a multi-frequency switching system according to a second implementation mode provided in an embodiment of the present application. Figure 3 As shown, the interface module B303 includes a first frequency setting point configuration register B320 and a second frequency setting point configuration register B322. The memory B301 includes a plurality of frequency point configuration registers, Figure 3exemplarily shows the frequency configuration register D310, the frequency configuration register E312, and the frequency configuration register F314. Figure 3 The multi-frequency switching system shown includes: an interface module B303, the interface module B303 provides a first frequency setting point configuration register B320 and a second frequency setting point configuration register B322. The interface module B303 is connected to a memory B301, and the memory B301 includes a plurality of frequency configuration registers (frequency configuration register D310, frequency configuration register E312, frequency configuration register F314) defined by a storage protocol. The plurality of frequency configuration registers (frequency configuration register D310, frequency configuration register E312, frequency configuration register F314) are respectively associated with different operating frequencies, and each of the plurality of frequency configuration registers (frequency configuration register D310, frequency configuration register E312, frequency configuration register F314) is used to store the trained interface parameters of the memory B301 defined by the storage protocol for the memory B301 to operate at the operating frequency associated with the frequency configuration register. The interface module B303 is used to: respond to the switching demand of the first operating frequency, when the first operating frequency and the operating frequencies associated with the multiple frequency configuration registers (frequency configuration register D310, frequency configuration register E312, frequency configuration register F314) are all different, use the first frequency setting point configuration register B320 to maintain the communication between the interface module B303 and the memory B301, and use the second frequency setting point configuration register B322 to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers (frequency configuration register D310, frequency configuration register E312, frequency configuration register F314), then, make the memory B301 switch to the first operating frequency, and make the interface module B303 switch to using the second frequency setting point configuration register B322 to maintain the communication between the interface module B303 and the memory B301. The multi-frequency switching system also includes an external memory 305, and the interface module B303 is connected to the external memory 305. The external memory 305 is used to store trained interface parameters corresponding to each of the multiple preset frequencies. The trained interface parameters corresponding to each of the multiple preset frequencies are used for the memory B301 to operate at the preset frequency. The trained interface parameters corresponding to the first preset frequency of the multiple preset frequencies are stored in the second frequency setting point configuration register B322.

[0058] In this way, by following the training plan in advance, the memory B301 can be trained according to the expected multiple frequency points and the corresponding interface parameters can be obtained. Then, in actual applications, the interface parameters corresponding to the corresponding working frequency can be obtained and stored on the interface module B303 through the interface module B303, so that the interface parameters corresponding to the new working frequency can be sent to the frequency configuration register of the memory B301, thus saving the time of retraining the memory B301 and reconfiguring the mode register of the memory B301. In this way, through time-division operation, by training in advance and using the interface module B303, the range of working frequencies that support fast switching is equivalently expanded, so that in actual applications, reconfiguring the mode register and retraining can be avoided, so as to switch to the new working frequency while keeping the business uninterrupted, which is conducive to fast response and improving the overall performance of the system. In addition, the multiple frequency configuration registers on the memory B301 are defined by the storage protocol. Therefore, there is no need to occupy additional resources on the memory B301. Instead, the first frequency setting point configuration register B320 and the second frequency setting point configuration register B322 on the interface module B303 connected to the memory B301 are utilized, which equivalently expands the number of quickly switchable operating frequencies supported by the multiple frequency configuration registers on the memory B301. This not only meets the need to switch between more than three frequencies, but also can be conveniently promoted and applied to various existing storage systems, memories, and storage particles, which is conducive to rapid response and improving the overall performance of the system.

[0059] In a possible implementation, the second frequency setting point configuration register B322 is used to store the trained interface parameters corresponding to the first operating frequency, including: when the first preset frequency is the same as the first operating frequency, the trained interface parameters corresponding to the first preset frequency stored in the second frequency setting point configuration register B322 are called; when the first preset frequency is different from the first operating frequency, and the second preset frequency among the multiple preset frequencies is the same as the first operating frequency, the trained interface parameters corresponding to the second preset frequency are obtained and stored from the external memory 305 using the second frequency setting point configuration register B322; when the multiple preset frequencies are different from the first operating frequency, the memory B301 is trained to obtain the trained interface parameters corresponding to the first operating frequency, and then the trained interface parameters corresponding to the first operating frequency are used to update the external memory 305 and the second frequency setting point configuration register B322. In this way, various storage protocols and memory specifications can be flexibly adapted, which is conducive to rapid response and improvement of overall system performance.

[0060] Figure 44 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 400 includes: one or more processors 410, a communication interface 420 and a storage module 430. The processor 410, the communication interface 420 and the storage module 430 are interconnected via a bus 440. Optionally, the computing device 400 may also include an input / output interface 450, and the input / output interface 450 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 410 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the computing device 400 performing various operations can refer to the specific details in the above-mentioned embodiments, such as the processor 410 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 400 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 420 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 410 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0061] It should be understood that Figure 4 The computing device 400 may include one or more processors 410, and the multiple processors 410 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 410 may form a processor sequence or a processor array, or the multiple processors 410 may be divided into a main processor and an auxiliary processor, or the multiple processors 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 4 The computing device 400 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 4 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0062] The processor 410 may have a variety of specific implementation forms. For example, the processor 410 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 410 may also be a single-core processor or a multi-core processor. The processor 410 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 410 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0063] The storage module 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The storage module 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The storage module 430 may also be used to store program codes and data, so that the processor 410 can call the program codes stored in the storage module 430 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 4 Show more or fewer components, or have different component configurations.

[0064] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0065] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0066] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0067] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0068] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0069] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A multi-frequency switching method, characterized in that: The multi-frequency switching method comprises: A first frequency setting point configuration register and a second frequency setting point configuration register are provided through an interface module, wherein the interface module is connected to a memory, the memory includes a plurality of frequency configuration registers defined by a storage protocol, the plurality of frequency configuration registers are respectively associated with different operating frequencies, and each of the plurality of frequency configuration registers is used to store trained interface parameters of the memory defined by the storage protocol for the memory to operate at the operating frequency associated with the frequency configuration register; In response to the switching demand of the first operating frequency, when the first operating frequency and the operating frequencies associated with the multiple frequency configuration registers are not the same, the first frequency setting point configuration register is used to maintain the communication between the interface module and the memory, and the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers, and then the memory is switched to the first operating frequency, and the interface module is switched to using the second frequency setting point configuration register to maintain the communication between the interface module and the memory.

2. The multi-frequency switching method according to claim 1, characterized in that: The multi-frequency switching method further includes: When the first operating frequency is the same as the operating frequency associated with the first frequency configuration register among the multiple frequency configuration registers, the memory is switched to the operating frequency associated with the first frequency configuration register, and the interface module is switched to using the second frequency setting point configuration register to maintain communication between the interface module and the memory.

3. The multi-frequency switching method according to claim 1, characterized in that: The first frequency setting point configuration register and the second frequency setting point configuration register are used to alternately support the interface module to operate at the current operating frequency of the memory so as to maintain the communication between the interface module and the memory.

4. The multi-frequency switching method according to claim 1, characterized in that: The memory uses a second frequency configuration register among the multiple frequency configuration registers to maintain communication with the interface module, wherein the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers, including: using the second frequency setting point configuration register to store the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency stored in the second frequency setting point configuration register to update a third frequency configuration register among the multiple frequency configuration registers that is different from the second frequency configuration register, and making the third frequency configuration register associated with the first operating frequency.

5. The multi-frequency switching method according to claim 4, characterized in that: Making the memory switch to the first operating frequency includes: making the memory switch to using the third frequency configuration register to maintain communication with the interface module.

6. The multi-frequency switching method according to claim 4, characterized in that: The interface module is connected to an external memory, which is used to store trained interface parameters corresponding to each of a plurality of preset frequencies. The trained interface parameters corresponding to each of the plurality of preset frequencies are used for the memory to operate at the preset frequency, and the trained interface parameters corresponding to a first preset frequency among the plurality of preset frequencies are stored in the second frequency set point configuration register.

7. The multi-frequency switching method according to claim 6, characterized in that: Utilizing the second frequency setting point configuration register to store trained interface parameters corresponding to the first operating frequency includes: When the first preset frequency is the same as the first operating frequency, calling the trained interface parameters corresponding to the first preset frequency stored in the second frequency setting point configuration register; When the first preset frequency is different from the first operating frequency, and a second preset frequency among the plurality of preset frequencies is the same as the first operating frequency, acquiring and storing the trained interface parameters corresponding to the second preset frequency from the external memory using the second frequency setting point configuration register; When the plurality of preset frequencies are not the same as the first operating frequency, the memory is trained to obtain trained interface parameters corresponding to the first operating frequency, and then the external memory and the second frequency set point configuration register are updated using the trained interface parameters corresponding to the first operating frequency.

8. The multi-frequency switching method according to claim 7, characterized in that: The multi-frequency switching method further includes: When the memory is idle, the memory is trained to obtain trained interface parameters corresponding to the additional preset frequency, and then the external memory and the second frequency setting point configuration register are updated using the trained interface parameters corresponding to the additional preset frequency.

9. The multi-frequency switching method according to claim 1, characterized in that: The multi-frequency switching method further includes: After the memory switches to the first operating frequency and the interface module switches to using the second frequency setting point configuration register to maintain communication between the interface module and the memory, in response to a switching requirement for the second operating frequency, when the second operating frequency and the operating frequencies associated with each of the multiple frequency point configuration registers are different, the second frequency setting point configuration register is used to maintain communication between the interface module and the memory, and the first frequency setting point configuration register is used to send the trained interface parameters corresponding to the second operating frequency to the multiple frequency point configuration registers, and then the memory is switched to the second operating frequency, and the interface module is switched to using the first frequency setting point configuration register to maintain communication between the interface module and the memory.

10. The multi-frequency switching method according to claim 1, characterized in that: The multi-frequency switching method is based on a ping-pong operation between the first frequency setting point configuration register and the second frequency setting point configuration register to realize communication between the interface module and the memory at the current operating frequency of the memory and to send trained interface parameters corresponding to new operating frequencies that are different from the operating frequencies associated with each of the multiple frequency configuration registers to the multiple frequency configuration registers.

11. The multi-frequency switching method according to claim 1, characterized in that: The storage protocol is a low power fourth generation double rate protocol or a low power fifth generation double rate protocol.

12. The multi-frequency switching method according to claim 1, characterized in that: The trained interface parameters of the memory defined by the storage protocol include a chip selection signal, a command address signal, a data strobe signal, and a data signal.

13. The multi-frequency switching method according to claim 1, characterized in that: The multiple frequency configuration registers are three frequency configuration registers.

14. The multi-frequency switching method according to claim 1, characterized in that: The memory also includes a mode register, which is used to configure the write enable function, operation mode function, and command bus training function associated with the multiple frequency configuration registers so as to enable the memory to switch between the operating frequencies associated with each of the multiple frequency configuration registers.

15. An electronic device, characterized in that: The electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 14 when executing the computer program.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 14.

17. A multi-frequency switching system, characterized in that: The multi-frequency switching system comprises: An interface module, the interface module provides a first frequency setting point configuration register and a second frequency setting point configuration register, wherein the interface module is connected to a memory, the memory includes a plurality of frequency configuration registers defined by a storage protocol, the plurality of frequency configuration registers are respectively associated with different operating frequencies, and each of the plurality of frequency configuration registers is used to store a trained interface parameter of the memory defined by the storage protocol for the memory to operate at the operating frequency associated with the frequency configuration register, The interface module is used to: respond to the switching demand of the first operating frequency, when the first operating frequency and the operating frequencies associated with the multiple frequency configuration registers are different, use the first frequency setting point configuration register to maintain the communication between the interface module and the memory, and use the second frequency setting point configuration register to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers, then make the memory switch to the first operating frequency, and make the interface module switch to using the second frequency setting point configuration register to maintain the communication between the interface module and the memory.

18. The multi-frequency switching system according to claim 17, characterized in that: The memory uses a second frequency configuration register among the multiple frequency configuration registers to maintain communication with the interface module, wherein the second frequency setting point configuration register is used to send the trained interface parameters corresponding to the first operating frequency to the multiple frequency configuration registers, including: using the second frequency setting point configuration register to store the trained interface parameters corresponding to the first operating frequency, and then using the trained interface parameters corresponding to the first operating frequency stored in the second frequency setting point configuration register to update a third frequency configuration register among the multiple frequency configuration registers that is different from the second frequency configuration register, and making the third frequency configuration register associated with the first operating frequency.

19. The multi-frequency switching system according to claim 18, characterized in that: The multi-frequency switching system also includes an external memory, the interface module is connected to the external memory, the external memory is used to store trained interface parameters corresponding to each of a plurality of preset frequencies, the trained interface parameters corresponding to each of the plurality of preset frequencies are used for the memory to operate at the preset frequency, and the trained interface parameters corresponding to the first preset frequency of the plurality of preset frequencies are stored in the second frequency setting point configuration register.

20. The multi-frequency switching system according to claim 19, characterized in that: Utilizing the second frequency setting point configuration register to store trained interface parameters corresponding to the first operating frequency includes: When the first preset frequency is the same as the first operating frequency, calling the trained interface parameters corresponding to the first preset frequency stored in the second frequency setting point configuration register; When the first preset frequency is different from the first operating frequency, and a second preset frequency among the plurality of preset frequencies is the same as the first operating frequency, acquiring and storing the trained interface parameters corresponding to the second preset frequency from the external memory using the second frequency setting point configuration register; When the plurality of preset frequencies are not the same as the first operating frequency, the memory is trained to obtain trained interface parameters corresponding to the first operating frequency, and then the external memory and the second frequency set point configuration register are updated using the trained interface parameters corresponding to the first operating frequency.

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