An Interrupt Scheduling Method, Apparatus, Device, and Computer Readable Storage Medium

Abstract

The present invention discloses an interrupt scheduling method, device, equipment and computer-readable storage medium, which are applied to the field of non-uniform memory access technology, and include: obtaining system load prediction data corresponding to a non-uniform memory access system; dynamically adjusting an interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy; determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and processing each interrupt based on the target interrupt processing device. Compared with the traditional method of scheduling interrupts based on a static scheduling policy, the present invention realizes the intelligence and dynamicization of interrupt scheduling and improves the accuracy of interrupt scheduling by obtaining system load prediction data, dynamically adjusting the interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy, and then scheduling interrupts based on the adjusted interrupt scheduling policy.

Description

Technical Field

[0001] The present invention relates to the technical field of non-uniform memory access, and particularly to an interrupt scheduling method, apparatus, device, and computer-readable storage medium. Background Art

[0002] In modern computer systems, especially in multi-processor systems adopting the non-uniform memory access (NUMA) architecture, the efficient scheduling of hardware interrupts is crucial for optimizing system performance. Interrupt scheduling refers to distributing interrupt requests to appropriate CPU cores for processing. Traditional interrupt scheduling methods usually rely on static policies, resulting in poor interrupt scheduling effects.

[0003] Obviously, how to improve the effect of interrupt scheduling is a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an interrupt scheduling method, apparatus, device, and computer-readable storage medium, which solves the technical problem of poor interrupt scheduling effect in the prior art.

[0005] To solve the above technical problem, the present invention provides an interrupt scheduling method, including:

[0006] Obtain system load prediction data corresponding to a non-uniform memory access system;

[0007] Dynamically adjust an interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy;

[0008] Determine a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and process each interrupt based on the target interrupt processing device.

[0009] On the one hand, before determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy and processing each interrupt based on the target interrupt processing device, it further includes:

[0010] Classify the priorities of interrupts according to the interrupt type and historical interrupt processing time to obtain the priority of each interrupt;

[0011] Adjust the target interrupt scheduling policy based on the priority of each interrupt to obtain an adjusted target interrupt scheduling policy;

[0012] Correspondingly, determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy and processing each interrupt based on the target interrupt processing device includes:

[0013] Determine the target interrupt handling device corresponding to each interrupt based on the adjusted target interrupt scheduling policy, and handle each interrupt based on the target interrupt handling device.

[0014] On the one hand, the prioritization of interrupts according to the interrupt type and historical interrupt handling time to obtain the priority of each interrupt includes:

[0015] When the interrupt types are inconsistent, prioritize the interrupts based on the interrupt type to obtain the priority of each interrupt;

[0016] When the interrupt types are the same, prioritize the interrupts based on the historical interrupt handling time to obtain the priority of each interrupt; among them, the larger the historical interrupt handling time, the higher the priority level.

[0017] On the one hand, before dynamically adjusting the interrupt scheduling policy based on the system load prediction data to obtain the target interrupt scheduling policy, it further includes:

[0018] Predict the target interrupt and the target interrupt time point based on historical interrupt data;

[0019] Based on the interrupt time point before the target interrupt occurs, load the data corresponding to the target interrupt into the cache to obtain the target cache.

[0020] On the one hand, after loading the data corresponding to the target interrupt into the cache to obtain the target cache based on the interrupt time point before the target interrupt occurs, it further includes:

[0021] When it is determined that the data size in the target cache is greater than the set data threshold, determine whether the interrupt handling frequency corresponding to each data in the target cache is greater than the set processing frequency threshold;

[0022] When the interrupt handling frequency is not greater than the set processing frequency threshold, determine to clear the data from the target cache;

[0023] When the interrupt handling frequency is greater than the set processing frequency threshold, determine not to process the data.

[0024] On the one hand, during the process of interrupt scheduling, it further includes:

[0025] Filter the system load prediction data based on the access control list to obtain the target acquisition data;

[0026] Use the data encryption mechanism to encrypt the target acquisition data and the interrupt scheduling result to obtain the target encrypted data.

[0027] On the one hand, before obtaining the system load prediction data corresponding to the non-uniform memory access system, it further includes:

[0028] Obtain the current system performance state and historical system performance data corresponding to the non-uniform memory access system;

[0029] Based on the current system performance state and the historical system performance data, perform a prediction to determine the system load prediction data.

[0030] On the one hand, based on the current system performance state and the historical system performance data, perform a prediction to determine the system load prediction data, including:

[0031] Update the parameters of the prediction model based on the current system performance state to obtain an updated target prediction model;

[0032] Use the target prediction model to perform a prediction according to the historical system performance data to determine the system load prediction data.

[0033] On the one hand, updating the parameters of the prediction model based on the current system performance state to obtain an updated target prediction model includes:

[0034] Update the parameters of the long short-term memory network model based on the current system performance state to obtain the updated target prediction model; wherein, the current system performance state is the system performance after executing an interrupt based on an interrupt scheduling policy; the training process of the long short-term memory network model includes data segmentation, model initialization, parameter optimization, and model verification;

[0035] Wherein, the data segmentation refers to segmenting the data according to the data type;

[0036] The model initialization refers to initializing the parameters of the long short-term memory network model;

[0037] The parameter optimization refers to adjusting the parameters of the model to minimize the loss function;

[0038] The model verification refers to determining the prediction performance of the trained long short-term memory network model.

[0039] On the one hand, dynamically adjusting the interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy, including:

[0040] Dynamically adjust the interrupt scheduling policy based on the system load prediction data and the current system performance state to obtain the target interrupt scheduling policy; wherein, the dynamically adjusted parameters include the interrupt affinity threshold, and the interrupt affinity includes interrupt priority scheduling to memory.

[0041] On the one hand, before predicting based on the current system performance state and the historical system performance data to determine the system load prediction data, it further includes:

[0042] Using the principal component analysis method to extract the key feature data from the historical system performance data; wherein, the key feature data includes the number of interrupts, memory utilization rate, number of devices, terminal frequency, and central processing unit load;

[0043] Performing scale unification processing on the key feature data to obtain the performance data with unified scale;

[0044] Correspondingly, predicting based on the current system performance state and the historical system performance data to determine the system load prediction data includes:

[0045] Predicting based on the current system performance state and the performance data with unified scale to determine the system load prediction data.

[0046] On the one hand, after determining the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy and processing each interrupt based on the target interrupt processing device, it further includes:

[0047] Obtaining the system performance feedback data after processing the interrupts based on the target interrupt scheduling policy; wherein, the system performance feedback data includes at least one of the central processing unit usage rate, memory access latency, input / output operation frequency, network traffic, waiting time, resource utilization rate, and interrupt response time;

[0048] Analyzing the system performance feedback data to determine the target performance parameter corresponding to the current system;

[0049] Comparing the target performance parameter with the performance parameter threshold;

[0050] When it is determined that the target performance parameter is less than the performance parameter threshold, no processing is performed;

[0051] When it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, it is determined to send a prompt message so that the client adjusts the interrupt scheduling policy based on the prompt message;

[0052] Taking the system load feedback data corresponding to the system load prediction data in the system performance feedback data;

[0053] Comparing the system load feedback data with the system load prediction data to determine the system load prediction difference;

[0054] Adjust the corresponding system load prediction model based on the difference in the system load prediction to obtain an adjusted system load prediction model.

[0055] An embodiment of the present invention further provides an interrupt scheduling device, including:

[0056] A data acquisition module, configured to acquire system load prediction data corresponding to a non-uniform memory access system;

[0057] A dynamic adjustment module, configured to dynamically adjust an interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy;

[0058] An interrupt scheduling module, configured to determine a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and process each interrupt based on the target interrupt processing device.

[0059] An embodiment of the present invention further provides an interrupt scheduling device, including:

[0060] A memory, configured to store a computer program;

[0061] A processor, configured to execute the computer program to implement the steps of the above-mentioned interrupt scheduling method.

[0062] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned interrupt scheduling method are implemented.

[0063] An embodiment of the present invention further provides a computer program product, including computer programs / instructions, and when the computer programs / instructions are executed by a processor, the steps of the above-mentioned interrupt scheduling method are implemented.

[0064] To solve the above technical problems, an embodiment of the present invention provides an interrupt scheduling method, which may include: acquiring system load prediction data corresponding to a non-uniform memory access system; dynamically adjusting an interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy; determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and processing each interrupt based on the target interrupt processing device.

[0065] As can be seen from the above technical solutions, the beneficial effects of the present invention are as follows: Compared with the traditional interruption scheduling strategy based on an unchanging interruption scheduling strategy, the present invention dynamically adjusts the interruption scheduling strategy based on system load prediction data to obtain a target interruption scheduling strategy, so that when scheduling interruptions, the interruptions can be scheduled in real time to a more accurate interruption processing device, and the interruptions can be scheduled based on the dynamically adjusted target interruption scheduling strategy, realizing the intelligence and dynamicness of interruption scheduling, as well as the accuracy of interruption scheduling. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the embodiments of the present invention, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0067] Figure 1 Flowchart of an interruption scheduling method provided by an embodiment of the present invention;

[0068] Figure 2 Flowchart of another interruption scheduling method provided by an embodiment of the present invention;

[0069] Figure 3 Flow implementation example of an interruption scheduling method provided by an embodiment of the present invention;

[0070] Figure 4 Structure framework diagram of an interruption scheduling method provided by an embodiment of the present invention;

[0071] Figure 5 Structure schematic diagram of an interruption scheduling device provided by an embodiment of the present invention;

[0072] Figure 6 Structure schematic diagram of an interruption scheduling device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0073] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0074] As used in the description of the present invention and the above-mentioned drawings, the terms "comprising" and "having", and any variations related to "comprising" and "having", are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0075] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0076] Next, a detailed introduction will be given to an interrupt scheduling method provided by an embodiment of the present invention. Figure 1 FIG. [X] is a flowchart of an interrupt scheduling method provided by an embodiment of the present invention, and the method includes:

[0077] S101, obtaining system load prediction data corresponding to a non-uniform memory access system.

[0078] This embodiment does not limit the specific execution entity. For example, the execution entity of this embodiment may be a computer; or the execution entity in this embodiment may also be a mobile phone, etc.; the execution entity in this embodiment may also be a node in the system. The non-uniform memory access (NUMA) system in this embodiment, the NUMA (Non-Uniform Memory Access) system is a computer architecture used in multi-processor or multi-core systems. This embodiment does not limit the specific manner of obtaining the system load prediction data. For example, this embodiment can be performed by analyzing historical load data, applying machine learning models, and adjusting resource allocation strategies. The following is a detailed introduction to the system load prediction data: Historical load data of the system needs to be collected, which includes indicators such as CPU (Central Processing Unit) usage rate, memory usage, disk I / O (Input / Output), and network traffic. The collected data is cleaned and preprocessed to ensure the accuracy of the analysis. This may include operations such as removing outliers and filling in missing values. By carefully analyzing the historical load data, characteristics such as the periodicity and trend of the load can be understood. Time series analysis is an important step among them, which helps to reveal the trend and periodicity of the data over time. Select a suitable machine learning algorithm to build a prediction model. Common algorithms include linear regression, decision tree, random forest, and neural network, etc. Use the historical load data as the training set to train the model. During the training process, the model parameters need to be adjusted to optimize the prediction performance. The prediction performance of the model is evaluated through a validation set or a test set. Commonly used evaluation indicators include mean squared error (MSE), mean absolute error (MAE), etc.

[0079] Note: In the original text, there is a placeholder in line and

[0075] in line , etc. Since they are not clear what they represent exactly, they are left unchanged in the translation. Also, in line , there is a placeholder "[X]" which should be replaced with the actual figure number if available. For the sake of translation integrity, it is left as it is here.S102. Dynamically adjust the interrupt scheduling policy based on the system load prediction data to obtain the target interrupt scheduling policy.

[0080] The interrupt scheduling in this embodiment refers to the process of how the operating system decides which task or process should be given priority when receiving an interrupt signal. By reasonably arranging the order of interrupt handling, the system response time can be reduced and the system performance can be improved. This embodiment does not limit the original interrupt scheduling policy. For example, the interrupt scheduling policy in this embodiment can be for each device corresponding to an interrupt, or the interrupt scheduling policy in this embodiment can also be the priority of each interrupt handling. This embodiment does not limit the specific manner of dynamically adjusting the interrupt scheduling policy based on the system load prediction data. For example, this embodiment can determine the load of each interrupt handling device based on the system load prediction data, determine the interrupt handling capacity according to the load, and preferentially allocate the interrupt to the interrupt handling device with strong interrupt handling capacity to ensure that the interrupt is preferentially allocated to the processing device with lower load and stronger processing capacity.

[0081] It should be further noted that, in order to improve the security of interrupt handling, before dynamically adjusting the interrupt scheduling policy based on the system load prediction data to obtain the target interrupt scheduling policy, it may further include: predicting the target interrupt and the target interrupt time point based on the historical interrupt data; loading the data corresponding to the target interrupt into the cache before the target interrupt occurs based on the interrupt time point to obtain the target cache. The target cache in this embodiment is used to store the data corresponding to each interrupt. After processing the interrupt, the data in the target cache can be deleted to improve the caching capacity of the target cache. This embodiment will predict the target interrupt and the target interrupt time point corresponding to the target interrupt based on the historical interrupt data, so as to timely store the data corresponding to the target interrupt into the cache based on the target interrupt time point and reduce the data loading time during interrupt handling.

[0082] It should be further noted that, after loading the data corresponding to the target interrupt into the cache based on the interrupt time point before the occurrence of the target interrupt to obtain the target cache, the following steps may further be included: when it is determined that the data size in the target cache is greater than the set data threshold, determine whether the interrupt processing frequency corresponding to each data in the target cache is greater than the set processing frequency threshold; when the interrupt processing frequency is not greater than the set processing frequency threshold, determine to clear the data from the target cache; when the interrupt processing frequency is greater than the set processing frequency threshold, determine not to process the data. When processing the data in the target cache in this embodiment, the interrupt processing frequency of the interrupt is considered, and the data corresponding to the interrupt with a low interrupt processing frequency will be preferentially cleared from the target cache to improve the storage capacity of the target cache. The reason why the data corresponding to the interrupt with a high interrupt processing frequency is generally not deleted in this embodiment is to reduce the frequency of writing the data corresponding to the interrupt into the target cache and improve the processing capacity. For the data corresponding to the interrupt with a high interrupt processing frequency, after the interrupt is processed, the data in the target cache can be updated in a timely manner according to the latest data corresponding to the interrupt.

[0083] S103. Determine the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and process each interrupt based on the target interrupt processing device.

[0084] The target interrupt processing device in this embodiment refers to a device that can process interrupts. The specific type of the target interrupt processing device is not limited in this embodiment; for example, the target interrupt processing device in this embodiment may be a CPU; or the target interrupt processing device in this embodiment may also be a DMA controller. A DMA (Direct Memory Access) controller allows peripheral devices to directly exchange data with the system memory without the intervention of the CPU. The target interrupt scheduling policy in this embodiment may include at least one of the correspondence between interrupts and interrupt processing devices, the interrupt processing device closest to the interrupt, and the processing capacity of the interrupt processing device corresponding to the interrupt. Specifically, the closest means belonging to the same NUMA. It can be understood that each interrupt initially has a corresponding device, which corresponds to a NUMA, and there are other interrupt processing devices under this NUMA. The interrupt can be preferentially allocated to the device under the same NUMA. The ability of the interrupt processing device in this embodiment refers to the own specifications and architecture of the interrupt processing device. This embodiment can schedule each interrupt to the target interrupt processing device with a low load based on the target interrupt scheduling policy. A low load means a device with a load lower than the set load value; or the loads of each target interrupt processing device can also be sorted from small to large according to the system load prediction data, the number of interrupts is determined, and from the sorted loads, the number of devices corresponding to the number of interrupts is selected from the front to process the interrupts.

[0085] It should be further noted that, in order to improve the effect of interrupt handling, before determining the target interrupt handling device corresponding to each interrupt based on the target interrupt scheduling policy and handling each interrupt based on the target interrupt handling device, the following steps may also be included: grading the priorities of interrupts according to the interrupt type and the historical interrupt handling time to obtain the priority of each interrupt; adjusting the target interrupt scheduling policy based on the priority of each interrupt to obtain an adjusted target interrupt scheduling policy; correspondingly, determining the target interrupt handling device corresponding to each interrupt based on the target interrupt scheduling policy and handling each interrupt based on the target interrupt handling device includes: determining the target interrupt handling device corresponding to each interrupt based on the adjusted target interrupt scheduling policy and handling each interrupt based on the target interrupt handling device. The specific interrupt type is not limited in this embodiment. For example, the interrupt type in this embodiment may be hardware interrupt and software interrupt, and generally speaking, the priority of hardware interrupt is higher than that of software interrupt because hardware interrupt may involve device failures or hardware errors and needs to be processed as soon as possible. For example, machine check interrupts (such as power failures, main memory errors, etc.) usually have a higher priority because they are related to the stability of the system and data security; or the interrupt type in this embodiment may also be disks, keyboards, mice, etc. of NUMA (Non-Uniform Memory Access). The historical interrupt handling time in this embodiment refers to the time for handling each interrupt. The relationship between the historical interrupt handling time and the priority in this embodiment can be determined according to requirements. For example, in this embodiment, the longer the historical interrupt handling time, the lower the priority, and it can be processed later, or in this embodiment, the longer the historical interrupt handling time, the higher the priority because the longer the time, the earlier it is processed to ensure that the interrupt can be processed within the set time. Adjusting the target interrupt scheduling policy based on the priority of each interrupt to obtain an adjusted target interrupt scheduling policy in this embodiment means that, according to the priority of the interrupt, the target device can be preferentially allocated to handle the interrupt with a higher priority.

[0086] It should be further noted that grading the priorities of interrupts according to the interrupt type and the historical interrupt handling time to obtain the priority of each interrupt may include: when the interrupt types are inconsistent, grading the priorities of interrupts based on the interrupt type to obtain the priority of each interrupt; when the interrupt types are consistent, grading the priorities of interrupts based on the historical interrupt handling time to obtain the priority of each interrupt; wherein, the larger the historical interrupt handling time, the higher the priority level. In this embodiment, the importance of the interrupt type in determining the priority of the interrupt is greater than the historical interrupt handling time.

[0087] It should be further noted that, in order to improve the security of interrupt scheduling, during the process of interrupt scheduling, it may further include: filtering the system load prediction data based on an access control list to obtain target acquisition data; encrypting the target acquisition data and the interrupt scheduling result by using a data encryption mechanism to obtain target encrypted data. The access control list (ACL for short) in this embodiment is a security mechanism used to define and restrict access permissions to system resources. The data encryption mechanism is a technical means that converts plaintext data into ciphertext through algorithms and keys to ensure the security during data transmission or storage. This embodiment does not limit the specific data encryption mechanism. For example, the data encryption mechanism in this embodiment may be symmetric encryption; or the data encryption mechanism in this embodiment may also be asymmetric encryption. This embodiment prevents malicious interrupt attacks and data leakage through the access control list (ACL) and data encryption technology.

[0088] An interrupt scheduling method provided by an embodiment of the present invention may include: S101, obtaining system load prediction data corresponding to a non-uniform memory access system; S102, dynamically adjusting an interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy; S103, determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and processing each interrupt based on the target interrupt processing device. Compared with the traditional static scheduling, the present invention dynamically adjusts the interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy, and can schedule interrupts based on the dynamically adjusted target interrupt scheduling policy, realizing the intelligence and dynamicization of interrupt scheduling.

[0089] For the convenience of understanding the present invention, please specifically refer to Figure 2 , Figure 2 which is a flowchart of another interrupt scheduling method provided by an embodiment of the present invention, and may specifically include:

[0090] S201, obtaining the current system performance state and historical system performance data.

[0091] The current system performance state in this embodiment refers to the performance of computer hardware and software during operation, including key indicators such as response speed, processing capacity, and stability. This embodiment does not limit the specific method for determining the system performance state. For example, this embodiment can determine the system performance based on the CPU usage rate: The CPU is the brain of the computer, and its usage rate reflects the current system load. A high usage rate may mean that a program is occupying too much computing resource, resulting in a slow system response. Or this embodiment can be determined based on the memory usage: Memory is where the computer temporarily stores running programs and data. If the available memory is insufficient, the system may need to frequently read data from the hard disk, which will significantly reduce performance. This embodiment can also be based on the disk read and write speed: The disk read and write speed directly affects the data access efficiency. If the disk is in a high-load state for a long time, it may be due to background services or applications performing a large amount of data exchange. This embodiment can also be based on the network bandwidth utilization rate: For applications that rely on the network, the utilization rate of network bandwidth is an important indicator. Network congestion may cause data transmission delays and affect the user experience. This embodiment can also be based on the system stability index: The system stability index and various events that occur in the system (such as software installation, system update, application crash, etc.) can be viewed through the reliability monitor. This information helps analyze whether the system performance is stable. This embodiment can also be based on third-party performance testing tools to comprehensively evaluate the system performance level. Or in this embodiment, the system performance can also be determined based on at least two of the above parameters. The system performance state in this embodiment is used to determine the level of the current system performance, so as to determine whether the performance has decreased after processing the interrupt based on the target interrupt scheduling policy. If it has decreased, it indicates that the current interrupt scheduling policy needs to be adjusted to ensure that the performance remains unchanged or even improves. This embodiment does not limit the specific historical system performance data. For example, the historical system performance data in this embodiment can be at least one of CPU load, memory usage rate, interrupt frequency, and network traffic.

[0092] S202, make a prediction based on the current system performance state and historical system performance data, and determine the system load prediction data.

[0093] This embodiment does not limit the specific method for making a prediction based on the current system performance state and historical system performance data to determine the system load prediction data. For example, this embodiment can make a prediction based on machine learning methods based on the current system performance state and historical system performance data to determine the system load prediction data; or this embodiment can also perform a prediction analysis based on the current system performance state and historical system performance data to obtain the law of load change, and determine the system load prediction data based on the law of load change.

[0094] It should be further noted that, in order to improve the accuracy of determining the system load prediction data, the above prediction based on the current system performance state and historical system performance data to determine the system load prediction data may include:

[0095] S2021, update the parameters of the prediction model based on the current system performance state to obtain an updated target prediction model;

[0096] S2022, use the target prediction model to make a prediction according to the historical system performance data to determine the system load prediction data.

[0097] In this embodiment, the parameters of the prediction model can be updated based on the current system performance state. When the prediction model is a long short-term memory model, the parameters that can be adjusted include the memory depth and the memory length. It can be understood that if, compared with before, the performance of the system decreases after adjusting the target interrupt scheduling policy based on the system load prediction data of the previous prediction, it means that there is a problem with the previous prediction, so it is necessary to adjust the parameters of the prediction model that affect a certain prediction data. This embodiment can predict the future system load and interrupt requirements in real time. The prediction model in this embodiment can adjust the parameters of the model in a timely manner according to the feedback (the current system performance state), improving the prediction effect of the model.

[0098] It should be further noted that the above update of the parameters of the prediction model based on the current system performance state to obtain an updated target prediction model may include: updating the parameters of the long short-term memory network model based on the current system performance state to obtain an updated target prediction model; where the current system performance state is the system performance after executing an interrupt based on the interrupt scheduling policy; the training process of the long short-term memory network model includes data segmentation, model initialization, parameter optimization, and model verification; where data segmentation refers to segmenting the data according to the data type; model initialization refers to initializing the parameters of the long short-term memory network model; parameter optimization refers to adjusting the parameters of the model to minimize the loss function; model verification refers to determining the prediction performance of the trained long short-term memory network model. In this embodiment, the LSTM (long short-term memory model) is sensitive to time and can learn the patterns and features in the time series data, and is suitable for tasks such as time series prediction and signal processing. This embodiment uses the long short-term memory network (LSTM) as the core prediction model, which can accurately capture the temporal changes and complex patterns of the system load. The LSTM model can effectively handle long-term dependencies through its memory units and gating mechanisms, and is suitable for the dynamic prediction of the system load. The innovation lies in combining the LSTM model with the real-time data stream to form a closed-loop prediction system, which can update the prediction results within milliseconds, thereby achieving accurate prediction of the system load.

[0099] It should be further noted that, in order to improve the accuracy of data, before predicting based on the current system performance state and historical system performance data to determine the system load prediction data, the following steps may also be included: using the principal component analysis method to extract the key feature data from the historical system performance data; wherein, the key feature data includes the number of interrupts, memory utilization rate, number of devices, terminal frequency, and central processing unit load; performing scale-uniform processing on the key feature data to obtain the scale-uniform performance data; correspondingly, predicting based on the current system performance state and historical system performance data to determine the system load prediction data may include: predicting based on the current system performance state and the scale-uniform performance data to determine the system load prediction data. This embodiment uses the principal component analysis (PCA) method to extract key feature data from historical system performance data. PCA is a statistical method used to transform the original data into a new coordinate system through linear transformation, so that the basis vectors of the new coordinate system are the main components of the original data. This can help us identify the most important features in the data and remove redundant information. This embodiment performs scale-uniform processing on the key feature data to eliminate the dimensionality effect between different features and make the data more suitable for subsequent analysis and prediction.

[0100] S203, dynamically adjust the interrupt scheduling policy based on the system load prediction data to obtain the target interrupt scheduling policy.

[0101] This embodiment can determine the performance of each target interrupt handling device based on the system load prediction data, and thus preferentially adjust the target interrupt handling device corresponding to each interrupt in the interrupt scheduling policy. In this embodiment, for the target interrupt scheduling policy, the mappings of the same network card are preferably given to the same CPU. Mapping to the same CPU means that in a multi-core processor system, in order to improve processing efficiency and system performance, the interrupt requests generated by specific hardware (such as a network card) are preferentially assigned to a fixed one or several CPU cores for processing. Specifically, this policy has the following key aspects: Interrupt affinity: By setting the interrupt affinity (IRQ Affinity), specific interrupt requests can be bound to specific CPUs. The purpose of this is to avoid all interrupt processing being concentrated on a few CPUs, resulting in these CPUs being overloaded while other CPUs are relatively idle. For network cards that support multiple queues, the interrupts can be evenly distributed to different CPUs through hardware queues; for network cards that do not support multiple queues, a similar effect can be achieved through software queues. In this way, each CPU can handle a part of the interrupts, thereby improving the overall processing efficiency. Binding the network card interrupts to a fixed CPU can reduce the overhead of interrupt processing, increase the throughput of network data, and reduce latency. This is because when multiple CPUs simultaneously process interrupts from the same network card, additional context switching and cache coherence problems may occur, thus affecting performance.

[0102] It should be further noted that, in order to improve the accuracy of the interruption strategy, the above dynamic adjustment of the interruption scheduling strategy based on the system load prediction data to obtain the target interruption scheduling strategy may include: dynamically adjusting the interruption scheduling strategy based on the system load prediction data and the current system performance state to obtain the target interruption scheduling strategy; wherein, the parameters for dynamic adjustment include the interruption affinity threshold, and the interruption affinity includes interrupting and preferentially scheduling to memory. The interruption affinity threshold in this embodiment includes interrupting and preferentially scheduling to memory. When the memory is insufficient, determine the maximum CPU threshold when each interruption is processed on each CPU. If the threshold of the current CPU is greater than the maximum CPU threshold, then this CPU cannot be scheduled at this time. This embodiment can preferentially allocate interruptions to the CPU with lower load based on the interruption affinity threshold, improving the efficiency of interruption processing.

[0103] S204, determine the target interruption processing device corresponding to each interruption based on the target interruption scheduling strategy, and process each interruption based on the target interruption processing device.

[0104] This embodiment does not limit the specific target interruption processing device. The target interruption processing device in this embodiment may be a CPU. This embodiment can adopt the Q-learning method, learn and optimize through the real-time feedback of the scheduling strategy. Q-learning is a value-based model-free reinforcement learning algorithm.

[0105] It should be further noted that, in the process of processing interruptions based on the interruption scheduling strategy, it may also include: determining whether the current interruption processing device is processing other interruptions. When it is processing, judge the priorities of the current interruption and other interruptions, and preferentially process the interruption request with a higher priority, masking the interrupt requests of the same level or lower levels to form interruption nesting. Or under the condition of a multi-core CPU (interruption processing device), if a large number of hardware interruptions are allocated to different CPU cores for processing. It can well balance the performance. For example, there are multiple CPU multi-cores, multiple network cards, and multiple hard disks on a server. If the network card interrupt can occupy a CPU core alone and the disk I / O interrupt can occupy a CPU core alone, it will greatly reduce the load of a single CPU and improve the overall processing efficiency.

[0106] It should be further noted that, based on any of the above embodiments, in order to improve the stability of system operation and the accuracy of prediction, after determining the target interrupt handling device corresponding to each interrupt based on the target interrupt scheduling policy and processing each interrupt based on the target interrupt handling device, it may further include: obtaining system performance feedback data after processing the interrupts based on the target interrupt scheduling policy; wherein, the system performance feedback data includes at least one of the central processing unit usage rate, memory access latency, input / output operation frequency, network traffic, waiting time, resource utilization rate, and interrupt response time; analyzing the system performance feedback data to determine the target performance parameter corresponding to the current system; comparing the target performance parameter with the performance parameter threshold; when it is determined that the target performance parameter is less than the performance parameter threshold, no processing is performed; when it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, it is determined to send a prompt message so that the client can adjust the interrupt scheduling policy based on the prompt message; the system load feedback data corresponding to the system load prediction data in the system performance feedback data; comparing the system load feedback data with the system load prediction data to determine the system load prediction difference; adjusting the corresponding system load prediction model based on the system load prediction difference to obtain an adjusted system load prediction model. In this embodiment, analyzing the system performance feedback data to determine the target performance parameter corresponding to the current system means comprehensively integrating all the system performance feedback data to determine a more definite target performance parameter, so that the target performance parameter can accurately reflect the state of the current system. In this embodiment, when it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, the system will send a prompt message to the client. These prompt messages may include performance warnings, recommended optimization measures, or adjustment suggestions for the interrupt scheduling policy, etc., so that the client can timely understand the system status and make corresponding adjustments. In this embodiment, based on the calculated system load prediction difference, the original system load prediction model is adjusted. This may include modifying model parameters, introducing new influencing factors, or replacing a more suitable prediction algorithm, etc. The adjusted model should be able to more accurately predict the future system load situation, thereby providing strong support for the optimization of the interrupt scheduling policy.

[0107] An interrupt scheduling method provided by an embodiment of the present invention dynamically adjusts the affinity and mapping policy of interrupts by calculating the load and interrupt handling capabilities of each CPU in real time. The innovation lies in introducing an adaptive threshold adjustment mechanism to dynamically adjust the parameters of the scheduling policy according to the current state of the system, ensuring that interrupts are preferentially allocated to CPUs with lower load and stronger processing capabilities. The specific beneficial effects include:

[0108] First: Improve system performance: In the scenario of high-load network requests, the interrupt processing time is reduced by 30%, and the overall throughput is increased by 25%.

[0109] Second: Enhance resource utilization rate: By dynamically adjusting the interruption strategy, waste of CPU and memory resources is reduced.

[0110] Third: Improve system stability: Through adaptive optimization and fault tolerance mechanisms, ensure that the system can still operate stably under abnormal conditions.

[0111] For easy understanding, please refer to Figure 3 , Figure 3 which is a flow example of an interruption scheduling method provided by an embodiment of the present invention, and specifically may include:

[0112] S301, Collect system performance data; wherein, the system performance data includes multi-dimensional data such as CPU load, memory usage rate, interruption frequency, and network traffic.

[0113] For easy understanding, please refer to Figure 4 , Figure 4 which is a structural framework diagram of an interruption scheduling method provided by an embodiment of the present invention. It can be seen from Figure 4 that the whole method includes a collection module, a data processing module, a prediction module, a machine learning module, a scheduling strategy, and a reinforcement feedback module. The design principle of the data collection module in this embodiment: The data collection module is responsible for real-time monitoring of the system operation status and collecting multi-dimensional data including CPU load, memory usage rate, interruption frequency, network traffic, etc. To ensure the accuracy and real-time nature of the data, the module uses high-precision sensors and data acquisition cards. Specific implementation: Deploy sensors at key nodes of the system to obtain various performance indicators in real time. The data is transmitted to the central processing unit through a high-speed bus and stored in a distributed database for subsequent processing and analysis.

[0114] S302, Perform data cleaning, normalization, and dimensionality reduction techniques on the system performance data to obtain target system performance data.

[0115] The design principle of the data processing module in this embodiment: After data collection, the system needs to perform feature extraction and preprocessing on the data to identify key factors affecting interruption scheduling. Data cleaning, normalization, and dimensionality reduction techniques are used to remove noise and redundant information and improve data quality. Specific implementation: Use the principal component analysis (PCA) technique to extract the main features in the data (the main features mainly refer to the number of interruptions, memory utilization rate, number of devices, overall interruption load, and CPU load), and convert the data to a unified scale through standardization processing. The data after feature extraction is stored in a feature database for use by the prediction model. The data processing in this embodiment may also include classifying the data, for example, classifying to determine which one belongs to the CPU, memory, network card, in which NUMA, and the hardware layout.

[0116] S303. Call the prediction model at fixed time intervals, make predictions based on system performance data, and determine the system load prediction data.

[0117] The design principle of the machine learning module in this embodiment: Use a long short-term memory network (LSTM) to build a prediction model, which can capture the temporal changes and complex patterns of system load. Use historical data for model training, and improve the generalization ability of the model through cross-validation and hyperparameter optimization. Specific implementation: Model training is carried out in a GPU-accelerated environment to improve training efficiency. The training process includes data segmentation, model initialization, parameter optimization, and model verification. The finally trained model is deployed on the prediction server to provide load prediction results in real time. Prediction-scheduling closed-loop system: Design a closed-loop system to feedback the load prediction results to the scheduling strategy in real time. By predicting future load changes, adjust the interrupt allocation strategy in advance to avoid performance bottlenecks during peak load periods. Dynamic parameter adjustment: Dynamically adjust the key parameters of the scheduling algorithm, such as the interrupt affinity threshold, load balancing strategy, etc., according to the predicted load trend. The design principle of the prediction module in this embodiment: Deploy the trained LSTM model to predict the future system load and interrupt requirements (interrupt requirements refer to the requirements for completing this interrupt) in real time. Based on the prediction results, dynamically adjust the interrupt affinity and mapping strategy, and preferentially allocate interrupts to CPUs with lower loads. Specific implementation: The system calls the prediction model at fixed time intervals and makes predictions based on the current system state (feedback) and historical data. The prediction results are used to update the interrupt scheduling table, which is stored in shared memory for the scheduler to access in real time. Priority classification: Divide interrupts into multiple priority levels (such as high, medium, low), and classify them according to the source, type, and historical processing time of the interrupts. Priority scheduling strategy: When designing the scheduling strategy, give priority to processing high-priority interrupts to ensure the timely response of critical tasks. At the same time, dynamically adjust the processing time of low-priority interrupts to avoid affecting the overall system performance. Cache prefetch mechanism: When it is predicted that certain interrupts are about to occur, load the relevant data into the cache in advance to reduce the data loading time during interrupt processing. Optimization of cache replacement strategy: Dynamically adjust the cache replacement strategy according to the frequency of interrupt processing and data access patterns, and preferentially retain data with high-frequency access.

[0118] S304. Adjust the interrupt scheduling strategy according to the system load prediction data to obtain the adjusted interrupt scheduling strategy.

[0119] S305. Adjust the adjusted interrupt scheduling strategy according to the interrupt type and historical processing time to obtain a priority-based interrupt scheduling strategy.

[0120] S306. Use the priority-based interrupt scheduling strategy to allocate interrupts to the corresponding CPUs.

[0121] S307. Continuously update the prediction model and the interrupt scheduling policy by interrupting the scheduling execution effect.

[0122] The adaptive optimization module in this embodiment: Design principle: Continuously update the machine learning model through a feedback mechanism to adapt to changes in the system environment. Introduce the Q-learning algorithm, adjust the policy parameters according to the scheduling effect, and achieve adaptive optimization. Specific implementation: The system records the scheduling effect after each scheduling, including metrics such as interrupt handling time and CPU utilization. Through the Q-learning algorithm, the system updates the policy parameters based on these feedbacks to optimize the scheduling performance. Policy exploration and optimization: Through the exploration mechanism in reinforcement learning, continuously try different combinations of scheduling policies and record their impacts on system performance. Reward mechanism design: Design a reasonable reward mechanism, taking interrupt handling efficiency, system load balance, etc. as reward metrics to guide the direction of policy optimization. Security and fault tolerance mechanism: Design principle: Design security policies to prevent malicious interrupt attacks and data leakage. Introduce a fault tolerance mechanism to ensure that the system can still operate stably in case of hardware failures or anomalies. Specific implementation: Protect the security of system data by setting up an access control list (ACL) and a data encryption mechanism. The system regularly conducts fault detection and automatically switches to a backup plan when an anomaly is detected to ensure the stability of the system.

[0123] The interrupt scheduling device provided by the embodiments of the present invention will be introduced below. The interrupt scheduling device described below can be correspondingly referred to the interrupt scheduling method described above.

[0124] Figure 5 The structural schematic diagram of an interrupt scheduling device provided by an embodiment of the present invention may include:

[0125] A data acquisition module 100, configured to acquire system load prediction data corresponding to a non-uniform memory access system;

[0126] A dynamic adjustment module 200, configured to dynamically adjust an interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy;

[0127] An interrupt scheduling module 300, configured to determine a target interrupt handling device corresponding to each interrupt based on the target interrupt scheduling policy, and handle each interrupt based on the target interrupt handling device.

[0128] Further, based on the above embodiment, the above interrupt scheduling device may further include:

[0129] A priority determination module, configured to classify the priorities of interrupts according to the interrupt type and the historical interrupt handling time to obtain the priority of each interrupt;

[0130] A module for adjusting the interrupt scheduling policy based on priorities, which is used to adjust the target interrupt scheduling policy based on the priorities of each interrupt to obtain an adjusted target interrupt scheduling policy;

[0131] Correspondingly, the interrupt scheduling module 300 includes:

[0132] An interrupt processing unit, which is used to determine the target interrupt processing device corresponding to each interrupt based on the adjusted target interrupt scheduling policy, and process each interrupt based on the target interrupt processing device.

[0133] Furthermore, based on any of the above embodiments, the above priority determination module may include:

[0134] A priority classification unit, which is used to classify the priorities of interrupts based on the interrupt types when the interrupt types are inconsistent to obtain the priority of each interrupt;

[0135] A priority determination unit, which is used to classify the priorities of interrupts based on the historical interrupt processing time when the interrupt types are the same to obtain the priority of each interrupt; among them, the larger the historical interrupt processing time, the higher the priority level.

[0136] Furthermore, based on any of the above embodiments, the above interrupt scheduling device may further include:

[0137] A target interrupt and target interrupt time point prediction module, which is used to predict the target interrupt and the target interrupt time point based on historical interrupt data;

[0138] A target cache determination unit, which is used to load the data corresponding to the target interrupt into the cache before the target interrupt occurs based on the interrupt time point to obtain a target cache.

[0139] Furthermore, based on the above embodiments, the above interrupt scheduling device may further include:

[0140] A judgment module, which is used to judge whether the interrupt processing frequency corresponding to each data in the target cache is greater than a set processing frequency threshold when it is determined that the data size in the target cache is greater than a set data threshold;

[0141] A data clearing module, which is used to determine to clear the data from the target cache when the interrupt processing frequency is not greater than the set processing frequency threshold;

[0142] A non-processing module, which is used to determine not to process the data when the interrupt processing frequency is greater than the set processing frequency threshold.

[0143] Furthermore, based on any of the above embodiments, the above interrupt scheduling device may further include:

[0144] A data filtering module, configured to filter the system load prediction data based on an access control list to obtain target acquisition data;

[0145] A data encryption module, configured to encrypt the target acquisition data and the interrupt scheduling result by using a data encryption mechanism to obtain target encrypted data.

[0146] Further, based on any of the above embodiments, the above interrupt scheduling device may further include:

[0147] A performance data acquisition module, configured to acquire the current system performance state and historical system performance data corresponding to the non-uniform memory access system;

[0148] A system load prediction data determination module, configured to perform prediction based on the current system performance state and the historical system performance data to determine the system load prediction data.

[0149] Further, based on the above embodiment, the above system load prediction data determination module may include:

[0150] A parameter update unit, configured to update the parameters of a prediction model based on the current system performance state to obtain an updated target prediction model;

[0151] A prediction unit based on the target prediction model, configured to perform prediction by using the target prediction model according to the historical system performance data to determine the system load prediction data.

[0152] Further, based on the above embodiment, the parameter update unit may include:

[0153] A parameter update subunit, configured to update the parameters of a long short-term memory network model based on the current system performance state to obtain the updated target prediction model; wherein, the current system performance state is the system performance after an interrupt is executed based on an interrupt scheduling policy; the training process of the long short-term memory network model includes data segmentation, model initialization, parameter optimization, and model verification;

[0154] Wherein, the data segmentation refers to segmenting the data according to the data type;

[0155] The model initialization refers to initializing the parameters of the long short-term memory network model;

[0156] The parameter optimization refers to adjusting the parameters of the model to minimize a loss function;

[0157] The model verification refers to determining the prediction performance of the trained long short-term memory network model.

[0158] Further, based on the above embodiments, the above dynamic adjustment module 200 may include:

[0159] A dynamic adjustment unit, configured to dynamically adjust the interrupt scheduling policy based on the system load prediction data and the current system performance state to obtain the target interrupt scheduling policy; wherein, the parameters for dynamic adjustment include the interrupt affinity threshold, and the interrupt affinity includes that interrupts are preferentially scheduled to the memory.

[0160] Further, the above interrupt scheduling device may further include:

[0161] A feature extraction module, configured to extract key feature data from historical system performance data by using the principal component analysis method; wherein, the key feature data includes the number of interrupts, memory utilization rate, number of devices, terminal frequency, and central processing unit load.

[0162] A scale unification module, configured to perform scale unification processing on the key feature data to obtain scale-unified performance data.

[0163] Correspondingly, the above system load prediction data determination module may include:

[0164] A system load prediction data determination unit, configured to perform prediction based on the current system performance state and the scale-unified performance data to determine the system load prediction data.

[0165] Further, based on any of the above embodiments, the above interrupt scheduling device may further include:

[0166] A system performance feedback data acquisition module, configured to acquire system performance feedback data after processing interrupts based on the target interrupt scheduling policy; wherein, the system performance feedback data includes at least one of the central processing unit usage rate, memory access latency, input / output operation frequency, network traffic, waiting time, resource utilization rate, and interrupt response time.

[0167] A target performance parameter determination module, configured to analyze the system performance feedback data to determine the target performance parameter corresponding to the current system.

[0168] A comparison module, configured to compare the target performance parameter with the performance parameter threshold.

[0169] A non-processing module, configured not to perform processing when it is determined that the target performance parameter is less than the performance parameter threshold.

[0170] A prompt message sending module, configured to determine to send a prompt message when it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, so that the client adjusts the interrupt scheduling policy based on the prompt message.

[0171] A system load feedback data determination module, configured to determine system load feedback data corresponding to the system load prediction data in the system performance feedback data;

[0172] A difference determination module, configured to compare the system load feedback data and the system load prediction data to determine a system load prediction difference;

[0173] An adjustment module, configured to adjust a corresponding system load prediction model based on the system load prediction difference to obtain an adjusted system load prediction model.

[0174] It should be noted that the order of the modules and units in the above interruption scheduling device can be changed before and after without affecting the logic.

[0175] Figure 5 For the description of the features in the corresponding embodiments, reference can be made to Figure 5 the relevant descriptions of the corresponding embodiments, which will not be elaborated here one by one.

[0176] The interruption scheduling device provided by the embodiment of the present invention may include: a data acquisition module 100, configured to acquire system load prediction data corresponding to a non-uniform memory access system; a dynamic adjustment module 200, configured to dynamically adjust an interruption scheduling policy based on the system load prediction data to obtain a target interruption scheduling policy; an interruption scheduling module 300, configured to determine a target interruption processing device corresponding to each interruption based on the target interruption scheduling policy, and process each interruption based on the target interruption processing device. Compared with the traditional static interruption scheduling, the present invention dynamically adjusts the interruption scheduling policy based on the system load prediction data to obtain a target interruption scheduling policy, and can schedule interruptions based on the dynamically adjusted target interruption scheduling policy, realizing the intelligence and dynamicization of interruption scheduling, and improving the accuracy of interruption scheduling.

[0177] Next, an interruption scheduling device provided by the embodiment of the present invention will be introduced. The interruption scheduling device described below can be correspondingly referred to the interruption scheduling method described above.

[0178] Figure 6 is a schematic structural diagram of an interruption scheduling device provided by the embodiment of the present invention, as Figure 6 shown, the interruption scheduling device includes: a memory 60, configured to store a computer program;

[0179] a processor 61, configured to implement the steps of the interruption scheduling method in the above embodiment when executing the computer program.

[0180] The interruption scheduling device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a notebook computer, or a desktop computer, etc.

[0181] Among them, the processor 61 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. The processor 61 may be implemented in at least one of the following hardware forms: digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may further include an artificial intelligence (AI) processor, and the AI processor is used to process computing operations related to machine learning.

[0182] The memory 60 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 60 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601. After the computer program is loaded and executed by the processor 61, it can implement the relevant steps of the interrupt scheduling method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may further include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, data required for interrupt scheduling.

[0183] In some embodiments, the interrupt scheduling device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0184] Those skilled in the art can understand that Figure 6 the structure shown in

[0185] It can be understood that if the interrupt scheduling method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), electrically erasable programmable ROMs, registers, hard disks, removable disks, CD-ROMs, magnetic disks, or optical discs.

[0186] Based on this, the embodiments of the present invention also provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the interrupt scheduling method as described above are implemented.

[0187] Based on this, the embodiments of the present invention also provide a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the above-mentioned interrupt scheduling method are implemented.

[0188] The above has introduced in detail an interrupt scheduling device provided by the embodiments of the present invention. The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part.

[0189] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0190] The above has introduced in detail a method, device, equipment and computer-readable storage medium for interrupt scheduling provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. An interrupt scheduling method, characterized in that Including: Obtain the current system performance state and historical system performance data corresponding to the non-uniform memory access system; Based on the current system performance state and the historical system performance data, perform prediction to determine system load prediction data, including: updating the parameters of the prediction model based on the current system performance state to obtain an updated target prediction model; the prediction model is constructed based on a machine learning algorithm; using the target prediction model to perform prediction according to the historical system performance data to determine system load prediction data; Dynamically adjust the interrupt scheduling policy based on the system load prediction data and the current system performance state to obtain a target interrupt scheduling policy; wherein, the dynamically adjusted parameter includes an interrupt affinity threshold, and the interrupt affinity includes interrupts being preferentially scheduled to memory; the target interrupt scheduling policy includes at least one of the correspondence between interrupts and interrupt handling devices, the interrupt handling device closest to the interrupt, and the processing capabilities of the interrupt handling devices corresponding to the interrupts; Based on the target interrupt scheduling policy, determine the target interrupt handling device corresponding to each interrupt, and handle each interrupt based on the target interrupt handling device.

2. The interrupt scheduling method according to claim 1, wherein Before determining the target interrupt handling device corresponding to each interrupt based on the target interrupt scheduling policy and handling each interrupt based on the target interrupt handling device, it further includes: Classify the priorities of interrupts according to the interrupt type and historical interrupt handling time to obtain the priority of each interrupt; Adjust the target interrupt scheduling policy based on the priority of each interrupt to obtain an adjusted target interrupt scheduling policy; Correspondingly, determining the target interrupt handling device corresponding to each interrupt based on the target interrupt scheduling policy and handling each interrupt based on the target interrupt handling device includes: Determine the target interrupt handling device corresponding to each interrupt based on the adjusted target interrupt scheduling policy, and handle each interrupt based on the target interrupt handling device.

3. The interrupt scheduling method according to claim 2, characterized in that The classifying the priorities of interrupts according to the interrupt type and historical interrupt handling time to obtain the priority of each interrupt includes: When the interrupt types are inconsistent, classify the priorities of interrupts based on the interrupt type to obtain the priority of each interrupt; When the interrupt types are the same, classify the priorities of interrupts based on the historical interrupt handling time to obtain the priority of each interrupt; wherein, the greater the historical interrupt handling time, the higher the priority level.

4. The interrupt scheduling method according to claim 1, wherein Before dynamically adjusting the interrupt scheduling policy based on the system load prediction data to obtain a target interrupt scheduling policy, it further includes: Predict the target interrupt and the target interrupt time point based on historical interrupt data; Based on the interrupt time point before the target interrupt occurs, load the data corresponding to the target interrupt into the cache to obtain a target cache.

5. The interrupt scheduling method according to claim 4, wherein After loading the data corresponding to the target interrupt into the cache to obtain a target cache based on the interrupt time point before the target interrupt occurs, it further includes: When it is determined that the data size in the target cache is greater than the set data threshold, determine whether the interrupt processing frequency corresponding to each data in the target cache is greater than the set processing frequency threshold; When the interrupt processing frequency is not greater than the set processing frequency threshold, determine to clear the data from the target cache; When the interrupt processing frequency is greater than the set processing frequency threshold, determine not to process the data.

6. The interrupt scheduling method according to claim 1, characterized in that During the process of interrupt scheduling, it further includes: Filter the system load prediction data based on the access control list to obtain the target acquisition data; Use the data encryption mechanism to encrypt the target acquisition data and the interrupt scheduling result to obtain the target encrypted data.

7. The interrupt scheduling method according to claim 1, wherein Update the parameters of the prediction model based on the current system performance state to obtain the updated target prediction model, including: Update the parameters of the long short-term memory network model based on the current system performance state to obtain the updated target prediction model; wherein, the current system performance state is the system performance after executing the interrupt based on the interrupt scheduling policy; the training process of the long short-term memory network model includes data segmentation, model initialization, parameter optimization, and model verification; Wherein, the data segmentation refers to segmenting the data according to the data type; The model initialization refers to initializing the parameters of the long short-term memory network model; The parameter optimization refers to adjusting the parameters of the model to minimize the loss function; The model verification refers to determining the prediction performance of the trained long short-term memory network model.

8. The interrupt scheduling method according to claim 1, wherein Before predicting based on the current system performance state and the historical system performance data to determine the system load prediction data, it further includes: Use the principal component analysis method to extract the key feature data from the historical system performance data; wherein, the key feature data includes the number of interrupts, memory utilization rate, number of devices, terminal frequency, and central processor load; Perform scale unification processing on the key feature data to obtain the performance data with unified scale; Correspondingly, predicting based on the current system performance state and the historical system performance data to determine the system load prediction data includes: Predict based on the current system performance state and the performance data with unified scale to determine the system load prediction data.

9. The interrupt scheduling method according to claim 1, wherein After determining the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy and processing each interrupt based on the target interrupt processing device, it further includes: Obtain the system performance feedback data after processing the interrupt based on the target interrupt scheduling policy; wherein, the system performance feedback data includes at least one of the central processor usage rate, memory access latency, input / output operation frequency, network traffic, waiting time, resource utilization rate, and interrupt response time; Analyze the system performance feedback data to determine the target performance parameters corresponding to the current system; Compare the target performance parameters with the performance parameter threshold; When it is determined that the target performance parameters are less than the performance parameter threshold, do not perform processing; When it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, it is determined to send a prompt message so that the client adjusts the interrupt scheduling policy based on the prompt message; the system load feedback data corresponding to the system load prediction data in the system performance feedback data; compare the system load feedback data with the system load prediction data to determine the system load prediction difference; adjust the corresponding system load prediction model based on the system load prediction difference to obtain an adjusted system load prediction model.

10. An interrupt scheduling device, characterized in that, including: a data acquisition module for acquiring system load prediction data corresponding to a non-uniform memory access system; a performance data acquisition module for acquiring the current system performance state and historical system performance data corresponding to the non-uniform memory access system; a system load prediction data determination module for predicting based on the current system performance state and the historical system performance data to determine the system load prediction data; the system load prediction data determination module includes: a parameter update unit for updating the parameters of the prediction model based on the current system performance state to obtain an updated target prediction model; the prediction model is constructed based on a machine learning algorithm; a prediction unit based on the target prediction model for predicting according to the historical system performance data using the target prediction model to determine the system load prediction data; a dynamic adjustment module for dynamically adjusting the interrupt scheduling policy based on the system load prediction data and the current system performance state to obtain a target interrupt scheduling policy; wherein, the dynamically adjusted parameters include an interrupt affinity threshold, and the interrupt affinity includes interrupts being preferentially scheduled to memory; the target interrupt scheduling policy includes at least one of the correspondence between interrupts and interrupt handling devices, the interrupt handling device closest to the interrupt, and the processing capabilities of the interrupt handling devices corresponding to the interrupts; an interrupt scheduling module for determining the target interrupt handling device corresponding to each interrupt based on the target interrupt scheduling policy and processing each interrupt based on the target interrupt handling device.

11. An interrupt scheduling device, characterized in that, including: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the interrupt scheduling method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the interrupt scheduling method according to any one of claims 1 to 9 are implemented.

13. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, the steps of the interrupt scheduling method according to any one of claims 1 to 9 are implemented.

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