Method and apparatus for improving address translation efficiency in memory virtualization

Abstract

The application relates to a memory virtualization address substitution efficiency improving method and device, wherein the method comprises the following steps: a core analyzes received last address reading response data and forms a current address, and sends a memory access request for the current address; an out-core Cache control component receives the memory access request for the current address, judges whether the generation of a next address depends on the current address, registers a prefetch starting flag and a low-bit address if the generation of the next address depends on the current address, and judges whether the prefetch request for the current address is executed; if the prefetch request for the current address is executed, reading response data of the current address is directly generated; if the prefetch request for the current address is not executed, the reading request for the current address is combined into the prefetch request for the current address, and the reading response data of the current address is generated after data from other cores or a main memory is received; the next address is formed based on the reading response data of the current address and the low-bit address, and a prefetch request for the next address is triggered. The application can improve the efficiency of substituting a guest machine virtual address into a host machine physical address.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of microstructure design of high-performance general-purpose processors, and particularly relates to a memory virtualization address substitution efficiency improving method and device. BACKGROUND

[0002] Virtualization technology is a resource management technology that creates an abstraction layer on hardware through software, allowing multiple operating systems and applications to run simultaneously on the same physical machine and share its CPU, memory, storage, and network hardware resources. Current virtualization technology has become an important support for cloud computing, making flexible configuration and efficient use of resources possible, and also has certain advantages in security enhancement.

[0003] Memory virtualization technology is a kind of virtualization technology that allows multiple virtual machines to share the memory resources of a physical machine while ensuring that each virtual machine can safely and independently run its own operating system and applications. Memory virtualization technology can effectively improve the resource utilization of processors, reduce costs, and provide more flexible resource management. Since virtual machines use virtual address spaces and physical machines use physical address spaces, the core technology of memory virtualization is to quickly convert virtual addresses into physical addresses.

[0004] For convenience of description, some terms are defined as follows:

[0005] Host: host machine, refers to a physical machine in a virtualization environment that installs virtualization management software, is responsible for executing virtualization management software, managing the allocation of physical resources (such as CPU, memory, storage, and network interface), and providing a running environment for virtual machines;

[0006] Guest: guest machine, refers to a virtual machine in a virtualization environment, which is created by the virtualization management software on the host machine, and each virtual machine can run different operating systems and install and run its own applications;

[0007] GVA: guest virtual address, refers to the instruction stream virtual address of an application access instruction or the data stream virtual address of an application access data on the guest machine;

[0008] GPA: guest physical address, refers to the physical address from the perspective of the guest machine;

[0009] HPA: host physical address, refers to the physical address that is actually mapped to the storage space of the processor, which is the actual physical address of the processor access;

[0010] GPT: guest page table, located in the physical memory of the guest machine, maintained by the operating system of the guest machine, and used to map the guest virtual address GVA to the guest physical address GPA;

[0011] APT: The host machine's Hypervisor manages page tables, which are located in the host machine's physical memory and maintained by the Hypervisor. They map the guest physical address (GPA) to the host physical address (HPA).

[0012] like Figure 1 As shown, the current mainstream hardware-assisted memory virtualization technology uses page-based virtualization management for both the guest and host machines. This means that the guest virtual address GVA needs to go through two layers of page table substitution to obtain the real physical address HPA. First, the guest page table GPT is used to substitute the guest virtual address GVA to obtain the virtual machine physical address GPA. This process is called traditional paging. Second, the Hypervisor manages the page table APT to substitute the guest physical address GPA to obtain the host physical address HPA. This process is called additional paging.

[0013] As processor system hardware and software scales up, the guest virtual address space also grows larger, and the effective bit width of the virtual address also increases. Therefore, most processors employ four- or five-level page tables for management. Taking four-level page table management as an example, the binary representation (no more than 64 bits) of a guest virtual address GVA is divided into five address regions, as shown in Table 1 below:

[0014] Table 1 Client Virtual Address Table

[0015] PGD Index PUD Index PMD Index PTE Index Page offset

[0016] PGD Index is the index address of accessing the Page Global Directory (PGD, hereinafter referred to as the first GPT page table directory) of the guest page table during the page table replacement, PUD Index is the index address of accessing the Page Upper Directory (PUD, hereinafter referred to as the second GPT page table directory) of the guest page table during the page table replacement, PMD Index is the index address of accessing the Page Middle Directory (PMD, hereinafter referred to as the third GPT page table directory) of the guest page table during the page table replacement, PTE Index is the index address of accessing the Page Table Entry (PTE, hereinafter referred to as the fourth GPT page table) of the guest page table during the page table replacement, and Page offset is the offset address of the GVA address in the page. The address bit width of each region is related to the page granularity size, and generally a page table entry occupies 64-bit in the main memory, therefore, the bit widths of PGD Index, PUD Index, PMD Index and PTE Index are the same, and are 3 bits less than the bit width of Page offset. For example, when the page granularity is 4KB, Page offset is 12 bits, and the other domains are 9 bits respectively, and the GVA is 48 bits in total; when the page granularity is 8KB, Page offset is 13 bits, and the other domains are 10 bits respectively, and the GVA is 53 bits in total.

[0017] The guest physical address is essentially mapped to the virtual address on the host, and is also managed by a four-level page table, and the binary representation (not more than 64 bits) of a guest physical address GPA is divided into five address regions, as shown in Table 2:

[0018] Table 2: Guest physical address table

[0019] APGD Index APUD Index APMD Index APTE Index APage offset

[0020] APGD Index is the index address of accessing the host page table global directory (Additional Page Global Directory, APGD, hereinafter referred to as the first-level APT page table directory) when the page table is replaced, APUD Index is the index address of accessing the host page table upper directory (Additional Page Upper Directory, APUD, hereinafter referred to as the second-level APT page table directory) when the page table is replaced, APMD Index is the index address of accessing the host page table middle directory (Additional Page Middle Directory, APMD, hereinafter referred to as the third-level APT page table directory) when the page table is replaced, APTE Index is the index address of accessing the host page table entry (Additional Page Table Entry, APTE, hereinafter referred to as the fourth-level APT page table) when the page table is replaced, and APage offset is the offset address of the GPA address in the page. Similarly, the bit width of APUD Index, APMD Index and APTE Index is the same, and is 3 bits less than the bit width of APage offset, and the bit width of APGD Index is determined according to the total address bit width of the GPA. For example, when the page granularity is 4KB, APage offset is 12 bits, and the other domains are 9 bits respectively, and the GPA is 48 bits in total; when the page granularity is 8KB, APage offset is 13 bits, the APGD Index domain is 5 bits, and the other domains are 10 bits respectively, and the GPA is 48 bits in total.

[0021] Figure 2 A GPA->HPA conversion schematic diagram is described. Figure 2 APTP is a register for storing the first-level APT page table directory base address, and the address is essentially a host physical address; since the page table itself is necessarily bounded according to the page granularity, only the high bits of the page address of the first-level APT page table directory are stored in APTP, and the page offset address is not included. It takes 9 steps to query the page table directory level by level and finally obtain the HPA address from a GPA address.

[0022] Figure 3 A GVA->GPA conversion schematic diagram is described. Figure 3In the prior art, the PTBR is the base address of the first-level GPT page table directory, which is a guest physical address (GPA). Similar to the APTP, only the high bits of the page address of the first-level GPT page table directory are stored in the PTBR, and no in-page offset address is included. The addresses stored in the GPT page table directory and the GPT page table are also guest physical addresses (GPAs). Therefore, when the GPT page table directory or the GPT page table is queried, the address conversion from a GPA to an HPA needs to be performed. In the memory virtualization technology, 24 steps are required to convert a guest virtual address (GVA) to a host physical address (HPA).

[0023] As can be seen, 24 memory access operations need to be performed to convert a guest virtual address GVA to a corresponding host physical address HPA, and the execution delay of the procedure is very large. Therefore, current processors provide some optimization methods to significantly reduce the number of memory access operations and reduce the delay overhead of address conversion by storing the address conversion relationship of a certain level in a buffer. For example, the mapping relationship between a GVA and an HPA is stored in an address translation buffer (TLB); the mapping relationship between a GPA and an HPA is also stored in an additional address translation buffer (ATLB); a first-level, second-level, and third-level GPT page table directory cache (PSC) is added to store the mapping relationship between a guest virtual address GVA and a GPT page table directory; a first-level, second-level, and third-level APT page table directory cache (APSC) is added to store the mapping relationship between a guest physical address GPA and an APT page table directory. When the address translation buffer or the page table directory cache of a certain level is hit, the number of memory access operations performed can be effectively reduced, and the address conversion efficiency can be improved.

[0024] Although the current processor has adopted multiple technologies to accelerate the efficiency of converting a guest virtual address (GVA) to a host physical address (HPA), when the guest virtual address (GVA) does not hit the address translation buffer (TLB, ATLB) or the page table directory cache (PSC, APSC), multiple read operations need to be performed on the main memory to obtain the final host physical address page table. The number of read operations performed on the main memory is closely related to the hit rate of the address translation buffer and the page table directory cache.

[0025] On one hand, chip architecture is becoming more and more complex, the number of cores integrated in the chip is increasing, the memory space that the chip can support is also increasing, and the overhead of transmitting the read request and response of the main memory and the overhead of performing data consistency processing is also increasing. Especially under the multi-core integration architecture, various requests and responses extended by a read memory operation will appear multiple cross-core transmissions, and the memory cost will also increase sharply. On the other hand, in the face of big data applications, program access across page granularity is more frequent, the hit rate of address translation buffer (TLB, ATLB) and page table directory buffer (PSC, APSC) is very limited, and the addresses of the page table directory at each level do not have obvious regularity, so the original data prefetching mechanism in the processor cannot cope with it, and a large number of page table directory accesses can only be read from the main memory, so the time overhead of address translation is very large, which will ultimately affect the overall performance of the program running. SUMMARY

[0026] The technical problem to be solved by the present application is to provide a memory virtualization address translation efficiency improving method and device, which can reduce the delay overhead of querying the page table directory and the page table when the address translation buffer or the page table directory buffer misses, and improve the efficiency of translating the guest machine virtual address into the host machine physical address.

[0027] The technical solution adopted by the present application to solve the technical problem is to provide a memory virtualization address translation efficiency improving method, comprising the following steps:

[0028] The core analyzes the received last address read response data, forms a current address based on the analyzed data, and sends a memory request for the current address; the memory request carries a prefetch start flag and a low address;

[0029] After the out-of-core Cache control component receives the memory request for the current address, it determines whether the generation of the next address depends on the read response data of the current address according to the prefetch start flag;

[0030] If the generation of the next address depends on the read response data of the current address, the out-of-core Cache control component registers the prefetch start flag and the low address, and queries the out-of-core Cache to determine whether the prefetch request for the current address has been executed;

[0031] If the prefetch request for the current address has been executed, the out-of-core Cache control component directly generates the read response data of the current address;

[0032] If the prefetch request for the current address has not been executed, the out-of-core Cache control component combines the read request for the current address into the prefetch request for the current address, and generates the read response data of the current address after receiving data from other cores or the main memory;

[0033] The extracore cache control component forms a next address based on the read response data of the current address and the low bit address, and triggers a prefetch request for the next address.

[0034] The prefetch start flag is set to two bits; when the prefetch start flag is "00", it indicates that the extracore cache prefetch is not started; when the prefetch start flag is "10", it indicates that the extracore cache read prefetch is started, the extracore cache stores the latest copy of the corresponding address, and there is no copy of the address in the internal cache of other cores or there is a shared read copy of the address; when the prefetch start flag is "11", it indicates that the extracore cache write prefetch is started, and the extracore cache stores the latest copy of the corresponding address, and there is no copy of the address in the internal cache of other cores.

[0035] The memory virtualization address substitution efficiency improvement method further comprises:

[0036] If the generation of the next address does not depend on the read response data of the current address, the extracore cache control component queries the extracore cache to determine whether the prefetch request for the current address is executed;

[0037] If the prefetch request for the current address has been executed, the extracore cache control component directly generates the read response data of the current address;

[0038] If the prefetch request for the current address has not been executed, the extracore cache control component combines the read request for the current address into the prefetch request for the current address, and generates the read response data of the current address after receiving data from other cores or the main memory.

[0039] When the current address is the first address, the extracore cache control component registers the prefetch start flag and the low bit address carried by the memory access request for the current address after receiving the memory access request for the current address, and queries the extracore cache to determine whether the read request for the current address hits the extracore cache;

[0040] If the read request for the current address hits the extracore cache, the extracore cache control component directly generates the read response data of the current address and returns it to the core;

[0041] If the read request for the current address does not hit the extracore cache, the extracore cache control component reads the current address, and parses the read response data of the current address from the data read out of the current address and returns it to the core.

[0042] The technical solution adopted by the application to solve the technical problems is: a memory virtualization address substitution efficiency improvement device is provided, comprising:

[0043] The analysis sending module is configured to control the core to analyze the received previous address read response data, form a current address based on the analyzed data, and send a memory access request for the current address; the memory access request carries a prefetch start flag and a low address;

[0044] The first receiving and judging module is configured to control the out-core Cache control component to, after receiving the memory access request for the current address, judge whether generation of a next address depends on read response data of the current address according to the prefetch start flag;

[0045] The register judging module is configured to, when the generation of the next address depends on the read response data of the current address, control the out-core Cache control component to register the prefetch start flag and the low address, and query the out-core Cache to judge whether the prefetch request for the current address is executed;

[0046] The first generating module is configured to, when the prefetch request for the current address is executed, control the out-core Cache control component to directly generate the read response data of the current address;

[0047] The second generating module is configured to, when the prefetch request for the current address is not executed, control the out-core Cache control component to combine the read request for the current address to the prefetch request for the current address, and generate the read response data of the current address after receiving data from other cores or the main memory;

[0048] The prefetch request triggering module is configured to control the out-core Cache control component to form a next address based on the read response data of the current address and the low address, and trigger a prefetch request for the next address.

[0049] The prefetch start flag is set to two bits; when the prefetch start flag is "00", it indicates that the out-core Cache prefetch is not started; when the prefetch start flag is "10", it indicates that the out-core Cache read prefetch is started, the out-core Cache stores the latest copy of the corresponding address, and the internal Cache of other cores does not store the copy of the address or stores a shared read copy of the address; when the prefetch start flag is "11", it indicates that the out-core Cache write prefetch is started, and the out-core Cache stores the latest copy of the corresponding address, and the internal Cache of other cores does not store the copy of the address.

[0050] The memory virtualization address substitution efficiency improving device further comprises:

[0051] The prefetch request execution judging module is configured to, when the generation of the next address does not depend on the read response data of the current address, control the out-core Cache control component to query the out-core Cache to judge whether the prefetch request for the current address is executed.

[0052] a third generating module, configured to control the out-core cache control component to directly generate read response data of the current address when the prefetch request for the current address has been executed;

[0053] a fourth generating module, configured to control the out-core cache control component to combine the read request for the current address into the prefetch request for the current address when the prefetch request for the current address has not been executed, and generate the read response data of the current address after receiving data from other cores or the main memory.

[0054] when the current address is the first address, further comprising:

[0055] a second receiving judging module, configured to register a prefetch start flag and a low address carried by the memory access request for the current address after the out-core cache control component receives the memory access request for the current address, and query the out-core cache to determine whether the read request for the current address hits the out-core cache;

[0056] a fifth generating module, configured to control the out-core cache control component to directly generate the read response data of the current address and return the read response data to the core when the read request for the current address hits the out-core cache;

[0057] a sixth generating module, configured to control the out-core cache control component to read the current address when the read request for the current address does not hit the out-core cache, and parse the read response data from the data read from the current address and return the read response data to the core.

[0058] The technical scheme adopted by the present application to solve the technical problem is: providing an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the memory virtualization address substitution efficiency improving method.

[0059] The technical scheme adopted by the present application to solve the technical problem is: providing a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of the memory virtualization address substitution efficiency improving method.

[0060] Advantages

[0061] Compared with the prior art, the present application has the following advantages and positive effects: the present application makes full use of the address dependency relationship in the directory of each level of page table and the page table query process, and the out-of-core Cache commonly used in current high-performance processors, a small amount of control logic is added in the core and out of the core, the out-of-core Cache is prompted by the core to prefetch the address to be accessed in advance, the data is stored in the out-of-core Cache, the memory access delay of the subsequent address is shortened, the performance bottleneck caused by the address replacement buffer or the miss of the directory buffer of a certain level of page table is compensated, and the memory virtualization technology is better supported. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 is an overview of the memory virtualization design in the prior art;

[0063] Figure 2 is a GPA address replacement schematic diagram in the prior art;

[0064] Figure 3 is a GVA address replacement schematic diagram in the prior art;

[0065] Figure 4 is a memory virtualization address replacement efficiency improving method flow chart of the first embodiment of the present application. DETAILED DESCRIPTION

[0066] The present application will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present application and not used to limit the scope of the present application. In addition, it should be understood that after reading the content taught by the present application, those skilled in the art can make various modifications or changes to the present application, and these equivalent forms also fall within the scope of the appended claims of the present application.

[0067] The first embodiment of the present application relates to a memory virtualization address replacement efficiency improving method, which makes use of the fact that in the existing memory virtualization technology, when a guest virtual address (GVA) is replaced by a host physical address (HPA), except for addresses Addr1, Addr6, Addr11, Addr16 and Addr21, the other 19 memory access addresses have the feature of similar chain access, i.e. the data obtained by the previous memory access participates in the generation of the address of the subsequent memory access, and the generation method is fixed. When the core issues an access to the directory of page table or page table, the special prefetch start flag and other information participating in the generation of the prefetch address are carried to the out-of-core Cache control component.

[0068] The pre-fetch start flag in the embodiment can be set as 2 bits. When the pre-fetch start flag is 2'b00, it indicates that the out-core cache pre-fetch is not started. When the pre-fetch start flag is 2'b10, it indicates that the out-core cache read pre-fetch is started, and the out-core cache stores the latest copy of the corresponding address, and the other core internal caches do not store the copy of the address or store the shared read copy of the address. When the pre-fetch start flag is 2'b11, it indicates that the out-core cache write pre-fetch is started, and the out-core cache stores the latest copy of the corresponding address, and the other cores do not store the copy of the address.

[0069] The generation of the pre-fetch address only needs the core to carry the in-page offset address as a low-bit address to the out-core cache control component. For example, when the page granularity is 4 KB, the carried low-bit address only needs 12 bits; when the page granularity is 8 KB, the carried low-bit address only needs 13 bits.

[0070] As shown in FIG. 1, the memory virtualization address replacement efficiency improving method of the embodiment specifically includes the following steps. Figure 4

[0071] Step 1, the core analyzes the received last address read response data, forms a current address based on the analyzed data, and sends a memory access request for the current address; the memory access request carries a pre-fetch start flag and a low-bit address;

[0072] Step 2, after the out-core cache control component receives the memory access request for the current address, it determines whether the generation of the next address depends on the read response data of the current address according to the pre-fetch start flag;

[0073] Step 3, if the generation of the next address depends on the read response data of the current address, the out-core cache control component registers the pre-fetch start flag and the low-bit address, and queries the out-core cache to determine whether the pre-fetch request for the current address is executed;

[0074] Step 4, if the pre-fetch request for the current address is executed, the out-core cache control component directly generates the read response data of the current address;

[0075] Step 5, if the pre-fetch request for the current address is not executed, the out-core cache control component combines the read request for the current address to the pre-fetch request for the current address, and generates the read response data of the current address after receiving the data from other cores or the main memory;

[0076] Step 6, the out-core cache control component forms the next address based on the read response data of the current address and the low-bit address, and triggers the pre-fetch request for the next address.

[0077] ​It can be found that, when the out-of-core Cache control component receives the response data of the page table directory or page table access request, the data is directly parsed according to the agreed page table format, the next level page table directory or page table access address is generated, and a prefetch request for the address is triggered to prefetch the data into the out-of-core Cache in advance. After the core receives the response data of the page table directory or page table access request, the data is also parsed according to the agreed page table format, the next level page table directory or page table access address is generated, and the address is sent to the out-of-core Cache. During this period, the prefetch request for the next level page table directory or page table access address has already started to be executed, so when the read request for the next level page table directory or page table access address sent by the core is received, the prefetch request may have already been executed, and the data required by the read request has been loaded into the out-of-core Cache. Even if the prefetch request has not been executed, the read request for the same address can be combined into the prefetch request, and once the required data is loaded into the out-of-core Cache, a response can be returned to the core. As can be seen, prefetching the next level page table directory or page table access address that will be accessed definitely can always reduce the delay of actually reading the address, thereby accelerating the entire page table directory and page table query process.

[0078] In addition, when the core sends an access request for the address Addr24, if the access request triggering the current round of virtual-real address conversion is a read type, the prefetch start flag 2'b10 is carried, and if the access request triggering the current round of virtual-real address conversion is a write type, the prefetch start flag 2'b11 is carried. At the same time, the low address GVA[Page offset] is carried. After the out-of-core generates the read response data of the address Addr24 and returns to the core, the page number PTE_APTE is parsed according to the agreed page table format of software and hardware, and the host physical address HPA is formed by splicing the low address GVA[Page offset] carried, and a prefetch request for the address HPA is triggered. When the core receives the read response data of Addr24, the HPA is also formed according to the same agreement rule. Thus, the GVA is successfully converted to the HPA, and according to the original access request type, a read or write access request for the HPA is sent.

[0079] In the memory virtualization address conversion efficiency improvement method of the embodiment, the core can set a state machine to control, and special prefetch start flags and other information for generating a prefetch address need to be carried when sending read requests for the addresses Addr1, Addr2, Addr3, Addr4, Addr6, Addr7, Addr8, Addr9, Addr11, Addr12, Addr13, Addr14, Addr16, Addr17, Addr18, Addr19, Addr21, Addr22, Addr23, and Addr24.

[0080] For sending read request of read address Addr1, Addr6, Addr11, Addr16, Addr21, since the generation of these addresses is not dependent on the previous address, it can be regarded as the first address, therefore, the out-of-core cache control component, after receiving the memory access request of the first address, registers the prefetch start flag and low address carried by the memory access request of the first address, and queries the out-of-core cache to determine whether the read request of the first address hits the out-of-core cache; if it hits the out-of-core cache, the out-of-core cache control component directly generates the read response data of the first address and returns it to the core; if it does not hit the out-of-core cache, the out-of-core cache control component reads the current address from the data read out of the first address, and returns the read response data of the current address to the core. After completion, the next address is formed based on the read response data of the first address and the low address, triggering a prefetch request for the next address.

[0081] For sending read request of read address Addr5, Addr10, Addr15, Addr20, since the generation of the next address is not dependent on the read response data of the current address, when the core sends the memory access request of the address, it carries the prefetch start flag 2'b00. At this time, the out-of-core cache control component can know that the generation of the next address is not dependent on the current address, at this time the out-of-core cache control component queries the out-of-core cache to determine whether the prefetch request for the current address is completed; if the prefetch request for the current address is completed, the out-of-core cache control component directly generates the read response data of the current address; if the prefetch request for the current address is not completed, the out-of-core cache control component combines the read request of the current address to the prefetch request for the current address, and generates the read response data of the current address after receiving data from other cores or main memory, which does not generate a prefetch request.

[0082] The following takes the complete 24 steps of replacing a certain guest virtual address (GVA) with a host physical address (HPA) in memory virtualization technology as an example to further illustrate the detailed process of core guiding out-of-core cache prefetching. For convenience of description, the following symbols and expressions are agreed to have the following meanings:

[0083] (1) Square brackets represent taking a certain region of the address, such as: GPA[APGD Index] represents taking the APGD Index domain of the GPA address;

[0084] (2) The brace and comma together represent concatenating different addresses bit by bit, for example, assuming that the APGD Index field is 9 bits, then {GPA[APGD Index], 3'bo} represents concatenating GPA[APGD Index] with 3 bits of 0, which is equivalent to left shifting GPA[APGD Index] by 3 bits and padding 0.

[0085] In the embodiment, the page granularity is 8 KB, the Page offset and the APage offset are both 13 bits, the APGD Index field is 5 bits, and the other fields are all 10 bits. The client virtual address (GVA) is 53 bits in total, and the client physical address (GPA) and the host physical address (HPA) are both 48 bits.

[0086] Specifically, the base address of the first-level APT page table directory is APTP[47:13] = {0x0, 0x0, 0xA0, 0xFF} (the high address is 35 bits in total, which is represented as 5 / 10 / 10 / 10 bits of concatenation bit by bit here), that is, APTP[47:13] = 0x280FF.

[0087] The base address of the first-level GPT page table directory is PTBR[47:13] = {0x1, 0x2, 0x3, 0x4} (the high address is 35 bits in total, which is represented as 5 / 10 / 10 / 10 bits of concatenation bit by bit here), that is, PTBR[47:13] = 0x40200C04. Among them, PTBR[APGD Index] = 0x1, PTBR[APUD Index] = 0x2, PTBR[APMD Index] = 0x3, and PTBR[APTE Index] = 0x4.

[0088] The client virtual address is GVA[52:13] = {0x5, 0xA, 0xF, 0x14} (the high address is 40 bits in total, which is represented as 10 / 10 / 10 / 10 bits of concatenation bit by bit here), that is, GVA[52:13] = 0x140A03C14. Among them, GVA[PGD Index] = 0x5, GVA[PUD Index] = 0xA, GVA[PMD Index] = 0xF, and GVA[PTE Index] = 0x14. In addition, GVA[Page offset] = 0x0.

[0089] The detailed process of address conversion and core-guided out-of-cache prefetching is as follows:

[0090] 1) When the core sends a memory access request to address Addr1, it carries the prefetch enable flag 2'b10 and the low address {PTBR[APUD Index], 3'b0} = 0x10. When the off-core Cache control unit receives the memory access request to address Addr1, it registers the prefetch enable flag and the low address (0x10) carried by the request, and queries the off-core Cache. If a hit is found, it directly generates the read response data of address Addr1 and returns it to the core; if a miss is found, it reads the memory address 1 (Addr1), Addr1[47:0] = {APTP, PTBR[APGD Index], 3'b0} = 0x501FE008, and the data read from Addr1 is parsed to obtain PTBR_APUD_Base, which is returned to the core. In this embodiment, PTBR_APUD_Base[47:13] = {0x0, 0x0, 0xA1, 0x1} = 0x28401. The off-core Cache control unit splices PTBR_APUD_Base and the low address 0x10 carried by address Addr1 to form address Addr2, Addr2 = {PTBR_APUD_Base, PTBR[APUD Index], 3'b0} = 0x50802010, and triggers a prefetch request to address Addr2.

[0091] 2) the core receives the read response data of address Addr1, and parses the data according to the page table format agreed by software and hardware, splices to form address Addr2, and sends a memory access request for address Addr2, while carrying a prefetch start flag 2'b10 and low address {PTBR[APMD Index], 3b'0} = 0x18. When the cache control component outside the core receives the memory access request for address Addr2, it registers the prefetch start flag and low address {0x18} carried by the memory access request, and queries the cache outside the core. If the prefetch request for address Addr2 has been executed, the read request for address Addr2 hits the cache outside the core, and the read response data of address Addr2 can be directly generated. If the prefetch request for address Addr2 has not been executed, the read request for address Addr2 is merged into the prefetch request for Addr2, and when data from other cores or the main memory is received, the read response data of address Addr2 is generated, and the data read out from Addr2 is parsed to obtain PTBR_APMD_Base. In this embodiment, PTBR_APMD_Base[47:13] = {0x0, 0x0, 0xA2, 0x2} = 0x28802. The cache control component outside the core splices PTBR_APMD_Base and the low address 0x18 carried by address Addr2 to form address Addr3, Addr3 = {PTBR_APMD_Base, PTBR[APMD Index], 3'b0} = 0x51004018, and triggers a prefetch request for address Addr3.

[0092] 3) the core receives the read response data of address Addr2, and parses the data according to the page table format agreed by software and hardware, splices to form address Addr3, and sends a memory access request for address Addr3, while carrying a prefetch start flag 2'b10 and low address {PTBR[APTE Index], 3b'0} = 0x20. When the core-external cache control component receives the memory access request for address Addr3, it registers the prefetch start flag and low address (0x20) carried by the memory access request, and queries the core-external cache. If the prefetch request for address Addr3 has been executed, the read request for address Addr3 hits the core-external cache, and the read response data of address Addr3 can be directly generated. If the prefetch request for address Addr3 has not been executed, the read request for address Addr3 is merged into the prefetch request for Addr3, and when data from other cores or the main memory is received, the read response data of address Addr3 is generated, and the data read out from Addr3 is parsed to obtain PTBR_APTE_Base. In this embodiment, PTBR_APTE_Base[47:13] = {0x0, 0x0, 0xA3, 0x3} = 0x28C03. The core-external cache control component splices PTBR_APTE_Base and the low address 0x20 carried by address Addr3 to form address Addr4, Addr4 = {PTBR_APTE_Base, PTBR[APTE Index], 3'b0} = 0x51806020, and triggers a prefetch request for address Addr4.

[0093] 4) The core receives the read response data of address Addr3, and parses the data according to the page table format agreed by software and hardware, splices to form address Addr4, and sends a memory access request for address Addr4, while carrying a prefetch start flag 2'b10 and a low address {GVA[PGD Index], 3b'0} = 0x28. When the core-external cache control component receives the memory access request for address Addr4, it registers the prefetch start flag and the low address (0x28) carried by the memory access request for address Addr4, and queries the core-external cache. If the prefetch request for address Addr4 has been executed, the read request for address Addr4 hits the core-external cache, and the read response data of address Addr4 can be directly generated. If the prefetch request for address Addr4 has not been executed, the read request for address Addr4 is merged into the prefetch request for Addr4, and when data from other cores or the main memory is received, the read response data of address Addr4 is generated, and the data read out from Addr4 is parsed to obtain PTBR_APTE. In this embodiment, PTBR_APTE[47:13] = {0x0, 0x0, 0xA4, 0x4} = 0x29004. The core-external cache control component splices PTBR_APTE and the low address 0x28 carried by address Addr4 to form address Addr5, Addr5 = {PTBR_APTE, GVA[PGD Index], 3b'0} = 0x52008028, and triggers a prefetch request for address Addr5.

[0094] 5) The core receives the read response data of address Addr4, and parses the data according to the page table format agreed by software and hardware, splices to form address Addr5, and sends a memory access request for address Addr5. Since the generation of address Addr6 does not directly depend on address Addr5, when the core sends the memory access request for address Addr5, it carries the pre-fetch start flag 2'b00; the out-core Cache control component sees that the pre-fetch start flag is 2'b00, does not parse the read response data, and does not generate a corresponding pre-fetch request. When the out-core Cache control component receives the memory access request for address Addr5, it queries the out-core Cache. If the pre-fetch request for address Addr5 has been executed, the read request for address Addr5 hits the out-core Cache, and the read response data of address Addr5 can be directly generated; if the pre-fetch request for address Addr5 has not been executed, the read request for address Addr5 is merged into the pre-fetch request for Addr5, and when data from other cores or the main memory is received, the read response data of address Addr5 is generated, and the page number read out from Addr5 is parsed to be PUD_Base, which in this embodiment is PUD_Base[47:13]={0x6,0x7,0x8,0x9}=0x180702009. The out-core Cache control component cannot obtain address Addr6 at this time, and thus does not generate a pre-fetch request.

[0095] Since the processing flow for addresses Addr6-Addr10, Addr11-Addr15, Addr16-Addr20, and Addr21-Addr23 is similar to that for Addr1-Addr5, in the following steps of Addr6-Addr23, only the parsed data obtained by reading the memory addresses is briefly described.

[0096] 6) Read the memory address 6 (Addr6), Addr6={APTP, PUD_Base[APGD Index], 3'b0}=0x501FE030, and parse the data read out from Addr6 to obtain PUD_Base_APUD_Base. In this embodiment, PUD_Base_APUD_Base[47:13]={0x0,0x0,0xA1,0x6}=0x28406;

[0097] 7) read access memory address 7 (Addr7), Addr7 = {PUD_Base_APMD_Base, PUD_Base[APMD Index], 3'b0} = 0x5080C038, the data read from Addr7 is parsed to obtain PUD_Base_APMD_Base, in this embodiment, PUD_Base_APMD_Base[47:13] = {0x0, 0x0, 0xA7, 0x7} = 0x29C07;

[0098] 8) read access memory address 8 (Addr8), Addr8 = {PUD_Base_APMD_Base, PUD_Base[APMD Index], 3'b0} = 0x5380E040, the data read from Addr8 is parsed to obtain PUD_Base_APTE_Base, in this embodiment, PUD_Base_APTE_Base[47:13] = {0x0, 0x0, 0xA8, 0x8} = 0x2A008;

[0099] 9) read access memory address 9 (Addr9), Addr9 = {PUD_Base_APTE_Base, PUD_Base[APTE Index], 3'b0} = 0x54010048, the data read from Addr9 is parsed to obtain PUD_Base_APTE, in this embodiment, PUD_Base_APTE[47:13] = {0x0, 0x0, 0xA9, 0x9} = 0x2A409;

[0100] 10) read access memory address 10 (Addr10), Addr10 = {PUD_Base_APTE, GVA[PUD Index], 3'b0} = 0x54812050, the data read from Addr10 is parsed to obtain the page number, denoted as PMD_Base, in this embodiment, PMD_Base[47:13] = {0xB, 0xC, 0xD, 0xE} = 0x2C0C0340E;

[0101] 11) read access memory address 11 (Addr11), Addr11 = {APTP, PMD_Base[APGD Index], 3'b0} = 0x501FE058, the page number read from Addr11 is parsed to obtain PMD_Base_APUD_Base, in this embodiment, PMD_Base_APUD_Base[47:13] = {0x0, 0x0, 0xA1, 0xB} = 0x2840B;

[0102] 12) read access memory address 12 (Addr 12), Addr 12 = {PMD_Base_APUD_Base, PMD_Base[APUD Index], 3'b0} = 0x50816060, the data read from Addr 12 is parsed to get PMD_Base_APMD_Base, in this embodiment, PMD_Base_APMD_Base[47:13] = {0x0, 0x0, 0xAC, 0xC} = 0x2B00C;

[0103] 13) read access memory address 13 (Addr 13), Addr 13 = {PMD_Base_APMD_Base, PMD_Base[APMD Index], 3'b0} = 0x56018068, the data read from Addr 13 is parsed to get PMD_Base_APTE_Base, in this embodiment, PMD_Base_APTE_Base[47:13] = {0x0, 0x0, 0xAD, 0xD} = 0x2B40D;

[0104] 14) read access memory address 14 (Addr 14), Addr 14 = {PMD_Base_APTE_Base, PMD_Base[APTE Index], 3'b0} = 0x5681A070, the data read from Addr 14 is parsed to get PMD_Base_APTE, in this embodiment, PMD_Base_APTE[47:13] = {0x0, 0x0, 0xAE, 0xE} = 0x2B80E;

[0105] 15) read access memory address 15 (Addr 15), Addr 15 = {PMD_Base_APTE, GVA[PMD Index], 3'b0} = 0x5701C078, the data read from Addr 15 is parsed to get page number, denoted as PTE_Base, in this embodiment, PTE_Base[47:13] = {0x10, 0x11, 0x12, 0x13} = 0x401104813;

[0106] 16) read access memory address 16 (Addr 16), Addr 16 = {APTP, PTE_Base[APGD Index], 3'b0} = 0x501FE080, the data read from Addr 16 is parsed to get PTE_Base_APUD_Base, in this embodiment, PTE_Base_APUD_Base[47:13] = {0x0, 0x0, 0xA1, 0x10} = 0x28410;

[0107] 17) read access memory address 17 (Addr 17), Addr 17 = {PTE_Base_APUD_Base, PTE_Base[APUD Index], 3'b0} = 0x50820088, the data read from Addr 17 is parsed to obtain PTE_Base_APMD_Base, in this embodiment, PTE_Base_APMD_Base[47:13] = {0x0, 0x0, 0xB1, 0x11} = 0x2C411;

[0108] 18) read access memory address 18 (Addr 18), Addr 18 = {PTE_Base_APMD_Base, PTE_Base[APMD Index], 3'b0} = 0x58822090, the data read from Addr 18 is parsed to obtain PTE_Base_APTE_Base, in this embodiment, PTE_Base_APTE_Base[47:13] = {0x0, 0x0, 0xB2, 0x12} = 0x2C812;

[0109] 19) read access memory address 19 (Addr 19), Addr 19 = {PTE_Base_APTE_Base, PTE_Base[APTE Index], 3'b0} = 0x59024098, the data read from Addr 19 is parsed to obtain PTE_Base_APTE, in this embodiment, PTE_Base_APTE[47:13] = {0x0, 0x0, 0xB3, 0x13} = 0x2CC13;

[0110] 20) read access memory address 20 (Addr 20), Addr 20 = {PTE_Base_APTE, GVA[PTE Index], 3'b0} = 0x598260A0, the data read from Addr 20 is parsed to obtain page number, denoted as PTE, in this embodiment, PTE[47:13] = {0x15, 0x16, 0x17, 0x18} = 0x541605C18;

[0111] 21) read access memory address 21 (Addr 21), Addr 21 = {APTP, PTE[APGD Index], 3'b0} = 0x501FE0A8, the data read from Addr 21 is parsed to obtain PTE_APUD_Base, in this embodiment, PTE_APUD_Base[47:13] = {0x0, 0x0, 0xA1, 0x15} = 0x28415;

[0112] 22) read access memory address 22 (Addr22), Addr22 = {PTE_APUD_Base, PTE[APUD Index], 3'b0} = 0x5082A0B0, the data read from Addr22 is parsed to obtain PTE_APMD_Base, in this embodiment, PTE_APMD_Base[47:13] = {0x0, 0x0, 0xB6, 0x16} = 0x2D816;

[0113] 23) read access memory address 23 (Addr23), Addr23 = {PTE_APMD_Base, PTE[APMD Index], 3'b0} = 0x5B02C0B8, the data read from Addr23 is parsed to obtain PTE_APTE_Base, in this embodiment, PTE_APTE_Base[47:13] = {0x0, 0x0, 0xB7, 0x17} = 0x2DC17;

[0114] 24) the core receives the read response data of address Addr23, parses the data according to the page table format agreed by software and hardware, splices to form address Addr24, Addr24 = {PTE_APTE_Base, PTE[APTE Index], 3'b0} = 0x5B82E0C0, and sends a memory access request to address Addr24, while carrying a prefetch start flag and a low address GVA[Page offset] = 0x0. If the memory access request triggering the virtual-real address conversion in this round is of the read type, the prefetch start flag 2'b10 is carried, and if the memory access request triggering the virtual-real address conversion in this round is of the write type, the prefetch start flag 2'b11 is carried. When the out-core Cache control component receives the memory access request to address Addr24, it queries the out-core Cache. If it hits, it directly generates the read response data of address Addr24 and returns it to the core; if it misses, it reads access memory address 24 (Addr24), and the data read from Addr24 is parsed to obtain PTE_APTE and returned to the core. In this embodiment, PTE_APTE[47:13] = {0x0, 0x0, 0xB8, 0x18} = 0x2E018. The out-core Cache control component splices PTE_APTE and the low address 0x0 carried by address Addr24 to form the host machine physical address HPA, and HPA = {PTE_APTE, GVA[Page offset]} = 0x5C030000, and triggers a prefetch request to address HPA. When the core receives the read response data of Addr24, it also forms HPA according to the same agreed rules. At this point, GVA is finally converted to HPA, and according to the original memory access request type, a read or write access request to HPA is sent.

[0115] It can be found that the present application makes full use of the address dependency in the page table directory and the page table query process, and the out-of-core Cache commonly used in the current high-performance processor, and by adding a small amount of control logic in the core and the out-of-core, the out-of-core Cache is prompted by the core to prefetch the address to be accessed in advance, and the data is stored in the out-of-core Cache, so as to shorten the subsequent memory access delay of the address, make up for the performance bottleneck caused by the address replacement buffer or the out-of-target of the page table directory buffer, and better support the memory virtualization technology.

[0116] The second embodiment of the present application relates to a memory virtualization address replacement efficiency improving device, which comprises:

[0117] The analysis sending module is used for controlling the core to analyze the received previous address read response data, forming a current address based on the analyzed data, and sending a memory access request for the current address; the memory access request carries a prefetch start flag and a low address;

[0118] The first receiving judging module is used for controlling the out-of-core Cache control component to judge whether the generation of the next address depends on the read response data of the current address according to the prefetch start flag after receiving the memory access request for the current address;

[0119] The register judging module is used for controlling the out-of-core Cache control component to register the prefetch start flag and the low address and query the out-of-core Cache to judge whether the prefetch request for the current address is executed when the generation of the next address depends on the read response data of the current address;

[0120] The first generating module is used for controlling the out-of-core Cache control component to directly generate the read response data of the current address when the prefetch request for the current address is executed;

[0121] The second generating module is used for controlling the out-of-core Cache control component to combine the read request of the current address to the prefetch request for the current address, and generate the read response data of the current address after receiving the data of other cores or the main memory when the prefetch request for the current address is not executed;

[0122] The prefetch request triggering module is used for controlling the out-of-core Cache control component to form the next address based on the read response data of the current address and the low address, and trigger the prefetch request for the next address.

[0123] The pre-fetch start flag is set as 2 bits; when the pre-fetch start flag is "00", it indicates that the out-core Cache pre-fetch is not started; when the pre-fetch start flag is "10", it indicates that the out-core Cache read pre-fetch is started, the out-core Cache stores the latest copy of the corresponding address, and the other core internal Cache does not store the copy of the address or stores the shared read copy of the address; when the pre-fetch start flag is "11", it indicates that the out-core Cache write pre-fetch is started, the out-core Cache stores the latest copy of the corresponding address, and the other core does not store the copy of the address.

[0124] The memory virtualization address substitution efficiency improving device further comprises:

[0125] The pre-fetch request execution judging module is configured to control the out-core Cache control component to query the out-core Cache to judge whether the pre-fetch request for the current address is executed when the generation of the next address does not depend on the read response data of the current address.

[0126] The third generation module is configured to control the out-core Cache control component to directly generate the read response data of the current address when the pre-fetch request for the current address is executed.

[0127] The fourth generation module is configured to control the out-core Cache control component to combine the read request of the current address to the pre-fetch request for the current address when the pre-fetch request for the current address is not executed, and generate the read response data of the current address after receiving the data of the other core or the main memory.

[0128] When the current address is the first address, the device further comprises:

[0129] The second receiving judging module is configured to register the pre-fetch start flag and the low address carried by the memory access request of the current address when the out-core Cache control component receives the memory access request of the current address, and query the out-core Cache to judge whether the read request of the current address hits the out-core Cache.

[0130] The fifth generation module is configured to control the out-core Cache control component to directly generate the read response data of the current address and return to the core when the read request of the current address hits the out-core Cache.

[0131] The sixth generation module is configured to control the out-core Cache control component to read the current address when the read request of the current address does not hit the out-core Cache, and parse the read response data from the read data of the current address and return to the core.

[0132] The third embodiment of the present application relates to an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the memory virtualization address substitution efficiency improving method of the first embodiment when executing the computer program.

[0133] The fourth embodiment of the present application relates to a computer readable storage medium, which stores a computer program, wherein the computer program implements the steps of the memory virtualization address substitution efficiency improving method of the first embodiment when executed by a processor.

[0134] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk memory and optical memory, etc.) containing computer-usable program code.

[0135] The present application is described with reference to flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1 The means for implementing the functions specified in one or more flows and / or blocks.

[0136] These computer program instructions can also be stored in a computer-readable memory capable of causing the computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction method, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1 The means for implementing the functions specified in one or more flows and / or blocks.

[0137] These computer program instructions can also be loaded into a computer or other programmable data processing device, so that a series of operation steps are performed on the computer or other programmable data processing device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing device provide a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1steps of the functions specified in the block or blocks.

[0138] The above description is merely that of a specific implementation of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, and all such changes or replacements should be encompassed within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims.

Claims

1. A method for improving the efficiency of memory virtualization address swapping, characterized in that, Includes the following steps: The core parses the received read response data from the previous address, forms the current address based on the parsed data, and issues a memory access request for the current address; the memory access request carries a prefetch start flag and the low-order address. After receiving the memory access request for the current address, the off-core cache control unit determines whether the generation of the next address depends on the read response data of the current address based on the prefetch start flag. If the generation of the next address depends on the read response data of the current address, the off-core cache control unit will register the prefetch start flag and the low-order address, and query the off-core cache to determine whether the prefetch request for the current address has been completed. If the prefetch request for the current address has been completed, the off-core cache control unit directly generates the read response data for the current address; If the prefetch request for the current address has not been completed, the off-core cache control unit will merge the read request for the current address into the prefetch request for the current address, and generate the read response data for the current address after receiving data from other cores or main memory. The off-core cache control unit forms the next address based on the read response data of the current address and the lower-order address, and triggers a prefetch request for the next address.

2. The method for improving memory virtualization address substitution efficiency according to claim 1, characterized in that, The prefetch start flag is set to 2 bits; when the prefetch start flag is "00", it means that the off-core cache prefetch is not started; when the prefetch start flag is "10", it means that the off-core cache read prefetch is started. The off-core cache stores the latest copy of the corresponding address, and other core internal caches do not have a copy of the address, or have a shared read copy of the address. When the prefetch start flag is "11", it indicates that the off-core cache write prefetch is started. The off-core cache stores the latest copy of the corresponding address, and there is no copy of that address in other cores.

3. The method for improving memory virtualization address substitution efficiency according to claim 1, characterized in that, Also includes: If the generation of the next address does not depend on the read response data of the current address, the off-core cache control unit queries the off-core cache to determine whether the prefetch request for the current address has been completed. If the prefetch request for the current address has been completed, the off-core cache control unit directly generates the read response data for the current address; If the prefetch request for the current address has not been completed, the off-core cache control unit merges the read request for the current address into the prefetch request for the current address, and generates the read response data for the current address after receiving data from other cores or main memory.

4. The method for improving memory virtualization address substitution efficiency according to claim 1, characterized in that, When the current address is the first address, after receiving the memory access request for the current address, the external cache control unit registers the prefetch start flag and the low address carried by the memory access request for the current address, and queries the external cache to determine whether the read request for the current address hits the external cache. If the read request at the current address hits the off-core cache, the off-core cache control unit directly generates the read response data for the current address and returns it to the core. If the read request for the current address does not hit the off-core cache, the off-core cache control unit reads the current address, parses the read response data for the current address from the data read from the current address, and returns it to the core.

5. A device for improving the efficiency of memory virtualization address swapping, characterized in that, include: The parsing and sending module is used by the control core to parse the received read response data from the previous address, form the current address based on the parsed data, and issue a memory access request for the current address; the memory access request carries a prefetch start flag and the low-order address; The first receiving and determining module is used to control the off-core cache control unit after receiving the memory access request for the current address. Based on the prefetch start flag, determine whether the generation of the next address depends on the read response data of the current address; The register judgment module is used to control the off-core cache control unit to register the prefetch start flag and the low-order address when the generation of the next address depends on the read response data of the current address, and to query the off-core cache to determine whether the prefetch request for the current address has been completed. The first generation module is used to control the off-core cache control unit to directly generate the read response data for the current address when the prefetch request for the current address has been completed. The second generation module is used to control the off-core cache control unit to merge the read request of the current address into the prefetch request of the current address before the prefetch request of the current address is completed, and to generate the read response data of the current address after receiving data from other cores or main memory. The prefetch request triggering module is used to control the off-core cache control unit to form the next address based on the read response data of the current address and the low-order address, and trigger a prefetch request for the next address.

6. The memory virtualization address substitution efficiency improvement device according to claim 5, characterized in that, The prefetch start flag is set to 2 bits; when the prefetch start flag is "00", it means that the off-core cache prefetch is not started; when the prefetch start flag is "10", it means that the off-core cache read prefetch is started. The off-core cache stores the latest copy of the corresponding address, and other core internal caches do not have a copy of the address, or have a shared read copy of the address. When the prefetch start flag is "11", it indicates that the off-core cache write prefetch is started. The off-core cache stores the latest copy of the corresponding address, and there is no copy of that address in other cores.

7. The memory virtualization address substitution efficiency improvement device according to claim 5, characterized in that, Also includes: The prefetch request execution judgment module is used to control the off-core cache control unit to query the off-core cache to determine whether the prefetch request for the current address has been completed when the generation of the next address does not depend on the read response data of the current address. The third generation module is used to control the off-core cache control unit to directly generate the read response data for the current address when the prefetch request for the current address has been completed. The fourth generation module is used to control the off-core cache control unit to merge the read request for the current address into the prefetch request for the current address before the prefetch request for the current address is completed, and to generate the read response data for the current address after receiving data from other cores or main memory.

8. The memory virtualization address substitution efficiency improvement device according to claim 5, characterized in that, When the current address is the first address, it also includes: The second receiving and judging module is used to register the prefetch start flag and low address carried by the memory access request of the current address after the external cache control unit receives the memory access request of the current address, and query the external cache to judge whether the read request of the current address hits the external cache. The fifth generation module is used to control the external cache control unit to directly generate the read response data for the current address when the read request for the current address hits the external cache, and return it to the core. The sixth generation module is used to control the external cache control unit to read and access the current address when the read request at the current address fails to hit the external cache, and to parse the read response data from the data read from the current address and return it to the core.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the memory virtualization address substitution efficiency improvement method as described in any one of claims 1-4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the memory virtualization address substitution efficiency improvement method as described in any one of claims 1-4.

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