Base address register resource management method, electronic device and medium

Abstract

The present application relates to the field of computer technology and provides a base address register resource management method, electronic device and medium. In the face of the problem of insufficient reservation of base address register resources caused by hot plugging, in response to detecting that a quick peripheral device interconnection link is in place, a virtual device is created as a placeholder device to reserve base address register resources, and by limiting the zeroth base address register space contained in the virtual device to be the first base address register space and its size, and then limiting the virtual device to be deleted only after the configuration of the last base address register space is determined to be completed, the integrity of the entire process of basic input and output system scanning and allocating base address register resources is ensured, the processing flow of basic input and output systems of different manufacturers can be adapted, and the requirements of various types of quick peripheral device interconnection terminal devices of different manufacturers can be flexibly adapted to achieve a hot plugging function that is not perceived by the system and ensure system stability.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a base address register resource management method, electronic device and medium. Background Art

[0002] In application scenarios such as high-performance computers, data centers, and cloud computing, heterogeneous computing-related technologies are widely used. Therefore, a large number of different types of devices are connected to the bus through the bus standards defined by Peripheral Component Interconnect (PCI) and Peripheral Component Interconnect Express (PCI Express, PCIE). In this way, PCI devices and PCIE devices connected based on the PCI bus and PCIE bus can be hot-swapped in a no-surprise manner, that is, users are allowed to insert or remove devices without prior notification to the system software. In order to expand the device, the base address register (Base Address Register, BAR) resources of the PCIE end device mounted under the PCIE bridge device are configured through the PCIE bridge device (PCIE Bridge), so that the PCIE end device can perform data uplink and downlink operations and interrupt operations through the bus. The base address register resource management solution in the prior art is to scan the PCIE end device mounted under the PCIE bridge device and allocate BAR resources through the Basic Input Output System (BIOS) during system startup and scanning the PCIE topology stage. However, implementing hot-plugging without accidents means that during the system startup and PCIE topology scanning stage, when BIOS scans the PCIE bridge device, there may be no PCIE end device mounted under the PCIE bridge device, but then in the operating system stage, a new PCIE end device may be added to the PCIE bridge device through hot-plugging. This will result in BIOS not reserving BAR resources for the newly added PCIE end device, so it is necessary to modify the startup items of the operating system to allocate BAR resources again, which is not conducive to improving the overall system efficiency.

[0003] To this end, the present application provides a base address register resource management method, electronic device and medium, which are used to address the technical problem of insufficient reservation of base address register resources caused by hot plugging. Summary of the invention

[0004] In the first aspect, the present application provides a base address register resource management method. The base address register resource management method includes: in response to detecting that a quick peripheral device interconnect link associated with a quick peripheral device interconnect bridge device is in place, determining whether there is an idle quick peripheral device interconnect end device under each downstream port connected to the upstream port of the quick peripheral device interconnect bridge device, thereby determining the idle quick peripheral device interconnect end device set associated with the quick peripheral device interconnect bridge device; for each idle quick peripheral device interconnect end device in the idle quick peripheral device interconnect end device set, creating a virtual device that only contains the zeroth base address register space and mounting the virtual device to the downstream port corresponding to the idle quick peripheral device interconnect end device, wherein the zeroth base address register space is associated with the quick peripheral device interconnect bridge device. The first base address register space among multiple base address register spaces defined by the Express Peripheral Device Interconnection standard, and the size of the zeroth base address register space included in the virtual device is the size of the maximum base address register space among all types of Express Peripheral Device Interconnection end devices supported by the Express Peripheral Device Interconnection bridge device, and then, at least after determining that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, deleting the virtual device and configuring the Express Peripheral Device Interconnection bridge device to no longer mount the Express Peripheral Device Interconnection end device to the downstream port corresponding to the idle Express Peripheral Device Interconnection end device, and setting the reply of the transaction layer data packet message with the destination being the virtual device to request not supported.

[0005] Through the first aspect of the present application, in the face of the problem of insufficient reservation of base address register resources caused by hot plugging, in response to detecting that a quick peripheral device interconnect link is in place, a virtual device is created as a placeholder device to reserve base address register resources, and by limiting the zeroth base address register space included in the virtual device to be the first base address register space and its size, and then limiting the virtual device to be deleted only after the configuration of the last base address register space is completed, the integrity of the entire process of basic input and output system scanning and allocating base address register resources is ensured, the processing flow of basic input and output systems of different manufacturers can be adapted, and the requirements of various types of quick peripheral device interconnection end devices of different manufacturers can be flexibly adapted, so as to realize the hot plug function that the system is not aware of and ensure the stability of the system.

[0006] In a possible implementation of the first aspect of the present application, all types of quick peripheral device interconnect end devices supported by the quick peripheral device interconnect bridge device include quick peripheral device interconnect end devices of network device type, quick peripheral device interconnect end devices of storage device type, and quick peripheral device interconnect end devices of remote direct memory access device type.

[0007] In a possible implementation of the first aspect of the present application, the size of the maximum base address register space in all types of quick peripheral device interconnect terminal devices supported by the quick peripheral device interconnect bridge device is determined based on the maximum base address register resources required by all types of quick peripheral device interconnect terminal devices supported by the quick peripheral device interconnect bridge device.

[0008] In a possible implementation of the first aspect of the present application, when a configuration transaction layer data packet message corresponding to the last base address register space among the multiple base address register spaces associated with the virtual device is received, it is determined that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed.

[0009] In a possible implementation manner of the first aspect of the present application, a basic input / output system associated with the peripheral device interconnect express bridge device scans a plurality of base address register spaces associated with devices mounted under each downstream port connected to an upstream port of the peripheral device interconnect express bridge device during a peripheral device interconnect express topology scanning phase, and allocates base address register resources required by each of the plurality of base address register spaces one by one in an order from a first base address register space of the plurality of base address register spaces to a last base address register space of the plurality of base address register spaces.

[0010] In a possible implementation of the first aspect of the present application, the virtual device is created before the basic input / output system scans the downstream port corresponding to the idle quick peripheral device interconnect device, the basic input / output system allocates base address register resources according to the size of the zeroth base address register space contained in the virtual device, and the virtual device is deleted after the basic input / output system scans the last base address register space among multiple base address register spaces associated with the virtual device.

[0011] In a possible implementation manner of the first aspect of the present application, the base address register resource management method further includes: when there is no idle quick peripheral device interconnect terminal device under each downstream port connected to the upstream port of the quick peripheral device interconnect bridge device, the virtual device is not created.

[0012] In a possible implementation of the first aspect of the present application, the multiple base address register spaces defined by the Express Peripheral Device Interconnect standard are, in sequence, the zeroth base address register space, the first base address register space, the second base address register space, the third base address register space, the fourth base address register space, and the fifth base address register space, wherein the fifth base address register space is the last base address register space among the multiple base address register spaces defined by the Express Peripheral Device Interconnect standard.

[0013] In a possible implementation of the first aspect of the present application, when the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, the downstream port corresponding to the idle quick peripheral device interconnect end device is reserved with a base address register resource determined based on the size of the zeroth base address register space contained in the virtual device, so as to be used for hot plugging of devices under the downstream port corresponding to the idle quick peripheral device interconnect end device.

[0014] In a possible implementation of the first aspect of the present application, the virtual device is created before the basic input / output system associated with the peripheral device interconnect quick bridge device scans the peripheral device interconnect quick topology stage, and the virtual device is deleted at least before the operating system stage, and in the operating system stage, the operating system does not perceive the hot plugging of the device under the downstream port corresponding to the idle peripheral device interconnect quick end device.

[0015] In a possible implementation manner of the first aspect of the present application, the base address register resource management method further includes: in response to detecting that the peripheral device interconnect express link is not in place, deleting the virtual device under the downstream port corresponding to each idle peripheral device interconnect express end device in the idle peripheral device interconnect express end device set.

[0016] In a possible implementation of the first aspect of the present application, the peripheral device interconnect express bridge device and the peripheral device interconnect express terminal device mounted under the peripheral device interconnect express bridge device are both simulated and generated by a simulator on the embedded central processing unit side of the data processor.

[0017] In a possible implementation of the first aspect of the present application, when no peripheral device interconnect quick end device is mounted under any downstream port connected to the upstream port of the peripheral device interconnect quick bridge device, it is determined that there is an idle peripheral device interconnect quick end device under any downstream port.

[0018] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0019] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0020] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A flowchart of a base address register resource management method provided in an embodiment of the present application;

[0023] Figure 2 A reference provided for the embodiments of this application Figure 1 A schematic diagram of a PCIE bridge device of a base address register resource management method shown;

[0024] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0026] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0027] Figure 1A flow chart of a base address register resource management method provided in an embodiment of the present application. Figure 1 As shown, the base address register resource management method includes the following steps.

[0028] Step S101: In response to detecting that a peripheral device interconnect express link associated with a peripheral device interconnect express bridge device is in place, determining whether there is an idle peripheral device interconnect express end device under each downstream port connected to an upstream port of the peripheral device interconnect express bridge device, thereby determining an idle peripheral device interconnect express end device set associated with the peripheral device interconnect express bridge device.

[0029] Step S103: for each idle quick peripheral device interconnection end device in the idle quick peripheral device interconnection end device set, create a virtual device containing only a zeroth base address register space and mount the virtual device to the downstream port corresponding to the idle quick peripheral device interconnection end device, wherein the zeroth base address register space is the first base address register space among multiple base address register spaces defined by the quick peripheral device interconnection standard associated with the quick peripheral device interconnection bridge device, and the size of the zeroth base address register space contained in the virtual device is the size of the largest base address register space among all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device, and then, at least after determining that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, delete the virtual device and configure the quick peripheral device interconnection bridge device not to mount the quick peripheral device interconnection end device to the downstream port corresponding to the idle quick peripheral device interconnection end device, and set the reply of the transaction layer data packet message with the destination being the virtual device to request not supported.

[0030] Figure 1The base address register resource management method shown can be applied to application scenarios such as high-performance computers, data centers, and cloud computing, and can be applicable to various technologies such as heterogeneous computing, virtualization, and paravirtualization. By connecting a large number of different types of devices through the bus standards defined by the peripheral component interconnect (PCI) and the PCI Express (PCIE), it can meet the user's customized input and output needs, and support hot plugging in a no surprise manner, that is, allowing users to insert or remove devices without notifying the system software in advance. The host system goes through the system startup stage and the operating system stage after booting up. In the system startup stage, also called the scanning of the PCI Express topology stage, the basic input and output system (BIOS) is used to scan the PCI Express end device under the PCI Express bridge device and allocate the base address register (BAR) resources, so that the PCI Express end device can use the allocated base address register resources to perform data uplink and downlink transmission and interrupt operations through the bus. After the system startup phase, that is, the phase of scanning the Quick Peripheral Device Interconnect topology, the operating system starts and enters the operating system phase. The operating system uses the result of the basic input and output system scanning the Quick Peripheral Device Interconnect topology by default. Therefore, if hot plugging is implemented in an accident-free manner, if not enough base address register resources are allocated in the Quick Peripheral Device Interconnect topology scanning phase, or even no base address register resources are allocated at all, it may cause the Quick Peripheral Device Interconnect end device newly added through hot plugging to lack suitable base address register resources to run. For this reason, the operating system startup item is required to allocate base address register resources again, which is not conducive to improving the overall system efficiency. Considering that hot plugging is implemented in an accident-free manner to add, delete or replace devices, this means that in the operating system phase, it is difficult for the operating system and system software to predict in advance the needs of new devices that may be added through hot plugging, and different types of devices may have different base address register resource requirements, and the overall base address register resources that the host can control are limited. It is necessary to optimize the overall resource utilization while trying to avoid the problem of insufficient resource reservation. The following is combined with Figure 1 To elaborate, Figure 1 The base address register resource management method shown in the figure can realize the hot-swap function that the system is not aware of, and can flexibly adapt to the needs of various types of quick peripheral device interconnection end devices of different manufacturers, as well as flexibly adapt to the system startup process of various basic input and output systems of different manufacturers and the operating characteristics of the scanning quick peripheral device interconnection topology stage.

[0031] refer to Figure 1 , in step S101, in response to detecting that the quick peripheral device interconnection link associated with the quick peripheral device interconnection bridge device is in place, it is determined whether there is an idle quick peripheral device interconnection end device under each downlink port connected to the uplink port of the quick peripheral device interconnection bridge device, thereby determining the idle quick peripheral device interconnection end device set associated with the quick peripheral device interconnection bridge device. Here, the quick peripheral device interconnection link associated with the quick peripheral device interconnection bridge device means that the signal of the link in place on the host side is detected. During the normal startup process of the server, the quick peripheral device interconnection link, that is, the PCIE link, will be powered on, so the quick peripheral device interconnection link can be detected by detecting the power-on signal of the quick peripheral device interconnection link. When the quick peripheral device interconnection link is in place, the basic input and output system starts to work, that is, enters the system startup phase, also called the quick peripheral device interconnection topology scanning phase, and the quick peripheral device interconnection end devices under the quick peripheral device interconnection bridge device are scanned by the basic input and output system and the base address register resources are allocated. In step S101, in response to detecting that the quick peripheral device interconnection link associated with the quick peripheral device interconnection bridge device is in place, it is determined whether there is an idle quick peripheral device interconnection end device under each downstream port connected to the upstream port of the quick peripheral device interconnection bridge device, thereby determining the idle quick peripheral device interconnection end device set associated with the quick peripheral device interconnection bridge device. This means that when no quick peripheral device interconnection end device is mounted under a certain downstream port, there is an idle quick peripheral device interconnection end device under the downstream port, so the idle quick peripheral device interconnection end device set associated with the quick peripheral device interconnection bridge device can be determined. In other words, by traversing each downstream port connected to the upstream port of the quick peripheral device interconnection bridge device, it can be determined whether a quick peripheral device interconnection end device is mounted under each downstream port. If no quick peripheral device interconnection end device is mounted, it means that there is an idle quick peripheral device interconnection end device, so all idle quick peripheral device interconnection end devices can be recorded through the idle quick peripheral device interconnection end device set associated with the quick peripheral device interconnection bridge device for the subsequent process of reserving base address register resources. If no idle quick peripheral device interconnect end device is detected after traversing each downstream port connected to the upstream port of the quick peripheral device interconnect bridge device, it means that quick peripheral device interconnect end devices are mounted under all downstream ports, and there is no need to continue to execute the subsequent process of reserving base address register resources.

[0032] Continue to refer Figure 1In step S103, for each idle quick peripheral device interconnection end device in the idle quick peripheral device interconnection end device set, a virtual device containing only the zeroth base address register space is created and the virtual device is mounted to the downstream port corresponding to the idle quick peripheral device interconnection end device. The zeroth base address register space is the first base address register space among the multiple base address register spaces defined by the quick peripheral device interconnection standard associated with the quick peripheral device interconnection bridge device, and the size of the zeroth base address register space contained in the virtual device is the size of the maximum base address register space among all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device. Here, for each idle quick peripheral device interconnection end device, that is, for each downstream port that does not mount any quick peripheral device interconnection end device, a virtual device (dummy) is created, and the virtual device is used to occupy a place, that is, to reserve a base address register resource. It should be understood that the creation of the virtual device occurs before the quick peripheral device interconnection topology scanning stage, so the basic input and output system will scan the created virtual device and allocate a base address register resource to the virtual device. Here, because the virtual device only includes the zeroth base address register space, the other base address register spaces of the virtual device are empty, which means that when the basic input and output system scans the zeroth base address register space included in the virtual device, it will determine the size of the zeroth base address register space and allocate corresponding base address register resources. Therefore, the base address register resources allocated to the virtual device correspond to the size of the maximum base address register space in all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device. Here, because the zeroth base address register space is the first base address register space among the multiple base address register spaces defined by the quick peripheral device interconnection standard associated with the quick peripheral device interconnection bridge device, the basic input and output system first scans the first base address register space, that is, the zeroth base address register space when scanning the multiple base address register spaces, thus ensuring that the basic input and output system allocates base address register resources equivalent to the size of the zeroth base address register space to the created virtual device in the quick peripheral device interconnection topology scanning stage.

[0033] Continue to refer Figure 1In step S103, after creating the virtual device and mounting the virtual device to the downstream port corresponding to the idle quick peripheral device interconnect terminal device, then, at least after determining that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, delete the virtual device and configure the quick peripheral device interconnect bridge device to no longer mount the quick peripheral device interconnect terminal device to the downstream port corresponding to the idle quick peripheral device interconnect terminal device, and set the reply of the transaction layer packet (Transaction Layer Packet, TLP) message with the destination as the virtual device to request not supported. Here, at least after determining that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, this means that the basic input and output system has scanned the multiple base address register spaces associated with the virtual device, and has scanned the last base address register space and completed the configuration. Therefore, in combination with the above-mentioned zeroth base address register space being the first base address register space among the multiple base address register spaces defined by the quick peripheral device interconnection standard associated with the quick peripheral device interconnection bridge device, it is required here that after the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is determined to be completed, in this way, it is ensured that the basic input and output system scans all the multiple base address register spaces, which helps to flexibly adapt to the needs of various types of quick peripheral device interconnection end devices of different manufacturers, and also helps to adapt the system startup process of various basic input and output systems of different manufacturers and the operating characteristics of the quick peripheral device interconnection topology stage. For example, the PCIE protocol stipulates that each PCIE device can have 6 BAR spaces, numbered BAR0 to BAR5. Depending on the specific device requirements and the system startup process of the BIOS, some PCIE devices may occupy BAR0 and BAR1, and some PCIE devices may occupy BAR0 to BAR3. Therefore, the number of these six BAR spaces to be occupied by each PCIE device and the size of each BAR space can be set based on the PCIE device's own needs and user customization needs. Moreover, servers, hosts, systems, etc. from different manufacturers may use different BIOS (basic input and output system) system startup processes.Therefore, in order to ensure that the created virtual device can successfully reserve the designed base address register resources, by defining the zeroth base address register space as the first base address register space among the multiple base address register spaces defined by the quick peripheral device interconnection standard associated with the quick peripheral device interconnection bridge device, it is ensured that when the basic input and output system scans the virtual device, it must read the information of the first base address register space, that is, the zeroth base address register space (BAR0), thereby allocating the base address register resources equivalent to the size of the largest base address register space in all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device. Then, by limiting that at least the last base address register space among the multiple base address register spaces associated with the virtual device is configured, the virtual device is deleted, which means that after all the multiple base address register spaces (for example, from BAR0 to BAR5) are completed, it is determined that the configuration of the last base address register space (such as BAR5) is completed. In this way, the integrity of the entire process of scanning and allocating base address register resources by the basic input and output system is ensured, and the processing flow of basic input and output systems of different manufacturers can be adapted to avoid the abnormality of the basic input and output system.

[0034] Continue to refer Figure 1, at least after determining that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, delete the virtual device and configure the quick peripheral device interconnect bridge device to no longer mount the quick peripheral device interconnect terminal device to the downstream port corresponding to the idle quick peripheral device interconnect terminal device, and set the reply of the transaction layer data packet message with the destination as the virtual device to request not supported. By configuring the quick peripheral device interconnect bridge device to no longer mount the quick peripheral device interconnect terminal device to the downstream port corresponding to the idle quick peripheral device interconnect terminal device, it is ensured that the reserved base address register resources will not be occupied, which meets the design purpose, that is, to reserve the base address register resources equivalent to the size of the maximum base address register space in all types of quick peripheral device interconnect terminal devices supported by the quick peripheral device interconnect bridge device. Here, the size of the maximum base address register space in all types of quick peripheral device interconnect terminal devices supported by the quick peripheral device interconnect bridge device. For example, all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device include network device types, storage device types, and remote direct memory access device types. Assume that the size of the base address register space required by the quick peripheral device interconnection end device of the network device type is 16 gigabytes (KB), the size of the base address register space required by the quick peripheral device interconnection end device of the storage device type is 16KB, and the size of the base address register space required by the quick peripheral device interconnection end device of the remote direct memory access device type is 32KB. Then the size of the maximum base address register space among all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device is the size of the base address register space required by the quick peripheral device interconnection end device of the remote direct memory access device type, that is, 32KB. By limiting the size of the zeroth base address register space included in the virtual device to be the size of the maximum base address register space in all types of quick peripheral device interconnect terminal devices supported by the quick peripheral device interconnect bridge device, by creating a virtual device and allocating base address register resources to the created virtual device, it is achieved that under the downstream port corresponding to the idle quick peripheral device interconnect terminal device, base address register resources equivalent to the size of the maximum base address register space in all types of quick peripheral device interconnect terminal devices supported by the quick peripheral device interconnect bridge device are reserved.The advantage of such a design is that in the subsequent operating system stage, any type of quick peripheral device interconnection end device can be selected from all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device, for example, any one of the device types can be selected from the network device type, the storage device type and the remote direct memory access device type. In this way, the selected device or device type can be added to the downstream port corresponding to the idle quick peripheral device interconnection end device in a hot-plug manner, and it is ensured that the reserved base address register resources are sufficient to support the operation of the newly added device, thereby realizing hot-plugging without system perception, and can flexibly adapt to the needs of various types of quick peripheral device interconnection end devices of different manufacturers, as well as the system startup process of various basic input and output systems of different manufacturers and the operating characteristics of the scanning quick peripheral device interconnection topology stage.

[0035] Continue to refer Figure 1 , set the reply of the transaction layer data packet message with the destination as the virtual device as request not supported. This means that, on the basis of configuring the quick peripheral device interconnect bridge device to no longer mount the quick peripheral device interconnect end device to the downstream port corresponding to the idle quick peripheral device interconnect end device, for example, by configuring the status register of the quick peripheral device interconnect bridge device to indicate that no quick peripheral device interconnect end device is mounted thereunder, further, for all received transaction layer data packet messages with the destination as the virtual device, it is necessary to reply with an unsupported request (Unsupported Request) message, that is, set the reply to be unsupported request. The advantage of such a design is that, on the basis of using the virtual device as a placeholder device to reserve the base address register resources, in order to avoid the placeholder device affecting the normal data service, the TLP messages with the destination as the virtual device are all replied with unsupported request, thereby ensuring the stability of the system.

[0036] In conclusion, Figure 1 The base address register resource management method shown in the figure, in the face of the problem of insufficient reservation of base address register resources caused by hot plugging, in response to detecting that the quick peripheral device interconnection link is in place, creates a virtual device as a placeholder device to reserve base address register resources, by limiting the zeroth base address register space included in the virtual device to be the first base address register space and its size, and then by limiting the virtual device to be deleted only after the configuration of the last base address register space is determined to be completed, thereby ensuring the integrity of the entire process of basic input and output system scanning and allocating base address register resources, can adapt to the processing flow of basic input and output systems of different manufacturers, and can also flexibly adapt to the needs of various types of quick peripheral device interconnection end devices of different manufacturers, thereby realizing the hot plugging function that the system is not aware of and ensuring system stability.

[0037] Figure 2 A reference provided for the embodiments of this application Figure 1 Schematic diagram of a PCIE bridge device of a base address register resource management method shown in FIG. Figure 2 As shown, the root port 203 of the host machine 201 is connected to the uplink port 220 of the quick peripheral device interconnection bridge device 210, and is further connected to multiple downlink ports through the uplink port 220, namely, downlink port A 230, downlink port B 232, downlink port C 234, and downlink port D 236. Here, the quick peripheral device interconnection bridge device 210 is a reference Figure 1 The PCIE bridge device of the base address register resource management method shown. The mounting conditions of multiple downstream ports are different. Among them, a network device 240 is mounted under the downstream port A230. No quick peripheral device interconnection end device is mounted under the downstream port B232. Therefore, there is an idle quick peripheral device interconnection end device under the downstream port B232. For this reason, a virtual device A242 is created and mounted to the downstream port B232. A block device 244 (block, BLK) is mounted under the downstream port C234. Here, the block device 244 can be a storage device generated based on virtualization technology, such as a virtio-BLK device generated based on virtio technology. The block device 244 can be generated by an emulator on the embedded central processing unit (Embedded CPU, ECPU) side of the data processor (data processing unit, DPU), such as an operating system emulator (Quick EMUlator, QEMU). No quick peripheral device is mounted under the downstream port D236. Therefore, there is an idle quick peripheral device under the downstream port D236. Therefore, a virtual device B246 is created and mounted under the downstream port D236. It can be seen that, by combining various virtualization technologies and paravirtualization technologies, the quick peripheral device mounted under the quick peripheral device bridge device 210 can be a physical quick peripheral device, a simulated virtual device, or a reference device. Figure 1 The base address register resource management method shown is used to create virtual device A242 and virtual device B246 that are specifically used to reserve base address register resources for idle peripheral device interconnect express end devices.

[0038] Figure 2The PCIE bridge device shown, faced with the problem of insufficient reservation of base address register resources caused by hot plugging, creates virtual devices (virtual device A242 and virtual device B246) as placeholder devices to reserve base address register resources in response to detecting that the quick peripheral device interconnection link is in place, and limits the zeroth base address register space contained in the virtual device (virtual device A242 and virtual device B246) to be the first base address register space and its size, and then limits the virtual device (virtual device A242 and virtual device B246) to be deleted only after the configuration of the last base address register space is determined to be completed, thereby ensuring the integrity of the entire process of basic input and output system scanning and allocating base address register resources, can adapt to the processing flow of basic input and output systems of different manufacturers, and can also flexibly adapt to the needs of various types of quick peripheral device interconnection end devices of different manufacturers, thereby realizing the hot plugging function that the system does not perceive and ensuring system stability.

[0039] refer to Figure 1 and Figure 2 In a possible implementation, all types of quick peripheral device interconnection terminal devices supported by the quick peripheral device interconnection bridge device include quick peripheral device interconnection terminal devices of network device type, quick peripheral device interconnection terminal devices of storage device type, and quick peripheral device interconnection terminal devices of remote direct memory access device type. In this way, the requirements of various types of quick peripheral device interconnection terminal devices of different manufacturers can be flexibly adapted.

[0040] In a possible implementation manner, the size of the maximum base address register space in all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device is determined based on the maximum base address register resource required by all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device. In this way, by limiting the size of the zeroth base address register space included in the virtual device to be the size of the maximum base address register space in all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device, by creating a virtual device and allocating base address register resources to the created virtual device, it is achieved that under the downstream port corresponding to the idle quick peripheral device interconnection end device, a base address register resource equivalent to the size of the maximum base address register space in all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device is reserved. The advantage of such a design is that in the subsequent operating system stage, any type of quick peripheral device interconnection end device can be selected from all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device, for example, any one of the device types can be selected from the network device type, the storage device type and the remote direct memory access device type. In this way, the selected device or device type can be added to the downstream port corresponding to the idle quick peripheral device interconnection end device in a hot-plug manner, and it is ensured that the reserved base address register resources are sufficient to support the operation of the newly added device, thereby realizing hot-plugging without system perception, and can flexibly adapt to the needs of various types of quick peripheral device interconnection end devices of different manufacturers, as well as the system startup process of various basic input and output systems of different manufacturers and the operating characteristics of the scanning quick peripheral device interconnection topology stage.

[0041] In a possible implementation, when a configuration transaction layer data packet message corresponding to the last base address register space among the multiple base address register spaces associated with the virtual device is received, it is determined that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed. In this way, in order to ensure that the created virtual device can successfully reserve the designed base address register resources, by defining the zeroth base address register space as the first base address register space among the multiple base address register spaces defined by the quick peripheral device interconnect standard associated with the quick peripheral device interconnect bridge device, it is ensured that the basic input and output system must read the information of the first base address register space, that is, the zeroth base address register space (BAR0) when scanning the virtual device, thereby allocating the maximum base address register space equivalent to all types of quick peripheral device interconnect terminal devices supported by the quick peripheral device interconnect bridge device. The base address register resource of the size of the virtual device is then limited to be deleted only after the configuration of the last base address register space in the multiple base address register spaces associated with the virtual device is determined to be completed. This means that after all the multiple base address register spaces (for example, from BAR0 to BAR5) are completed, it is determined that the configuration of the last base address register space (such as BAR5) is completed. In this way, the integrity of the entire process of scanning and allocating base address register resources by the basic input and output system is ensured, and the processing flow of the basic input and output systems of different manufacturers can be adapted to avoid the abnormality of the basic input and output system.

[0042] In a possible implementation, the basic input / output system associated with the quick peripheral device interconnection bridge device scans the multiple base address register spaces associated with the devices mounted under each downlink port connected to the uplink port of the quick peripheral device interconnection bridge device in the quick peripheral device interconnection topology scanning stage, and allocates the base address register resources required by each of the multiple base address register spaces one by one in the order from the first base address register space of the multiple base address register spaces to the last base address register space of the multiple base address register spaces. The creation of the virtual device occurs before the quick peripheral device interconnection topology scanning stage, so the basic input / output system will scan the created virtual device and allocate base address register resources for the virtual device. Here, because the virtual device only contains the zeroth base address register space, the other base address register spaces of the virtual device are empty, which means that the basic input / output system will determine the size of the zeroth base address register space and allocate corresponding base address register resources when scanning the zeroth base address register space contained in the virtual device, so the base address register resources allocated to the virtual device correspond to the size of the maximum base address register space in all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device. Here, because the zeroth base address register space is the first base address register space among the multiple base address register spaces defined by the peripheral device interconnect express standard associated with the peripheral device interconnect express bridge device, the basic input and output system first scans the first base address register space, that is, the zeroth base address register space when scanning the multiple base address register spaces. In this way, it is ensured that the basic input and output system allocates base address register resources equivalent to the size of the zeroth base address register space to the created virtual device during the peripheral device interconnect express topology scanning stage.

[0043] In some embodiments, the virtual device is created before the basic input / output system scans the downstream port corresponding to the idle quick peripheral device interconnect terminal device, the basic input / output system allocates base address register resources according to the size of the zeroth base address register space contained in the virtual device, and the virtual device is deleted after the basic input / output system scans the last base address register space among the multiple base address register spaces associated with the virtual device. At least after determining that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, it means that the basic input / output system has scanned the multiple base address register spaces associated with the virtual device, and has scanned the last base address register space and completed the configuration. Therefore, in combination with the above-mentioned fact that the zeroth base address register space is the first base address register space among the multiple base address register spaces defined by the quick peripheral device interconnect standard associated with the quick peripheral device interconnect bridge device, it is required here that after the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is determined to be completed, it is ensured that the basic input and output system scans all the multiple base address register spaces, which helps to flexibly adapt to the needs of various types of quick peripheral device interconnection end devices of different manufacturers, and also helps to adapt the system startup process of various basic input and output systems of different manufacturers and the operating characteristics of the quick peripheral device interconnection topology scanning stage.

[0044] In a possible implementation, the base address register resource management method further includes: when there is no idle quick peripheral device interconnection end device under each downstream port connected to the upstream port of the quick peripheral device interconnection bridge device, the virtual device is not created. By traversing each downstream port connected to the upstream port of the quick peripheral device interconnection bridge device, it can be determined whether a quick peripheral device interconnection end device is mounted under each downstream port. If no quick peripheral device interconnection end device is mounted, it means that there is an idle quick peripheral device interconnection end device, so that all idle quick peripheral device interconnection end devices can be recorded through the idle quick peripheral device interconnection end device set associated with the quick peripheral device interconnection bridge device for the subsequent process of reserving base address register resources. If no idle quick peripheral device interconnection end device is detected after traversing each downstream port connected to the upstream port of the quick peripheral device interconnection bridge device, it means that all downstream ports are mounted with quick peripheral device interconnection end devices, and then there is no need to continue to execute the subsequent process of reserving base address register resources. In this way, it is helpful to adapt to complex and changeable application environments.

[0045] In a possible implementation, the multiple base address register spaces defined by the Peripheral Device Interconnect Express standard are the zeroth base address register space, the first base address register space, the second base address register space, the third base address register space, the fourth base address register space, and the fifth base address register space, wherein the fifth base address register space is the last base address register space among the multiple base address register spaces defined by the Peripheral Device Interconnect Express standard. This helps to flexibly adapt to the specific definition of the Peripheral Device Interconnect Express standard.

[0046] In a possible implementation, when the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, the downstream port corresponding to the idle quick peripheral device interconnection terminal device is reserved with a base address register resource determined based on the size of the zeroth base address register space contained in the virtual device, so as to be used for hot plugging of the device under the downstream port corresponding to the idle quick peripheral device interconnection terminal device. In this way, hot plugging is achieved without system perception, and the requirements of various types of quick peripheral device interconnection terminal devices of different manufacturers can be flexibly adapted, as well as the system startup process of various basic input and output systems of different manufacturers and the operation characteristics of the quick peripheral device interconnection topology scanning stage can be flexibly adapted.

[0047] In some embodiments, the virtual device is created before the BIOS associated with the PICI bridge device scans the PICI topology stage, and the virtual device is deleted at least before the operating system stage, and in the operating system stage, the operating system does not perceive the hot plugging of the device under the downstream port corresponding to the idle PICI terminal device. In this way, the hot plugging function that the system does not perceive is realized, and the requirements of various types of PICI terminal devices of different manufacturers can be flexibly adapted, as well as the system startup process of various BIOSes of different manufacturers and the operating characteristics of the PICI topology scanning stage.

[0048] In a possible implementation, the base address register resource management method further includes: in response to detecting that the quick peripheral device interconnect link is not in place, deleting the virtual device under the downstream port corresponding to each idle quick peripheral device interconnect end device in the idle quick peripheral device interconnect end device set. In this way, if it is detected that the quick peripheral device interconnect link, that is, the PCIE link, is not in place, for example, the host is shut down, then all virtual devices are deleted, which helps to avoid system abnormalities. Generally, the created virtual device should be deleted after it is determined that the configuration of the last base address register space in the multiple base address register spaces associated with the virtual device is completed. By additionally detecting that the quick peripheral device interconnect link is not in place, deleting all virtual devices helps to avoid system abnormalities and improves system stability.

[0049] In a possible implementation, the quick peripheral device interconnection bridge device and the quick peripheral device interconnection terminal device mounted under the quick peripheral device interconnection bridge device are simulated and generated by a simulator on the embedded central processing unit side of the data processor. It can be generated by a simulator on the embedded central processing unit (Embedded CPU, ECPU) side of the data processor (data processing unit, DPU), such as an operating system simulator (Quick EMUlator, QEMU). In this way, various virtualization, paravirtualization technologies and DPU-based systems can be adapted.

[0050] In a possible implementation, when no quick peripheral device interconnection end device is mounted under any downstream port connected to the upstream port of the quick peripheral device interconnection bridge device, it is determined that there is an idle quick peripheral device interconnection end device under any downstream port. In this way, by traversing each downstream port connected to the upstream port of the quick peripheral device interconnection bridge device, it can be determined whether a quick peripheral device interconnection end device is mounted under each downstream port. If no quick peripheral device interconnection end device is mounted, it means that there is an idle quick peripheral device interconnection end device, so that all idle quick peripheral device interconnection end devices can be recorded through the idle quick peripheral device interconnection end device set associated with the quick peripheral device interconnection bridge device for the subsequent process of reserving base address register resources. If no idle quick peripheral device interconnection end device is detected after traversing each downstream port connected to the upstream port of the quick peripheral device interconnection bridge device, it means that quick peripheral device interconnection end devices are mounted under all downstream ports, and then there is no need to continue to execute the subsequent process of reserving base address register resources.

[0051] Figure 33 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0052] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0053] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0054] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0055] The bus 340 may be a peripheral component interconnect express (PCIE) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0056] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0057] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0058] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0059] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0060] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A base address register resource management method, characterized in that: The base address register resource management method comprises: In response to detecting that a peripheral device interconnect express link associated with a peripheral device interconnect express bridge device is in place, determining whether there is an idle peripheral device interconnect express end device under each downstream port connected to an upstream port of the peripheral device interconnect express bridge device, thereby determining an idle peripheral device interconnect express end device set associated with the peripheral device interconnect express bridge device; For each idle quick peripheral device interconnection end device in the idle quick peripheral device interconnection end device set, a virtual device containing only a zeroth base address register space is created and the virtual device is mounted to the downstream port corresponding to the idle quick peripheral device interconnection end device, wherein the zeroth base address register space is the first base address register space among multiple base address register spaces defined by the quick peripheral device interconnection standard associated with the quick peripheral device interconnection bridge device, and the size of the zeroth base address register space contained in the virtual device is the size of the largest base address register space among all types of quick peripheral device interconnection end devices supported by the quick peripheral device interconnection bridge device, and then, at least after determining that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, the virtual device is deleted and the quick peripheral device interconnection bridge device is configured not to mount the quick peripheral device interconnection end device to the downstream port corresponding to the idle quick peripheral device interconnection end device, and the reply of the transaction layer data packet message with the destination as the virtual device is set to request not supported, The basic input / output system associated with the peripheral device interconnect quick bridge device scans a plurality of base address register spaces associated with devices mounted under each downstream port connected to the upstream port of the peripheral device interconnect quick bridge device during the peripheral device interconnect quick topology scanning stage, and allocates base address register resources required by each of the plurality of base address register spaces one by one in the order from the first base address register space of the plurality of base address register spaces to the last base address register space of the plurality of base address register spaces, The virtual device is created before the basic input / output system scans the downstream port corresponding to the idle quick peripheral device interconnect device, the basic input / output system allocates base address register resources according to the size of the zeroth base address register space contained in the virtual device, and the virtual device is deleted after the basic input / output system scans the last base address register space among multiple base address register spaces associated with the virtual device.

2. The base address register resource management method according to claim 1, characterized in that: All types of PDI terminal devices supported by the PDI bridge device include PDI terminal devices of network device type, PDI terminal devices of storage device type and PDI terminal devices of remote direct memory access device type.

3. The base address register resource management method according to claim 1, characterized in that: The size of the maximum base address register space in all types of peripheral interconnect express end devices supported by the peripheral interconnect express bridge device is determined based on the maximum base address register resource required by all types of peripheral interconnect express end devices supported by the peripheral interconnect express bridge device.

4. The base address register resource management method according to claim 1, characterized in that: When a configuration transaction layer data packet message corresponding to the last base address register space among the multiple base address register spaces associated with the virtual device is received, it is determined that the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed.

5. The base address register resource management method according to claim 1, characterized in that: The base address register resource management method further includes: When there is no idle peripheral device interconnect express terminal device under each downstream port connected to the upstream port of the peripheral device interconnect express bridge device, the virtual device is not created.

6. The base address register resource management method according to claim 1, characterized in that: The multiple base address register spaces defined by the Express Peripheral Device Interconnection Standard are, in sequence, the zeroth base address register space, the first base address register space, the second base address register space, the third base address register space, the fourth base address register space, and the fifth base address register space, wherein the fifth base address register space is the last base address register space among the multiple base address register spaces defined by the Express Peripheral Device Interconnection Standard.

7. The base address register resource management method according to claim 1, characterized in that: When the configuration of the last base address register space among the multiple base address register spaces associated with the virtual device is completed, the downstream port corresponding to the idle quick peripheral device interconnect end device is reserved with a base address register resource determined based on the size of the zeroth base address register space included in the virtual device, so as to be used for hot plugging of devices under the downstream port corresponding to the idle quick peripheral device interconnect end device.

8. The base address register resource management method according to claim 7, characterized in that: The virtual device is created before a basic input / output system associated with the peripheral device interconnect express bridge device scans a peripheral device interconnect express topology phase, and the virtual device is deleted at least before an operating system phase, and in the operating system phase, the operating system does not perceive hot plugging of a device under a downstream port corresponding to the idle peripheral device interconnect express end device.

9. The base address register resource management method according to claim 1, characterized in that: The base address register resource management method further includes: In response to detecting that the peripheral device interconnect express link is not in place, deleting the virtual device under the downstream port corresponding to each idle peripheral device interconnect express terminal device in the idle peripheral device interconnect express terminal device set.

10. The base address register resource management method according to claim 1, characterized in that: The quick peripheral device interconnection bridge device and the quick peripheral device interconnection terminal device mounted under the quick peripheral device interconnection bridge device are both simulated and generated by a simulator on the embedded central processing unit side of the data processor.

11. The base address register resource management method according to claim 1, characterized in that: When any downstream port to which the upstream port of the peripheral device interconnect quick bridge device is connected does not have any peripheral device interconnect quick terminal device mounted thereon, it is determined that there is an idle peripheral device interconnect quick terminal device under any downstream port.

12. An electronic device, characterized in that: The electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 11.

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