Asynchronous serial port communication protocol automatic identification method, system, device and medium

Abstract

The invention relates to the technical field of asynchronous serial port communication, in particular to an asynchronous serial port communication protocol automatic identification method, system and device and a medium, which can calculate the Baud rate of a protocol by using the time difference of pulses with different widths. The high dominant frequency logic circuit of the programmable logic is used for rapidly comparing data in the cache, the identification speed is high, and the method is very beneficial to field equipment arrangement and application occasions where protocols are not known. According to the invention, the baud rate can be calculated only by sampling 3-6 low pulse width counts, and the minimum unit value is calculated by using different length values of 3-6 pulses and differences among the 3-6 pulses; the Baud rate of a protocol is calculated by utilizing the time difference of pulses with different widths, then online data is cached into a programmable logic device according to the Baud rate, and the data in the cache are quickly compared by utilizing a high dominant frequency logic circuit of programmable logic, so that a data format is obtained, and finally protocol identification is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of asynchronous serial communication, and in particular to an automatic identification method, system, equipment and medium for an asynchronous serial communication protocol. Background Art

[0002] Asynchronous serial communication is widely used in electronic devices, usually for low-speed data transmission and device debugging. The general practice now is to predict the baud rate of the sender in advance and the receiver receives it fixedly; or to predict the baud rate required by the receiver in advance and the user sends at the specified baud rate, but this operation is cumbersome and has poor scalability, and it is easy to cause data anomalies due to negligence.

[0003] At present, there are some automatic serial communication protocol recognition technologies that can automatically identify the baud rate and data format of the protocol after receiving a certain amount of communication data, thereby omitting the setting process. The current serial communication protocol recognition technology can directly parse out the standard baud rate, achieve frame synchronization and speed matching, and completely restore real-time data. However, this method still has great limitations. Specifically, it sets a calculation threshold for parsing the baud rate, and starts the parsing process when the threshold is reached. This is prone to redundant calculations, or even erroneous calculations, which wastes calculation time and cannot guarantee the accuracy and precision of recognition. Summary of the invention

[0004] In view of this, the present invention provides an asynchronous serial communication protocol automatic identification method, system, device and medium, which can calculate the baud rate of the protocol by using the time difference of pulses of different widths; use the high main frequency logic circuit of programmable logic to quickly compare the data in the cache, and the identification speed is fast, which is very beneficial for on-site equipment layout and application scenarios where the protocol is unknown.

[0005] To achieve the above object, the present invention provides an automatic identification method for asynchronous serial communication protocol, which first obtains the baud rate and then identifies the data format; wherein the baud rate is obtained in the following manner:

[0006] By obtaining 3-6 low pulse signals with different widths, the duration of the single-bit signal can be obtained by calculation. The reciprocal of the single-bit duration is the baud rate. Specifically, obtain the three low pulse signal widths t1, t2 and t3 on the signal line. If the single-bit count can be calculated, output the result; otherwise, continue to obtain t4, t5 and t6 one by one. If the single-bit count can be calculated during the acquisition process, output the result and stop acquiring.

[0007] Among them, in the identification data format, according to the protocol standard, the start bit is a low level, followed by data, and finally a stop bit, and the length of the data in between is unknown; then use different data lengths to compare the existing data, and the length that meets the standard is the length currently used for communication, and confirm the word length output; otherwise, add 1 to the bit length and write it back to the FIFO again, and then process it according to the word length n to determine whether the start bit plus n bits is followed by a stop bit except for the head and tail. If so, confirm the word length output, otherwise continue to add 1 and repeat this process until the word length output is confirmed.

[0008] Among them, if there are several different word lengths, multiple comparisons are performed when using different data lengths to compare existing data. Each time the data is read out, it is written back to the FIFO for next use.

[0009] Among them, in the identification of data word length in UART serial communication, the online data is continuously temporarily stored in FIFO according to the baud rate, and the FIFO contains some redundant idle bits.

[0010] Wherein, a programmable logic device is used to obtain the low pulse signal width on the signal line.

[0011] The present invention also provides an asynchronous serial communication protocol automatic identification system, including a baud rate acquisition module circuit and a data format identification unit;

[0012] Among them, the baud rate acquisition unit is used to obtain the baud rate, and the baud rate acquisition module circuit is mainly composed of registers and divider IP. Multiple registers store multiple values, and the divider is used to identify each integer multiple ratio; the data format recognition unit is used to identify the data format, and the recognition is performed according to the protocol standard. The start bit is a low level, followed by data, and finally a stop bit. The data length in the middle is obtained through a word length recognition module; the baud rate acquisition module circuit is implemented by constructing a logic circuit through a programmable logic device FPGA.

[0013] Wherein, the word length recognition module includes a FIFO module, a sampling module, a read-write control module and a comparison module;

[0014] The FIFO module uses the internal storage resources of the FPGA and is implemented in the form of IP. The FIFO module stores the original data sampled by the UART bus;

[0015] The sampling module samples the data of the UART bus according to the BPS and writes it into the FIFO. The sampling is realized through a counter, which cycles back and forth from 0 to the BPS count and samples the data when the BPS count is 50%. It also includes another counter to eliminate the interference of redundant idle bits. After sampling 10 bits of high level continuously, the subsequent high level will not be written into the FIFO until the sampling is low level.

[0016] The read / write control module reads data from the FIFO and writes it back to the FIFO;

[0017] The function of the comparison module is to compare the long string data in the FIFO byte by byte according to the UART data format. If all of them match, the UART data format is obtained. During the comparison process, the data length is changed, and each length is compared with the entire FIFO storage data. If there is no match or the matching length is greater than one, the entire recognition process needs to be restarted.

[0018] The read-write control module and the comparison module include two counters, one for writing back to the FIFO and the other for single comparison of data. When reading out data, the corresponding length data is read out once according to the set word length and output to the comparison module; if the model comparison fails halfway, the remaining data will be read out continuously and written back.

[0019] Among them, in the comparison module, there is a parity bit identification unit, which is calculated according to the formula parity = data[0]^data[1]^…^data[n], where n is the assumed data length; if the data length matches, the parity check result is statistically calculated, all of which are 0 or 1, corresponding to even or odd check respectively. If this rule is not met, there is no check.

[0020] The present invention also provides an electronic device, which includes a processor and a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the asynchronous serial port communication protocol automatic identification method described in the present invention.

[0021] The present invention also provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the method for automatically identifying the asynchronous serial communication protocol of the present invention.

[0022] Beneficial effects:

[0023] 1. The method of the present invention can calculate the baud rate by sampling 3-6 low pulse width counts, and calculate the minimum unit value by using the different length values ​​of the 3-6 pulses themselves and the difference between them; calculate the baud rate of the protocol by using the time difference of pulses with different widths, and then cache the online data in the programmable logic device according to the baud rate, and use the high main frequency logic circuit of the programmable logic to quickly compare the data in the cache to obtain the data format, and finally complete the protocol recognition. The online asynchronous signal of the present invention can meet the requirements by sending 2-3 bytes, and the recognition speed is fast, which is very beneficial to the layout of field equipment and applications where the protocol is unknown.

[0024] 2. The method of the present invention utilizes programmable logic devices for rapid sampling to obtain a more accurate pulse time count; data format recognition only caches data once, and valid data is cached and used repeatedly until a matching data word length is found, and parity bit and stop bit information are obtained; when processing cached data, the programmable logic device utilizes a high main frequency circuit, and the processing only takes about 1-2 bit times. If the cached data is small and no result can be obtained, the next round of recognition can be quickly started.

[0025] 3. In the method of the present invention, there is no need to wait for the idle period of the UART bus, and it can be identified at any time period. There is no need to find the start bit, and there is no need to wait for a single-bit pulse signal.

[0026] 4. The system of the present invention is used to implement the method of the present invention. As long as 3-6 low pulse width counts are sampled, the baud rate can be calculated. The different length values ​​of the 3-6 pulses themselves and the difference between them are used to calculate the minimum unit value; the baud rate of the protocol is calculated using the time difference of pulses with different widths, and then the online data is cached in the programmable logic device according to the baud rate. The high main frequency logic circuit of the programmable logic is used to quickly compare the data in the cache, thereby obtaining the data format and finally completing the protocol recognition. The online asynchronous signal of the present invention can meet the requirements by sending 2-3 bytes, and the recognition speed is fast, which is very beneficial to the layout of field equipment and applications where the protocol is unknown.

[0027] 5. In the system of the present invention, programmable logic devices are used for fast sampling to obtain more accurate pulse time counting; data format recognition only caches data once, and valid data is cached and used repeatedly until a matching data word length is found, and parity bit and stop bit information are obtained; when processing cached data, the programmable logic device uses a high main frequency circuit, and the processing only takes 1-2 bit times. If the cached data is small and no result can be obtained, the next round of recognition can be quickly started.

[0028] 6. In the system of the present invention, there is no need to wait for the idle period of the UART bus, and it can be identified at any time period. There is no need to find the start bit, and there is no need to wait for a single-bit pulse signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a diagram of a typical data frame format for a UART serial port.

[0030] Figure 2 The figure is a schematic diagram of the baud rate processing flow in the embodiment of the method of the present invention.

[0031] Figure 3 Schematic diagram of three low pulses of the serial port signal in the method embodiment of the present invention.

[0032] Figure 4The figure is a schematic diagram of the internal logic of the word length recognition module of the present invention.

[0033] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0035] The electrical signals of asynchronous serial communication include RS232, RS485 and RS422. After electrical conversion, TTL signals are obtained, which are generally called UART serial ports. The typical data frame format is as follows: Figure 1 shown. Figure 1 The format of 8-bit data is shown in the figure, with 1 start bit and 1 stop bit. The protocol standard supports 5-8-bit data. Parity check is not supported for 5-bit data, and an additional parity check bit can be added for 8-bit data. The start bit is represented by a low level, and the stop bit is represented by a high level. It supports 1 bit, 1.5 bit and 2 bit lengths. When the communication bus is idle, it is represented by a high level, and there is no change in the stop bit.

[0036] The invention provides an automatic identification method for an asynchronous serial communication protocol, which first obtains the baud rate and then identifies the data format.

[0037] The acquisition of baud rate makes full use of the characteristic of UART serial communication that the width of all low pulse signals is an integer multiple of the width of single-bit signals. By acquiring 3-6 low pulse signals of different widths, the duration of single-bit signals can be calculated. The reciprocal of the single-bit duration is the baud rate. Specifically, the baud rate processing flow is as follows: Figure 2 As shown, the following steps are included: using a programmable logic device to obtain the three low pulse signal widths t1, t2 and t3 on the signal line, if a single-bit count can be calculated, then the result is output, otherwise t4, t5 and t6 are continuously obtained one by one; if a single-bit count can be calculated during the process of obtaining one by one, then the result is output and no further acquisition is continued. The key to the result is that the ratio of n counts of different widths is unique under limited conditions. Specific examples are as follows:

[0038] exist Figure 2In the example, the serial port signal input can get three low pulse signal width counts t1, t2 and t3. First, sort by size, we can get t3>t1>t2, and get two difference values ​​ta=t3-t1 and tb=t1-t2, and then sort again to get t3>t1>t2>ta=tb. Assuming that the value of tmin (i.e. the minimum value, here ta and tb) is 1 times the single bit, the ratio of t3, t1, t2, ta and tb is 4:3:2:1:1 or 8:6:4:2:2 (tmin is 2 times the single bit), and it cannot be 12:9:6:3:3, because the longest low level is 10 bits, which includes 1 start bit, 8 data bits and 1 check bit. According to the above counts t1, t2 and t3, it is impossible to obtain a single-bit count, so another count t4 is needed. t4 is not equal to one of t1, t2 and t3. If it is equal to ta, then the ratio of multiple pulse widths still has two possibilities, and no result can be obtained. At this time, t5 is obtained. If its value is 5 times of tmin, then the obtained ratio is 5:4:3:2:1:1:1, or it can be 10:8:6:4:2:2:2. No result can be obtained. This situation is the most extreme. Then t6 is obtained. The width is required to be different from t1-t5, so the obtained pulse width must be between 6-10 times the single bit. The obtained ratio is unique, and the single-bit width duration count can be obtained. In another case, if the ratio of the above t3, t1 and t2 is 8:5:3, there is no need to obtain t4 to obtain the single-bit duration. Under this ratio, the minimum tmin = t1-t2. If it is set to 1 times the single bit, then the ratio is 4:2.5:1.5:1.5:1, which does not meet the single-bit integer multiple requirement. If tmin is set to 2 times the single bit, 8:5:3:3:2 is obtained, which just meets the requirement. In the embodiment of the method of the present invention, the three low pulses of the serial port signal are as follows Figure 3 shown.

[0039] In the data format recognition, according to the protocol standard, the start bit is low level, followed by data, and finally the stop bit, and the length of the data in between is unknown; then use different data lengths to compare the existing data, and the one that meets the standard is the length currently used for communication, and confirm the word length output; otherwise, add 1 to the bit length and write it back to FIFO again, and then process it according to the word length n to determine whether the start bit plus n bits is followed by the stop bit except the head and tail. If so, confirm the word length output, otherwise continue to add 1 and repeat this process until the word length output is confirmed. Since there are several different word lengths, there may be multiple comparisons, and each time the data is read out, it needs to be written back to FIFO again for the next use. Specifically, in this embodiment, it is first assumed that n is the data length, so that a data length n is read out at one time, and it is checked whether the last bit is high. If it is high, the next data length is read out, and this cycle is repeated until the entire FIFO space is read. If all are in compliance, it is confirmed; if there is a non-compliance in the middle, the next length confirmation is started, that is, the data length is n+1, and then it is checked whether the last bit is high, and the same operation as the previous word length is taken; after multiple rounds of reading and comparison, the data length is obtained. In the identification of data word length in UART serial communication, the data on the line is continuously temporarily stored in FIFO (first-in, first-out memory in FPGA) according to the baud rate, and it will be used later. When reading the FIFO output data, it needs to be written back to the FIFO. This embodiment adopts head-tail loop reading and writing to achieve it. In order not to miss valid data, FIFO will contain some redundant idle bits.

[0040] The invention also provides an asynchronous serial communication protocol automatic identification system for identifying the method of the invention, comprising a baud rate acquisition module circuit and a data format identification unit.

[0041] The baud rate acquisition unit is used to obtain the baud rate, and all functions are mainly realized by constructing a logic circuit through a programmable logic device FPGA. In the baud rate acquisition, a higher frequency sampling clock is required to obtain the width counts of different low pulses. If the frequency is low, the sampling count is small, and the calculated error will be large, resulting in a low accuracy rate of the result. The system of the present invention mainly constitutes a baud rate acquisition module circuit with registers and a divider IP. Multiple registers store multiple values, and the divider is used to identify each integer multiple ratio. According to the baud rate acquisition principle in the method, tmin is used as a divisor, and the other several tn (referring to the other several pulse width counts) are used as dividends. The divider is used to obtain several quotients, thereby obtaining a ratio relationship. In fact, tmin can only be 1, 2 or 3 times the single-bit count, and the remainder generated by the division operation can only be 0, 1 / 2, 1 / 3 and 2 / 3. In actual operation, an integer ratio is obtained accordingly.

[0042] The data format recognition unit is used to identify the data format. It is identified according to the protocol standard. The start bit is low level, followed by data, and finally the stop bit. The data length in between is obtained through the word length recognition module. The functional block diagram of the word length recognition module is as follows Figure 4 As shown, it includes a FIFO module, a sampling module, a read-write control module and a comparison module.

[0043] The FIFO module uses the internal storage resources of the FPGA and is implemented in the form of IP. The FIFO module mainly stores the original data sampled by the UART bus. Its independent read and write ports and first-in-first-out method are particularly suitable for serial data processing.

[0044] The main function of the sampling module is to sample the data of the UART bus according to the BPS and write it into the FIFO. The sampling is mainly realized by a counter, which cycles back and forth from 0 to the BPS count and samples the data at 50% of the BPS count. In addition, a counter is needed to eliminate the interference of extra idle bits (due to the long waiting time between asynchronous transmission bytes), so after sampling 10 bits of high level continuously, the subsequent high level will not be written into the FIFO until the sampling is low level to resume writing.

[0045] The main function of the read-write control module is to read data from the FIFO and then write it back to the FIFO. The purpose of writing back is that if the data is to be used multiple times, it must be intact and there must be no shift at the head or tail.

[0046] The function of the comparison module is to compare the long string of data in the FIFO byte by byte according to the UART data format. If all of them match, the UART data format is obtained. During the comparison process, the data length needs to be changed, and each length is compared with the entire FIFO storage data. If there is no match or the length of the match is greater than one, the entire recognition process needs to be restarted.

[0047] In the comparison module, there is a parity bit identification unit, which is calculated according to the formula parity = data[0]^data[1]^…^data[n], where n is the assumed data length. If the data length matches, the parity check result is counted, all 0 or 1, corresponding to even or odd check respectively. If this rule is not met, there is no check.

[0048] The read-write control module and the comparison module require two counters, one for writing back to the FIFO and the other for single comparison of data. When reading out data, the corresponding length data is read out once according to the set word length and output to the comparison module; if the model comparison fails halfway, then only the remaining data needs to be read out and written back continuously.

[0049] Furthermore, there may be redundant high levels between two compared word lengths. This is because the sampling module performs multiple sampling in order not to lose actual data. During the comparison, the redundant data needs to be discarded.

[0050] The embodiment of the present application also provides an electronic device, Figure 5 The structure of the electronic device provided by the embodiment of the present invention is shown. For example, the electronic device 50 may include a processor 51, a memory 52 and a transmission device 53. The processor 51 is used to execute the asynchronous serial communication protocol automatic identification method mentioned in the above embodiment, wherein the processor and the memory may be connected by a bus or other means, taking the bus connection as an example. The transmission device may be connected to the processor and the memory by wire or wirelessly. The memory, as a non-transient computer-readable storage medium, may be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the asynchronous serial communication protocol automatic identification method in the embodiment of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the asynchronous serial communication protocol automatic identification method in the above method embodiment is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The one or more modules are stored in the memory, and when executed by the processor, the method for automatically identifying the asynchronous serial communication protocol in the embodiment is executed.

[0051] As another aspect, the present application also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the device described in the above embodiment; or a computer-readable storage medium that exists independently and is not assembled into a device. The computer-readable storage medium may be a tangible storage medium, such as a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium known in the technical field. The computer-readable storage medium stores one or more programs, and the programs are used by one or more processors to execute the asynchronous serial communication protocol automatic identification method described in the present application.

[0052] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for automatically identifying an asynchronous serial communication protocol, characterized in that: First obtain the baud rate, then identify the data format; the method for obtaining the baud rate is: By obtaining 3-6 low pulse signals with different widths, the duration of the single-bit signal can be obtained by calculation. The reciprocal of the single-bit duration is the baud rate. Specifically, obtain the three low pulse signal widths t1, t2 and t3 on the signal line. If the single-bit count can be calculated, output the result; otherwise, continue to obtain t4, t5 and t6 one by one. If the single-bit count can be calculated during the acquisition process, output the result and stop acquiring.

2. The method according to claim 1, characterized in that ,In the identification data format, according to the protocol standard, the start bit is a low level, followed by data, and finally a stop bit, and the length of the data in between is unknown; then use different data lengths to compare the existing data, and the one that meets the standard is the length currently used for communication, and confirm the word length output; otherwise, add 1 to the bit length and write it back to the FIFO again, and then process it according to the word length n to determine whether the start bit plus n bits is followed by the stop bit except for the head and tail. If so, confirm the word length output, otherwise continue to add 1 and repeat this process until the word length output is confirmed.

3. The method according to claim 2, characterized in that ,If there are several different word lengths, multiple comparisons are performed when using different data lengths to compare the existing data. Each time the data is read out, it is written back to the FIFO for the next use.

4. The method according to claim 3, characterized in that In the identification of data word length in UART serial communication, the data on the line is continuously temporarily stored in FIFO according to the baud rate. The FIFO contains some redundant idle bits.

5. The method according to any one of claims 1 to 4, characterized in that: The programmable logic device is used to obtain the low pulse signal width on the signal line.

6. An automatic identification system for asynchronous serial communication protocols, characterized in that: It includes a baud rate acquisition module circuit and a data format identification unit; Among them, the baud rate acquisition unit is used to obtain the baud rate, and the baud rate acquisition module circuit is mainly composed of registers and divider IP. Multiple registers store multiple values, and the divider is used to identify each integer multiple ratio; the data format recognition unit is used to identify the data format, and the recognition is performed according to the protocol standard. The start bit is a low level, followed by data, and finally a stop bit. The data length in the middle is obtained through a word length recognition module; the baud rate acquisition module circuit is implemented by constructing a logic circuit through a programmable logic device FPGA.

7. The system according to claim 6, characterized in that The word length recognition module includes a FIFO module, a sampling module, a read-write control module and a comparison module; The FIFO module uses the internal storage resources of the FPGA and is implemented in the form of IP. The FIFO module stores the original data sampled by the UART bus; The sampling module samples the data of the UART bus according to the BPS and writes it into the FIFO. The sampling is realized through a counter, which cycles back and forth from 0 to the BPS count and samples the data when the BPS count is 50%. It also includes another counter to eliminate the interference of redundant idle bits. After sampling 10 bits of high level continuously, the subsequent high level will not be written into the FIFO until the sampling is low level. The read / write control module reads data from the FIFO and writes it back to the FIFO; The function of the comparison module is to compare the long string data in the FIFO byte by byte according to the UART data format. If all of them match, the UART data format is obtained. During the comparison process, the data length is changed, and each length is compared with the entire FIFO storage data. If there is no match or the matching length is greater than one, the entire recognition process needs to be restarted. The read-write control module and the comparison module include two counters, one for writing back to the FIFO and the other for single comparison of data. When reading out data, the corresponding length data is read out once according to the set word length and output to the comparison module; if the model comparison fails halfway, the remaining data will be read out continuously and written back.

8. The system according to claim 6 or 7, characterized in that In the comparison module, there is a parity bit identification unit, which is calculated according to the formula parity = data[0]^data[1]^…^data[n], where n is the assumed data length. If the data length matches, the parity check result is statistically calculated, which is all 0 or 1, corresponding to even or odd check respectively. If this rule is not met, there is no check.

9. An electronic device, characterized in that: The electronic device includes a processor and a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the automatic identification method of the asynchronous serial communication protocol described in any one of claims 1-5 above.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and the computer program is used to execute the method for automatically identifying the asynchronous serial communication protocol as described in any one of claims 1 to 5.

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