Chip operation reliability determination method, device, computer equipment, readable storage medium and program product

Abstract

The present application relates to a method, apparatus, computer equipment, computer-readable storage medium, and computer program product for determining chip operational reliability, and relates to the technical field of chip reliability operational analysis, which can improve the accuracy of chip operational reliability analysis results. The method comprises: obtaining historical chip operational data, performing feature extraction on the historical chip operational data, and obtaining a first chip feature reflecting the operational status and chip performance of the chip; obtaining real-time operational data of the chip, performing feature cross-talk between the first chip feature and the real-time operational data of the chip, and obtaining a second chip feature reflecting the comprehensive operational performance of the chip; using the second chip feature to train a machine learning model, and obtaining a trained operational reliability prediction model corresponding to the chip when a training end condition is met; and obtaining a chip operational reliability prediction result of the chip based on the trained operational reliability prediction model.

Description

Technical Field

[0001] The present application relates to the technical field of chip reliability operation analysis, and in particular to a chip operation reliability determination method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] With the rapid development of electronic technology, chips, as core components of electronic devices, are crucial to the performance and reliability of the entire system. Therefore, ensuring stable operation of chips in complex and changing working environments has become a key issue in chip design and manufacturing.

[0003] Among related technologies, statistical reliability analysis techniques are used to analyze chip operational reliability. These techniques measure and statistically analyze a large number of chip samples, establish probability distribution models for process parameters, and predict chip reliability performance under varying process variations. Artificial intelligence and machine learning techniques also help identify potential reliability problem patterns by studying large amounts of chip reliability data, providing valuable reference and predictions for designers.

[0004] However, the application of statistical reliability analysis technology, artificial intelligence, and machine learning technology in chip reliability analysis has improved the accuracy and efficiency of prediction to a certain extent. However, due to limited generalization capabilities, the established prediction models are often only applicable to specific chip types or process conditions. For new chips or process variations, the model's predictive ability is affected and it cannot effectively predict the chip's operational reliability. Summary of the Invention

[0005] Based on this, it is necessary to provide a chip operation reliability determination method, device, computer equipment, computer-readable storage medium and computer program product to address the above technical problems.

[0006] In a first aspect, the present application provides a method for determining chip operation reliability, comprising:

[0007] Acquiring historical operating data of a chip, performing feature extraction on the historical operating data of the chip, and obtaining a first chip feature reflecting an operating state and chip performance of the chip;

[0008] Acquire real-time operating data of the chip, perform feature cross-correlation on the first chip feature and the real-time operating data of the chip, and obtain a second chip feature reflecting the comprehensive operating performance of the chip;

[0009] Performing model training on a machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0010] A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

[0011] In one embodiment, extracting features from the historical operating data of the chip to obtain a first chip feature reflecting the operating state and chip performance of the chip includes:

[0012] Processing the historical operation data of the chip according to a preset data preprocessing method to obtain processed historical operation data, wherein the data preprocessing method includes at least one of outlier filtering, missing value supplementation, data denoising, and data formatting;

[0013] Determining performance parameters reflecting the processing speed, power consumption, and temperature of the chip from the processed historical operation data, and determining resource occupancy parameters of the chip from the processed historical operation data;

[0014] The performance parameters and the resource occupancy parameters are calculated and quantified to obtain a first chip characteristic reflecting the average processing speed, maximum power consumption, temperature fluctuation range, and resource utilization of the chip.

[0015] In one embodiment, performing feature cross-talk between the first chip feature and the real-time operating data of the chip to obtain a second chip feature reflecting the comprehensive operating performance of the chip includes:

[0016] Determining target potential correlation features related to the first chip feature from the real-time operation data of the chip, and performing cluster analysis based on the target potential correlation features to obtain target correlation features;

[0017] Combining the obtained target-related features to obtain a corresponding first feature set, and combining the first chip features to obtain a corresponding second feature set;

[0018] Traversing each element in the first feature set, during the traversal process, multiplying the currently traversed element with each element in the second feature set, and performing a weighted summation on the obtained multiplication results to obtain a combined feature corresponding to the currently traversed element; wherein each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model;

[0019] The combined feature corresponding to each element in the first feature set is determined as a second chip feature reflecting the comprehensive operating performance of the chip.

[0020] In one embodiment, determining a target potential associated feature related to the first chip feature from the real-time operation data of the chip includes:

[0021] Determining potential correlation indicators from a plurality of data indicators corresponding to the real-time operation data of the chip based on a principal component analysis method;

[0022] For each of the potential correlation indicators, calculating a correlation coefficient between the potential correlation indicator and a feature indicator corresponding to the first chip feature;

[0023] According to the magnitude of the coefficients of the correlation coefficients, the potential correlation indicators are sorted in descending order, and the first K potential correlation indicators are used as target potential correlation indicators; K is a positive integer greater than or equal to 1;

[0024] The real-time operation data under the target potential correlation index is obtained from the real-time operation data of the chip as the target potential correlation feature.

[0025] In one embodiment, performing cluster analysis based on the target potential association features to obtain target association features includes:

[0026] Determine a target data set consisting of all target potential correlation features, wherein each data point in the target data set corresponds to one of the target potential correlation features;

[0027] Based on the data distribution characteristics of the target data set, M data points are selected from the target data set as initial cluster centers; M is a positive integer greater than or equal to 2;

[0028] Clustering the target data set based on the initial cluster centers to obtain a plurality of clusters, and determining a cluster representative feature corresponding to each of the clusters;

[0029] A plurality of target-related features are obtained according to the cluster representative features of each of the plurality of clusters.

[0030] In one embodiment, the performing model training on the machine learning model using the second chip feature includes:

[0031] Obtaining an operation reliability label of the chip under the real-time operation data; the operation reliability label indicates the chip operation reliability when the chip has the real-time operation data;

[0032] Inputting the second chip feature into the machine learning model for forward propagation to obtain a predicted output of the model;

[0033] Calculating a loss function value based on a prediction error between the prediction output and the operational reliability label;

[0034] Executing a back propagation algorithm based on the loss function value to determine the gradient of the model parameters of the machine learning model;

[0035] Estimate the mean of the gradient by an exponentially weighted moving average to obtain the first-order moment estimate, and estimate the mean of the square of the gradient by an exponentially weighted moving average to obtain the second-order moment estimate;

[0036] According to the adaptive bias correction and momentum decay factor adjustment, the first-order moment estimation and the second-order moment estimation are bias corrected, and in combination with the global learning rate, the update amount of each model parameter is calculated, and the model parameters of the machine learning model are updated;

[0037] Return to execute inputting the second chip feature into the machine learning model for forward propagation, obtain the predicted output of the model, iteratively adjust the model parameters of the machine learning model until the training end condition is met, and obtain a trained machine learning model.

[0038] In a second aspect, the present application further provides a device for determining chip operation reliability, comprising:

[0039] a historical feature extraction module, configured to obtain historical operating data of a chip, perform feature extraction on the historical operating data of the chip, and obtain a first chip feature reflecting the operating state and chip performance of the chip;

[0040] a feature crossover module, configured to obtain real-time operating data of the chip, perform feature crossover on the first chip feature and the real-time operating data of the chip, and obtain a second chip feature reflecting the comprehensive operating performance of the chip;

[0041] A model training module, configured to perform model training on a machine learning model using the second chip characteristics, and obtain a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0042] The model prediction module is used to obtain the chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

[0043] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0044] Acquiring historical operating data of a chip, performing feature extraction on the historical operating data of the chip, and obtaining a first chip feature reflecting an operating state and chip performance of the chip;

[0045] Acquire real-time operating data of the chip, perform feature cross-correlation on the first chip feature and the real-time operating data of the chip, and obtain a second chip feature reflecting the comprehensive operating performance of the chip;

[0046] Performing model training on a machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0047] A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

[0048] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0049] Acquiring historical operating data of a chip, performing feature extraction on the historical operating data of the chip, and obtaining a first chip feature reflecting an operating state and chip performance of the chip;

[0050] Acquire real-time operating data of the chip, perform feature cross-correlation on the first chip feature and the real-time operating data of the chip, and obtain a second chip feature reflecting the comprehensive operating performance of the chip;

[0051] Performing model training on a machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0052] A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

[0053] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the following steps:

[0054] Acquiring historical operating data of a chip, performing feature extraction on the historical operating data of the chip, and obtaining a first chip feature reflecting an operating state and chip performance of the chip;

[0055] Acquire real-time operating data of the chip, perform feature cross-correlation on the first chip feature and the real-time operating data of the chip, and obtain a second chip feature reflecting the comprehensive operating performance of the chip;

[0056] Performing model training on a machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0057] A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

[0058] The above-mentioned chip operation reliability determination method, apparatus, computer device, computer-readable storage medium, and computer program product can obtain historical operation data of the chip, perform feature extraction on the historical operation data of the chip, and obtain a first chip feature reflecting the operation status and chip performance of the chip; obtain real-time operation data of the chip, perform feature cross-reference on the first chip feature with the real-time operation data of the chip, and obtain a second chip feature reflecting the comprehensive operation performance of the chip; then use the second chip feature to train a machine learning model, and obtain a trained operation reliability prediction model corresponding to the chip when the training end condition is met; and then obtain the chip operation reliability prediction result of the chip based on the trained operation reliability prediction model. In this embodiment, on the one hand, by obtaining the historical operation data and real-time operation data of the target chip and performing feature extraction and feature cross-reference, the operation status and performance changes of the chip can be more comprehensively reflected, which helps to capture the performance degradation trend and potential problems of the chip during long-term operation; on the other hand, by introducing historical operation data, the model can learn more information about the performance changes of the chip, thereby enhancing the generalization ability of the model, enabling the model to better adapt to the chip reliability analysis needs under different process conditions and working environments, and effectively improving the accuracy of the chip operation reliability prediction results under different conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0060] Figure 1 A schematic flow chart of a method for determining chip operation reliability in one embodiment;

[0061] Figure 2 A schematic flow chart of a step of obtaining a first chip feature in one embodiment;

[0062] Figure 3 This is a structural block diagram of a device for determining chip operation reliability in one embodiment;

[0063] Figure 4 is a diagram of the internal structure of a computer device in one embodiment;

[0064] Figure 5FIG. 1 is a diagram showing the internal structure of another computer device in one embodiment. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0066] In one embodiment, Figure 1 As shown, a method for determining chip operation reliability is provided. This embodiment uses the method applied to a terminal as an example for illustration. It is understandable that the method can also be applied to a server, or to a system including a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0067] S101 , obtaining historical operation data of a chip, performing feature extraction on the historical operation data of the chip, and obtaining a first chip feature reflecting the operation status and chip performance of the chip.

[0068] As an example, the chip may be an enhanced chip, such as a high-voltage, high-speed, and highly integrated chip.

[0069] In actual applications, the historical operation data of the chip can be collected, wherein the historical operation data of the chip can be the operation data collected during the past operation of the chip. The historical operation data of the chip can be the historical operation data of the same chip, or the historical operation data of the chip of the same model or type. In some optional embodiments, the historical operation data of the chip can be collected from a preset data source, and the preset data source can include at least one of a chip operation log and a monitoring system. Of course, the preset data source also includes other types of data collection systems, such as performance monitoring tools, hardware sensor data, etc., depending on the actual application scenario.

[0070] After acquiring the historical operating data, feature extraction can be performed on the historical operating data. Based on the extraction results, chip features that can reflect the operating status and performance of the chip are obtained. For ease of distinction, the chip features obtained based on the analysis of the chip's past historical operating data are referred to as first chip features.

[0071] S102 , obtaining real-time operation data of the chip, performing feature cross-talk between the first chip feature and the real-time operation data of the chip, and obtaining a second chip feature reflecting the comprehensive operation performance of the chip.

[0072] In this step, the real-time operation data of the chip can also be obtained, and then the first chip feature and the real-time operation data of the chip are subjected to feature cross-combination. Based on the result of the feature cross-combination, the chip feature that can reflect the comprehensive performance of the chip operation is obtained. For the convenience of distinction, the chip feature obtained after feature cross-combination is called the second chip feature.

[0073] Among them, feature crossing, also known as combined features, refers to the cross-combination of two or more features of different types or dimensions to generate new features. Feature crossing can capture the impact of multiple features on the target variable when they appear at the same time, thereby enhancing the model's expressive power and prediction accuracy.

[0074] S103, using the second chip feature to perform model training on the machine learning model, and obtaining a trained operation reliability prediction model corresponding to the chip when the training end condition is met.

[0075] After acquiring the second chip features, the second chip features can be used to train the machine learning model. In a specific implementation, the second chip features are used to perform supervised training on the machine learning model, and an adaptive learning rate adjustment strategy is introduced during the training process to update the model parameters. In some exemplary embodiments, the machine learning model can be any of the following: a neural network, a linear classifier, a support vector machine, a decision tree, a random forest, a naive Bayesian, or a reinforcement learning model.

[0076] When the training end condition is met, a trained operation reliability prediction model corresponding to the chip can be obtained, and the operation reliability prediction model can be used to predict the operation reliability of the chip under a characteristic environment.

[0077] S104 , obtaining a chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

[0078] In some embodiments, a user can specify a target operating environment for a chip. This target operating environment can be the operating environment in which the chip will be deployed, and can be characterized by corresponding operating environment parameters. The chip's operating data in the target operating environment can then be input into an operational reliability prediction model. The model then predicts the chip's performance in the target operating environment and outputs a chip operational reliability prediction result.

[0079] In the above-mentioned chip operation reliability determination method, the historical operation data of the chip can be obtained, and feature extraction can be performed on the historical operation data of the chip to obtain a first chip feature reflecting the operation status and chip performance of the chip; the real-time operation data of the chip can be obtained, and the first chip feature can be cross-referenced with the real-time operation data of the chip to obtain a second chip feature reflecting the comprehensive operation performance of the chip; then the second chip feature can be used to train the machine learning model, and when the training end condition is met, a trained operation reliability prediction model corresponding to the chip can be obtained; and then the chip operation reliability prediction result of the chip can be obtained based on the trained operation reliability prediction model. In this embodiment, on the one hand, by obtaining the historical operation data and real-time operation data of the target chip and performing feature extraction and feature cross-reference, the operation status and performance changes of the chip can be more comprehensively reflected, which helps to capture the performance degradation trend and potential problems of the chip during long-term operation; on the other hand, by introducing historical operation data, the model can learn more information about the performance changes of the chip, thereby enhancing the generalization ability of the model, so that the model can better adapt to the chip reliability analysis needs under different process conditions and working environments, and effectively improve the accuracy of the chip operation reliability prediction results under different conditions.

[0080] In some exemplary embodiments, Figure 2 As shown, in step S102, real-time operation data of the chip is obtained, and feature cross-reference is performed between the first chip feature and the real-time operation data of the chip to obtain a second chip feature reflecting the comprehensive operation performance of the chip, which may include the following steps:

[0081] S201, processing the historical operation data of the chip according to a preset data preprocessing method to obtain processed historical operation data, the data preprocessing method including at least one of outlier filtering, missing value supplementation, data denoising, and data formatting.

[0082] In some embodiments, for outlier filtering, a corresponding filtering threshold can be defined based on statistical distribution, and outliers can be removed based on the filtering threshold; for missing value filling, mean filling, interpolation, etc. can be selected to fill missing values ​​according to the characteristics of the data; for data denoising, filtering, smoothing and other techniques can be used to reduce the noise in the data to reduce the impact of noise on subsequent analysis; for data formatting, the data can be converted into a unified format and unit to facilitate subsequent processing and analysis.

[0083] In some embodiments, since missing values ​​may affect subsequent data updates and processing, missing values ​​may be supplemented first, followed by outlier filtering and data denoising. After completing the aforementioned steps, data formatting may be performed.

[0084] S202 , determining performance parameters reflecting chip processing speed, power consumption, and temperature from the processed historical operation data, and determining chip resource occupancy parameters from the processed historical operation data.

[0085] The resource usage parameter may include one or more of the following: resource utilization of a central processing unit (CPU), resource utilization of a memory, and resource utilization of storage resources.

[0086] In practical applications, after obtaining the processed historical operation data, the processed historical operation data can be analyzed and processed. In some embodiments, the target parameters can be read directly from the processed historical operation data. For example, for performance parameters, the CPU utilization, memory occupancy, temperature, etc. can be directly read. For features that need to be obtained through calculation, such as processing speed, power consumption, and storage resource utilization, statistical methods (such as mean, median, standard deviation, maximum value, minimum value, etc.) can be used to analyze the data of a specific time period. Among them, the processing speed can be evaluated based on the task completion time or the number of transactions processed per second, the power consumption can be evaluated based on the change in energy consumption per unit time, and the storage resource utilization can be evaluated based on the occupancy of the storage space.

[0087] S203 , calculating and quantifying the performance parameters and resource occupancy parameters to obtain a first chip characteristic reflecting the average processing speed, maximum power consumption, temperature fluctuation range, and resource utilization of the chip.

[0088] Among them, the average processing speed reflects the average rate at which the chip processes tasks within the preset time; the maximum power consumption reflects the maximum energy consumed by the chip during operation; the temperature fluctuation range reflects the amplitude of the chip temperature change; resource utilization can reflect the use of resources, for example, CPU utilization reflects the use of CPU resources.

[0089] In this step, performance and resource utilization parameters are calculated and quantified by averaging the completion times of all tasks within a specified time period to determine the average processing speed. Maximum power consumption is determined by filtering out the maximum value from the power consumption data. The temperature fluctuation range is determined by calculating the difference between the maximum and minimum values ​​in the temperature data. Resource utilization is determined by calculating the ratio of the CPU time spent executing a task to the total CPU execution time. It should be noted that throughout the entire process, timestamp consistency can be maintained when processing data to ensure accurate analysis of data within a specific time period.

[0090] Furthermore, the average processing speed, maximum power consumption, temperature fluctuation range, and resource utilization of the chip can be determined as the first chip characteristics.

[0091] In this embodiment, by extracting and quantifying key features from the historical operating data of the chip, such as average processing speed, maximum power consumption, temperature fluctuation range, and resource utilization, and by converting the data into a feature set that is highly descriptive of the chip's operating status and performance, the first chip features can more accurately reflect the actual performance and behavior of the chip, providing strong support for subsequent analysis and prediction.

[0092] In some exemplary embodiments, the first chip feature may include multiple features. In step S102, performing feature cross-talk between the first chip feature and the real-time operation data of the chip to obtain a second chip feature reflecting the comprehensive operation performance of the chip may include the following steps:

[0093] S1021 , determining target potential correlation features related to the first chip feature from the real-time operation data of the chip, performing cluster analysis based on the target potential correlation features, and obtaining target correlation features.

[0094] In practical applications, after acquiring the chip's real-time operating data, target potential correlation features related to the first chip feature can be determined from the real-time operating data. The target potential correlation features can be understood as features that are correlated with the chip's past performance. Cluster analysis can then be performed on the target potential correlation features, differentially classifying and analyzing them to obtain target correlation features.

[0095] S1022: Combine the obtained target-related features to obtain a corresponding first feature set, and combine the first chip features to obtain a corresponding second feature set.

[0096] Then, the target-related features can be combined to obtain a first feature set, which can include one or more elements, each of which is obtained by combining at least two target-related features. Alternatively, the first chip features can be combined to obtain a second feature set, which can include one or more elements, each of which is obtained by combining at least two first chip features.

[0097] S1023, traversing each element in the first feature set, multiplying the currently traversed element with each element in the second feature set during the traversal process, performing weighted summation on the multiplication results, and obtaining the combined feature corresponding to the currently traversed element.

[0098] Among them, each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model.

[0099] In a specific implementation, after obtaining the first feature set, each element in the first feature set can be traversed. During the traversal process, the currently traversed element is multiplied with each element in the second feature set to obtain the multiplication result of the currently traversed element and each element in the second feature set. For example, if the second feature set includes X elements, the currently traversed element in the first feature set can be multiplied with X elements respectively to obtain X multiplication results. Each multiplication result can be assigned a weight variable, which can be adaptively optimized and adjusted according to the prediction error during the training process of the machine learning model. Then, the weighted sum of the obtained multiplication results can be obtained to obtain the combined feature corresponding to the currently traversed element.

[0100] Specifically, in the process of traversing the first feature set, each element will be multiplied with each element in the second set, and a weight variable will be assigned to each multiplication result. It should be noted that these weight variables are initially determined by equal weight initialization (that is, all weights are set to the same value, which can be a random value within a certain range and is not currently specified). During model training, these weight variables will be adaptively adjusted based on the prediction error. Specifically, the gradient of the weight variable will be calculated based on the prediction error, and the value of the weight variable will be updated based on the gradient through backpropagation. This process will be repeated until the prediction error reaches an acceptable level or other stopping conditions are met. In other words, when training the model based on each batch of second chip features, the weight of the multiplication result can be adjusted according to the previous model training situation to update the second chip features of the current batch.

[0101] S1024: Determine the combined feature corresponding to each element in the first feature set as a second chip feature reflecting the comprehensive operating performance of the chip.

[0102] After obtaining the combined feature corresponding to each element in the first feature set, the combined feature corresponding to each element can be determined as a second chip feature reflecting the comprehensive operating performance of the chip.

[0103] In this embodiment, in the process of multiplying and weighted summing feature combinations, weight variables are introduced and adaptive optimization adjustments are performed based on the prediction error. This weight optimization mechanism can automatically adjust the contribution of different feature combinations to the second chip feature that reflects the comprehensive performance of the chip operation, thereby improving the accuracy and robustness of the model.

[0104] In some exemplary embodiments, determining a target potential associated feature related to a first chip feature from real-time operating data of a chip may include the following steps:

[0105] Based on the principal component analysis method, potential correlation indicators are determined from multiple data indicators corresponding to the real-time operation data of the chip; for each potential correlation indicator, the correlation coefficient between the potential correlation indicator and the feature indicator corresponding to the first chip feature is calculated; according to the coefficient size of each correlation coefficient, the potential correlation indicators are sorted in descending order, and the first K potential correlation indicators are used as target potential correlation indicators; the real-time operation data under the target potential correlation indicator is obtained from the real-time operation data of the chip as the target potential correlation feature.

[0106] Wherein, K is a positive integer greater than or equal to 1.

[0107] In a specific implementation, the real-time operation data of the chip has corresponding multiple data indicators, and the first chip feature is the value under the corresponding feature indicator. The first chip feature can be determined based on the real-time operation data under some or all of the multiple data indicators. Based on the professional knowledge and experience in the field of chip design, the staff can determine the candidate data indicators that may be associated with the data indicators corresponding to the first chip feature among the multiple data indicators corresponding to the real-time operation data, such as memory access delay, power supply voltage fluctuation, network delay, cache hit rate, etc. One or more. Afterwards, based on the principal component analysis method, the potential correlation indicators are determined from the manually screened candidate data indicators. The principal component analysis method is used here as a preprocessing step, the purpose of which is to extract the main information components from the real-time operation data of the chip.

[0108] Afterwards, in order to further improve the accuracy of feature extraction, the correlation between each extracted potential correlation indicator and the characteristic indicator corresponding to the first chip feature can be analyzed, that is, a correlation evaluation can be performed. Specifically, the correlation coefficient between each potential correlation indicator and each characteristic indicator can be calculated. The correlation coefficient can quantify the degree of correlation between a potential correlation indicator and a characteristic indicator.

[0109] In one embodiment, the correlation between each potential correlation indicator and the characteristic indicator corresponding to the first chip characteristic can be evaluated based on the Pearson correlation coefficient. (where j = 1, 2, ..., m), the Pearson correlation coefficient between it and the characteristic index Y corresponding to the first chip feature It can be calculated by the following formula:

[0110]

[0111] in, represents the i-th observation value of the j-th potential correlation indicator, represents the average value of the jth potential correlation index, Indicates the i-th observation value of the characteristic index corresponding to the first chip feature, represents the average value of the characteristic index corresponding to the first chip feature, and n represents the number of observations.

[0112] Then, based on the correlation evaluation results, target potential correlation features that are highly correlated with the characteristic indicators of the first chip feature are screened. In some embodiments, the potential correlation indicators can be sorted in descending order based on their corresponding correlation coefficients, where the sorting results will reflect the strength of the correlation between each potential correlation indicator and the corresponding characteristic indicator of the first chip feature. The target potential correlation indicators can then be extracted from the sorting results according to a preset ratio (e.g., the top 80%), and real-time operating data under the target potential correlation indicators can be obtained from the chip's real-time operating data as target potential correlation features. These selected features will be used in subsequent model construction.

[0113] In this embodiment, through correlation quantification and feature sorting, features with low correlation with target features are removed, key information is retained, and the accuracy of analysis is improved.

[0114] In some exemplary embodiments, performing cluster analysis based on target potential association features to obtain target association features may include the following steps:

[0115] Determine a target data set consisting of target potential association features; based on the data distribution characteristics of the target data set, select M data points from the target data set as initial cluster centers; cluster the target data set based on the initial cluster centers to obtain multiple clusters, and determine the cluster representative features corresponding to each cluster; obtain multiple target association features based on the cluster representative features of the multiple clusters.

[0116] Wherein, M is a positive integer greater than or equal to 2.

[0117] In practical applications, after acquiring multiple target potential correlation features, a target dataset consisting of these potential correlation features can be obtained. Each data point in the target dataset corresponds to a target potential correlation feature. Initial cluster centers can then be selected based on the data distribution characteristics to reduce the algorithm's dependence on the initial selection and improve the stability and accuracy of the clustering results. After determining the initial cluster centers, the target dataset can be clustered based on these initial cluster centers to obtain multiple clusters.

[0118] Specifically, for each data point in the target dataset, the distance between the data point and each initial cluster center is calculated, and the data point is assigned to the cluster with the closest distance. For example, the distance between the data point and the cluster center is calculated and assigned to the closest cluster. Then, for each cluster, the average value of all data points in the cluster along the weighted feature dimension is calculated based on the feature weights to form a new cluster center. For example, when calculating the cluster center, rather than simply taking the average value of all data points in the cluster along each feature dimension, the value of each feature dimension can be weighted according to the feature weights and then the average is taken. Specifically, for each cluster and each feature dimension, the sum of all weighted data points along that dimension is calculated and then divided by the total number of weighted data points to obtain a weighted average. This weighted average is then used as the new cluster center value for the corresponding feature dimension. In this way, the new cluster center takes into account the importance of different features to the clustering result. This process is repeated until the preset convergence conditions are met, resulting in multiple clusters.

[0119] Furthermore, a representative feature can be selected from each currently formed cluster as a cluster representative feature, and multiple target-related features can be obtained based on the cluster representative features of each cluster. For example, the center or average value corresponding to each cluster can be used as the cluster representative feature.

[0120] In this embodiment, selecting the initial cluster center based on the data distribution characteristics can reduce the algorithm's sensitivity to the initial selection, thereby reducing the risk of falling into a local optimal solution, which helps to improve the stability and accuracy of the clustering results. Taking feature weights into account when calculating the cluster center can make the clustering process more focused on features that have an important impact on the clustering results. In this way, the formation of cluster centers will be more in line with the actual distribution of the data, so that the cluster representative features can more accurately reflect the inherent structure and characteristics of the data.

[0121] In one embodiment, in step S103, using the second chip feature to perform model training on the machine learning model may include the following steps:

[0122] Obtain the operational reliability label of the chip under real-time operational data; input the second chip feature into the machine learning model for forward propagation to obtain the predicted output of the model; calculate the loss function value based on the prediction error between the predicted output and the operational reliability label; execute the backpropagation algorithm based on the loss function value to determine the gradient of the model parameters of the machine learning model; estimate the mean of the gradient by exponentially weighted moving average to obtain the first-order moment estimate, and estimate the mean of the square of the gradient by exponentially weighted moving average to obtain the second-order moment estimate; perform bias correction on the first-order moment estimate and the second-order moment estimate based on the adaptive bias correction and momentum attenuation factor adjustment, and calculate the update amount of each model parameter in combination with the global learning rate, and update the model parameters of the machine learning model; return to execute the second chip feature input into the machine learning model for forward propagation to obtain the predicted output of the model, iteratively adjust the model parameters of the machine learning model until the training end conditions are met, and obtain a trained machine learning model.

[0123] The operation reliability label represents the chip operation reliability when the chip has real-time operation data.

[0124] In practical applications, the second chip features can be input into a machine learning model for forward propagation to obtain the model's predicted output, which can be understood as the chip's operational reliability predicted by the machine learning model based on the second chip features. The prediction error between the predicted output and the previously acquired operational reliability label can then be determined, and the loss function value calculated based on the prediction error.

[0125] Afterwards, the backpropagation algorithm can be executed based on the loss function value to determine the gradient of the model parameters of the machine learning model, and the mean of the gradient is estimated by exponentially weighted moving average to obtain the first-order moment estimate. The mean of the square of the gradient is estimated by exponentially weighted moving average to obtain the second-order moment estimate, and then the first-order moment estimate and the second-order moment estimate are bias-corrected.

[0126] In the prior art, bias correction typically uses a fixed decay rate to calculate the moving average bias correction term. To further improve the adaptability and stability of the algorithm, this embodiment introduces an adaptive bias correction method. This method dynamically adjusts the decay rate of the bias correction term based on the statistical properties of the gradient. Specifically, when the gradient distribution fluctuates significantly, the decay rate is increased to more quickly correct the bias; when the gradient distribution is relatively stable, the decay rate is appropriately reduced to maintain estimation stability. Furthermore, regarding the adjustment of the momentum decay factor, considering that different momentum strengths may be required at different training stages to accelerate convergence or escape local optima, this embodiment also designs a strategy for dynamically adjusting the momentum decay factor. This adjustment can be based on the rate of change of the gradient, the rate of decline of the loss function, or the improvement in model performance. For example, when the loss function declines slowly, the momentum decay factor is appropriately increased to enhance the momentum effect; when the loss function fluctuates significantly, the momentum decay factor is appropriately reduced to stabilize the training process.

[0127] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0128] Based on the same inventive concept, embodiments of the present application also provide a device for determining chip operation reliability for implementing the aforementioned method for determining chip operation reliability. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more embodiments of the device for determining chip operation reliability provided below can be found in the aforementioned limitations of the method for determining chip operation reliability, and will not be further elaborated here.

[0129] In an exemplary embodiment, Figure 3 As shown, a device for determining chip operation reliability is provided, comprising:

[0130] A historical feature extraction module 301 is configured to obtain historical operating data of a chip, perform feature extraction on the historical operating data of the chip, and obtain a first chip feature reflecting the operating state and chip performance of the chip;

[0131] A feature crossover module 302 is configured to obtain real-time operating data of the chip, perform feature crossover on the first chip feature and the real-time operating data of the chip, and obtain a second chip feature reflecting the comprehensive operating performance of the chip;

[0132] A model training module 303 is configured to perform model training on a machine learning model using the second chip characteristics, and obtain a trained operation reliability prediction model corresponding to the chip when a training end condition is met;

[0133] The model prediction module 304 is configured to obtain a chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

[0134] In one embodiment, the historical feature extraction module 301 is used to:

[0135] Processing the historical operation data of the chip according to a preset data preprocessing method to obtain processed historical operation data, wherein the data preprocessing method includes at least one of outlier filtering, missing value supplementation, data denoising, and data formatting;

[0136] Determining performance parameters reflecting the processing speed, power consumption, and temperature of the chip from the processed historical operation data, and determining resource occupancy parameters of the chip from the processed historical operation data;

[0137] The performance parameters and the resource occupancy parameters are calculated and quantified to obtain a first chip characteristic reflecting the average processing speed, maximum power consumption, temperature fluctuation range, and resource utilization of the chip.

[0138] In one embodiment, the feature intersection module 302 is configured to:

[0139] Determining target potential correlation features related to the first chip feature from the real-time operation data of the chip, and performing cluster analysis based on the target potential correlation features to obtain target correlation features;

[0140] Combining the obtained target-related features to obtain a corresponding first feature set, and combining the first chip features to obtain a corresponding second feature set;

[0141] Traversing each element in the first feature set, during the traversal process, multiplying the currently traversed element with each element in the second feature set, and performing a weighted summation on the obtained multiplication results to obtain a combined feature corresponding to the currently traversed element; wherein each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model;

[0142] The combined feature corresponding to each element in the first feature set is determined as a second chip feature reflecting the comprehensive operating performance of the chip.

[0143] In one embodiment, the feature intersection module 302 is configured to:

[0144] Determining potential correlation indicators from a plurality of data indicators corresponding to the real-time operation data of the chip based on a principal component analysis method;

[0145] For each of the potential correlation indicators, calculating a correlation coefficient between the potential correlation indicator and a feature indicator corresponding to the first chip feature;

[0146] According to the magnitude of the coefficients of the correlation coefficients, the potential correlation indicators are sorted in descending order, and the first K potential correlation indicators are used as target potential correlation indicators; K is a positive integer greater than or equal to 1;

[0147] The real-time operation data under the target potential correlation index is obtained from the real-time operation data of the chip as the target potential correlation feature.

[0148] In one embodiment, the feature intersection module 302 is configured to:

[0149] Determine a target data set consisting of all target potential correlation features, wherein each data point in the target data set corresponds to one of the target potential correlation features;

[0150] Based on the data distribution characteristics of the target data set, M data points are selected from the target data set as initial cluster centers; M is a positive integer greater than or equal to 2;

[0151] Clustering the target data set based on the initial cluster centers to obtain a plurality of clusters, and determining a cluster representative feature corresponding to each of the clusters;

[0152] A plurality of target-related features are obtained according to the cluster representative features of each of the plurality of clusters.

[0153] In one embodiment, the model training module 303 is used to:

[0154] Obtaining an operation reliability label of the chip under the real-time operation data; the operation reliability label indicates the chip operation reliability when the chip has the real-time operation data;

[0155] Inputting the second chip feature into the machine learning model for forward propagation to obtain a predicted output of the model;

[0156] Calculating a loss function value based on a prediction error between the prediction output and the operational reliability label;

[0157] Executing a back propagation algorithm based on the loss function value to determine the gradient of the model parameters of the machine learning model;

[0158] Estimate the mean of the gradient by an exponentially weighted moving average to obtain the first-order moment estimate, and estimate the mean of the square of the gradient by an exponentially weighted moving average to obtain the second-order moment estimate;

[0159] According to the adaptive bias correction and momentum decay factor adjustment, the first-order moment estimation and the second-order moment estimation are bias corrected, and in combination with the global learning rate, the update amount of each model parameter is calculated, and the model parameters of the machine learning model are updated;

[0160] Return to execute inputting the second chip feature into the machine learning model for forward propagation, obtain the predicted output of the model, iteratively adjust the model parameters of the machine learning model until the training end condition is met, and obtain a trained machine learning model.

[0161] Each module in the aforementioned chip operational reliability determination device may be implemented in whole or in part through software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor in a computer device in hardware form, or may be stored in a computer device memory in software form, so that the processor can call and execute the corresponding operations of each module.

[0162] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 4 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store chip operation data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for determining chip operation reliability is implemented.

[0163] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 5As shown. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals via wired or wireless means, and the wireless means can be implemented via Wi-Fi, a mobile cellular network, near-field communication (NFC), or other technologies. When executed by the processor, the computer program implements a method for determining chip operation reliability. The display unit of the computer device is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0164] Those skilled in the art will understand that Figure 4 and Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0165] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0166] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0167] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0168] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0169] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0170] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0171] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for determining chip operation reliability, characterized in that: The method comprises: Acquiring historical operating data of a chip, performing feature extraction on the historical operating data of the chip, and obtaining a first chip feature reflecting an operating state and chip performance of the chip; Acquire real-time operating data of the chip, determine target potential associated features related to the first chip features from the real-time operating data of the chip, perform cluster analysis based on the target potential associated features to obtain target associated features, combine the obtained target associated features to obtain a corresponding first feature set, and combine the first chip features to obtain a corresponding second feature set, traverse each element in the first feature set, and during the traversal process, multiply the currently traversed element with each element in the second feature set, perform weighted summation on the obtained multiplication results to obtain a combined feature corresponding to the currently traversed element, and determine the combined feature corresponding to each element in the first feature set as a second chip feature reflecting the comprehensive operating performance of the chip; wherein each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model; Performing model training on the machine learning model using the second chip feature, and obtaining a trained operation reliability prediction model corresponding to the chip when a training end condition is met; A chip operation reliability prediction result of the chip is obtained based on the trained operation reliability prediction model.

2. The method according to claim 1, characterized in that The extracting features from the historical operation data of the chip to obtain a first chip feature reflecting the operation status and chip performance of the chip includes: Processing the historical operation data of the chip according to a preset data preprocessing method to obtain processed historical operation data, wherein the data preprocessing method includes at least one of outlier filtering, missing value supplementation, data denoising, and data formatting; Determining performance parameters reflecting the processing speed, power consumption, and temperature of the chip from the processed historical operation data, and determining resource occupancy parameters of the chip from the processed historical operation data; The performance parameters and the resource occupancy parameters are calculated and quantified to obtain a first chip characteristic reflecting the average processing speed, maximum power consumption, temperature fluctuation range, and resource utilization of the chip.

3. The method according to claim 1, characterized in that The determining, from the real-time operating data of the chip, a target potential associated feature related to the first chip feature, includes: Determining potential correlation indicators from a plurality of data indicators corresponding to the real-time operation data of the chip based on a principal component analysis method; For each of the potential correlation indicators, calculating a correlation coefficient between the potential correlation indicator and a feature indicator corresponding to the first chip feature; According to the magnitude of the coefficients of the correlation coefficients, the potential correlation indicators are sorted in descending order, and the first K potential correlation indicators are used as target potential correlation indicators; K is a positive integer greater than or equal to 1; The real-time operation data under the target potential correlation index is obtained from the real-time operation data of the chip as the target potential correlation feature.

4. The method according to claim 3, characterized in that The cluster analysis based on the target potential correlation features to obtain target correlation features includes: Determine a target data set consisting of all target potential correlation features, wherein each data point in the target data set corresponds to one of the target potential correlation features; Based on the data distribution characteristics of the target data set, M data points are selected from the target data set as initial cluster centers; M is a positive integer greater than or equal to 2; Clustering the target data set based on the initial cluster centers to obtain a plurality of clusters, and determining a cluster representative feature corresponding to each of the clusters; A plurality of target-related features are obtained according to the cluster representative features of each of the plurality of clusters.

5. The method according to any one of claims 1 to 4, characterized in that The performing model training on the machine learning model by using the second chip feature includes: Obtaining an operation reliability label of the chip under the real-time operation data; the operation reliability label indicates the chip operation reliability when the chip has the real-time operation data; Inputting the second chip feature into the machine learning model for forward propagation to obtain a predicted output of the model; Calculating a loss function value based on a prediction error between the prediction output and the operational reliability label; Executing a back propagation algorithm based on the loss function value to determine the gradient of the model parameters of the machine learning model; Estimate the mean of the gradient by an exponentially weighted moving average to obtain the first-order moment estimate, and estimate the mean of the square of the gradient by an exponentially weighted moving average to obtain the second-order moment estimate; According to the adaptive bias correction and momentum decay factor adjustment, the first-order moment estimation and the second-order moment estimation are bias corrected, and in combination with the global learning rate, the update amount of each model parameter is calculated, and the model parameters of the machine learning model are updated; Return to execute inputting the second chip feature into the machine learning model for forward propagation, obtain the predicted output of the model, iteratively adjust the model parameters of the machine learning model until the training end condition is met, and obtain a trained machine learning model.

6. A device for determining chip operation reliability, characterized in that: The device comprises: a historical feature extraction module, configured to obtain historical operating data of a chip, perform feature extraction on the historical operating data of the chip, and obtain a first chip feature reflecting the operating state and chip performance of the chip; A feature cross-module is used to obtain real-time operating data of the chip, determine target potential associated features related to the first chip features from the real-time operating data of the chip, perform cluster analysis based on the target potential associated features to obtain target associated features, combine the obtained target associated features to obtain a corresponding first feature set, and combine the first chip features to obtain a corresponding second feature set, traverse each element in the first feature set, and during the traversal process, multiply the currently traversed element with each element in the second feature set, perform weighted summation on the obtained multiplication results, and obtain a combined feature corresponding to the currently traversed element, and determine the combined feature corresponding to each element in the first feature set as a second chip feature reflecting the comprehensive operating performance of the chip; wherein each multiplication result has a corresponding weight, and the weight is adjusted according to the prediction error of the machine learning model; a model training module, configured to perform model training on the machine learning model using the second chip characteristics, and obtain a trained operation reliability prediction model corresponding to the chip when a training end condition is met; The model prediction module is used to obtain the chip operation reliability prediction result of the chip based on the trained operation reliability prediction model.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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