A method for realizing automatic connection of differential pairs in analog layout

Abstract

The present invention provides a method for realizing automatic wiring of differential pairs in analog layout, and belongs to the field of analog layout automation technology. In view of the characteristics that the matching form of differential pairs is fixed and the symmetry of routing is required to be high, the present invention arranges routing in a reasonable order so that the nets that need to be matched obtain basically equal parasitics, realizes one-key position matching and automatic wiring, and only needs a few constraint parameter settings, such as the number of rows and columns, routing levels, and line width and line spacing constraints, to realize one-key automatic wiring of differential pairs according to the conventional wiring method of the analog layout. With more concise pre-constraints, the automatic wiring of the differential pair layout can be completed quickly, and the user can basically complete all work with one click after selecting the differential pair device that needs to be matched. A highly symmetrical node matching relationship can be achieved, which has certain advantages over the existing methods in terms of parasitic symmetry consistency. The implementation method of the present invention does not rely on dedicated routing channels, saving array area.

Description

Technical Field

[0001] The invention belongs to the technical field of analog layout automation, and in particular relates to a method for realizing automatic connection of differential pairs in analog layout. Background Art

[0002] In the process of layout realization of analog circuits, the manufacturing and working environment of the layout devices will affect the working performance of the devices. Specifically, the environmental impact mainly includes: manufacturing etching accuracy, residual stress, and temperature gradient during operation. The same devices placed in different environments will produce characteristic deviations between each other. These deviations are often avoided as much as possible for circuit performance realization. Therefore, in the layout design process, the environmental differences between devices are often minimized by matching the device positions.

[0003] When designing the layout, first of all, all the devices that need to be matched need to be placed in the same matching array according to the type and quantity of the devices. There are various types of matching arrays, and the most common ones are cross-coupling matching, common centroid matching, and interdigital matching. After the matching array is completed, it is necessary to connect the devices scattered throughout the array to achieve the same connection relationship as the analog circuit. In order to improve work efficiency, layout engineers often have a strong demand for automation of the above process. However, due to the variety of types, processes, quantities and matching types of matching devices, the current mainstream electronic design automation (EDA) tools are difficult to provide one-click fully automatic matching placement and wiring functions. Although some tools provide related functions, the wiring template is either single and inflexible, or the wiring form is not in line with habits and cannot be adjusted, or many constraints need to be preset. Compared with manual wiring, the wiring form also has disadvantages in terms of area and parasitics. There are also tools that are flexible and fast in layout automation, but the learning cost is too high.

[0004] For the matching of differential pairs, the connection patterns provided by mainstream EDA tools generally require dedicated routing channel areas. Once the routing channel area overlaps with the device area, most connection patterns cannot support it, which will occupy additional layout area. Summary of the invention

[0005] The purpose of the present invention is to propose a method for realizing automatic connection of differential pairs in analog layout, so as to solve the technical problems proposed in the above background technology for differential pair matching scenarios, such as low layout drawing efficiency, additional layout area occupied and disadvantages in parasitics.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A method for realizing automatic connection of differential pairs in a simulation layout comprises the following steps:

[0008] S01. Obtaining constraints, including obtaining layout process metal layer information, obtaining device placement information, obtaining twig, trunk, strap layer, line width, line spacing, direction information, and also obtaining device number information;

[0009] S02. Calculate and list the number of feasible rows and columns;

[0010] S03. According to the selected rows and columns, the device arrangement is automatically completed according to the arrangement rules, and the arrangement rules include quantity check rules, position arrangement rules and direction arrangement rules. The quantity check rules refer to: first determine whether the total number of devices is divisible by 4, if not, then determine whether it is divisible by 2. If the total number of devices is not divisible by 2, the system prompts "device quantity error". If the total number of devices is divisible by 4 or by 2, the position arrangement rules and direction arrangement rules are executed in sequence; the position arrangement rules refer to: if the total number of devices is divisible by 4, take the row and column combination of even rows and even columns: when the row number and column number meet the "j+[i / 2] is an even number", device A is placed, and device B is placed when the row number and column number satisfy "j+[i / 2] is an odd number"; the total number of devices is divisible by 2, and the row and column combination of even rows and odd columns is taken: when the row number and column number satisfy "j+i is an even number", device A is placed, and when the row number and column number satisfy "j+i is an odd number", device B is placed; where "j" represents the row number and "i" represents the column number; the direction arrangement rule means that when the total number of devices is divisible by 4, the devices in the odd rows are mirrored along the X axis, and the devices in the odd columns are mirrored along the Y axis; when the total number of devices is divisible by 2, the devices in the odd rows are mirrored along the X axis;

[0011] S04. The number of trunks in each row is calculated based on the total number of nets existing in the gate, source, and drain of the MOS field effect transistor. Then, the required twig length is calculated based on the preset routing constraints of the trunk, and the twig connection is generated. Then, the trunk connection required for the gate, source, and drain is generated. Next, the strap connection line required for the cross-row connection is generated, and the position of the matching net needs to be kept symmetrical and the parasitics are similar. Finally, the connection line between the gates needs to be crossed with the trunk layer and the strap layer.

[0012] Furthermore, step S02 also includes screening all feasible common divisors, and preferentially recommending solutions with even-numbered rows and the closest number of rows to columns for selection.

[0013] Furthermore, in step S04, the gate trunk is limited within the width of the MOS field effect transistor; the source and drain corresponding trunks are connected within the entire matching array width, and the nets corresponding to the generated trunks are arranged in order to meet the matching relationship between the nets.

[0014] Preferably, the order means that the common nets are arranged close to the gate trunk, and the non-common nets are arranged close to the common nets alternately according to odd and even rows.

[0015] Furthermore, in step S04, when generating the strap connection lines required for cross-row connection, the specific steps of allocating the strap to each column are as follows:

[0016] (1) Determine whether the number of device columns C is greater than or equal to the number of source and drain nets N. This judgment is the primary condition of the entire allocation process. It determines the subsequent different allocation strategies.

[0017] (2) If C is greater than or equal to N, it means that there may be relatively more columns in the layout that can be used to allocate straps.

[0018] There is one strap trace per column, for a total of C strap traces.

[0019] If the number of columns C is even: arrange all nets in a circular order from C / 2 to 1; arrange all nets in a circular order from C / 2 to C in reverse order.

[0020] If the number of columns C is an odd number, it is necessary to further determine whether the number of nets N is an odd number, which mainly affects the type of net placed at a specific column position and the cyclic arrangement order of the nets.

[0021] If N is odd:

[0022] Place the public net in the (C+1) / 2th column. From the (C-1) / 2th column to the 1st column, arrange all the nets in a circular order starting with the non-public net. From the (C+1) / 2+1th column to the Cth column, arrange all the nets in a circular order starting with the non-public net.

[0023] If N is even:

[0024] Place a dummy strap in the (C+1) / 2th column. Arrange all nets in a loop from the (C-1) / 2th column to the 1st column. Arrange all nets in a loop in reverse order from the (C+1) / 2+1th column to the Cth column.

[0025] (3) If C is greater than or equal to N, it means that the layout is relatively compact.

[0026] Arrange 2 strap lines in each column, for a total of 2C strap lines. Arrange all nets in a loop from C to 1; and arrange all nets in a loop from C+1 to 2C in the reverse order.

[0027] Furthermore, in step S04, after the strap connection line is generated, a Via is generated at the intersection node of the strap and the trunk of the same net.

[0028] The present invention has the following beneficial effects:

[0029] 1. Use simpler pre-constraints to quickly complete the automatic wiring of the differential pair layout. Users can basically complete all work with one click after selecting the differential pair devices that need to be matched.

[0030] 2. It can achieve highly symmetrical node matching relationships and has certain advantages over existing methods in terms of parasitic symmetry consistency.

[0031] 3. The implementation method of the present invention is equivalent to a fixed wiring pattern, which conforms to the wiring habits of the analog layout, does not rely on dedicated wiring channels, and saves array area. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0033] Figure 1 It is the overall operation steps of the present invention;

[0034] Figure 2 A diagram showing the arrangement rules for device positions and directions;

[0035] Figure 3 Logic diagram of the method for assigning straps to each column;

[0036] Figure 4 This is the circuit schematic corresponding to a simple differential pair connection;

[0037] Figure 5 The following is a schematic diagram of possible differential pair matching arrays when multi=3;

[0038] Figure 6 A schematic diagram of a possible differential pair matching array when multi=4;

[0039] Figure 7 To generate a Twig routing diagram;

[0040] Figure 8 To generate a trunk routing diagram;

[0041] Fig. 9 To generate a strap routing diagram;

[0042] Fig.10 To generate a connection diagram between Gates. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] See also Figure 1-3 As shown, a method for realizing automatic connection of differential pairs in a simulation layout specifically comprises the following steps:

[0045] Step 1, obtain constraints. The constraints include obtaining layout process metal level information, obtaining device placement information (such as the minimum spacing of active areas, etc.), and obtaining twig, trunk, strap level, line width, direction and other constraints. Twig is the smallest branch connecting the device port, and is generally connected using the first layer of metal in the back-end process; trunk can be understood as a thicker branch, and generally the second layer of metal in the back-end process can be used. The trunk can be used to connect the twig holes of the same connection relationship (net) in multiple devices in a row together; strap is the bus that ultimately connects the trunks of different rows with the same connection relationship (net), and the strap can be completed using the third layer of metal. It also includes obtaining device number information. The default differential matching device is two groups of MOS field effect transistors with symmetrical connection relationships. Therefore, the total number of devices should be an even number. If the total number is an odd number, the selected device does not meet the differential pair matching requirements, and the program is terminated with an error.

[0046] Step 2. Calculate and list the feasible number of rows and columns; select all feasible common divisors, and give priority to recommending solutions with even numbers of rows and the closest number of rows and columns for users to choose.

[0047] Step 3. After obtaining the above information, the program will automatically complete the device arrangement according to the selected rows and columns. The specific arrangement rules are as follows. Please refer to Figure 2 shown.

[0048] 1. Quantity Inspection Rules

[0049] First determine whether the total number of devices is divisible by 4. If not, determine whether it is divisible by 2. If the total number of devices is not divisible by 2, the system prompts "device quantity error"; if the total number of devices is divisible by 4 or 2, proceed to the next step of position and direction arrangement rules.

[0050] 2. Position Arrangement Rules

[0051] The total number of devices is divisible by 4, and the row and column combinations of even rows and even columns are taken:

[0052] When the row number and column number satisfy "j+[i / 2] is an even number", device A is placed. Here, "j" represents the row number, and "i" represents the column number. Whether device A is placed is determined by a specific calculation result of the row number and the column number.

[0053] When the row number and column number satisfy "j+[i / 2] is an odd number", device B is placed. Similarly, device B is placed based on a specific calculation result of the row number and column number.

[0054] The total number of devices is divisible by 2, and the row and column combinations of even rows and odd columns are taken:

[0055] When the row number and column number satisfy "j+i is an even number", device A is placed.

[0056] When the row number and column number satisfy "j+i is an odd number", device B is placed.

[0057] 3. Direction arrangement rules

[0058] When the total number of devices is divisible by 4:

[0059] For devices in odd rows, they are mirrored along the X axis. This means that the devices in odd rows are flipped horizontally and presented in a specific mirrored manner. For devices in odd columns, they are mirrored along the Y axis. That is, the devices in odd columns are flipped vertically and presented in a direction that is symmetrical to the normal state.

[0060] When the total number of devices is divisible by 2:

[0061] Devices in odd rows are mirrored along the X-axis.

[0062] Step 4. Calculate the number of trunks in each row based on the total number of nets existing in the gate, source, and drain of the MOS field effect transistor, and then calculate the required twig length based on the preset routing constraints of the trunk (line width and line spacing, etc.) to generate twig connections; then generate the trunk connections required for the gate, source, and drain. The gate trunk is limited to the width of the MOS field effect transistor, and the nets corresponding to the trunk generated by the source and drain are arranged in order to meet the matching relationship between the nets; then, generate the strap connection lines required for cross-row connections, and keep the positions of the matching nets symmetrical and parasitic. Finally, generate the connection lines between the gates, which require the trunk layer and the strap layer to cross.

[0063] In the above Step 4, when generating the strap connection lines required for cross-row connection, the present invention provides a method for allocating straps to each column to obtain better and more uniform layout matching. The code logic framework is as follows: Figure 3 The specific steps of this method are as follows:

[0064] 1. Judgment conditions

[0065] Determine whether the number of device columns C is greater than or equal to the number of source and drain Nets N. This judgment is the primary condition of the entire allocation process. It determines the subsequent different allocation strategies.

[0066] Second, if C is greater than or equal to N, it means that there may be relatively more columns in the layout that can be used to allocate straps.

[0067] There is one strap trace per column, for a total of C strap traces.

[0068] If the number of columns C is even: arrange all nets in a circular order from C / 2 to 1; arrange all nets in a circular order from C / 2 to C in reverse order.

[0069] If the number of columns C is an odd number, it is necessary to further determine whether the number of nets N is an odd number, which mainly affects the type of net placed at a specific column position and the cyclic arrangement order of the nets.

[0070] If N is odd:

[0071] Place the public net in the (C+1) / 2th column. From the (C-1) / 2th column to the 1st column, arrange all the nets in a circular order starting with the non-public net. From the (C+1) / 2+1th column to the Cth column, arrange all the nets in a circular order starting with the non-public net.

[0072] If N is even:

[0073] Place a dummy strap in the (C+1) / 2th column. Arrange all nets in a loop from the (C-1) / 2th column to the 1st column. Arrange all nets in a loop in reverse order from the (C+1) / 2+1th column to the Cth column.

[0074] 3. If C is greater than or equal to N, it means that the number of column resources is small.

[0075] Arrange 2 strap lines in each column, for a total of 2C strap lines. Arrange all nets in a loop from C to 1; and arrange all nets in a loop from C+1 to 2C in the reverse order.

[0076] See also Figure 4-Figure 10 As shown in the figure, two specific examples are used to illustrate the device arrangement rules of Step 3 and the process of automatically generating connection lines in Step 4:

[0077] Figure 4 , is a circuit schematic diagram corresponding to a simple differential pair connection, where the number of MOS field effect transistors A and B is equal to x. When x=3, the corresponding layout is arranged as follows Figure 5 When x=4, the corresponding layout is arranged as follows Figure 6 shown.

[0078] Taking the array case of multi=4 as an example, the process of automatically generating connecting lines in step 4 is explained:

[0079] ① First, calculate the number of trunks in each row based on the total number of nets in the gate, source and drain of the MOS tube, then calculate the required twig length based on the preset routing constraints of the trunk (line width and line spacing, etc.), and then generate the twig connection, such as Figure 7 shown.

[0080] ② Generate the trunk connections required for gate, source and drain, where the gate trunk is limited within the MOS width according to the spacing and routing constraints of the MOS arrangement; the trunks corresponding to the source and drain are connected within the entire matching array width, and the nets corresponding to the generated trunks need to be arranged in a certain order to satisfy the matching relationship between the nets. For example, a feasible arrangement is: the public net (net1) of MosA and MosB is arranged close to the gate trunk, and the non-public nets (net2, net3) are arranged alternately close to the public net according to the odd and even rows, so as to ensure that net2 and net3 have basically the same size of parasitics. Figure 8 shown.

[0081] ③ Generate the strap connection lines required for cross-row connection. This step still needs to keep the position of the matching net symmetrical and similar parasitics. For a group of differential pairs, there is generally a common terminal, that is, a total of 3 types of nets; it may not have a common terminal, that is, a total of 4 types of nets. In a differential device array, the number of columns should be an integer greater than or equal to 2. According to the above method of allocating straps, Figure 8 The 2-row, 4-column example will generate Fig. 9 The strap shown in the figure generates a Via at the intersection of the strap and trunk in the same net.

[0082] ④ To further generate the connection lines between the gates, the trunk layer and the strap layer need to be crossed, such as Fig.10 shown.

[0083] If the number of rows is greater than 2, cross-row joins are required, which is not shown in the above example.

[0084] In view of the characteristics of fixed matching form of differential pairs and high requirements for routing symmetry, the present invention arranges routing in a reasonable order so that the nets that need to be matched obtain basically equal parasitics, and proposes code logic and methodology for automatically generating connections between differential pair devices at one time, realizing one-click position matching and automatic wiring. Only a few constraint parameter settings are required, such as the number of rows and columns, routing levels, and line width and line spacing constraints, so that the differential pairs can be automatically connected in one click according to the conventional wiring method of the analog layout.

[0085] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.

Claims

1. A method for realizing automatic connection of differential pairs in analog layout, characterized in that: The following steps are involved: S01. Obtaining constraint conditions, wherein the constraint conditions include obtaining layout process metal layer information, obtaining device placement information, obtaining layer, line width, line spacing, and direction information of twig, trunk, and strap, and also obtaining device number information. Twig is the smallest branch connecting device ports. Trunk connects twigs of the same net in multiple devices in a row. Strap is a bus that connects trunks of different rows of the same net. S02. Calculate and list the number of feasible rows and columns; S03. According to the selected rows and columns, the device arrangement is automatically completed according to the arrangement rules. The arrangement rules include quantity check rules, position arrangement rules and direction arrangement rules. The quantity check rules refer to: first determine whether the total number of devices is divisible by 4. If not, determine whether it is divisible by 2. If the total number of devices is not divisible by 2, the system prompts "device quantity error". If the total number of devices is divisible by 4 or by 2, the position arrangement rules and direction arrangement rules are executed in sequence; the position arrangement rules refer to: if the total number of devices is divisible by 4, take the row and column combination of even rows and even columns: when the row number and column number meet "j+[i / 2] is an even number", device A is placed, and device B is placed when the row number and column number satisfy "j+[i / 2] is an odd number"; the total number of devices is divisible by 2, and the row and column combination of even rows and odd columns is taken: when the row number and column number satisfy "j+i is an even number", device A is placed, and when the row number and column number satisfy "j+i is an odd number", device B is placed; where "j" represents the row number, and "i" represents the column number; the direction arrangement rule means: when the total number of devices is divisible by 4, the devices in the odd rows are mirrored along the X axis, and the devices in the odd columns are mirrored along the Y axis; when the total number of devices is divisible by 2, the devices in the odd rows are mirrored along the X axis; S04. The number of trunks in each row is calculated based on the total number of nets existing in the gate, source, and drain of the MOS field effect transistor. Then, the required twig length is calculated based on the preset routing constraints of the trunk, and the twig connection is generated. Then, the trunk connection required for the gate, source, and drain is generated. Next, the strap connection line required for the cross-row connection is generated, and the position of the matching net needs to be kept symmetrical and the parasitics are similar. Finally, the connection line between the gates needs to be crossed with the trunk layer and the strap layer.

2. A method for realizing automatic connection of differential pairs in analog layout according to claim 1, characterized in that: Step S02 also includes screening all feasible common divisors, and preferentially recommending solutions with even-numbered rows and the closest number of rows to columns for selection.

3. A method for realizing automatic connection of differential pairs in analog layout according to claim 1, characterized in that: In step S04, the trunk of the gate is limited within the width of the MOS field effect transistor; the trunks corresponding to the source and drain are pulled through within the entire width of the matching array, and the nets corresponding to the generated trunks are arranged in order.

4. A method for realizing automatic connection of differential pairs in analog layout according to claim 3, characterized in that: The order means that the common nets are arranged close to the gate trunk, and the non-common nets are arranged close to the common nets alternately according to the odd and even rows.

5. The method for realizing automatic connection of differential pairs in analog layout according to claim 1, characterized in that: In step S04, when generating the strap connection lines required for cross-row connection, the specific method of assigning the strap to each column is as follows: (1) Determine whether the number of device columns C is greater than or equal to the number of source and drain nets N; (2) If C is greater than or equal to N, then it is: There is one strap line in each column, for a total of C strap lines. If the number of columns C is even: arrange all nets in order from C / 2 to 1; arrange all nets in reverse order from C / 2 to C; If the number of columns C is an odd number, it is necessary to further determine whether the number of Nets N is an odd number; If N is odd: Place the public net in the (C+1) / 2th column; from the (C-1) / 2th column to the 1st column, arrange all the nets in a circular order starting from the non-public net; from the (C+1) / 2+1th column to the Cth column, arrange all the nets in a circular order starting from the non-public net; If N is even: Place a virtual strap in the (C+1) / 2th column; arrange all nets in a loop from the (C-1) / 2th column to the 1st column; arrange all nets in a loop in reverse order from the (C+1) / 2+1th column to the Cth column; (3) If C is greater than or equal to N, then it is not: Two strap lines are arranged in each column, for a total of 2C strap lines. All nets are arranged in a loop from the Cth to the 1st; all nets are arranged in a loop from the C+1th to the 2Cth in the reverse order.

6. A method for realizing automatic connection of differential pairs in analog layout according to claim 1, characterized in that: In step S04, after the strap connection line is generated, a Via is generated at the intersection node of the strap and trunk of the same net.

Images