Method and apparatus for image augmentation for wafer map

Abstract

The present disclosure describes methods and apparatus for image augmentation for a wafer map, where a method according to an aspect of the present disclosure includes: determining a first reference defect rate of a die having a first set of defects on a wafer based on existing wafer map data, where the first set of defects includes at least one die defect; for each spatial distribution mode in one or more preset defective tube core spatial distribution modes, new wafer map data is created, and in the created wafer map data, one or more defective tube core spatial distribution modes are created; marking dies randomly selected based on a first target defect rate within a die position range corresponding to the spatial distribution pattern on a wafer as having the first group of defects, and wherein the first target defect rate is obtained by amplifying the first reference defect rate by a specified multiple; and generating a wafer map in an image format according to the created wafer map data.

Description

Technical Field

[0001] The present disclosure relates to methods and apparatus for image augmentation for wafer maps. Background Art

[0002] A wafer map (also called a wafer diagram) is an effective means for visually displaying the differences in test results of individual semiconductor devices (die) on a semiconductor wafer. Each die on a wafer can be represented as a grid on the wafer map of the wafer, and the test results of a single die can be distinguished by different grid fill colors. As an example, the grid corresponding to a normal die that passes all tests may be green, while the grid corresponding to a defective die that fails all tests may be red. Furthermore, for defective dies, different colors may be assigned to the corresponding grids depending on the specific defect type determined by the test results.

[0003] The spatial distribution of these defective dies or their parts on the whole wafer presented by the wafer map can serve as an effective clue to analyze the specific causes of defects. For example, defects caused by a specific process or operation process may cause the spatial distribution of some defective dies on the whole wafer presented by the wafer map to show a specific pattern. There are many ways to distinguish these spatial distribution patterns presented on the wafer map, including manual identification based on human observation to automatic identification using computer vision technology, etc.

[0004] For solutions that utilize machine learning, especially deep learning technology, for example, using an image classification model based on a neural network (such as a convolutional neural network (CNN)) to classify wafer maps in image format (which serves as the input of the model) to identify different spatial distribution patterns, a large amount of training data is essential to ensure performance indicators such as the inference accuracy of the trained image classification model. Summary of the invention

[0005] In the Summary section, some selected concepts are introduced in a simplified form, which will be further elaborated in the Detailed Description section below. This Summary section is not intended to identify any key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0006] According to one aspect of the present disclosure, a method for image augmentation for a wafer map is provided, the method comprising: determining a first baseline defect rate of dies having a first group of defects on a wafer based on existing wafer map data, wherein the first group of defects includes at least one die defect; for each of one or more preset spatial distribution patterns of defective dies: creating new wafer map data, wherein, in the created wafer map data, dies randomly selected on the wafer within a range of die positions corresponding to the spatial distribution pattern based on a first target defect rate are marked as having the first group of defects, and wherein the first target defect rate is obtained by amplifying the first baseline defect rate by a specified multiple; and generating a wafer map in an image format based on the created wafer map data.

[0007] According to another aspect of the present disclosure, a computing device is provided, comprising: at least one processor; and a memory coupled to the at least one processor and used to store instructions, wherein the instructions, when executed by the at least one processor, cause the at least one processor to perform the method described in the present disclosure.

[0008] According to yet another aspect of the present disclosure, a computer-readable storage medium is provided, on which instructions are stored. When the instructions are executed by at least one processor, the at least one processor executes the method described in the present disclosure.

[0009] According to yet another aspect of the present disclosure, a computer program product is provided, comprising instructions, which, when executed by at least one processor, cause the at least one processor to perform the method described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Implementations of the present disclosure are illustrated by way of example and not limitation in the accompanying drawings in which like reference numerals designate the same or similar parts and in which:

[0011] Figure 1A , 1B shows an example of a wafer map according to some implementations of the present disclosure;

[0012] Figure 2 shows examples of wafer map data according to some implementations of the present disclosure;

[0013] Figure 3 A flowchart illustrating an exemplary method according to some implementations of the present disclosure is shown;

[0014] Figure 4 A block diagram illustrating an exemplary apparatus according to some implementations of the present disclosure; and

[0015] Figure 5 A block diagram of an exemplary computing device according to some implementations of the present disclosure is shown. DETAILED DESCRIPTION

[0016] In the following description, for the purpose of explanation, a large number of specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, these specific details are merely exemplary and non-restrictive, and it is apparent to those skilled in the art that the implementation of the present disclosure can be implemented without these specific details. In other examples, well-known circuits, structures, and techniques are not shown in detail to avoid unnecessarily affecting the understanding of the description.

[0017] References throughout the specification to "an implementation," "implementation," "exemplary implementations," "some implementations," "various implementations," etc., indicate that the implementations of the present disclosure described may include specific features, structures, or characteristics, however, it does not mean that every implementation must include these specific features, structures, or characteristics. In addition, some implementations may have some, all, or none of the features described for other implementations.

[0018] In a manner that is most helpful for understanding the claimed subject matter, various operations may be described as multiple discrete actions or processes in sequence. However, the order of description should not be interpreted as implying that these operations are necessarily dependent on this order. On the contrary, these operations may not be performed in the order presented. In some other implementations, various other operations may also be performed, and / or various operations that have been described may be ignored.

[0019] In the specification and claims, the phrase "A and / or B" may appear to mean one of the following: (A), (B), (A and B). Similarly, the phrase "A, B and / or C" may appear to mean one of the following: (A), (B), (C), (A and B), (A and C), (B and C), (A and B and C).

[0020] The spatial distribution of die with some types of defects across the wafer may show a specific pattern, which can be effectively presented through a graphical representation such as a wafer map. As an example of a spatial distribution pattern, in a column pattern, the die located in a specific column or columns on the wafer have a relatively concentrated number of defects, and in some cases these defects may be concentrated in a certain type or types. Other examples of spatial distribution patterns may also include: a row pattern, in which the die located in a specific row or rows on the wafer have a relatively concentrated number of defects; a center pattern, in which the die located in the central area on the wafer have a relatively concentrated number of defects; an annular pattern, in which the die located in an annular area on the wafer have a relatively concentrated number of defects; and so on.

[0021] Such spatial distribution patterns can also serve as effective clues for analyzing the specific causes of defects. For example, one spatial distribution pattern may be related to a specific process in the wafer manufacturing process, while another spatial distribution pattern may be related to the pick-and-place operation of a single die after wafer dicing. Therefore, accurately identifying the spatial distribution pattern presented on the wafer map becomes one of the important bases for defect or failure analysis.

[0022] The recognition or discrimination work can be done automatically using a deep learning-based image classification model. The trained image classification model takes a wafer map in image format as input, and the output can indicate whether the wafer map presents and what kind of spatial distribution pattern it presents. The image classification model needs to rely on a large number of training images to learn feature expressions during the training process. However, the reality is often that the wafer maps of a certain number of wafers are not enough to support good training.

[0023] Image augmentation is widely used to expand the size of training datasets for image classification models. Typical image augmentation usually generates new images by performing various transformations on the original images. Such transformations typically may include mirroring (reversing), cropping, scaling, rotation, color transformation, brightness adjustment, etc. However, using these conventional image augmentation techniques to transform existing wafer map images to generate new wafer map images to supplement the training dataset does not improve the performance of the image classification model used for the above purpose.

[0024] In view of this, the present disclosure proposes a method for image augmentation for a wafer map, the method comprising:

[0025] Determining a first baseline defect rate for dies on the wafer having a first set of defects based on the existing wafer map data, wherein the first set of defects includes at least one die defect;

[0026] For each of the one or more predetermined defective die spatial distribution patterns,

[0027] Fabric Pattern:

[0028] creating new wafer map data, wherein in the created wafer map data, randomly selected dies on the wafer within a range of die positions corresponding to the spatial distribution pattern based on a first target defect rate are marked as having the first set of defects, and wherein the first target defect rate is obtained by amplifying the first baseline defect rate by a specified multiple; and

[0029] A wafer map in an image format is generated based on the created wafer map data.

[0030] Hereinafter, an image augmentation mechanism for wafer maps proposed according to some implementations of the present disclosure will be discussed in detail with reference to the accompanying drawings and examples.

[0031] Figure 1A , 1B An example of a wafer map according to some implementations of the present disclosure is shown. Figure 1A , which may be a wafer map of an existing wafer, and the wafer may be a wafer used to manufacture a die product, and the die product may be, for example, a CPU die, a GPU die, an NPU die, a DRAM die, an NVRAM die, and the like, but the present disclosure is not limited thereto.

[0032] exist Figure 1A In the wafer map example shown, each rectangular grid corresponds to a die at a corresponding position on the wafer, wherein the dies indicated by the red rectangular grids are dies that have been tested and found to have defects of interest (also referred to as target defects). Defects of interest may include one or more of a variety of die defects that can be discovered through wafer testing and / or die testing, and this / these defects are the ones that should be focused on in the application scenarios of the present disclosure. The defects of interest mentioned here may, for example, correspond to the first group of defects mentioned above.

[0033] According to some implementations of the present disclosure, each die defect may correspond to a different bin code assigned to the individual die by a binning operation according to the test results. In one example, all of the dies indicated by the red grid may correspond to the same bin code; and in another example, the dies indicated by the red grid may correspond to multiple different bin codes, such as two, three, or even more.

[0034] exist Figure 1AIn the wafer map example shown, those dies indicated by the blue rectangular grid are dies that have been tested and found to have defects of no interest (also referred to as non-target defects). Defects of no interest refer to defects other than the aforementioned defects of interest. Similarly, defects of no interest may include one or more die defects. As an example, assume that wafer testing and / or die testing can be used to detect 30 different die defects (e.g., which may correspond to 30 different box codes), of which only 5 are identified as defects of interest, and the remaining 25 are classified as defects of no interest. The defects of no interest mentioned here may, for example, correspond to the second group of defects to be described below.

[0035] Furthermore, in some implementations, defects of interest may include all types of defects, and accordingly in this case, there are no defects of no interest.

[0036] In addition, Figure 1A In the wafer map example shown, those dies indicated by the green rectangular grid are the dies that have been tested and found to be defect-free, which in some implementations can indicate that these dies have passed all one or more tests. For example, the dies that have been tested and found to be defect-free are also assigned a specific bin code.

[0037] like Figure 1A As shown, the red grid on the wafer map shows that the spatial distribution of those dies with defects of interest on the entire wafer is approximately a unique annular pattern. This identification result can serve as an important basis for analyzing the specific cause of the defect.

[0038] Figure 1B It can be a wafer map of another existing wafer, which may be used to manufacture a different die product. Figure 1A The die products corresponding to the wafers. Figure 1A The color marking method is similar to Figure 1B In the wafer map example shown, those dies indicated by the red rectangular grid are dies that were tested and found to have defects of interest, those dies indicated by the blue rectangular grid are dies that were tested and found to have defects of no interest, and those dies indicated by the green rectangular grid are dies that were tested and found to be non-defective.

[0039] like Figure 1B As shown, the red grid on the wafer map shows that the spatial distribution of the dies with defects of interest on the entire wafer approximates a unique column pattern (here, the dies with defects of interest are concentrated in the 3rd, 6th, and 9th columns from the left). Similarly, this identification result can serve as an important basis for analyzing the specific cause of the defect.

[0040] In addition, Figure 1A , 1B In the example shown in FIG. 1 , three different colors, red, blue and green, are used. However, those skilled in the art should understand that other color schemes are also feasible, as long as the selected colors are relatively easy to distinguish visually.

[0041] Despite Figure 1A , 1B In the example of FIG. 1 , red, blue, and green are used to respectively show the distribution positions of the dies with defects of interest, the dies with defects of no interest, and the dies without defects on the entire wafer. However, according to some implementations of the present disclosure, the dies with defects of no interest may not be shown separately (in FIG. Figure 1A , 1B In some implementations, all dies on the wafer may be simply divided into dies with defects of interest and dies without defects of interest, the latter including the aforementioned dies with defects of no interest and dies without defects. In some implementations, for those dies without defects of interest, their corresponding grids may be uniformly displayed as green grids, or using another color different from the red used in the above example.

[0042] like Figure 1A , 1B The graphical representation of the wafer map shown may correspond to structured wafer map data. In some implementations, the structured wafer map data may be a data table or a portion of a data table, for example, it may be a separate spreadsheet file, or may be a table in a database, etc., however, the present disclosure is not limited thereto. Other forms of structured data are also possible.

[0043] Figure 2 An example of wafer map data according to some implementations of the present disclosure is shown, which may be structured wafer map data of an existing wafer. Figure 2 As shown, the structured data is in the form of a data table, which includes fields such as batch ID, wafer ID, die position X coordinate, die position Y coordinate, box code, defect classification, etc. from left to right.

[0044] Wafer ID is used to uniquely identify a wafer (in Figure 2 The batch ID can be used to uniquely identify the production batch to which the wafer belongs (in Figure 2Each die on the wafer is uniquely identified by a combination of the corresponding die position X coordinate and the die position Y coordinate. The reference position (i.e., the origin of the X-axis and the Y-axis) may refer to the position of the die at the exact center of the wafer, however, other reference position settings are also possible and the present disclosure is not prior to this. In addition, it should be understood that due to the shape of the wafer itself, there may be no die at the position corresponding to some values ​​of (X, Y).

[0045] The bin code field is used to indicate the bin code assigned to the corresponding individual die through binning according to the test results of wafer testing and / or die testing, which can be used as the basis for the subsequent defect classification field annotation. Figure 2 In the example, box code 200 indicates that the die is a non-defective die, box code 210 indicates that the die is a die with a first defect, box code 220 indicates that the die is a die with a second defect, and box code 230 indicates that the die is a die with a third defect. For ease of description, it is assumed that there are only these three types of defects.

[0046] The defect classification field is used to indicate which dies on the wafer have defects of interest, which have defects of no interest, and which are defect-free. It should be noted that in some implementations of the present disclosure, the marking of the latter two is optional.

[0047] exist Figure 2 In the example shown, the first and third defects corresponding to box codes 210 and 230 are defects of interest, and the die with the defects of interest are marked as 100 in the defect partition field; accordingly, the second defect corresponding to box code 220 is a defect of no interest, and the die with the defects of no interest is marked as a different value 010 in the defect partition field; box code 200 corresponds to a non-defective die, which is marked as another different value 000 in the defect partition field.

[0048] It should be understood that the various values ​​in the above examples are only given for the purpose of illustration and do not represent any practical meaning.

[0049] According to some implementations of the present disclosure, Figure 2 One or more fields in the data table shown are optional. For example, in some exemplary implementations, the data table may not include a separate batch ID field or even a wafer ID field. In other exemplary implementations, the bin code field may also be optional. In this case, as long as the location of each die on a wafer and the defect classification of the corresponding die can be determined based on such a data table, the structured wafer map data can be converted into the following. Figure 1A ,1B Graphical representation shown.

[0050] In addition, despite the Figure 2 An example of structured wafer map data is shown using a data table as an example, but according to some implementations of the present disclosure, the wafer map data may also be in the form of semi-structured data, such as a document in XML format, etc. For example, the position of each die on the wafer and its corresponding defect classification may be identified by setting corresponding tags.

[0051] Reference below Figure 3 , which shows a flow chart of an exemplary method 300 according to some implementations of the present disclosure. The exemplary method 300 is used to implement the mechanism for image augmentation for wafer maps described herein. Using this mechanism, a new wafer map image (similar to Figure 1A , 1B As shown in FIG. 3 , a large number of wafer map images generated in this way and capable of maintaining sufficient diversity are used to supplement or serve as a training data set, so that the corresponding deep learning-based image classification model can be better trained. It can be understood by those skilled in the art that method 300 can be implemented in software, hardware, firmware, or any combination thereof.

[0052] Method 300 begins at step 310, in which a first baseline defect rate of dies having a first set of defects on a wafer is determined based on existing wafer map data. According to some implementations of the present disclosure, the first set of defects may correspond to defects of interest, and the defects of interest may be a specific type of die defects, such as represented by a certain bin code; in other implementations, the defects of interest may also include more than one type of die defects, for example, the defects of interest may correspond to several different bin codes. That is, the first set of defects may include at least one die defect.

[0053] According to some implementations of the present disclosure, the existing wafer map data may be structured or semi-structured data as described above, and by reading the data, it may be determined which dies on the wafer have the first group of defects. In some implementations of the present disclosure, the first baseline defect rate refers to the ratio of dies on the wafer having the first group of defects to all dies on the wafer. As an example, for a wafer containing 200 dies, if 11 of the dies are dies with the first group of defects (for example, 7 dies may have one defect in the first group of defects, and the remaining 4 dies may have another defect in the first group of defects), the above ratio is 5.5%. In some implementations of the present disclosure, the ratio calculated in the above manner may also be applied to some rounding rules and other processing as needed.

[0054] According to some implementations of the present disclosure, in the case where wafer map data of multiple wafers are available, for example, wafer map data of k wafers that have actually been manufactured (these k wafers may include wafers used to manufacture at least one die product) are currently available, then the ratio of the dies with the first group of defects on the wafer to all the dies on the wafer can be counted based on the wafer map data of each of the wafers. As an example, for the first wafer among the k wafers, the ratio counted in this way is 5.5%; the ratio counted for the second wafer is 5%; the ratio counted for the third wafer is 7%..., and so on. Accordingly, after k ratio values ​​are counted for k wafers, the average value of these ratios (for example, 6.2%) can be calculated as the first benchmark defect rate.

[0055] After completing step 310 and determining a first baseline defect rate of dies with a first set of defects on a wafer, the method 300 may then proceed to perform subsequent processing for each of one or more preset defective die spatial distribution patterns.

[0056] According to some implementations of the present disclosure, the preset defective die spatial distribution pattern is a spatial distribution pattern associated with the first group of defects. According to some implementations of the present disclosure, the preset defective die spatial distribution pattern may include more than one spatial distribution pattern. As an example, the preset defective die spatial distribution pattern may include one or more of various known defective die spatial distribution patterns, including but not limited to various column patterns (wherein, the die located in one or more columns on a specific wafer have relatively concentrated defects), row patterns (wherein, the die located in one or more rows on a specific wafer have relatively concentrated defects), center patterns (wherein, the die located in the central area on the wafer have relatively concentrated defects), annular patterns (wherein, the die located in an annular area on the wafer have relatively concentrated defects), and the like.

[0057] As an example, a preset defective die spatial distribution pattern may indicate that defects are concentrated in the dies in the 3rd, 6th, and 9th columns on the wafer (for example, this can be identified by the die position X coordinate in the wafer map data structure); another preset defective die spatial distribution pattern may indicate that defects are concentrated in the dies in the 3rd, 4th, and 7th columns on the wafer; a third preset defective die spatial distribution pattern may indicate that defects are concentrated in the dies in the 10th column on the wafer; yet another spatial distribution pattern may indicate that defects are concentrated in the 5th and 7th rows on the wafer (for example, this can be identified by the die position Y coordinate in the wafer map data structure), and so on.

[0058] Each preset defective die spatial distribution pattern can indicate the position range of the dies corresponding to the pattern on the wafer in a rule-based manner.

[0059] Returning to method 300, for each of the one or more preset defective die spatial distribution patterns, the method 300 may perform step 320. In this step, new wafer map data is created, wherein in the created wafer map data, dies randomly selected on the wafer based on the first target defect rate within the die position range corresponding to the spatial distribution pattern are marked as having the first group of defects.

[0060] According to some implementations of the present disclosure, the new wafer map data may have the same Figure 2 The wafer map data for existing wafers described in the same or similar format as those described in its variants may be expressed in the form of structured data or semi-structured data, for example, by identifying the position of each die on the wafer (which can be uniquely identified by position coordinates (X, Y)) through fields or labels.

[0061] According to some implementations of the present disclosure, for a specific spatial distribution pattern, the dies that belong to the position range can be found based on the position range specified by the spatial distribution pattern (continuing the previous example, the pattern specifies the 3rd, 6th, and 9th columns on the wafer, which can correspond to a specific column pattern) and the die position coordinates contained in the new wafer map data. Accordingly, a certain number of dies are randomly selected from those dies that belong to the position range and are marked as having the first set of defects. This result can be marked in the defect partitioning information (e.g., field or label) of the newly created wafer map data.

[0062] More specifically, the above-mentioned random selection is performed based on the first target defect rate. Different from the first baseline defect rate determined in step 310, the first target defect rate is obtained by amplifying the first baseline defect rate by a specified multiple. As an example, the first baseline defect rate is 6.2%, and the first target defect rate is 5 times larger, that is, 31%. In other words, for those dies in the position range specified by the spatial distribution pattern, the dies randomly selected based on the ratio of 31% are marked as having the first set of defects. According to some implementations of the present disclosure, the specified multiple may be a value selected between 5-10. In some implementations, the specified multiple may vary depending on the different spatial distribution patterns.

[0063] According to some implementations of the present disclosure, in the created wafer map data, whether each die within the die position range corresponding to the spatial distribution pattern on the wafer is selected obeys a binomial distribution with n and p as parameters, where n is equal to 1 and p corresponds to a probability, which is the first target defect rate here. In this way, within the position range corresponding to a spatial distribution pattern on the wafer, a certain number of dies are randomly selected and marked as having the first set of defects.

[0064] Next, method 300 proceeds to step 330, in which a wafer map in image format is generated based on the wafer map data created in step 320. The specific selection of the image format is not limited in the present disclosure; in a preferred implementation, all wafer maps generated using the mechanism described in the present disclosure uniformly adopt the same format. According to some implementations of the present disclosure, in the generated wafer map in image format, the grids corresponding to the tube cores having the first group of defects are represented as red grids. In addition, according to some implementations of the present disclosure, step 330 may also include generating the wafer map in the image format at a specified resolution, or may include converting the generated wafer map in the image format to a specified resolution, so as to achieve image standardization of the wafer map.

[0065] Based on the existing wafer map data, for a specific spatial distribution pattern, the exemplary method 300 can generate a new wafer map that conforms to the pattern. According to some implementations of the present disclosure, the operation of creating new wafer map data in step 320 and the operation of generating a wafer map in an image format in step 330 can be repeatedly performed in sequence until a specified number of wafer maps that conform to the requirements are obtained for a spatial distribution pattern.

[0066] In the process of repeating the above operation, since which tube cores on the wafer will be marked as having the first group of defects are randomly selected based on the first target defect rate each time step 320 is executed, although each marking is performed on the tube cores within the position area corresponding to a spatial distribution pattern, the marking results will be different each time. For example, in the third column, the three tube cores in the 1st, 3rd, and 7th rows are selected for the first time, and the three tube cores in the 1st, 2nd, and 5th rows may be selected for the second time, and the two tube cores in the 6th and 8th rows may be selected for the third time, and so on. Therefore, a large number of new wafer maps generated based on such marking results ensure sufficient differences on the basis of complying with the requirements of the spatial distribution pattern.

[0067] For the situation where there are multiple preset spatial distribution patterns, for example, there may be more than a dozen, dozens, or even more, a required number of wafer maps can be obtained for each spatial distribution pattern, thereby effectively achieving large-scale image augmentation for wafer maps that comply with these preset spatial distribution patterns.

[0068] In addition, according to some implementations of the present disclosure, in addition to making annotations related to the first group of defects in the created wafer map data in step 320, randomly selected dies on the wafer based on the first baseline defect rate outside the die position range corresponding to the spatial distribution pattern may be annotated as having the first group of defects in the created wafer map data. Continuing with reference to an example, the current spatial distribution pattern specifies columns 3, 6, and 9, in which randomly selected dies based on a higher first target defect rate (e.g., in this example, 6.2%*5=31%) are annotated as having the first group of defects, which makes the spatial distribution pattern more prominent in the correspondingly generated wafer map; and for those dies in other columns on the wafer other than these three columns, randomly selected dies based on a lower first baseline defect rate (6.2% in this example) are annotated as having the first group of defects, thereby effectively increasing the noise.

[0069] According to some implementations of the present disclosure, in the created wafer map data, whether each tube core on the wafer outside the position range corresponding to the spatial distribution pattern is selected and marked as having the first set of defects obeys a binomial distribution with n and p as parameters, where n is equal to 1 and p here is the first baseline defect rate.

[0070] In addition, according to some implementations of the present disclosure, method 300 may further include: Figure 3 (not shown): determining a second baseline defect rate of dies having a second group of defects on the wafer based on the existing wafer map data, wherein the second group of defects includes other die defects in addition to at least one die defect included in the first group of defects. The first group of defects may correspond to defects of interest, and the training data set expanded by the image augmentation mechanism described in this article may be used to train an image classification model to accurately identify the spatial distribution pattern exhibited by dies having defects of interest in the wafer map image as input; the second group of defects may correspond to defects of no interest, i.e., defects other than the defects of interest. The calculation method of the second baseline defect rate is similar to that of the first baseline defect rate, and will not be repeated here.

[0071] According to some implementations of the present disclosure, before making annotations related to the first set of defects in step 320, randomly selected dies from all dies on the wafer based on the second baseline defect rate are annotated as having the second set of defects in the created wafer map data. According to some implementations of the present disclosure, whether each die on the entire wafer is selected and annotated as having the second set of defects follows a binomial distribution with n and p as parameters, where n is equal to 1 and p is the second baseline defect rate.

[0072] It should be understood that the results of the annotations related to the second set of defects will be overwritten by the results of the annotations related to the first set of defects. In addition, according to some implementations of the present disclosure, in the generated wafer map in the image format, the grids corresponding to the dies with the second set of defects are represented as blue grids.

[0073] Furthermore, according to some implementations of the present disclosure, before making the annotations related to the second set of defects as described above, all the dies on the wafer are marked as non-defective in the created wafer map data. That is, these dies are considered to be non-defective dies by default. It should also be understood here that the results of the annotations related to non-defective will be overwritten by the results of the annotations related to the second set of defects. Furthermore, according to some implementations of the present disclosure, in the generated wafer map in image format, the grids corresponding to the non-defective dies are represented as green grids. The wafer map in image format thus generated is similar to Figure 1A , 1B Example shown.

[0074] Reference below Figure 4 , which shows a block diagram of an exemplary apparatus 400 according to some implementations of the present disclosure. The exemplary apparatus 400 is used to implement the mechanism for image augmentation for wafer maps described herein. It will be appreciated by those skilled in the art that the apparatus 400 may be implemented in software, hardware, firmware, or any combination thereof.

[0075] like Figure 4As shown, the device 400 may include a module 410 for determining a first baseline defect rate of dies having a first group of defects on a wafer based on existing wafer map data, wherein the first group of defects includes at least one die defect. The device 400 may also include a module 420 for creating new wafer map data for each of one or more preset spatial distribution patterns of defective dies, wherein in the created wafer map data, dies randomly selected on the wafer based on a first target defect rate within a die position range corresponding to the spatial distribution pattern are marked as having the first group of defects, and wherein the first target defect rate is obtained by amplifying the first baseline defect rate by a specified multiple. In addition, the device may also include a module 430 for generating a wafer map in an image format according to the created wafer map data for the spatial distribution pattern.

[0076] In some implementations of the present disclosure, the apparatus 400 may further include additional modules for performing other operations described in the specification, such as combining Figure 3 In addition, in some implementations, the various modules of the apparatus 400 may be combined or split depending on actual needs without departing from the scope of the present disclosure.

[0077] Figure 5 A block diagram of an exemplary computing device 500 is shown in accordance with some implementations of the present disclosure. The exemplary computing device 500 is used to implement the mechanisms described herein for image augmentation for wafer maps.

[0078] like Figure 5 As shown, the computing device 500 may include at least one processor 510. The processor 510 may include any type of general-purpose processing unit (such as a CPU, GPU), a dedicated processing unit, a core, a circuit, a controller, etc. In addition, the computing device 500 may also include a memory 520. The memory 520 may include any type of medium that can be used to store data. In some implementations, the memory 520 is configured to store instructions that, when executed by the at least one processor 510, cause the processor 510 to perform the operations described herein, for example, in conjunction with Figure 3 Those operations are described with reference to a flowchart of exemplary operations 300 and various variations thereof.

[0079] Furthermore, in some implementations, the computing device 500 is also equipped with a communication interface, which can support various types of wired / wireless communication protocols to communicate with a communication network.

[0080] Those skilled in the art will appreciate that the above description of the structure of the computing device 500 is merely exemplary and not restrictive, and devices with other structures are also feasible as long as they can be used to implement the functions described herein.

[0081] Various implementations of the present disclosure may include or operate multiple components, parts, units, modules, instances or mechanisms, which may be implemented in hardware, software, firmware, or any combination thereof. Examples of hardware may include, but are not limited to: devices, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), storage units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software may include, but are not limited to: software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, software modules, routines, subroutines, functions, methods, processes, software interfaces, application programming interfaces (APIs), instruction sets, computer codes, computer code segments, words, values, symbols, or any combination thereof. Determining whether an implementation is performed using hardware, software, and / or firmware can vary depending on a variety of factors, such as desired computational rates, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints as desired for a given implementation.

[0082] Some implementations described herein may include articles of manufacture. Articles of manufacture may include storage media. Examples of storage media may include volatile and non-volatile, removable and non-removable media implemented by any method or technology to store information (e.g., computer-readable instructions, data structures, program modules, or other data). Storage media may include, but are not limited to: random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other semiconductor memory, compact disk (CD), digital versatile disk (DVD) or other optical storage, cassette, tape, disk storage or other magnetic storage device, or any other medium capable of storing information. In some implementations, articles of manufacture may store executable computer program instructions that, when executed by one or more processing units, cause the processing units to perform the operations described herein. Executable computer program instructions may include any suitable type of code, for example, source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. Executable computer program instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language.

[0083] Some exemplary implementations of the present disclosure are described below.

[0084] Example 1 describes a method for image augmentation for a wafer map, the method comprising: determining a first baseline defect rate of dies having a first group of defects on a wafer based on existing wafer map data, wherein the first group of defects includes at least one die defect; for each of one or more preset defective die spatial distribution patterns: creating new wafer map data, wherein, in the created wafer map data, dies randomly selected on the wafer within a range of die positions corresponding to the spatial distribution pattern based on a first target defect rate are marked as having the first group of defects, and wherein the first target defect rate is obtained by amplifying the first baseline defect rate by a specified multiple; and generating a wafer map in an image format based on the created wafer map data.

[0085] Example 2 may include the subject matter described in Example 1, wherein determining a first baseline defect rate of die having a first set of defects on a wafer based on existing wafer map data comprises: counting the ratio of die having the first set of defects on the wafer to all die on the wafer based on wafer map data of each wafer in the existing wafer map data of multiple wafers; and calculating the average value of the ratios corresponding to the multiple wafers as the first baseline defect rate.

[0086] Example 3 may include the subject matter of any one of Examples 1-2, the method further comprising: repeatedly performing the operations of labeling and generating in sequence until a specified number of wafer maps in image format are generated for the spatial distribution pattern.

[0087] Example 4 may include the subject matter of any one of Examples 1-3, the method further comprising: determining a second baseline defect rate of dies on the wafer having a second set of defects based on the existing wafer map data, wherein the second set of defects includes other die defects in addition to at least one die defect included in the first set of defects, and wherein, before making annotations related to the first set of defects, randomly selected dies from all dies on the wafer based on the second baseline defect rate are annotated as having the second set of defects in the created wafer map data.

[0088] Example 5 may include the subject matter of Example 4, wherein prior to making annotations associated with the second set of defects, all dies on the wafer are annotated as non-defective in the created wafer map data.

[0089] Example 6 may include the subject matter of Example 5, wherein, in a wafer map in an image format generated based on the created wafer map data, grids corresponding to defect-free dies are represented as green grids, grids corresponding to dies having the second set of defects are represented as blue grids, and grids corresponding to dies having the first set of defects are represented as red grids.

[0090] Example 7 may include the subject matter of any one of Examples 1-6, wherein, in the created wafer map data, randomly selected dies on the wafer outside the die position range corresponding to the spatial distribution pattern based on the first baseline defect rate are marked as having the first set of defects, and wherein whether each die on the wafer within the die position range corresponding to the spatial distribution pattern is selected and marked as having the first set of defects follows a binomial distribution with a probability of the first target defect rate, and whether each die on the wafer outside the die position range corresponding to the spatial distribution pattern is selected and marked as having the first set of defects follows a binomial distribution with a probability of the first baseline defect rate.

[0091] Example 8 describes a computing device comprising: at least one processor; and a memory coupled to the at least one processor and used to store instructions, wherein the instructions, when executed by the at least one processor, cause the at least one processor to perform a method according to any one of the aforementioned Examples 1-7.

[0092] Example 9 describes a computer-readable storage medium having instructions stored thereon, which, when executed by at least one processor, causes the at least one processor to perform a method according to any one of the aforementioned examples 1-7.

[0093] Example 10 describes a computer program product comprising instructions, which, when executed by at least one processor, cause the at least one processor to perform the method according to any one of the preceding examples 1-7.

[0094] Example 11 describes an apparatus comprising a module for performing the method described in any one of the preceding Examples 1-7.

[0095] What has been described above includes examples of the disclosed architecture. It is certainly not possible to describe every conceivable combination of components and / or methods, but those skilled in the art will appreciate that many other combinations and permutations are possible. Therefore, the novel architecture is intended to encompass all such substitutions, modifications, and variations that fall within the spirit and scope of the appended claims.

Claims

1. A method for image augmentation for a wafer map, the method comprising: Determining a first baseline defect rate for dies on the wafer having a first set of defects based on the existing wafer map data, wherein the first set of defects includes at least one die defect; For each of the one or more predetermined defective die spatial distribution patterns: creating new wafer map data, wherein in the created wafer map data, randomly selected dies on the wafer within a range of die positions corresponding to the spatial distribution pattern based on a first target defect rate are marked as having the first set of defects, and wherein the first target defect rate is obtained by amplifying the first baseline defect rate by a specified multiple; and A wafer map in an image format is generated based on the created wafer map data.

2. The method according to claim 1, wherein: Determining a first baseline defect rate for dies having a first set of defects on a wafer based on the existing wafer map data includes: Based on the wafer map data of each wafer among the existing wafer map data of the plurality of wafers, counting the ratio of the dies having the first group of defects on the wafer to all the dies on the wafer; An average value of the ratios corresponding to the plurality of wafers is calculated as the first reference defect rate.

3. The method according to claim 1, further comprising: The operations of marking and generating are repeatedly performed in sequence until a specified number of wafer maps in image format are generated for the spatial distribution pattern.

4. The method according to claim 1, further comprising: determining a second baseline defect rate of dies on the wafer having a second set of defects based on the existing wafer map data, wherein the second set of defects includes other die defects in addition to at least one die defect included in the first set of defects, and Before making annotations related to the first group of defects, randomly selected dies from among all dies on the wafer based on the second baseline defect rate are annotated as having the second group of defects in the created wafer map data.

5. The method according to claim 4, wherein: Prior to making annotations associated with the second set of defects, all dies on the wafer are annotated as non-defective in the created wafer map data.

6. The method according to claim 5, wherein: In the wafer map in image format generated based on the created wafer map data, the grids corresponding to the defect-free dies are represented as green grids, the grids corresponding to the dies with the second set of defects are represented as blue grids, and the grids corresponding to the dies with the first set of defects are represented as red grids.

7. The method according to claim 1, wherein: In the created wafer map data, randomly selected dies on the wafer outside the die position range corresponding to the spatial distribution pattern based on the first baseline defect rate are marked as having the first set of defects, and Among them, whether each tube die on the wafer within the tube die position range corresponding to the said spatial distribution pattern is selected and marked as having the first group of defects obeying the binomial distribution with the probability of the first target defect rate, and whether each tube die on the wafer outside the tube die position range corresponding to the said spatial distribution pattern is selected and marked as having the first group of defects obeying the binomial distribution with the probability of the first benchmark defect rate.

8. A computing device, comprising: at least one processor; as well as A memory, coupled to the at least one processor and configured to store instructions, wherein when the instructions are executed by the at least one processor, the at least one processor is enabled to perform the method according to any one of claims 1 to 7.

9. A computer-readable storage medium having instructions stored thereon, wherein when the instructions are executed by at least one processor, the at least one processor executes the method according to any one of claims 1 to 7.

10. A computer program product comprising instructions, which, when executed by at least one processor, cause the at least one processor to perform the method according to any one of claims 1 to 7.

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