Driving circuit and control method thereof, display panel, controller and display device

Abstract

The invention provides a driving circuit and a control method thereof, a display panel, a controller and a display device. Relates to the technical field of driving display. The driving circuit comprises a first sub-circuit used for outputting a grouping control signal under the action of a first driving signal and a first clock signal, and the grouping control signal is used for controlling whether two adjacent rows of pixel circuits are driven at the same time or not; one end of the second sub-circuit is electrically connected with the first sub-circuit, the other end of the second sub-circuit is used for being electrically connected with a pixel circuit, and the second sub-circuit is used for outputting a line scanning signal under the action of the grouping control signal. The rendering signal is generated under the action of the first driving signal by using the hardware circuit so as to drive the pixel circuit to complete corresponding display without waiting for a display driving integrated circuit to generate all rendering signals, so that the rendering efficiency is greatly improved, and the power consumption of the circuit is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of drive display technology, and more specifically, to a drive circuit, a display panel, a control method of the drive circuit, a controller and a display device. Background Art

[0002] Foveated rendering is a device performance optimization technology that can concentrate resources on rendering the display area that the human eye is looking at. The area where the human eye is looking can be rendered at high resolution, and the peripheral area of ​​the area where the eye is looking can be rendered at low resolution. In this way, the resources used to render the scene can be reduced, while ensuring that there is no loss in the area where the eye is looking, and the user's visual experience will not be affected. In the prior art, the display driver integrated circuit (DDIC) generally generates all the rendering signals corresponding to the above-mentioned partition rendering based on the eye movement signal, and then gives the rendering signal to the drive circuit to drive the pixel circuit to complete the corresponding display. To a certain extent, the efficiency of the foveated rendering is reduced, affecting the user's experience. At the same time, for different DDICs, if the original drive circuit cannot complete the driving of the pixel circuit under the action of the rendering signal, an additional drive circuit matching it must be added, which significantly increases the circuit power consumption and wastes resources.

[0003] Therefore, a new technical solution is urgently needed to solve the above technical problems. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present invention provides a driving circuit, comprising:

[0006] The first subcircuit is used to output a grouping control signal under the action of a first driving signal and a first clock signal, wherein the grouping control signal is used to control whether two adjacent rows of pixel circuits are driven simultaneously, and the period of the first clock signal is the refresh time of a row of pixel circuits. x is a natural number greater than 1;

[0007] The second sub-circuit has one end electrically connected to the first sub-circuit, and the other end electrically connected to the pixel circuit. The second sub-circuit is used to output a row scanning signal under the action of a grouping control signal.

[0008] In some embodiments, the first subcircuit includes: a first trigger and a second trigger electrically connected;

[0009] The first trigger is used to output a first control signal under the action of a first clock signal and a first trigger signal;

[0010] The second trigger is used to output a grouping control signal under the action of the first control signal and the first driving signal.

[0011] In some implementations, the first control signal is a clock trigger signal of the second flip-flop, and the first control signal is a single pulse signal.

[0012] In some embodiments, the driving circuit includes N levels, the n-th level driving circuit includes an n-th level first subcircuit and an n-th level second subcircuit, the n-th level second subcircuit includes an n-th level first branch and an n-th level second branch, the n-th level first branch is used to output a row scanning signal of the n-th row pixel circuit under the action of a grouping control signal provided by the n-th level first subcircuit, the n-th level second branch is used to output a row scanning signal of the n-th row pixel circuit under the action of a grouping control signal provided by the n-th level first subcircuit, and the n-th level second branch is also used to output a row scanning signal of the n+1-th row pixel circuit under the action of a grouping control signal provided by the n-th level first subcircuit.

[0013] In some embodiments, the first trigger of the first subcircuit of the nth level is electrically connected to the first trigger of the first subcircuit of the n+1th level, and the first trigger of the first subcircuit of the nth level is used to transmit a first control signal to the first trigger of the first subcircuit of the n+1th level, and the first control signal is a first trigger signal of the first trigger of the first subcircuit of the n+1th level, wherein N and n are both natural numbers greater than 0, and n+1≤N.

[0014] In some embodiments, the first trigger and the second trigger are used to reset under the action of a reset signal, and the effective level end point of the reset signal is before the effective level start points of the first trigger signal, the first control signal, and the first drive signal.

[0015] In some embodiments, the first subcircuit of the first level includes a first transmission gate, which is used to transmit a frame start signal to a first trigger, the frame start signal is a first trigger signal received by the first trigger of the first level, and the first transmission gate is used to be turned on or off under the action of a rendering start signal.

[0016] In some implementations, a valid level start point of the rendering start signal is after a valid level end point of the reset signal, and a valid level end point of the rendering start signal is before a valid level start point of the first driving signal.

[0017] In some embodiments, the second sub-circuit includes a second transmission gate, a third transmission gate, a fourth transmission gate, a third flip-flop, and a fourth flip-flop;

[0018] The second transmission gate is electrically connected to the third transmission gate and the third trigger respectively, and is used to output a second trigger signal to the third transmission gate and the third trigger when being turned on;

[0019] The third transmission gate is electrically connected to the third trigger and the fourth trigger respectively, the fourth transmission gate is electrically connected to the third trigger and the fourth trigger respectively, the third transmission gate is electrically connected to the fourth transmission gate, and the third transmission gate and the fourth transmission gate are both used to be turned on or off under the action of the grouping control signal;

[0020] When the third transmission gate is turned on and the fourth transmission gate is turned off, the third transmission gate outputs a second trigger signal to the fourth flip-flop;

[0021] When the fourth transmission gate is turned on and the third transmission gate is turned off, the fourth transmission gate outputs a second control signal to the fourth flip-flop, wherein the second control signal is output by the third flip-flop under the triggering of the second trigger signal and the second clock signal.

[0022] In some embodiments, the second sub-circuit also includes a fifth transmission gate electrically connected between the fourth trigger and the third transmission gate, the fifth transmission gate is used to be turned on or off under the action of the second drive signal, and the second transmission gate is used to be turned on or off under the action of the second drive signal.

[0023] In a second aspect, a display panel is also proposed, comprising:

[0024] A drive circuit as described above;

[0025] Pixel circuit, the number of rows of pixel circuit is greater than the number of stages of driving circuit.

[0026] In a third aspect, a control method of a driving circuit is also proposed, which is applied to the driving circuit as described above, and the control method includes:

[0027] The first subcircuit is controlled to output a grouping control signal under the action of the first driving signal and the first clock signal, wherein the grouping control signal is used to control whether two adjacent rows of pixels are driven simultaneously, and the period of the first clock signal is the refresh time of a row of pixel circuits. x is a natural number greater than 1;

[0028] The second sub-circuit is controlled to output a row scanning signal to the pixel circuit under the action of the grouping control signal.

[0029] In some implementations, before controlling the first sub-circuit to output the grouping control signal under the action of the first driving signal and the first clock signal, the method further includes:

[0030] The first trigger and the second trigger are controlled to be reset under the action of a reset signal, and the effective level end point of the reset signal is before the effective level start points of the first trigger signal, the first control signal and the first drive signal.

[0031] In some embodiments, the method further comprises:

[0032] When the first transmission gate is turned on by the rendering start signal, the first transmission gate is controlled to transmit the frame start signal to the first trigger, and the frame start signal is the first trigger signal received by the first trigger of the first stage.

[0033] In some implementations, a valid level start point of the rendering start signal is after a valid level end point of the reset signal, and a valid level end point of the rendering start signal is before a valid level start point of the first driving signal.

[0034] In some embodiments, the method further comprises:

[0035] The second transmission gate and the fifth transmission gate are controlled to be turned on or off under the action of the second driving signal.

[0036] In a fourth aspect, a controller is also proposed, comprising:

[0037] a memory storing a computer program;

[0038] The processor is used to call the computer program in the memory, and the computer program is used to execute the control method as described above.

[0039] In a fifth aspect, a display device is also proposed, comprising the display panel as described above and / or the controller as described above.

[0040] In some embodiments, the display device further comprises:

[0041] A driving chip, the driving chip is electrically connected to a driving circuit of the display panel;

[0042] The control main board is electrically connected to the driver chip.

[0043] According to the above technical solution, the pixel circuits are quickly grouped under the action of the first drive signal and the first clock signal by a driving circuit having the above hardware circuit structure, ensuring that more grouping control signals are prepared before display to control whether two adjacent rows of pixel circuits in the grouped pixel circuits are driven at the same time, and then different row scanning signals are output. The row scanning signal and the data signal are combined so that the same group of pixel circuits can display the same content at the same time. For the non-attention area, that is, the case where multiple rows of pixel circuits are a group, since multiple rows of pixel circuits display the same content, the effect of rendering and displaying the non-attention area at a low resolution is achieved. For the attention area, that is, the case where a row of pixel circuits is a group, since only a row of pixel circuits is used to display the corresponding content, a high-resolution display effect is achieved. In the process of using DDIC for gaze point rendering, all rendering signals are first generated based on the eye movement signal, and then the rendering signal is given to the driving circuit so that the driving circuit drives the pixel circuit to complete the corresponding display. In the above-mentioned embodiment of the present disclosure, the eye tracking signal is first converted into a first driving signal by using DDIC, and then a rendering signal is generated by using a hardware circuit under the action of the first driving signal to drive the pixel circuit to complete the corresponding display, without waiting for DDIC to generate all the rendering signals, which greatly improves the rendering efficiency. In addition, the rendering signal is directly generated by the driving circuit, and there is no need to add an additional driving circuit that matches DDIC and is used to receive the rendering signal, which effectively reduces the circuit power consumption.

[0044] The driving circuit of the present invention, other advantages, objectives and features of the present invention will be reflected in part through the following description, and in part will be understood by those skilled in the art through research and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0047] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the exemplary embodiments below. The accompanying drawings are only for the purpose of illustrating exemplary embodiments and are not to be considered as limiting the present disclosure. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0048] Figure 1 A schematic structural block diagram of a driving circuit provided in an embodiment of the present disclosure;

[0049] Figure 2 A schematic circuit structure diagram of a first sub-circuit provided in an embodiment of the present disclosure;

[0050] Figure 3 A schematic structural block diagram of another driving circuit provided in an embodiment of the present disclosure;

[0051] Figure 4 A schematic circuit structure diagram of another first sub-circuit provided in an embodiment of the present disclosure;

[0052] Figure 5 A schematic circuit structure diagram of a second sub-circuit provided in an embodiment of the present disclosure;

[0053] Figure 6 A driving timing diagram of a driving circuit provided in an embodiment of the present disclosure;

[0054] Figure 7 A schematic structural block diagram of a display panel provided in an embodiment of the present disclosure;

[0055] Figure 8 A schematic flow chart of a control method of a driving circuit provided in an embodiment of the present disclosure;

[0056] Fig. 9 A schematic structural block diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0058] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments.

[0059] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0060] Usually, DDIC generates all rendering signals corresponding to the partition rendering based on the eye movement signal, and then gives the rendering signal to the driving circuit to drive the pixel circuit to complete the corresponding display. For different DDICs, if the original driving circuit cannot drive the pixel circuit under the action of the rendering signal, an additional driving circuit matching it must be added, which significantly increases the circuit power consumption and wastes resources. In addition, the work of DDIC and the driving circuit is completely independent of time-sharing, that is, DDIC must first complete the generation of all rendering signals before it can transmit the generated rendering signal to the driving circuit. Only after the driving circuit receives the rendering signal can it drive the pixel circuit to complete the corresponding display. During the period when DDIC generates the rendering signal, the driving circuit is in the stage of waiting for the signal response. The duration of this stage is affected by the performance of DDIC, which seriously affects the efficiency of the entire gaze point rendering display, resulting in display delays and affecting the user experience.

[0061] In order to solve the above technical problem, according to a first aspect of the present disclosure, a driving circuit is proposed. Figure 1 A schematic structural block diagram of a driving circuit provided in an embodiment of the present disclosure. For example, see Figure 1 The driving circuit 100 may include: a first subcircuit 110 and a second subcircuit 120. The first subcircuit 110 is used to output a grouping control signal under the action of a first driving signal and a first clock signal, wherein the grouping control signal is used to control whether two adjacent rows of pixel circuits are driven simultaneously.

[0062] It should be noted that in the gaze point rendering technology, as the human eye moves, the display area can be divided into a gaze area and a non-gaze area. For the gaze area, it can be rendered and displayed at a high resolution. For the non-gaze area, it can be rendered and displayed at a low resolution. Exemplarily, the user's eye movement can be tracked by any existing or future technical means, so as to obtain an eye tracking signal using a device such as a display driver integrated circuit. The eye tracking signal can be subjected to signal processing and other operations to obtain and send a first drive signal to the first sub-circuit. Exemplarily, the first drive signal can be obtained by the eye tracking signal as described above, or it can be obtained in response to a user's input instruction. In some embodiments, the user can input an area division instruction through an input device such as a touch screen, and based on the area division instruction, the area circled by the user can be determined as a gaze area, and other uncircled areas can be determined as non-gaze areas, thereby obtaining a first drive signal. The first drive signal can be understood as an input signal for indicating the division of the display area into a gaze point area and a non-gaze point area, and can be obtained in a variety of forms. The above embodiments are merely exemplary and do not mean a limitation on the first drive signal. Exemplarily, see Figure 1 , the first drive signal FRD_IN and the first clock signal FRD_CKV can be transmitted to the first sub-circuit 110. Under the action of the first drive signal FRD_IN and the first clock signal FRD_CKV, the first sub-circuit 110 can divide the row pixels of the pixel circuit 200, for example, into the row pixels of the attention area and the row pixels of the non-attention area, thereby outputting the corresponding grouping control signal EN_GRP. Exemplarily, the period of the first clock signal is the refresh time of a row of pixel circuits. x is a natural number greater than 1. The refresh time of a row of pixel circuits is the row period H, and the period of the first clock signal can be x can be a natural number greater than 1, such as 2, 3 or 4. Taking x=3 as an example, the period of the first clock signal is Therefore, the first driving signal can be read three times in one row period, and a corresponding group control signal can be generated. In some embodiments, the group control signal can be used to achieve simultaneous driving of 3+1=4 rows of pixel circuits.

[0063] Therefore, in one row period, compared with a common clock signal with a period equal to the row period, using a first clock signal with a faster period as a clock trigger signal of the first sub-circuit can ensure that it generates more group control signals in one row period, ensuring that more group control signals are prepared before display, and realizing simultaneous driving of multiple rows of pixel circuits.

[0064] The value of the grouping control signal EN_GRP can determine the synchronization of the output signal, that is, whether two adjacent rows of pixel circuits are driven simultaneously. When the grouping control signal EN_GRP=0, the two adjacent rows of pixel circuits are not driven simultaneously; when the grouping control signal EN_GRP=1, the two adjacent rows of pixel circuits are driven simultaneously.

[0065] Exemplarily, for the pixel row in the attention area, a row of pixel circuits may be included, that is, each row of pixel circuits is driven and displayed separately as a group of pixel circuits. In this case, the adjacent pixel circuits of the row of pixel circuits belong to different groups of pixel circuits. Therefore, a grouping control signal with a value of 0 may be generated. When the value of the grouping control signal is 0, the pixel circuits of the row and the pixel circuits adjacent to the row of pixel circuits may be controlled to be driven in a time-sharing manner.

[0066] Exemplarily, for the non-attention area row pixels, multiple rows of pixel circuits may be included. That is, multiple rows of pixel circuits are driven and displayed together as a group of pixel circuits, and multiple rows of pixel circuits can display the same content. In this case, a grouping control signal with a value of 1 may be generated. When the value of the grouping control signal is 1, two adjacent rows of pixel circuits in the group of pixel circuits may be controlled to be driven simultaneously. Two adjacent rows of pixel circuits in the pixel circuits of the groups are not driven at the same time, that is, the pixel circuits in different groups are not driven at the same time, and the pixel circuits in the same group are driven at the same time.

[0067] It should be noted that when two adjacent rows of pixel circuits are driven simultaneously, it can be indicated that the gates of the driving transistors of the two adjacent rows of pixel circuits are turned on or off at the same time, that is, the conduction and cutoff conditions of the two adjacent rows of pixel circuits are synchronized, and then when the two adjacent rows of pixel circuits are turned on, the two adjacent rows of pixel circuits can read the same display data and output the corresponding display results to achieve the effect of gaze point rendering. When the two adjacent rows of pixel circuits are not driven simultaneously, it can be indicated that the gates of the driving transistors of the two adjacent rows of pixel circuits are turned on or off in the opposite manner, that is, the conduction and cutoff conditions of the two adjacent rows of pixel circuits are opposite. In the two adjacent rows of pixel circuits, if the pixel circuits of the previous row are in the on state, the pixel circuits of the next row are in the off state.

[0068] For example, see Figure 1 One end of the second sub-circuit 120 is electrically connected to the first sub-circuit 110 for receiving the grouping control signal EN_GRP. The other end of the second sub-circuit 120 is electrically connected to the pixel circuit 200. The second sub-circuit 120 is used to output the row scanning signal Q under the action of the grouping control signal EN_GRP. i . Wherein, i may represent the number of rows of pixel circuits.

[0069] Exemplarily, the value of the grouping control signal EN_GRP can control whether every two adjacent rows of pixel circuits are driven simultaneously, so the number of grouping control signals is less than the number of rows of pixel circuits. In some embodiments, the number of grouping control signals = the number of rows of pixel circuits - 1. Exemplarily, for the first row of pixel circuits and the second row of pixel circuits, when the grouping control signal EN_GRP = 0, the second sub-circuit can successively output two row scanning signals Q1 and Q2 under the action of the grouping control signal. Therefore, the first row of pixel circuits and the second row of pixel circuits cannot display content at the same time. When the grouping control signal EN_GRP = 1, the second sub-circuit can simultaneously output two row scanning signals Q1 and Q2 under the action of the grouping control signal. Therefore, the first row of pixel circuits and the second row of pixel circuits can simultaneously display corresponding content when data signals are written.

[0070] According to the above technical solution, the pixel circuits are quickly grouped under the action of the first drive signal and the first clock signal by a driving circuit having the above hardware circuit structure, ensuring that more grouping control signals are prepared before display to control whether two adjacent rows of pixel circuits in the grouped pixel circuits are driven at the same time, and then different row scanning signals are output. The row scanning signal and the data signal are combined so that the same group of pixel circuits can display the same content at the same time. For the non-attention area, that is, the case where multiple rows of pixel circuits are a group, since multiple rows of pixel circuits display the same content, the effect of rendering and displaying the non-attention area at a low resolution is achieved. For the attention area, that is, the case where a row of pixel circuits is a group, since only a row of pixel circuits is used to display the corresponding content, a high-resolution display effect is achieved. In the process of using DDIC for gaze point rendering, all rendering signals are first generated based on the eye movement signal, and then the rendering signal is given to the driving circuit so that the driving circuit drives the pixel circuit to complete the corresponding display. In the above-mentioned embodiment of the present disclosure, the eye tracking signal is first converted into a first driving signal by using DDIC, and then a rendering signal is generated by using a hardware circuit under the action of the first driving signal to drive the pixel circuit to complete the corresponding display, without waiting for DDIC to generate all the rendering signals, which greatly improves the rendering efficiency. In addition, the rendering signal is directly generated by the driving circuit, and there is no need to add an additional driving circuit that matches DDIC and is used to receive the rendering signal, which effectively reduces the circuit power consumption.

[0071] Figure 2 A schematic circuit structure diagram of a first sub-circuit provided in an embodiment of the present disclosure. Figure 2, the first subcircuit 110 may include: a first trigger 111 and a second trigger 112 electrically connected. The first trigger 111 and the second trigger 112 may be D triggers. The triggering modes of the D trigger include level triggering and edge triggering. Among them, level triggering means that it can be triggered when the clock pulse = 1, and edge triggering is mostly triggered at the leading edge of the clock pulse, that is, when it jumps from 0→1. The next state of the D trigger depends on the state of the D terminal before the trigger, that is, the next state = D. The D trigger has two stable states, namely 0 and 1, and can flip from one stable state to another stable state under the action of certain external signals. Therefore, the D trigger has two functions of setting 0 and setting 1. See Figure 2 , the clock terminal CK of the first flip-flop 111 is used to receive the first clock signal FRD_CKV, and the D terminal of the first flip-flop 111 is used to receive the first trigger signal IN. The first flip-flop 111 can write the first trigger signal IN at the D terminal under the triggering of the first clock signal FRD_CKV, and then the first flip-flop 111 can output the first control signal C1 from the output terminal OUT. In combination with the foregoing, for example, the period of the first clock signal FRD_CKV can be In this case, the first trigger signal IN can be shifted backward by 3 lines in one line period. Figure 2 , the clock terminal CK of the second trigger 112 is used to receive the first control signal C1. The D terminal of the second trigger 112 can read the first drive signal FRD_IN three times in one row cycle. The second trigger 112 can write the first drive signal FRD_IN at the D terminal under the triggering of the first control signal C1, and then the second trigger 112 can output the group control signal EN_GRP from the first output terminal OUT1 and output the non-operation signal EN_GRP' of the group control signal from the second output terminal OUT2. The group control signal EN_GRP output based on the above embodiment can realize the simultaneous driving of 4 rows of pixel circuits.

[0072] Therefore, the stable characteristics of the trigger can be used to output a more accurate group control signal, providing reliable protection for subsequent group drive display.

[0073] In some embodiments, the first trigger and the second trigger are used to reset under the action of a reset signal, and the effective level end point of the reset signal is before the effective level start points of the first trigger signal, the first control signal, and the first drive signal.

[0074] For example, see Figure 2, the first trigger 111 and the second trigger 112 are both provided with a reset port Rn. The reset port Rn is used to receive a reset signal FRD_RN. Under the action of the reset signal FRD_RN, the first trigger 111 and the second trigger 112 can perform a reset operation. It should be noted that, for the trigger, the reset operation can make it enter a certain state that can operate stably. This certain state can be an initial operating state or a normal state relative to an error state. In this way, it can be ensured that the trigger is in a known and determined stable state before each triggering, thereby ensuring the stability and reliability of subsequent signal transmission. Exemplarily, the effective level end point of the reset signal is before the effective level starting point of the first trigger signal, the first control signal and the first drive signal. Among them, for the reset signal, the first trigger signal, the first control signal and the first drive signal, their effective levels can all be high levels. In this case, the effective level end point can be the moment when the signal changes from a high level to a low level, and the effective level starting point can be the moment when the signal changes from a low level to a high level. In order to further improve the stability and reliability of subsequent signal transmission and avoid state errors of the trigger, the effective level end point of the reset signal is set before the effective level starting point of the first trigger signal, the first control signal and the first drive signal. That is, the falling edge of the active level of the reset signal is located before the rising edges of the active levels of the first trigger signal, the first control signal, and the first driving signal.

[0075] For example, see Figure 2 In some embodiments, the first control signal C1 is a clock trigger signal of the second flip-flop 112, that is, the first control signal C1 at the input end of the second flip-flop 112 is the clock end CK of the second flip-flop 112. And the first control signal C1 is a single pulse signal, that is, in one frame, the first control signal has only one pulse. According to the working principle of the flip-flop, during the period of clock pulse = 1, the circuit has a maintaining blocking effect, and even if the data state of the D end changes, it will not affect the output state of the flip-flop. Therefore, when the clock trigger signal is a single pulse signal, it can be guaranteed that the grouping control signal output by the second flip-flop in one frame is stable and unchanged. The n-th level second subcircuit includes an n-th level first branch and an n-th level second branch, the n-th level first branch is used to output a row scanning signal of the n-th row pixel circuit under the action of the grouping control signal provided by the n-th level first subcircuit, the n-th level second branch is used to output a row scanning signal of the n+1-th row pixel circuit under the action of the grouping control signal provided by the n-th level first subcircuit, and the n-th level second branch is also used to output a row scanning signal of the n+1-th row pixel circuit under the action of the grouping control signal provided by the n+1-th level first subcircuit

[0076] Figure 3 This is a schematic structural block diagram of another driving circuit provided by an embodiment of the present disclosure. Figure 3 The driving circuit 100 may include N stages, and each stage of the driving circuit may include a first sub-circuit 110 and a second sub-circuit 120. Each stage of the second sub-circuit 120 may include a first branch 130 and a second branch 140. Figure 3 In the first-stage driving circuit, the first sub-circuit 110 can provide the grouping control signal EN_GRP1 to the first-stage first branch 130 and the first-stage second branch 140 respectively. The first-stage first branch 130 can output the row scanning signal Q1 of the first-row pixel circuit under the action of the grouping control signal EN_GRP1. The row scanning signal Q1 can be used to drive the first-row pixel circuit. The first-stage second branch 140 can output the row scanning signal Q2 of the second-row pixel circuit under the action of the grouping control signal EN_GRP1. The row scanning signal Q2 can be used to drive the second-row pixel circuit. In the second-stage driving circuit, the first sub-circuit 110 can provide the grouping control signal EN_GRP2 to the second-stage first branch 130 and the second-stage second branch 140 respectively. The second-stage first branch 130 can output the row scanning signal Q2 of the second-row pixel circuit under the action of the grouping control signal EN_GRP2. The second branch 140 of the second level can output the row scanning signal Q3 of the third row pixel circuit under the action of the grouping control signal EN_GRP2. Among them, the first branch of the second level can be the same circuit as the second branch of the first level. That is, there can be a shared circuit in the second sub-circuit of the first level and the second sub-circuit of the second level. For this part of the shared circuit, when it is used to receive the grouping control signal of the first sub-circuit of the previous level, such as the first sub-circuit of the nth level, it can be regarded as the second branch in the second sub-circuit of the nth level. When it is used to receive the grouping control signal of the first sub-circuit of the next level, the first sub-circuit of the n+1th level, it can be regarded as the first branch in the second sub-circuit of the n+1th level. By analogy, the second sub-circuit of the nth level can output the row scanning signal Q to the corresponding n-row pixel circuit under the action of n-1 grouping control signals. n That is, the number of stages of the driving circuit is less than the number of rows of the pixel circuit. When a stable and unchanged grouping control signal is obtained according to the above technical solution, it can be accurately determined whether every two adjacent rows of pixel circuits are controlled simultaneously, thereby ensuring the stability of the row scanning signal output by the second sub-circuit and ensuring the rendering display effect.

[0077] In some embodiments, the driving circuit includes N stages, and the n-th stage driving circuit may include an n-th stage first subcircuit and an n-th stage second subcircuit. The first trigger of the n-th stage first subcircuit is electrically connected to the first trigger of the n+1-th stage first subcircuit, and the first trigger of the n-th stage first subcircuit is used to transmit a first control signal to the first trigger of the n+1-th stage first subcircuit, and the first control signal is a first trigger signal of the first trigger of the n+1-th stage first subcircuit, wherein N and n are both natural numbers greater than 0, and n+1≤N.

[0078] Figure 4 A schematic circuit structure diagram of another first sub-circuit provided in an embodiment of the present disclosure. Figure 4 In the embodiment shown, n=1, that is, Figure 4 The connection relationship between the first sub-circuit of the first level and the first sub-circuit of the second level is shown. Figure 4 , the first flip-flop 111 and the second flip-flop 112 are both provided with a reset port Rn. The reset port Rn is used to receive a reset signal FRD_RN. Under the action of the reset signal FRD_RN, the first flip-flop 111 and the second flip-flop 112 can perform a reset operation. The D terminal of the first flip-flop 111 of the first sub-circuit 110 of the first level is used to receive the first trigger signal IN, and the clock terminal CK of the first flip-flop 111 of the first sub-circuit 110 of the first level is used to receive the first clock signal FRD_CKV. The first flip-flop 111 of the first sub-circuit 110 of the first level can write the first trigger signal IN at the D terminal under the triggering of the first clock signal FRD_CKV, and then output the first control signal C1 from the output terminal OUT. The output terminal OUT of the first flip-flop 111 of the first sub-circuit 110 of the first level is electrically connected to the clock terminal of the second flip-flop 112 of the first sub-circuit 110 of the first level and the D terminal of the first flip-flop 111 of the second sub-circuit 110 of the second level, respectively. See. Figure 4It can be seen that the first control signal C1 is not only used as the clock trigger signal of the second flip-flop 112 of the first sub-circuit 110 of the first level, but also as the D-end input signal of the first flip-flop 111 of the first sub-circuit 110 of the second level, that is, the first trigger signal. The first flip-flop 111 of the first sub-circuit 110 of the second level can output a new first control signal C1 from the output end OUT under the joint action of the first clock signal FRD_CKV and the first control signal C1. The new first control signal output by the first flip-flop of the first sub-circuit of the second level, which is the same as the first control signal C1 output by the first flip-flop of the first sub-circuit of the first level, is simultaneously used as the clock trigger signal of the second flip-flop of the first sub-circuit of the second level, and the first trigger signal of the first flip-flop of the first sub-circuit of the third level. By analogy, the first control signal output by the first flip-flop of the first sub-circuit of the nth level is simultaneously used as the clock trigger signal of the second flip-flop of the first sub-circuit of the nth level, and the first trigger signal of the first flip-flop of the first sub-circuit of the n+1th level. Exemplarily, the first control signal C1 is used as the clock trigger signal of the second flip-flop 112 of the first sub-circuit 110 of the first level. The first driving signal FRD_IN is used as a D trigger signal of the second trigger 112 of the first sub-circuit 110 of the first stage. Under the action of the first control signal C1 and the first driving signal FRD_IN, the second trigger 112 of the first sub-circuit 110 of the first stage outputs the grouping control signal EN_GRP from the output terminal OUT1. <1> , the group control signal EN_GRP' is output from the output terminal OUT2 <1> Similarly, the second flip-flop 112 of the first sub-circuit 110 of the nth stage can output the grouping control signal EN_GRP from the output terminal OUT1. <n>, the group control signal EN_GRP' is output from the output terminal OUT2 <n>.

[0079] Therefore, through the circuit structure with the above connection relationship, the signal level transmission can be realized by inputting the first trigger signal to the D terminal of the first trigger of the first sub-circuit of the first level, and there is no need to input the trigger signal to the first trigger of each level of the first sub-circuit respectively, thereby reducing the signal input. From the hardware level, the circuit connection relationship is simplified, and there is no need to set a signal input terminal with an electrical connection relationship for the D terminal of the first trigger of each level of the first sub-circuit, thereby reducing external signal interference.

[0080] In some embodiments, for example, see Figure 4 , the first stage first sub-circuit 110 may include a first transmission gate 113. The input terminal 1 of the first transmission gate 113 is used to receive the frame start signal FRD_STV. When the first transmission gate 113 is turned on, the frame start signal FRD_STV may be transmitted to the first trigger 111 of the first stage first sub-circuit 110 via the output terminal 2. The frame start signal FRD_STV is the first trigger signal IN received by the first stage first trigger 111. Figure 4 , the first transmission gate 113 also includes a control terminal 3, and the control terminal 3 is used to receive the rendering start signal READY_IN. Exemplarily, when the rendering start signal READY_IN=1, the first transmission gate 113 can be turned on. When the rendering start signal READY_IN=0, the first transmission gate 113 is in a cut-off state. The frame start signal is used as the start signal of a frame image. According to the above technical solution, when the first transmission gate is in a conducting state, the frame start signal can be input to the first trigger of the first stage as the D trigger signal of the trigger. In the entire driving circuit, the first transmission gate can be set only before the first trigger of the first stage, and the rendering start signal can be used as a condition for writing the frame start signal into the first trigger of the first stage, thereby realizing a fast response of the rendering display.

[0081] In some embodiments, the effective level starting point of the rendering start signal is after the effective level end point of the reset signal, and the effective level end point of the rendering start signal is before the effective level starting point of the first drive signal. Exemplarily, the effective level of the rendering start signal can be a high level, and its effective level starting point is the moment when the low level changes to the high level, and its effective level end point is the moment when the high level changes to the low level. The effective level end point of the reset signal is set before the effective level starting point of the rendering start signal, and before the rendering start signal acts on the first transmission gate, the reset signal completes the reset operation of the first trigger of the first level. As described above, the reset signal can ensure that the trigger is in a known and determined stable state before each trigger, thereby controlling the trigger to be in a stable state before the first trigger of the first level receives the first trigger signal. For the effective level end point of the rendering start signal, it can be set before the effective level starting point of the first drive signal. Exemplarily, the rendering start signal can be regarded as a start signal for the driving circuit to perform rendering work, and the first drive signal can be regarded as a demand signal or an expected signal for specific rendering. Setting the effective level end point of the rendering start signal before the effective level start point of the first drive signal can ensure timely response of the first drive signal to the drive circuit, avoid the loss of the first drive signal causing deviation in the rendering result, and ensure the rendering display effect.

[0082] Figure 5 A schematic circuit structure diagram of a second sub-circuit provided in an embodiment of the present disclosure. Figure 5 The illustrated embodiment includes a first-stage second subcircuit and a second-stage second subcircuit. The second subcircuit 120 of each stage may include a second transmission gate 121, a third transmission gate 122, a fourth transmission gate 123, a third flip-flop 124, and a fourth flip-flop 125. For the first-stage second subcircuit, the first branch may include the third transmission gate 122 and the third flip-flop 124, and the second branch may include the third transmission gate 122, the fourth transmission gate 123, and the fourth flip-flop 125. For the second-stage second subcircuit, the first branch may include the third transmission gate 122 and the fourth flip-flop 125 in the first-stage second subcircuit. The second branch may include the third transmission gate 122, the fourth transmission gate 123, and the fourth flip-flop 125 in the second-stage second subcircuit. See FIG. Figure 5 , the fourth trigger 125 in the second sub-circuit of the first level also serves as the third trigger 124 in the second sub-circuit of the second level. The second sub-circuit of the first level is described in detail below, see Figure 5 , the second transmission gate 121 is electrically connected to the third transmission gate 122 and the third trigger 124 respectively. The input terminal IN of the second transmission gate 121 is used to receive the frame start signal STV. When the second transmission gate 121 is in the on state, the second trigger signal C2 can be transmitted to the third transmission gate 122 and the third trigger 124 electrically connected thereto via the output terminal OUT. The third transmission gate 122 is electrically connected to the third trigger 124 and the fourth trigger 125 respectively. The fourth transmission gate 123 is electrically connected to the third trigger 124 and the fourth trigger 125 respectively. The third transmission gate 122 and the fourth transmission gate 123 are electrically connected. The input terminal IN of the third transmission gate 122 is used to receive the second trigger signal C2 transmitted by the second transmission gate 121. The control terminal 1 of the third transmission gate 122 is used to receive the group control signal EN_GRP output from the second trigger in the first sub-circuit. When the group control signal EN_GRP=1, the third transmission gate 122 can be turned on. See Figure 5 , the control terminal 1 of the fourth transmission gate 123 is also used to receive the grouping control signal EN_GRP output from the second trigger in the first sub-circuit. Unlike the third transmission gate 122, a NOT gate is added at the control terminal 1 of the fourth transmission gate 123. Therefore, when the grouping control signal EN_GRP=1, the third transmission gate 122 can be turned on, while the fourth transmission gate 123 is in the opposite off state. Conversely, when the grouping control signal EN_GRP=0, the third transmission gate 122 is turned off, while the fourth transmission gate 123 is in the opposite on state. For example, see Figure 5 , when the third transmission gate 122 is turned on and the fourth transmission gate 123 is turned off, the third transmission gate 122 can output the second trigger signal C2 to the fourth trigger 125. At this time, the third trigger 124 and the fourth trigger 125 can both output the row scanning signal through the output terminal out under the action of the clock trigger signal CK and the second trigger signal C2. Among them, the third trigger 124 can output the row scanning signal Q1, and the fourth trigger 125 can output the row scanning signal Q2. Figure 5 It can be seen that in this embodiment, since there is no delay caused by other components, and when the group control signal EN_GRP=1, since the fourth transmission gate 123 is in the off state, there is no shunt loss in the second trigger signal C2 transmitted from the third transmission gate 122 to the fourth trigger 125, so the row scan signal Q1 and the row scan signal Q2 can be output at the same time. Combined with the above, when the group control signal EN_GRP=1, the first branch of the second sub-circuit of the first level can output the row scan signal Q1, and at the same time, the second branch of the second sub-circuit of the first level can output the row scan signal Q2, thereby realizing the simultaneous driving of two adjacent rows of pixel circuits.

[0083] For example, see Figure 5 When the fourth transmission gate 123 is turned on and the third transmission gate 122 is turned off, the third trigger 124 can output the second control signal through the output terminal out under the action of the clock trigger signal and the second trigger signal C2. Figure 5 It can be seen that the second control signal is used as the input signal of the row scan signal Q1 and the fourth transmission gate 123 at the same time. When the group control signal EN_GRP=0, the fourth transmission gate 123 is in the on state and can output the second control signal to the D terminal of the fourth trigger 125. The fourth trigger 125 can output the row scan signal Q2 through the output terminal under the action of the second control signal and the clock trigger signal. After the row scan signal Q1 is output, the second control signal is transmitted through the fourth transmission gate 123 to trigger the fourth trigger to output the row scan signal Q2. Therefore, in this embodiment, the row scan signal Q1 and the row scan signal Q2 are not output at the same time, and the row scan signal Q2 is outputted after the row scan signal Q1. Combined with the above, when the group control signal EN_GRP=0, the first branch of the second sub-circuit of the first level can output the row scan signal Q1, and then, the second branch of the second sub-circuit of the first level can output the row scan signal Q2, so that the adjacent two rows of pixel circuits are not driven at the same time.

[0084] In some embodiments, for example, see Figure 5 , the second sub-circuit 120 may further include a fifth transmission gate 126. The fifth transmission gate 126 is electrically connected between the fourth trigger 125 and the third transmission gate 122. Figure 5 , the second transmission gate 121 can be respectively arranged at the position corresponding to the pixel circuit of the starting row and the position corresponding to the pixel circuit of the ending row. Figure 5 In the illustrated embodiment, the control terminal 1 of the second transmission gate 121 is used to receive the second drive signal GSD_FW, and the control terminal 2 is used to receive the second drive signal GSD_BW. Compared with the second transmission gate 121 located at the corresponding position of the pixel circuit of the starting row, the second transmission gate 121 located at the corresponding position of the pixel circuit of the ending row is provided with a NOT gate at the control terminal 1. Compared with the second transmission gate 121 located at the corresponding position of the pixel circuit of the ending row, the second transmission gate 121 located at the corresponding position of the pixel circuit of the starting row is provided with a NOT gate at the control terminal 2. The control terminals 1 of the fifth transmission gate 126-1 and the fifth transmission gate 126-2 are used to receive the second drive signal GSD_FW, and the control terminals 2 of the fifth transmission gate 126-1 and the fifth transmission gate 126-2 are used to receive the second drive signal GSD_BW. Wherein, unlike the fifth transmission gate 126-1, the fifth transmission gate 126-2 is provided with a NOT gate at the control terminal 2. Unlike the fifth transmission gate 126-2, the fifth transmission gate 126-1 is provided with a NOT gate at the control terminal 1. Exemplarily, when the second drive signal GSD_FW=1 and the second drive signal GSD_BW=0, the control signals received by the control terminal 1 and the control terminal 2 of the second transmission gate 121 and the fifth transmission gate 126-2 at the corresponding position of the starting row pixel circuit are both high level, while the control signals received by the control terminal 1 and the control terminal 2 of the second transmission gate 121 and the fifth transmission gate 126-1 at the corresponding position of the ending row pixel circuit are both low level. Therefore, when the second drive signal GSD_FW=1 and the second drive signal GSD_BW=0, the second transmission gate 121 and the fifth transmission gate 126-2 at the corresponding position of the starting row pixel circuit are turned on, while the second transmission gate 121 and the fifth transmission gate 126-1 at the corresponding position of the ending row pixel circuit are turned off. In this case, the positive scanning function can be realized, that is, for the row pixel circuit, the row scanning is performed from top to bottom. On the contrary, when the second drive signal GSD_FW=0 and the second drive signal GSD_BW=1, the control signals received by the control terminal 1 and the control terminal 2 of the second transmission gate 121 and the fifth transmission gate 126-1 at the corresponding position of the pixel circuit of the termination row are both high level, while the control signals received by the control terminal 1 and the control terminal 2 of the second transmission gate 121 and the fifth transmission gate 126-2 at the corresponding position of the pixel circuit of the start row are both low level. Therefore, when the second drive signal GSD_FW=1 and the second drive signal GSD_BW=0, the second transmission gate 121 and the fifth transmission gate 126-1 at the corresponding position of the pixel circuit of the termination row are turned on, while the second transmission gate 121 and the fifth transmission gate 126-2 at the corresponding position of the pixel circuit of the start row are turned off. In this case, the reverse scanning function can be realized, that is, for the row pixel circuit, the row scanning is performed from bottom to top.

[0085] Therefore, a fifth transmission gate can be added to the second sub-circuit, and the forward and reverse scanning functions can be realized through the above technical solution to meet various requirements.

[0086] Figure 6 A driving timing diagram of a driving circuit provided in an embodiment of the present disclosure. For example, see Figure 6 , taking the driving of 4 rows of pixel circuits as an example, combined with the above, the corresponding number of driving circuits is 3, including V1, V2 and V3. Figure 6 In the timing diagram corresponding to V1, FRD_STV is the D trigger signal of the first trigger of the first level. When it is at a high level, the corresponding clock trigger signal FRD_CKV is also a high level signal. At this time, the first trigger of the first level outputs a high level signal DFF_Q1. DFF_Q1 serves as the clock trigger signal of the second trigger of the first level, and the first drive signal FRD_IN serves as the D trigger signal of the second trigger of the first level. When DFF_Q1 and FRD_IN are both at high levels, the second trigger of the first level outputs a high level grouping control signal EN_GRP1. That is, EN_GRP1=1, at this time, the pixel circuits of the first row and the pixel circuits of the second row are driven at the same time. See Figure 6 In the timing diagram corresponding to V2, DFF_Q1 also serves as the D trigger signal of the first trigger of the second stage. When it is at a high level and the clock trigger signal FRD_CKV is also a high level signal, the first trigger of the second stage can output a high level signal DFF_Q2. DFF_Q2 serves as the clock trigger signal of the second trigger of the second stage, and the first drive signal FRD_IN serves as the D trigger signal of the second trigger of the second stage. When DFF_Q2 and FRD_IN are both at high levels, the second trigger of the second stage outputs a high level grouping control signal EN_GRP2. That is, EN_GRP2 = 2, at this time, the pixel circuits of the second row and the pixel circuits of the third row are driven simultaneously. See Figure 6 In the timing diagram corresponding to V3, DFF_Q2 also serves as the D trigger signal of the first trigger of the third level. When it is at a high level and the clock trigger signal FRD_CKV is also a high level signal, the first trigger of the third level can output a high level signal DFF_Q3. DFF_Q3 serves as the clock trigger signal of the second trigger of the third level, and the first drive signal FRD_IN serves as the D trigger signal of the second trigger of the third level. When DFF_Q3 is at a high level but the first drive signal FRD_IN is at a low level, the second trigger of the third level outputs a low level grouping control signal EN_GRP3. That is, EN_GRP3=0, at this time, the pixel circuit of the third row and the pixel circuit of the fourth row are not driven at the same time. Combined with the previous text, the pixel circuit of the first row, the pixel circuit of the second row and the pixel circuit of the third row are driven simultaneously as the first group of pixel circuits. The pixel circuit of the fourth row is separately used as the second group of pixel circuits and is not driven simultaneously with the first group of pixel circuits. In addition, in Figure 6 In the illustrated embodiment, since DFF_Q1, DFF_Q2 and DFF_Q3 are all single pulse signals in one row period, according to the working principle of the D flip-flop, the grouping control signal output by the second flip-flop of each level is stable and unchanged.

[0087] According to a second aspect of the embodiments of the present disclosure, a display panel is also proposed. Figure 7 A schematic structural block diagram of a display panel provided in an embodiment of the present disclosure. For example, see Figure 7 The display panel 700 may include: the driving circuit 100 and the pixel circuit 200 as described above. The driving circuit 100 may include N-level first sub-circuits 110 and N-level second sub-circuits 120. The number of rows of the pixel circuit 200 is greater than the number of levels of the driving circuit 100.

[0088] According to a third aspect of the embodiments of the present disclosure, a control method for a driving circuit is proposed, which is applied to the driving circuit as described above. Figure 8 A schematic flow chart of a control method of a drive circuit provided in an embodiment of the present disclosure. Figure 8 , the control method may include the following steps.

[0089] Step S810: Control the first sub-circuit to output a grouping control signal under the action of the first driving signal and the first clock signal, wherein the grouping control signal is used to control whether two adjacent rows of pixels are driven simultaneously.

[0090] Step S820: Control the second sub-circuit to output a row scanning signal to the pixel circuit under the action of the grouping control signal.

[0091] Exemplarily, the eye tracking signal may be subjected to operations such as signal processing to obtain and send a first drive signal to the first subcircuit. The first subcircuit may divide the row pixels of the pixel circuit under the action of the first drive signal and the first clock signal, thereby outputting more grouping control signals before display. The value of the grouping control signal may determine the synchronization of the output signal, that is, whether two adjacent rows of pixel circuits are driven simultaneously. Exemplarily, for the first row of pixel circuits and the second row of pixel circuits, when the grouping control signal is equal to 0, the second subcircuit may output two row scanning signals successively under the action of the grouping control signal. Therefore, the first row of pixel circuits and the second row of pixel circuits cannot display content at the same time. When the grouping control signal is equal to 1, the second subcircuit may output two row scanning signals simultaneously under the action of the grouping control signal.

[0092] In some embodiments, before controlling the first subcircuit to output a group control signal under the action of the first drive signal, the method may further include: controlling the first trigger and the second trigger to reset under the action of a reset signal, and the effective level end point of the reset signal is before the effective level starting point of the first trigger signal, the first control signal and the first drive signal.

[0093] Exemplarily, under the action of the reset signal, the first trigger and the second trigger can perform a reset operation. For the trigger, the reset operation can make it enter a certain state that can operate stably. For the reset signal, the first trigger signal, the first control signal and the first drive signal, their effective levels can all be high levels. In this case, the effective level end point can be the moment when the signal changes from a high level to a low level, and the effective level starting point can be the moment when the signal changes from a low level to a high level. In order to further improve the stability and reliability of subsequent signal transmission and avoid state errors of the trigger, the effective level end point of the reset signal is set before the effective level starting points of the first trigger signal, the first control signal and the first drive signal.

[0094] In some embodiments, the method may further include: when the first transmission gate is turned on by the rendering start signal, controlling the first transmission gate to transmit a frame start signal to the first trigger, where the frame start signal is the first trigger signal received by the first trigger of the first stage.

[0095] Exemplarily, the input end of the first transmission gate is used to receive the frame start signal, and the control end of the first transmission gate is used to receive the rendering start signal. When the rendering start signal is equal to 1, the first transmission gate can be turned on. When the rendering start signal is equal to 0, the first transmission gate is in a cut-off state. When the first transmission gate is turned on, the frame start signal can be transmitted to the first trigger of the first sub-circuit of the first stage via the output end.

[0096] In some implementations, a valid level start point of the rendering start signal is after a valid level end point of the reset signal, and a valid level end point of the rendering start signal is before a valid level start point of the first driving signal.

[0097] Exemplarily, the effective level of the rendering start signal can be a high level, and its effective level starting point is the moment when the low level changes to the high level, and its effective level end point is the moment when the high level changes to the low level. The effective level end point of the reset signal is set before the effective level starting point of the rendering start signal, and before the rendering start signal acts on the first transmission gate, so that the reset signal completes the reset operation of the first trigger of the first level. Exemplarily, the rendering start signal can be regarded as a start signal for the driving circuit to perform rendering work, and the first driving signal can be regarded as a demand signal or an expected signal for specific rendering. The effective level end point of the rendering start signal is set before the effective level starting point of the first driving signal, which can ensure the timely response of the first driving signal to the driving circuit, avoid the occurrence of the first driving signal loss causing deviation in the rendering result, and ensure the rendering display effect.

[0098] In some implementations, the method may further include: controlling the second transmission gate and the fifth transmission gate to be turned on or off under the action of the second driving signal.

[0099] For example, see Figure 5 , when the second driving signal GSD_FW=1 and the second driving signal GSD_BW=0, the control signals received by the control terminals 1 and 2 of the second transmission gate 121 and the fifth transmission gate 126-2 at the corresponding positions of the starting row pixel circuit are both high level, while the control signals received by the control terminals 1 and 2 of the second transmission gate 121 and the fifth transmission gate 126-1 at the corresponding positions of the ending row pixel circuit are both low level. Therefore, the second transmission gate 121 and the fifth transmission gate 126-2 at the corresponding positions of the starting row pixel circuit are turned on, and the second transmission gate 121 and the fifth transmission gate 126-1 at the corresponding positions of the ending row pixel circuit are turned off. In this case, the positive scanning function can be realized. On the contrary, when the second driving signal GSD_FW=0 and the second driving signal GSD_BW=1, the control signals received by the control terminal 1 and the control terminal 2 of the second transmission gate 121 and the fifth transmission gate 126-1 at the corresponding position of the pixel circuit of the termination row are both high level, and the control signals received by the control terminal 1 and the control terminal 2 of the second transmission gate 121 and the fifth transmission gate 126-2 at the corresponding position of the pixel circuit of the start row are both low level. Therefore, the second transmission gate 121 and the fifth transmission gate 126-1 at the corresponding position of the pixel circuit of the termination row are turned on, and the second transmission gate 121 and the fifth transmission gate 126-2 at the corresponding position of the pixel circuit of the start row are turned off. In this case, the reverse scanning function can be realized.

[0100] According to a fourth aspect of the embodiments of the present disclosure, a controller is proposed, comprising: a memory storing a computer program; and a processor for calling the computer program in the memory, wherein the computer program is used to execute the control method as described above.

[0101] Exemplarily, the controller may be integrated into a driving circuit. In some implementations, the controller may also be integrated into a driving chip.

[0102] According to a fifth aspect of the embodiments of the present disclosure, a display device is provided, comprising the display panel as described above and / or the controller as described above. Fig. 9 A schematic structural block diagram of a display device provided in an embodiment of the present disclosure. Fig. 9 In the illustrated embodiment, the display device 900 may include both the display panel 700 described above and the controller 910 described above. In some embodiments, the display device 900 may further include one of the display panel 700 or the controller 910.

[0103] In some embodiments, the display device may further include: a driver chip electrically connected to a driver circuit of the display panel; and a control mainboard electrically connected to the driver chip. Exemplarily, the control mainboard may be a device such as a DDIC for collecting and processing eye tracking signals and generating a first drive signal. The control mainboard may send a first drive signal to the driver chip, so that the drive circuit may realize the above-mentioned drive function under the drive of the driver chip, and the driver chip may be bound to a non-display area of ​​the display panel.

[0104] Illustratively, the display device of the embodiment of the present disclosure can be applied to scenarios such as vehicle-mounted display, smart phones, computers, medical monitors, televisions, smart wearable displays, etc. Smart wearable devices may include smart watches, AR (augmented reality) devices, and VR (virtual reality) devices, etc., which are not specifically limited by the embodiment of the present disclosure.

[0105] A person skilled in the art may understand the specific details and beneficial effects of the display panel, the controller and the display device by reading the above description of the driving circuit and the control method thereof, which will not be described herein for the sake of brevity.

[0106] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and / or equipment can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0109] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0110] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.< / n> < / n>

Claims

1. A driving circuit, characterized in that: include: The first subcircuit is used to output a grouping control signal under the action of a first driving signal and a first clock signal, wherein the grouping control signal is used to control whether two adjacent rows of pixel circuits are driven simultaneously, and the period of the first clock signal is the refresh time of a row of the pixel circuits. x is a natural number greater than 1; The second sub-circuit, one end of the second sub-circuit is electrically connected to the first sub-circuit, the other end of the second sub-circuit is used to be electrically connected to the pixel circuit, and the second sub-circuit is used to output a row scanning signal under the action of the grouping control signal.

2. The driving circuit according to claim 1, characterized in that: The first subcircuit includes: a first trigger and a second trigger electrically connected; The first trigger is used to output a first control signal under the action of the first clock signal and the first trigger signal; The second trigger is used to output the grouping control signal under the action of the first control signal and the first driving signal.

3. The driving circuit according to claim 2, characterized in that: The first control signal is a clock trigger signal of the second flip-flop, and the first control signal is a single pulse signal.

4. The driving circuit according to claim 2, characterized in that: The driving circuit includes N stages, the n-th stage driving circuit includes an n-th stage first subcircuit and an n-th stage second subcircuit, the n-th stage second subcircuit includes an n-th stage first branch and an n-th stage second branch, the n-th stage first branch is used to output a row scanning signal of an n-th row pixel circuit under the action of a grouping control signal provided by the n-th stage first subcircuit, the n-th stage second branch is used to output a row scanning signal of an n-th row pixel circuit under the action of a grouping control signal provided by the n-th stage first subcircuit, and the n-th stage second branch is also used to output a row scanning signal of an n+1-th row pixel circuit under the action of a grouping control signal provided by the n-th stage first subcircuit.

5. The driving circuit according to claim 4, characterized in that: The first trigger of the first subcircuit of the nth level is electrically connected to the first trigger of the first subcircuit of the n+1th level, and the first trigger of the first subcircuit of the nth level is used to transmit the first control signal to the first trigger of the first subcircuit of the n+1th level, and the first control signal is the first trigger signal of the first trigger of the first subcircuit of the n+1th level, wherein N and n are both natural numbers greater than 0, and n+1≤N.

6. The driving circuit according to claim 5, characterized in that: The first trigger and the second trigger are used to reset under the action of a reset signal, and the effective level end point of the reset signal is before the effective level starting points of the first trigger signal, the first control signal and the first drive signal.

7. The driving circuit according to claim 6, characterized in that: The first subcircuit of the first level includes a first transmission gate, which is used to transmit a frame start signal to the first trigger. The frame start signal is the first trigger signal received by the first trigger of the first level. The first transmission gate is used to be turned on or off under the action of a rendering start signal.

8. The driving circuit according to claim 7, characterized in that: The effective level starting point of the rendering start signal is after the effective level ending point of the reset signal, and the effective level ending point of the rendering start signal is before the effective level starting point of the first driving signal.

9. The driving circuit according to any one of claims 2 to 8, characterized in that: The second sub-circuit includes a second transmission gate, a third transmission gate, a fourth transmission gate, a third flip-flop and a fourth flip-flop; The second transmission gate is electrically connected to the third transmission gate and the third trigger respectively, and is used to output a second trigger signal to the third transmission gate and the third trigger when being turned on; The third transmission gate is electrically connected to the third trigger and the fourth trigger respectively, the fourth transmission gate is electrically connected to the third trigger and the fourth trigger respectively, the third transmission gate is electrically connected to the fourth transmission gate, and the third transmission gate and the fourth transmission gate are both used to be turned on or off under the action of the group control signal; When the third transmission gate is turned on and the fourth transmission gate is turned off, the third transmission gate outputs the second trigger signal to the fourth flip-flop; When the fourth transmission gate is turned on and the third transmission gate is turned off, the fourth transmission gate outputs a second control signal to the fourth trigger, wherein the second control signal is output by the third trigger under the triggering of the second trigger signal and the second clock signal.

10. The driving circuit according to claim 9, characterized in that: The second sub-circuit also includes a fifth transmission gate electrically connected between the fourth trigger and the third transmission gate, the fifth transmission gate is used to be turned on or off under the action of a second drive signal, and the second transmission gate is used to be turned on or off under the action of the second drive signal.

11. A display panel, characterized in that: include: The driving circuit according to any one of claims 1 to 10; The pixel circuit has a row number greater than the stage number of the driving circuit.

12. A control method for a driving circuit, characterized in that: Applied to the driving circuit according to any one of claims 1 to 10, the control method comprises: Control the first subcircuit to output the grouping control signal under the action of the first drive signal and the first clock signal, wherein the grouping control signal is used to control whether two adjacent rows of pixels are driven simultaneously, and the period of the first clock signal is the refresh time of the pixel circuit of one row x is a natural number greater than 1; The second sub-circuit is controlled to output a row scanning signal to the pixel circuit under the action of the grouping control signal.

13. The control method according to claim 12, characterized in that: Before controlling the first sub-circuit to output the grouping control signal under the action of the first driving signal and the first clock signal, the method further includes: The first trigger and the second trigger are controlled to be reset under the action of a reset signal, and the effective level end point of the reset signal is before the effective level starting points of the first trigger signal, the first control signal and the first drive signal.

14. The control method according to claim 13, characterized in that: The method further comprises: When the first transmission gate is turned on by the rendering start signal, the first transmission gate is controlled to transmit a frame start signal to the first trigger, where the frame start signal is the first trigger signal received by the first-stage first trigger.

15. The control method according to claim 14, characterized in that: The effective level starting point of the rendering start signal is after the effective level ending point of the reset signal, and the effective level ending point of the rendering start signal is before the effective level starting point of the first driving signal.

16. The control method according to claim 12, characterized in that: The method further comprises: The second transmission gate and the fifth transmission gate are controlled to be turned on or off under the action of the second driving signal.

17. A controller, characterized in that: include: a memory storing a computer program; A processor, configured to call the computer program in the memory, wherein the computer program is configured to execute the control method according to any one of claims 12 to 16.

18. A display device, characterized in that: Includes the display panel as claimed in claim 11 and / or the controller as claimed in claim 17.

19. The display device according to claim 18, characterized in that Also includes: A driving chip, the driving chip is electrically connected to a driving circuit of the display panel; A control mainboard is electrically connected to the driving chip.

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