Display module, display device and display driving method

Abstract

The invention provides a display module, a display device and a display driving method, and relates to the technical field of display, the display module comprises a display panel, the display panel comprises a pixel array, the pixel array comprises a plurality of first sub-arrays and a plurality of second sub-arrays, and the first sub-arrays and the second sub-arrays are arranged at intervals in the column direction; the display driving circuit is used for driving the first sub-array to display a picture of the first sub-data and driving the second sub-array to display a picture of the second sub-data in a first driving mode under the condition of the first picture data, and driving the pixel array to display a picture of the second picture data in a second driving mode under the condition of the second picture data; the first picture data at most comprises first sub-data and second sub-data; the data filled in the pixel row in the first driving mode is the first sub-data or the second sub-data, and the data filled in at least one pixel row in the second driving mode is obtained according to the data filled in the adjacent pixel row. The display effect of the display module on special pictures can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display module, a display device and a display driving method. Background Art

[0002] In some high-resolution / high-refresh rate display devices in the related art, the amount of pixel row data in the frame image data transmitted by the system to the display driving circuit is reduced by half. For example, for an 8k (column) × 4k (row) pixel architecture, the image data only has 8k (column) × 2k (row) data.

[0003] At present, 8k×4k resolution display screen can be realized by controlling the timing of driving signal. For example, by adopting the driving mode of hardware super resolution (HSR), the accurate data of the frame screen is charged into the odd-numbered rows of pixels in odd frames, and the middle value of the two adjacent rows of data is charged into the even-numbered rows of pixels. In the even-numbered frames, the accurate data is charged into the even-numbered rows of pixels, and the middle value of the two adjacent rows of data is charged into the odd-numbered rows of pixels, thereby realizing high-resolution display screen.

[0004] However, for special images such as interlaced black and white images and checkerboard images, charging the middle value of two adjacent lines of image data into a certain pixel row will cause abnormal display problems such as full black, full white or gradient colors, such as a flickering black and white image display effect, resulting in a poor display effect for special images on the display device. Summary of the invention

[0005] The present application provides a display module, a display device and a display driving method, which can solve the problem of abnormal display caused by charging the middle value of two adjacent rows of picture data into a certain pixel row, resulting in poor display effect of the display device for special pictures.

[0006] In a first aspect, the present application provides a display module, the display module comprising:

[0007] The display panel comprises a pixel array, wherein the pixel array comprises a plurality of first sub-arrays and a plurality of second sub-arrays, wherein the first sub-arrays and the second sub-arrays are arranged at intervals at least along a column direction; and the first sub-arrays and the second sub-arrays respectively comprise a plurality of pixel rows;

[0008] a display driving circuit, electrically connected to the display panel, configured to, when the display data is first picture data, drive the first sub-array to display a picture corresponding to the first sub-data using a first driving mode, and drive the second sub-array to display a picture corresponding to the second sub-data, and, when the display data is second picture data, drive the pixel array to display a picture corresponding to the second picture data using a second driving mode;

[0009] Among them, the first picture data includes at most the first sub-data and the second sub-data, and the first sub-data and the second sub-data are different data; in the first driving mode, the data charged into the pixel row is the first sub-data or the second sub-data, and in the second driving mode, the data charged into at least one of the pixel rows is obtained based on the data charged into the adjacent pixel rows.

[0010] Optionally, the display driving circuit includes a timing control circuit and a gate driving circuit, and the timing control circuit is electrically connected to the gate driving circuit; each pixel row of the pixel array is provided with at least one scanning line, and the gate driving circuit is electrically connected to the scanning line;

[0011] The timing control circuit is configured to control the gate driving circuit to send a row scanning signal to the scanning line corresponding to each pixel row in the first driving mode, so that each pixel row is turned on, each pixel row of the first sub-array is charged with the first sub-data, and each pixel row of the second sub-array is charged with the second sub-data.

[0012] Optionally, the display driving circuit further includes a source driving circuit, and the timing control circuit is electrically connected to the source driving circuit; each pixel column of the pixel array is provided with at least one data line, and the source driving circuit is electrically connected to the data line;

[0013] The timing control circuit is configured to control the source driving circuit to send a data signal to the data line in the first driving mode, so that the valid signal interval of the first sub-data corresponding to the first sub-array covers the turn-on interval of the multiple pixel rows in the first sub-array, and the valid signal interval of the second sub-data corresponding to the second sub-array covers the turn-on interval of the multiple pixel rows in the second sub-array.

[0014] Optionally, the gate driving circuit includes a plurality of gate driving terminals, each of which is electrically connected to the corresponding pixel row through the scanning line;

[0015] The timing control circuit is configured to control the multiple gate driving ends of the gate driving circuit in the first driving mode, and send the row scanning signal to the scanning line corresponding to each pixel row in turn, so that the pixel array is turned on row by row along the column direction, and the turn-on intervals of different pixel rows do not overlap with each other.

[0016] Optionally, the first sub-array includes N pixel rows; the second sub-array includes M pixel rows;

[0017] The duration of the open interval of each pixel row in the first subarray is equal to the row scanning duration, and the duration of the open interval of each pixel row in the second subarray is equal to the row scanning duration;

[0018] The duration of the valid signal interval of the first sub-data corresponding to the first sub-array is substantially equal to N times the row scanning duration, and the duration of the valid signal interval of the second sub-data corresponding to the second sub-array is substantially equal to M times the row scanning duration; wherein N and M are positive integers respectively.

[0019] Optionally, the gate driving circuit includes a plurality of gate driving terminals, each of which is electrically connected to the corresponding pixel row through the scanning line;

[0020] The timing control circuit is configured to control the multiple gate driving terminals of the gate driving circuit in the first driving mode, and sequentially send the row scanning signals to the scanning lines corresponding to the first subarray and the scanning lines corresponding to the second subarray, so that the multiple first subarrays and the multiple second subarrays are turned on one by one along the column direction, the multiple pixel rows in the first subarray are turned on at the same time, and the multiple pixel rows in the second subarray are turned on at the same time.

[0021] Optionally, the first sub-array includes N pixel rows; the second sub-array includes M pixel rows;

[0022] The duration of the open interval of each pixel row in the first subarray is equal to N times the row scanning duration, and the duration of the open interval of each pixel row in the second subarray is equal to M times the row scanning duration;

[0023] The duration of the valid signal interval of the first sub-data corresponding to the first sub-array is substantially equal to N times the row scanning duration, and the duration of the valid signal interval of the second sub-data corresponding to the second sub-array is substantially equal to M times the row scanning duration; wherein N and M are positive integers respectively.

[0024] Optionally, the display driving circuit includes a timing control circuit and a gate driving circuit, and the timing control circuit is electrically connected to the gate driving circuit; each pixel row of the pixel array is provided with at least one scanning line, and the gate driving circuit is electrically connected to the scanning line;

[0025] The plurality of pixel rows include at least one first pixel row and at least one second pixel row; the first pixel row and the second pixel row are arranged at intervals along the column direction;

[0026] The timing control circuit is configured to control the gate driving circuit to send row scanning signals to the scanning lines corresponding to the first pixel rows respectively in the first driving mode, so that each of the first pixel rows is turned on, the first pixel rows of the first sub-array are charged with the first sub-data, and the first pixel rows of the second sub-array are charged with the second sub-data,

[0027] Alternatively, the gate driving circuit is controlled to send the row scanning signal to the scanning lines corresponding to the second pixel rows respectively, so that each second pixel row is turned on, the second pixel rows of the first sub-array are charged with the first sub-data, and the second pixel rows of the second sub-array are charged with the second sub-data.

[0028] Optionally, the display driving circuit further includes a source driving circuit, and the timing control circuit is electrically connected to the source driving circuit; each pixel column of the pixel array is provided with at least one data line, and the source driving circuit is electrically connected to the data line;

[0029] The timing control circuit is configured to control the source driving circuit to send a data signal to the data line in the first driving mode, so that the valid signal interval of the first sub-data corresponding to the first sub-array covers the open interval of the first pixel row in the first sub-array, and the valid signal interval of the second sub-data corresponding to the second sub-array covers the open interval of the first pixel row in the second sub-array,

[0030] Alternatively, the valid signal interval of the first sub-data corresponding to the first sub-array covers the on-interval of the second pixel row in the first sub-array, and the valid signal interval of the second sub-data corresponding to the second sub-array covers the on-interval of the second pixel row in the second sub-array.

[0031] Optionally, the first pixel row is an odd-numbered row of the pixel array, and the second pixel row is an even-numbered row of the pixel array; the timing control circuit is configured as follows:

[0032] In an odd frame, in the first driving mode, the gate driving circuit is controlled to send row scanning signals to the scanning lines corresponding to the first pixel rows respectively, so that each of the first pixel rows is turned on and each of the second pixel rows is turned off for display;

[0033] In an even frame, under the first driving mode, the gate driving circuit is controlled to send the row scanning signal to the scanning lines corresponding to the second pixel rows respectively, so that each second pixel row is turned on and each first pixel row is turned off for display.

[0034] Optionally, the gate driving circuit includes a plurality of gate driving terminals, each of which is electrically connected to the corresponding pixel row through the scanning line;

[0035] The timing control circuit is configured to control the multiple gate driving ends in the first driving mode to send the row scanning signal to the scanning line corresponding to each of the first pixel rows in turn, so that the first pixel rows are turned on row by row along the column direction, or to control the multiple gate driving ends to send the row scanning signal to the scanning line corresponding to each of the second pixel rows in turn, so that the second pixel rows are turned on row by row along the column direction.

[0036] Optionally, the gate driving circuit comprises a plurality of cascaded gate driving units, and the gate driving units are electrically connected to the scanning lines corresponding to the pixel rows;

[0037] The display panel further comprises at least two frame start signal lines; the frame start signal lines are electrically connected to at least one of the gate driving units, and the frame start signal lines are also electrically connected to the timing control circuit;

[0038] The at least two frame start signal lines include a first frame start signal line and a second frame start signal line; wherein the gate driving unit corresponding to the first pixel row is controlled by a frame start signal transmitted by the first frame start signal line, and the gate driving unit corresponding to the second pixel row is controlled by the frame start signal transmitted by the second frame start signal line;

[0039] The timing control circuit is configured to, in the first driving mode, send the frame start signal to the first frame start signal line so that the gate driving unit corresponding to the first pixel row controls the first pixel row to turn on, or to send the frame start signal to the second frame start signal line so that the gate driving unit corresponding to the second pixel row controls the second pixel row to turn on.

[0040] Optionally, the first sub-data represents that the pixel row displays a black picture, and the second sub-data represents that the pixel row displays a white picture;

[0041] Alternatively, the first sub-data represents that the pixel row displays a first black and white checkered picture, and the second sub-data represents that the pixel row displays a second black and white checkered picture, wherein in the first black and white checkered picture, the first pixel in the pixel row displays black checkered pictures, and in the second black and white checkered pictures, the first pixel in the pixel row displays white checkered pictures.

[0042] In a second aspect, the present application provides a display device, comprising the display module as described in the first aspect.

[0043] In a third aspect, the present application provides a display driving method for driving the display module as described in the first aspect, the display driving method comprising:

[0044] The display driving circuit, when the display data is first picture data, drives the first sub-array of the pixel array to display a picture corresponding to the first sub-data by using a first driving mode, and drives the second sub-array of the pixel array to display a picture corresponding to the second sub-data, and, when the display data is second picture data, drives the pixel array to display a picture corresponding to the second picture data by using a second driving mode;

[0045] Among them, the first picture data includes at most the first sub-data and the second sub-data, and the first sub-data and the second sub-data are different data; in the first driving mode, the data charged into the pixel row is the first sub-data or the second sub-data, and in the second driving mode, the data charged into at least one of the pixel rows is obtained based on the data charged into the adjacent pixel rows.

[0046] A display module, a display device and a display driving method provided by the present application have at least the following advantages: the first picture data includes at most two different data, the first sub-data and the second sub-data, and the display picture corresponding to the first picture data includes at most two different pictures, the picture corresponding to the first sub-data and the picture corresponding to the second sub-data. The display driving circuit is configured to, when the display data is the first picture data, use the first driving mode to drive the first sub-array in the pixel array to display the picture corresponding to the first sub-data, and drive the second sub-array in the pixel array to display the picture corresponding to the second sub-data, so that the picture corresponding to the first picture data is displayed through the pixel array of the display panel. And the display driving circuit is configured to, when the display data is the second picture data, use the second driving mode to drive the pixel array to display the picture corresponding to the second picture data. In this way, in the first driving mode, the data charged into the pixel row is the first sub-data or the second sub-data, and in the second driving mode, the data charged into at least one pixel row is obtained based on the data charged into the adjacent pixel rows. Therefore, for the display screen corresponding to the first screen data, the data charged into the pixel row in the first driving mode has nothing to do with the adjacent pixel rows, which is different from the second driving mode. This avoids the problem in the related technology that for special screens such as interlaced black and white screens and checkerboard screens, the middle value of two adjacent rows of screen data is charged into a certain pixel row, which will cause abnormal display problems such as full black, full white or gradient colors, and can improve the display effect of the display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0048] Figure 1 It is a driving flow chart of hardware super resolution in the related art;

[0049] Figure 2 It is a timing diagram of a driving signal in the related art;

[0050] Figure 3 It is a schematic diagram of a black and white line picture in the related art;

[0051] Figure 4 is a structural schematic diagram of a display module provided in an embodiment of the present application;

[0052] Figure 5 is a structural schematic diagram of a multiplexing switch circuit provided in an embodiment of the present application;

[0053] Figure 6 is a schematic diagram of the structure of a display panel in a display module provided in an embodiment of the present application;

[0054] Figure 7 is a timing diagram of a first driving mode provided in an embodiment of the present application;

[0055] Figure 8 is a timing diagram of another first driving mode provided in an embodiment of the present application;

[0056] Fig. 9 is a schematic diagram of the structure of a display panel in another display module provided in an embodiment of the present application;

[0057] Fig.10 This is a timing diagram of another first driving mode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in some embodiments to clearly and completely describe the technical solutions in some embodiments. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0059] Figure 1This is a driving flow chart of hardware super resolution in related technologies. Currently, in high-resolution / high-refresh-rate displays, each column of pixels is connected to the same data line, and each row of pixels is connected to the same row of scan lines. The 8k (column) × 2k (row) data transmitted by the system to the timing controller (TCON) is half the amount of row data for the 8k (column) × 4k (row) pixel architecture. In order to achieve the display effect of 8k (column) × 4k (row), it is necessary to match the waveform of the gate drive signal with the source drive signal to achieve a display with a resolution of 8k (column) × 4k (row), which is the driving method of hardware super resolution (HSR). In this way, the processing data speed of the timing controller-related integrated circuit (IC) is halved, and the specifications of the source drive IC are reduced.

[0060] Figure 2 FIG. 1 is a timing diagram of a driving signal in the related art. Figure 2 As shown, in the first frame, after the frame start signal line STV1 sends the frame start signal, the data line directly inputs the data corresponding to the first row of pixels without delay. At the same time, the scanning (Gate) line G1 corresponding to the first row of pixels sends a row scanning signal. The high level time of the row scanning signal of the scanning line G1 is set to T, and the high level overlap interval of the row scanning signal corresponding to each row of pixels is 1 / 2T. Figure 2 As shown, the data charged into the first row of pixels is the data of the first row of data input by the data line, and the data charged into the second row of pixels is the data of the first and second rows of data input by the data line. The pixel charging level should be the middle value of the data of the first and second rows, that is, (data(1)+data(2)) / 2. Then the data charged into the third row of pixels is the data of the second row of data input by the data line, and so on. Then the pixels of the odd rows (1, 3, 5…4319) are charged with all the data of the data line input data (1, 2, 3…2160), while the data charged into the pixels of the even rows is the middle value of the data corresponding to the two adjacent pixel rows.

[0061] like Figure 2 As shown, in the second frame, after the frame start signal line STV1 sends the frame start signal, the data line inputs the first row of data after a delay of 1 / 2T, and the scan line G1 sends the row scan signal 1 / 2T ahead of the first row of data of the data line, and the high level overlap interval of the row scan signal corresponding to each row of pixels is 1 / 2T. Figure 2As shown in the figure, the data charged into the second row of pixels is the data of the first row input by the data line, the data charged into the third row of pixels is the data of the first and second rows input by the data line, the final pixel charging level should be the middle value of the data of the first and second rows, the data charged into the fourth row of pixels is the data of the second row input by the data line, and so on. Then the data charged into the pixels of the even rows (2, 4, 6...4320) is all the data (1, 2, 3...2160) input by the data line, and the data charged into the pixels of the odd rows is the middle value of the data corresponding to the two adjacent pixel rows.

[0062] The HSR drive method is used so that in odd frames, the data of odd rows are the accurate data input by the data line, while the data of even rows are filled with the intermediate value of the adjacent rows, and the data corresponding to each row of pixels is not repeated, thus achieving a display resolution of 4K (row). Similarly, the same is true for even frames.

[0063] Figure 3 It is a schematic diagram of a black and white line picture in the related art. For the display data of the black and white line picture transmitted by the system end, such as the system on chip (SOC), such as black / white (0 / 255 grayscale), it should be displayed as follows Figure 3 The picture shown. However, if the HSR driving method is adopted, in odd frames, the odd rows can accurately display the data input by the data lines, but the data corresponding to the even rows is the middle value of the data of the adjacent pixel rows, then the even rows will not display white, but the middle value of the pixel data of the upper and lower rows, that is, (0+0) / 2=0, 0 grayscale is black, and it will be displayed as a completely black picture. Similarly, in even frames, the even rows can accurately display the data input by the data lines, but the data corresponding to the odd rows is the middle value of the data of the adjacent pixel rows, then the odd rows will not display black, but the middle value of the pixel data of the upper and lower rows, that is, (255+255) / 2=255, 255 grayscale is white, and it will be displayed as a completely white picture, resulting in a display effect of flickering black and white pictures, causing the display panel 10 to be unable to display black and white row pictures normally.

[0064] Therefore, for special images such as black and white rows and checkerboard images, the driving method in which the data charged into a row of pixels is the middle value of the data corresponding to the adjacent pixel rows will cause abnormal display problems such as full black, full white or gradient colors, resulting in poor display effect of the display panel 10 for special images.

[0065] Figure 4 is a schematic diagram of the structure of a display module provided in an embodiment of the present application, such as Figure 4 As shown, the display module includes:

[0066] The display panel 10 includes a pixel array, the pixel array includes a plurality of first sub-arrays 101 and a plurality of second sub-arrays 102, the first sub-arrays 101 and the second sub-arrays 102 are arranged at least in a column direction; the first sub-arrays 101 and the second sub-arrays 102 respectively include a plurality of pixel rows;

[0067] The display driving circuit 20 is electrically connected to the display panel 10 and is configured to, when the display data is the first picture data, drive the first sub-array 101 to display the picture corresponding to the first sub-data using the first driving mode, and drive the second sub-array 102 to display the picture corresponding to the second sub-data, and, when the display data is the second picture data, drive the pixel array to display the picture corresponding to the second picture data using the second driving mode;

[0068] Among them, the first picture data includes at most the first sub-data and the second sub-data, and the first sub-data and the second sub-data are different data; in the first driving mode, the data charged into the pixel row is the first sub-data or the second sub-data, and in the second driving mode, the data charged into at least one pixel row is obtained based on the data charged into the adjacent pixel row.

[0069] In some embodiments, the display panel 10 includes a pixel array composed of a plurality of pixel arrays, the pixel array including a plurality of pixel rows and a plurality of pixel columns. Each pixel row is provided with at least one scan line, that is, each row of pixels is electrically connected to a corresponding scan line. Each pixel column is provided with at least one data line, that is, each column of pixels is electrically connected to a corresponding data line.

[0070] In some embodiments, the pixel array is divided into a plurality of first sub-arrays 101 and a plurality of second sub-arrays 102, each of the first sub-arrays 101 includes a plurality of pixel rows, and each of the second sub-arrays 102 also includes a plurality of pixel rows. The plurality of first sub-arrays 101 and the plurality of second sub-arrays 102 are arranged at least along the column direction, and the first sub-arrays 101 and the second sub-arrays 102 are arranged at intervals. The interval arrangement means that along the column direction, the second sub-array 102 is adjacent to the first sub-array 101, and the first sub-array 101 is adjacent to the second sub-array 102.

[0071] In some embodiments, the display driving circuit 20 is used to drive the display panel 10 to display a picture according to the display data. The display driving circuit 20 may include a timing control circuit, a gate driving circuit, and a source driving circuit. The timing control circuit is electrically connected to the gate driving circuit, and the gate driving circuit is electrically connected to multiple scan lines of the display panel 10 respectively. The timing control circuit is also electrically connected to the source driving circuit, and the source driving circuit is electrically connected to multiple data lines of the display panel 10 respectively. The gate driving circuit can send a row scanning signal to the pixel row through the scanning line, thereby controlling each pixel in the pixel row to turn on, so that the pixel in the row can receive the data signal transmitted by the data line. The source driving circuit can send a data signal to the pixel column through the data line, so as to input the display data into the pixels in each pixel column to drive the pixel array to display the picture.

[0072] In some embodiments, based on the pixel architecture of the pixel array of the display panel 10, if the display data received by the display driving circuit 20 has a complete amount of column data but insufficient amount of row data, such data can be determined as the second picture data. At this time, the display driving circuit 20 can adopt the second driving mode, so that the data charged into at least one pixel row is obtained based on the data charged into the adjacent pixel rows, thereby driving the pixel array to display the picture corresponding to the second picture data.

[0073] Specifically, if the amount of row data in the display data is only half, then in odd frames, the data of the odd rows is the data signal input by the data line and the even rows are charged with the middle value of the adjacent row data, that is, the data charged into the pixels of the even rows is obtained based on the data charged into the adjacent odd rows of pixels. In even frames, the data of the even rows is the data signal input by the data line and the even rows are charged with the middle value of the adjacent row data, that is, the data charged into the pixels of the odd rows is obtained based on the data charged into the adjacent even rows of pixels. In this way, the pixel array of the display panel 10 can be driven to display the picture corresponding to the second picture data without reducing the resolution. For example, the HSR driving method in the related art can be adopted as the second driving mode in this embodiment.

[0074] In some embodiments, the first screen data corresponding to some special screens include at most the first sub-data and the second sub-data, and the first sub-data and the second sub-data are different data. For example, in the first screen data corresponding to the black and white line screen, the first sub-data may be the black line data, and the second sub-data may be the white line data. In the first screen data corresponding to the black and white chessboard screen, the first sub-data may be a row of black and white grid data starting with the black grid, and the second sub-data may be a row of black and white grid data starting with the white grid. This is only an example, and the embodiments of the present application are not limited to this.

[0075] In some embodiments, if the display data received by the display driving circuit 20 includes at most the first sub-data and the second sub-data, the display data is the first picture data, and the display picture corresponding to the first picture data is a special picture such as a black and white line picture, a checkerboard picture, etc., then the display driving circuit 20 adopts the first driving mode to drive the pixel array of the display panel 10 to display the picture corresponding to the first picture data.

[0076] Specifically, the display driving circuit 20 displays a picture corresponding to the first sub-data by driving the first sub-array 101, and displays a picture corresponding to the second sub-data by driving the second sub-array 102. Since the first sub-array 101 and the second sub-array 102 respectively include a plurality of pixel rows, and the first sub-array 101 and the second sub-array 102 are arranged at intervals along the column direction, the picture displayed by the first sub-array 101 and the picture displayed by the second sub-array 102 can constitute some special pictures with a repetitive pattern.

[0077] For example, for a black-and-white line picture, the first sub-data may be black line data, the second sub-data may be white line data, and the first picture data corresponding to the black-and-white line picture also only includes two different types of data, black line data and white line data. The black-and-white line picture can be displayed by the multiple first sub-arrays 101 and the multiple second sub-arrays 102 of the display panel 10, meeting the display requirements of special pictures such as black-and-white line pictures.

[0078] For example, for a black-and-white checkerboard image, the first sub-data may be a row of black-and-white grid data displayed in the order of black grid / white grid / black grid / white grid, and the second sub-data may be a row of black-and-white data displayed in the order of white grid / black grid / white grid / black grid, and the black-and-white checkerboard image also only includes these two different data. Then, the black-and-white checkerboard image may be displayed by the multiple first sub-arrays 101 and the multiple second sub-arrays 102 of the display panel 10, meeting the display requirements of a special image such as a black-and-white checkerboard image.

[0079] Among them, since the first subarray 101 and the second subarray 102 respectively include multiple pixel rows, taking the black and white row picture as an example, the black row may not be limited to being displayed by one row of pixels, but may also be displayed by multiple continuous pixel rows at the same time, and the white row is also not limited to being displayed by one row of pixels. The first sub-data may include picture data corresponding to one or more rows of pixels, and the second pixel may also include picture data corresponding to one or more rows of pixels. The first subarray 101 and the second subarray 102 display black rows and white rows respectively along the column direction, and the pixel array can display the black and white row picture. Among them, if the number of pixel rows included in the first subarray 101 and the second subarray 102 is equal, the width of the black row and the white row in the black and white row picture is also equal. The same is true for other special pictures such as checkerboard pictures, which will not be repeated here.

[0080] In the embodiment of the present application, the first picture data includes at most two different data, the first sub-data and the second sub-data, and the display picture corresponding to the first picture data includes at most two different pictures, the picture corresponding to the first sub-data and the picture corresponding to the second sub-data. The display driving circuit 20 is configured to drive the first sub-array 101 in the pixel array to display the picture corresponding to the first sub-data using the first driving mode when the display data is the first picture data, and drive the second sub-array 102 in the pixel array to display the picture corresponding to the second sub-data, so that the picture corresponding to the first picture data is displayed through the pixel array of the display panel 10. And the display driving circuit 20 is configured to drive the pixel array to display the picture corresponding to the second picture data using the second driving mode when the display data is the second picture data. In this way, in the first driving mode, the data charged into the pixel row is the first sub-data or the second sub-data, and in the second driving mode, the data charged into at least one pixel row is obtained based on the data charged into the adjacent pixel rows. Therefore, for the display screen corresponding to the first screen data, the data charged into the pixel row in the first driving mode has nothing to do with the adjacent pixel rows, which is different from the second driving mode. This avoids the problem in the related technology that for special screens such as interlaced black and white screens and checkerboard screens, the middle value of two adjacent rows of screen data is charged into a certain pixel row, which will cause abnormal display problems such as full black, full white or gradient colors, and can improve the display effect of the display module.

[0081] Optionally, the display driving circuit 20 includes a timing control circuit and a gate driving circuit, the timing control circuit is electrically connected to the gate driving circuit; each pixel row of the pixel array is provided with at least one scanning line, and the gate driving circuit is electrically connected to the scanning line;

[0082] The timing control circuit is configured to control the gate driving circuit to send a row scanning signal to the scanning line corresponding to each pixel row in the first driving mode, so that each pixel row is turned on, each pixel row of the first sub-array 101 is charged with the first sub-data, and each pixel row of the second sub-array 102 is charged with the second sub-data.

[0083] In some embodiments, in the first driving mode, each pixel row in the first subarray 101 is turned on under the control of a row scanning signal sent by a gate driving circuit, and each pixel row in the second subarray 102 is also turned on under the control of a row scanning signal sent by a gate driving circuit, so each pixel row in the pixel array is turned on.

[0084] In some embodiments, since each pixel row of the first subarray 101 is charged with the first subdata, each pixel row of the first subarray 101 displays the picture corresponding to the first subdata, so that the first subarray 101 displays the picture corresponding to the first subdata. Since each pixel row of the second subarray 102 is charged with the second subdata, each pixel row of the second subarray 102 displays the picture corresponding to the second subdata, so that the second subarray 102 displays the picture corresponding to the second subdata. In this way, by turning on each pixel row, the resolution of the displayed picture corresponding to the first picture data is avoided from being reduced.

[0085] In some embodiments, the timing control circuit can be connected to a system end, such as a system-on-chip (SOC) of a display device, receive display data sent by the system end, and detect the display data to detect whether the display data is first-screen data corresponding to a special screen, and detect whether the display data is second-screen data with insufficient row data volume.

[0086] For example, Figure 5 As shown, when the timing control circuit detects that there is first picture data including at most two different data, the first sub-data and the second sub-data, in the display data, the timing control circuit executes the first driving mode, that is, drives the first sub-array 101 to display the picture corresponding to the first sub-data. When the timing control circuit detects that the amount of data in the display data is insufficient relative to the pixel architecture row, the timing control circuit executes the second driving mode, that is, drives the pixel array to display the picture corresponding to the second picture data. Among them, the first driving mode is the driving mode provided in this embodiment, and the second driving mode can be a driving mode of hardware super resolution (HSR) to avoid display abnormality when the display panel 10 displays special pictures.

[0087] Optionally, the display driving circuit 20 further includes a source driving circuit, and the timing control circuit is electrically connected to the source driving circuit; each pixel column of the pixel array is provided with at least one data line, and the source driving circuit is electrically connected to the data line;

[0088] The timing control circuit is configured to control the source driving circuit to send a data signal to the data line in the first driving mode, so that the valid signal interval of the first sub-data corresponding to the first sub-array 101 covers the turn-on interval of multiple pixel rows in the first sub-array 101, and the valid signal interval of the second sub-data corresponding to the second sub-array 102 covers the turn-on interval of multiple pixel rows in the second sub-array 102.

[0089] In some embodiments, the source driving circuit is electrically connected to multiple data lines of the display panel 10 respectively, and the source driving circuit can send data signals to the data lines, thereby inputting the data signals into pixels in each pixel column to drive the pixel array to display the picture corresponding to the first picture data.

[0090] In some embodiments, the timing control circuit adopts the first driving mode when detecting that the display data is the first screen data including at most the first sub-data and the second sub-data. In the first driving mode, the timing control circuit drives the first sub-array 101 to display the screen corresponding to the first sub-data and drives the second sub-array 102 to display the screen corresponding to the second sub-data by controlling the gate driving circuit and the source driving circuit to adjust the waveform of the driving signal. The timing control circuit controls the timing relationship between the row scanning signal sent by the gate driving circuit and the data signal sent by the source driving circuit so that the pixel array of the display panel 10 displays the display screen corresponding to the first screen data.

[0091] Specifically, the timing control circuit controls the gate driving circuit to send row scanning signals to the scanning lines corresponding to each pixel row in the first driving mode, and the timing control circuit controls the source driving circuit to send data signals to the data lines, so that each pixel row in the first subarray 101 and each pixel row in the second subarray 102 are turned on, and the effective signal interval of the first sub-data corresponding to the first subarray 101 covers the turn-on intervals of multiple pixel rows in the first subarray 101, and the effective signal interval of the second sub-data corresponding to the second subarray 102 covers the turn-on intervals of multiple pixel rows in the second subarray 102. In this way, each pixel row in the first subarray 101 is charged with the first sub-data, and each pixel row in the second subarray 102 is charged with the second sub-data.

[0092] The on-interval of the pixel row indicates the time interval of the effective duration of the row scanning signal corresponding to the pixel row. The effective signal interval of the first sub-data corresponding to the first sub-array 101 indicates the time interval of the effective duration of the data signal transmitted to each pixel in the first sub-array 101 by the source driving circuit through the data line, and the data signal is obtained according to the first sub-data corresponding to the first sub-array 101. The effective signal interval of the second sub-data corresponding to the second sub-array 102 is similar, indicating the time interval of the effective duration of the data signal transmitted to each pixel in the second sub-array 102 by the source driving circuit through the data line, and the data signal is obtained according to the first sub-data corresponding to the second sub-array 102.

[0093] In this embodiment, the valid signal interval of the first sub-data corresponding to the first sub-array 101 covers the on-interval of multiple pixel rows in the first sub-array 101, and the valid signal interval of the second sub-data corresponding to the second sub-array 102 covers the on-interval of multiple pixel rows in the second sub-array 102, so that each pixel row of the first sub-array 101 is charged with the first sub-data, and each pixel row of the second sub-array 102 is charged with the second sub-data.

[0094] Among them, the first signal edge of the data signal transmitted by the data line to each pixel in the first sub-array 101 is advanced by a certain time length of the first signal edge of the row scanning signal received by the first pixel row in the first sub-array 101. In addition, the second signal edge of the data signal transmitted by the data line to each pixel in the first sub-array 101 is delayed by a certain time length of the first signal edge of the row scanning signal received by the last pixel row in the first sub-array 101. That is, the valid signal interval of the first sub-data corresponding to the first sub-array 101 covers the opening interval of multiple pixel rows in the first sub-array 101. The second sub-array 102 is the same, which will not be repeated here. The advance or delay time length is greater than zero. The first signal edge can be a rising edge or a falling edge, and the second signal edge is a signal edge opposite to the first signal edge.

[0095] In this way, the timing control circuit controls the timing relationship between the row scanning signal sent by the gate driving circuit and the data signal sent by the source driving circuit, so that multiple pixel rows in the first sub-array 101 and the second sub-array 102 are turned on, and each pixel row of the first sub-array 101 is charged with the first sub-data to display the corresponding picture, and each pixel row of the second sub-array 102 is charged with the second sub-data to display the corresponding picture, so that the pixel array of the display panel 10 can normally display the display picture corresponding to the first picture data without reducing the picture resolution.

[0096] Optionally, the gate driving circuit includes a plurality of gate driving terminals, each gate driving terminal being electrically connected to a corresponding pixel row via a scanning line;

[0097] The timing control circuit is configured to control multiple gate driving terminals of the gate driving circuit in the first driving mode to send row scanning signals to the scanning lines corresponding to each pixel row in turn, so that the pixel array is turned on row by row along the column direction, and the turn-on intervals of different pixel rows do not overlap.

[0098] In some embodiments, the timing control circuit controls the gate driving circuit to scan the pixel array row by row along the column direction, so that the pixel array is turned on row by row along the column direction. In the pixel array of this embodiment, a plurality of first sub-arrays 101 and a plurality of second sub-arrays 102 are arranged at intervals along the column direction, and the first sub-array 101 and the second sub-array 102 respectively include a plurality of pixel rows. The timing control circuit controls the gate driving circuit to scan row by row, and then the plurality of pixel rows of each first sub-array 101 are also turned on row by row, and the plurality of pixel rows of each second sub-array 102 are also turned on row by row.

[0099] In some embodiments, the gate driving circuit may include multiple gate driving terminals of the gate driving circuit, and multiple gate driving terminals of the gate driving circuit may be multiple output terminals of the gate driving IC. Alternatively, the gate driving circuit may include multiple gate driving units connected in cascade, and the gate driving circuit may include multiple gate driving terminals of the gate driving circuit, and multiple gate driving terminals of the gate driving circuit may be output terminals of the multiple gate driving units.

[0100] Specifically, in the first driving mode, the timing control circuit controls the multiple gate driving terminals of the gate driving circuit to sequentially send row scanning signals to the scanning lines corresponding to each pixel row, and controls the corresponding pixel row to be turned on through the row scanning signals, so that the pixels in the pixel row can receive the data signal transmitted by the data line. Among them, the time intervals of the effective duration of the row scanning signals corresponding to different pixel rows do not overlap with each other, so that the opening intervals of different pixel rows do not overlap with each other.

[0101] Thus, in the first driving mode, the gate driving circuit scans row by row so that the pixel array is turned on row by row, and each pixel row of the first sub-array 101 receives the data signal transmitted by the data line after being turned on, so as to be charged with the first sub-data, and each pixel row of the second sub-array 102 receives the data signal transmitted by the data line after being turned on, so as to be charged with the second sub-data. Therefore, the data charged into the pixel row is directly the first sub-data or the second sub-data, and has nothing to do with the data charged into the adjacent pixel row.

[0102] Optionally, the first sub-array 101 includes N pixel rows; the second sub-array 102 includes M pixel rows;

[0103] The duration of the open interval of each pixel row in the first subarray 101 is equal to the row scanning duration, and the duration of the open interval of each pixel row in the second subarray 102 is equal to the row scanning duration;

[0104] The duration of the valid signal interval of the first sub-data corresponding to the first sub-array 101 is substantially equal to N times the row scanning duration, and the duration of the valid signal interval of the second sub-data corresponding to the second sub-array 102 is substantially equal to M times the row scanning duration; wherein N and M are positive integers respectively.

[0105] In some embodiments, the effective duration of the row scanning signal corresponding to each pixel row in the first sub-array 101 and the second sub-array 102 is one row scanning duration, where the row scanning duration indicates the duration required to turn on a row of pixels, and one row scanning duration is represented by 1H. In this way, the duration of the turn-on interval of each pixel row in the first sub-array 101 is equal to 1H, and the duration of the turn-on interval of each pixel row in the second sub-array 102 is equal to 1H.

[0106] In some embodiments, the first sub-array 101 includes N pixel rows, and the second sub-array 102 includes M pixel rows, where N and M are positive integers, respectively, and N and M may be equal or unequal, and the embodiments of the present application do not limit this. The effective duration of the data signal transmitted by the data line to each pixel in the first sub-array 101 is substantially equal to N times the row scanning duration, so that the effective signal interval of the first sub-data corresponding to the first sub-array 101 covers the opening interval of multiple pixel rows in the first sub-array 101. Similarly, the effective duration of the data signal transmitted by the data line to each pixel in the second sub-array 102 is substantially equal to M times the row scanning duration, so that the effective signal interval of the second sub-data corresponding to the second sub-array 102 covers the opening interval of multiple pixel rows in the second sub-array 102.

[0107] Figure 6 is a schematic diagram of the structure of a display panel 10 in a display module provided in an embodiment of the present application, such as Figure 6 As shown, the pixel array of the display panel 10 includes N pixel rows, each pixel row corresponds to a scan line, and the display panel 10 includes scan lines G1~G(n). The pixel array includes M pixel columns, each pixel column corresponds to a data line, and the display panel 10 includes data lines S1~Sm. A plurality of GOA units are also provided on the left and right sides of the pixel array, respectively, and GOA is a gate driver integrated unit (Gate Driver OnArray, GOA) on the array substrate. A pixel row is driven by the GOA units on both sides, that is, each GOA unit is electrically connected to the scan line of the corresponding pixel row. The timing control circuit can be a driver IC, and each GOA unit is also electrically connected to the driver IC, and sends a row scan signal to the scan line under the control of the driver IC to drive the corresponding pixel row to turn on.

[0108] In some embodiments, the gate drive circuit may include a plurality of cascaded gate drive units. The timing control circuit is electrically connected to the plurality of cascaded gate drive units via a frame start signal line, the frame start signal line is electrically connected to at least one gate drive unit, and the timing control circuit may send a frame start signal to the frame start signal line. The cascaded gate drive units are also electrically connected to a plurality of clock signal lines to receive clock signals transmitted by the clock signal lines. Figure 7 is a timing diagram of a first driving mode provided in an embodiment of the present application, such as Figure 7 As shown, the timing control circuit can send a frame start signal STV1 to the cascaded gate drive unit through the frame start signal line. The cascaded gate drive unit receives the clock signals clk1-clk4 transmitted by the clock signal line and outputs the row scan signals G1-G4320. The source drive circuit sends the data signals Data1-Data2160 through multiple data lines, so the row data volume is only half of the column data volume.

[0109] The first sub-array 101 and the second sub-array 102 may include two pixel rows respectively. Figure 7 As shown, the gate drive circuit scans row by row, and the odd and even frame drive timings are the same. Specifically, multiple gate drive units send row scan signals to the scan lines corresponding to each pixel row in turn, and the effective time intervals of the row scan signals received by different pixel rows do not overlap with each other. The duration of the opening interval of each pixel row is equal to 1H, and the duration of each effective signal interval of the data signal is approximately equal to 2H. In this way, the first data of the first screen data data is charged into the pixels of the 1st and 2nd rows, the second data of data is charged into the pixels of the 3rd and 4th rows, and so on, the 2160th data of data is charged into the 2159th and 2160th rows of data. In this way, the display screen corresponding to the first screen data is displayed in full screen, and each row of pixels is accurately charged with the data signal determined according to the first screen data. There is no situation where the data charged into a certain pixel row is the middle value of the upper and lower rows of pixels. Therefore, for special screens such as black and white rows or checkerboard screens, there will be no abnormal display problem.

[0110] In this way, the data signal obtained according to the first sub-data corresponding to the first sub-array 101 will not be charged into the pixels in the second sub-array 102, and the data signal obtained according to the second sub-data corresponding to the second sub-array 102 will not be charged into the pixels in the first sub-array 101, thereby avoiding the display abnormality problem of the pictures displayed by the first sub-array 101 and the second sub-array 102.

[0111] Optionally, the gate driving circuit includes a plurality of gate driving ends, each gate driving end being electrically connected to a corresponding pixel row through a scanning line; the timing control circuit is configured to control the plurality of gate driving ends of the gate driving circuit in the first driving mode, and sequentially send row scanning signals to the scanning lines corresponding to the first sub-array 101 and the scanning lines corresponding to the second sub-array 102, so that the plurality of first sub-arrays 101 and the plurality of second sub-arrays 102 are turned on one by one along the column direction, the plurality of pixel rows in the first sub-array 101 are turned on simultaneously, and the plurality of pixel rows in the second sub-array 102 are turned on simultaneously.

[0112] In some embodiments, the timing control circuit controls the gate driving circuit to scan the multiple first sub-arrays 101 and the multiple second sub-arrays 102 of the pixel array one by one along the column direction, and can control the multiple gate driving ends of the gate driving circuit to send row scanning signals to the scanning lines corresponding to the first sub-array 101 and the scanning lines corresponding to the second sub-array 102 in sequence.

[0113] The gate driving circuit may simultaneously send row scanning signals to scanning lines corresponding to multiple pixel rows in a first sub-array 101, so that multiple pixel rows in the first sub-array 101 are turned on at the same time, and then simultaneously send row scanning signals to scanning lines corresponding to multiple pixel rows in the next first sub-array 101. The same is true for the second sub-array 102. The gate driving circuit may simultaneously send row scanning signals to scanning lines corresponding to multiple pixel rows in a second sub-array 102, so that multiple pixel rows in the second sub-array 102 are turned on at the same time, and then simultaneously send row scanning signals to scanning lines corresponding to multiple pixel rows in the next second sub-array 102.

[0114] Thus, in the first driving mode, the gate driving circuit scans the plurality of first sub-arrays 101 and the plurality of second sub-arrays 102 row by row, so that the first sub-arrays 101 and the plurality of second sub-arrays 102 are turned on one by one, and after the plurality of pixel rows of the first sub-array 101 are turned on at the same time, they all receive the data signal transmitted by the data line and are thus charged with the first sub-data, and after the plurality of pixel rows of the second sub-array 102 are turned on at the same time, they all receive the data signal transmitted by the data line and are thus charged with the second sub-data. Therefore, the data charged into the pixel row is directly the first sub-data or the second sub-data, and has nothing to do with the data charged into the adjacent pixel row.

[0115] Optionally, the first sub-array 101 includes N pixel rows; the second sub-array 102 includes M pixel rows;

[0116] The duration of the open interval of each pixel row in the first subarray 101 is equal to N times the row scanning duration, and the duration of the open interval of each pixel row in the second subarray 102 is equal to M times the row scanning duration;

[0117] The duration of the valid signal interval of the first sub-data corresponding to the first sub-array 101 is substantially equal to N times the row scanning duration, and the duration of the valid signal interval of the second sub-data corresponding to the second sub-array 102 is substantially equal to M times the row scanning duration; wherein N and M are positive integers respectively.

[0118] In some embodiments, N pixel rows in the first subarray 101 are turned on at the same time, and the gate driving circuit needs N times the row scanning time to scan the first subarray 101, then the effective time length of the row scanning signal corresponding to each pixel row in the first subarray 101 is N times the row scanning time, so that the time length of the turn-on interval of each pixel row in the first subarray 101 is equal to N times the row scanning time. The same is true for the second subarray 102. Multiple pixel rows in the second subarray 102 are turned on at the same time, and the gate driving circuit needs M times the row scanning time to scan the second subarray 102, then the effective time length of the row scanning signal corresponding to each pixel row in the second subarray 102 is M times the row scanning time, so that the time length of the turn-on interval of each pixel row in the second subarray 102 is equal to M times the row scanning time.

[0119] In some embodiments, the first sub-array 101 includes N pixel rows, and the second sub-array 102 includes M pixel rows, where N and M are positive integers, respectively, and N and M may be equal or unequal, and the embodiments of the present application do not limit this. The effective duration of the data signal transmitted by the data line to each pixel in the first sub-array 101 is substantially equal to N times the row scanning duration, so that the effective signal interval of the first sub-data corresponding to the first sub-array 101 covers the opening interval of multiple pixel rows in the first sub-array 101. Similarly, the effective duration of the data signal transmitted by the data line to each pixel in the second sub-array 102 is substantially equal to M times the row scanning duration, so that the effective signal interval of the second sub-data corresponding to the second sub-array 102 covers the opening interval of multiple pixel rows in the second sub-array 102.

[0120] In some embodiments, the gate drive circuit may include a plurality of cascaded gate drive units. The timing control circuit is electrically connected to the plurality of cascaded gate drive units via a frame start signal line, the frame start signal line is electrically connected to at least one gate drive unit, and the timing control circuit may send a frame start signal to the frame start signal line. The cascaded gate drive units are also electrically connected to a plurality of clock signal lines to receive clock signals transmitted by the clock signal lines. Figure 8 is another timing diagram of the first driving mode provided in an embodiment of the present application, such as Figure 8 As shown, the timing control circuit can send a frame start signal STV1 to the cascaded gate drive unit through the frame start signal line. The cascaded gate drive unit receives the clock signals clk1-clk4 transmitted by the clock signal line and outputs the row scan signals G1-G4320. The source drive circuit sends the data signals Data1-Data2160 through multiple data lines, so the row data volume is only half of the column data volume.

[0121] The first sub-array 101 and the second sub-array 102 may include two pixel rows respectively. Figure 8As shown, the gate drive circuit scans every two rows of pixels one by one, and the odd and even frame drive timings are the same. Specifically, multiple gate drive units send row scan signals to the scan lines corresponding to every two pixel rows in turn, and every two pixel rows are turned on at the same time, and the duration of the opening interval of the pixel row is equal to 2H. In this way, the pixels in the 1st and 2nd rows are turned on at the same time, and the pixels in the 3rd and 4th rows are turned on at the same time, and the duration of each valid signal interval of the data signal is approximately equal to 2H. Therefore, the pixels in the 1st and 2nd rows display the first data sent by the data line, and the pixels in the 3rd and 4th rows display the second data sent by the data line. By analogy, the pixels in the 4319th and 4320th rows display the 2160th data sent by the data line. This method realizes the full-screen display of the display screen corresponding to the first screen data, and each row of pixels is accurately charged with the data signal determined according to the first screen data. There is no situation where the data charged into a certain pixel row is the middle value of the upper and lower rows of pixels. Therefore, for special screens such as black and white rows or checkerboard screens, there will be no abnormal display problem.

[0122] In this way, the data signal obtained according to the first sub-data corresponding to the first sub-array 101 will not be charged into the pixels in the second sub-array 102, and the data signal obtained according to the second sub-data corresponding to the second sub-array 102 will not be charged into the pixels in the first sub-array 101, thereby avoiding the display abnormality problem of the pictures displayed by the first sub-array 101 and the second sub-array 102.

[0123] Optionally, the display driving circuit 20 includes a timing control circuit and a gate driving circuit, the timing control circuit is electrically connected to the gate driving circuit; each pixel row of the pixel array is provided with at least one scanning line, and the gate driving circuit is electrically connected to the scanning line;

[0124] The plurality of pixel rows include at least one first pixel row and at least one second pixel row; the first pixel row and the second pixel row are arranged alternately along a column direction;

[0125] The timing control circuit is configured to control the gate driving circuit to send row scanning signals to the scanning lines corresponding to the first pixel rows respectively in the first driving mode, so that each first pixel row is turned on, the first pixel row of the first sub-array 101 is charged with the first sub-data, and the first pixel row of the second sub-array 102 is charged with the second sub-data,

[0126] Alternatively, the control gate driving circuit sends row scanning signals to the scanning lines corresponding to the second pixel rows respectively, so that each second pixel row is turned on, the second pixel row of the first subarray 101 is charged with the first subdata, and the second pixel row of the second subarray 102 is charged with the second subdata.

[0127] In some embodiments, the gate driving circuit may include a plurality of cascaded gate driving units, and the gate driving units may be provided on the display panel 10 and electrically connected to the scan lines corresponding to the pixel rows. The timing control circuit may be electrically connected to at least one gate driving unit in the gate driving circuit through a frame start signal line, and the timing control circuit controls the cascaded gate driving units by sending a frame start signal to the frame start signal line, so that the gate driving units send a row scan signal to the scan line to drive the corresponding pixel row to turn on.

[0128] In some embodiments, the plurality of pixel rows of the first subarray 101 include at least one first pixel row and at least one second pixel row, and the plurality of pixel rows of the second subarray 102 include at least one first pixel row and at least one second pixel row. In the pixel array of the display panel 10, the plurality of first pixel rows and the plurality of second pixel rows are arranged at intervals along the column direction, that is, the second pixel rows are adjacent to the first pixel rows along the column direction, and the first pixel rows are adjacent to the second pixel rows. The number of pixel rows included in the first subarray 101 and the second subarray 102 may be equal or unequal, as long as the first pixel rows and the second pixel rows are arranged at intervals along the column direction.

[0129] In some embodiments, the timing control circuit originally executes the second driving mode, and the data charged into at least one pixel row is obtained based on the data charged into the adjacent pixel row, so that when the row data amount of the second picture data is insufficient, the pixel array of the display panel 10 can still display the picture corresponding to the second picture data. When the timing control circuit detects that the display data includes at most two different data, the first sub-data and the second sub-data, and the row data amount is only half of the first picture data, the timing control circuit switches to execute the first driving mode, and at this time, the picture corresponding to the first picture data can be displayed by turning on the first pixel row and turning off the second pixel row, or by turning off the first pixel row and turning on the second pixel row.

[0130] In some embodiments, since each first pixel row of the first subarray 101 is charged with the first subdata, or since the second pixel row of the first subarray 101 is charged with the first subdata, the first subarray 101 can display a picture corresponding to the first subdata. Since the first pixel row of the second subarray 102 is charged with the second subdata, or since the second pixel row of the second subarray 102 is charged with the second subdata, the second subarray 102 can display a picture corresponding to the second subdata.

[0131] Therefore, in the first driving mode, whether the first pixel row is turned on and the second pixel row is turned off, or the picture corresponding to the first picture data is displayed by turning off the first pixel row and turning on the second pixel row, the first sub-array 101 can be driven to display the picture corresponding to the first sub-data, and the second sub-array 102 can be driven to display the picture corresponding to the second sub-data. In this way, the picture corresponding to the first picture data can be displayed by multiple first sub-arrays 101 and multiple second sub-arrays 102.

[0132] Although turning on the first pixel row and turning off the second pixel row, or turning off the first pixel row and turning on the second pixel row, there will be a problem of reduced picture resolution. However, after the timing control circuit switches from the second driving mode originally executed to the first driving mode, the row scanning signal sent by the gate driving circuit only needs to control the first pixel row or the second pixel row in the pixel array to turn on, and the waveform of the data signal sent by the source driving circuit to the data line can be consistent with that in the second driving mode, thereby reducing the difficulty of timing control. Moreover, under the premise of avoiding display abnormalities, the picture corresponding to the first picture data is displayed through the pixel array.

[0133] Optionally, the display driving circuit 20 further includes a source driving circuit, and the timing control circuit is electrically connected to the source driving circuit; each pixel column of the pixel array is provided with at least one data line, and the source driving circuit is electrically connected to the data line;

[0134] The timing control circuit is configured to control the source driving circuit to send a data signal to the data line in the first driving mode, so that the valid signal interval of the first sub-data corresponding to the first sub-array 101 covers the open interval of the first pixel row in the first sub-array 101, and the valid signal interval of the second sub-data corresponding to the second sub-array 102 covers the open interval of the first pixel row in the second sub-array 102.

[0135] Alternatively, the valid signal interval of the first sub-data corresponding to the first sub-array 101 covers the on-interval of the second pixel row in the first sub-array 101 , and the valid signal interval of the second sub-data corresponding to the second sub-array 102 covers the on-interval of the second pixel row in the second sub-array 102 .

[0136] In some embodiments, the timing control circuit controls the gate driving circuit to send a row scan signal to the scan line corresponding to each first pixel row in the first driving mode, and the timing control circuit controls the source driving circuit to send a data signal to the data line, so that each first pixel row in the first subarray 101 and each first pixel row in the second subarray 102 are turned on, and the effective signal interval of the first sub-data corresponding to the first subarray 101 covers the turn-on intervals of multiple first pixel rows in the first subarray 101, and the effective signal interval of the second sub-data corresponding to the second subarray 102 covers the turn-on intervals of multiple first pixel rows in the second subarray 102. In this way, each first pixel row of the first subarray 101 is charged with the first sub-data, and each first pixel row of the second subarray 102 is charged with the second sub-data.

[0137] Alternatively, the timing control circuit controls the gate driving circuit to send a row scanning signal to the scanning line corresponding to each second pixel row in the first driving mode, and the timing control circuit controls the source driving circuit to send a data signal to the data line, so that each second pixel row in the first subarray 101 and each second pixel row in the second subarray 102 are turned on, and the effective signal interval of the first sub-data corresponding to the first subarray 101 covers the turn-on intervals of multiple second pixel rows in the first subarray 101, and the effective signal interval of the second sub-data corresponding to the second subarray 102 covers the turn-on intervals of multiple second pixel rows in the second subarray 102. In this way, each second pixel row in the first subarray 101 is charged with the first sub-data, and each second pixel row in the second subarray 102 is charged with the second sub-data.

[0138] In this way, in the first driving mode, the first pixel row or the second pixel row of the pixel array displays the picture corresponding to the first picture data, so that the data charged into the pixel row has nothing to do with the adjacent pixel rows, thereby avoiding abnormal display problems caused by charging the intermediate value of two adjacent rows of picture data into a certain pixel row.

[0139] Optionally, the first pixel row is an odd-numbered row of the pixel array, and the second pixel row is an even-numbered row of the pixel array; and the timing control circuit is configured as follows:

[0140] In an odd frame, in a first driving mode, the gate driving circuit is controlled to send row scanning signals to the scanning lines corresponding to the first pixel rows, so that each first pixel row is turned on and each second pixel row is turned off for display;

[0141] In an even frame, in the first driving mode, the gate driving circuit is controlled to send row scanning signals to the scanning lines corresponding to the second pixel rows respectively, so that each second pixel row is turned on and each first pixel row is turned off for display.

[0142] In some embodiments, compared with the HSR driving method used in the related art, that is, when the odd frame is an odd-numbered frame, the data of the odd-numbered row is the accurate data input by the data line and the even-numbered row is filled with the intermediate value of the data of the adjacent row; when the even frame is an even-numbered frame, the data of the even-numbered row is the accurate data input by the data line and the odd-numbered row is filled with the intermediate value of the data of the adjacent row. In the display module provided by this embodiment, the first pixel row can be an odd-numbered row of the pixel array, and the second pixel row can be an even-numbered row of the pixel array. In an odd-numbered frame, the first pixel row, i.e., the odd-numbered row, can be turned on, and the second pixel row, i.e., the even-numbered row, can be turned off; and in an even-numbered frame, the second pixel row, i.e., the even-numbered row, can be turned on, and the first pixel row, i.e., the odd-numbered row, can be turned off.

[0143] Specifically, in the first driving mode, during odd frames, the timing control circuit controls the gate driving circuit to send row scanning signals to the scanning lines corresponding to the first pixel rows, so that each first pixel row is turned on. Since the gate driving circuit does not send row scanning signals to the scanning lines corresponding to the second pixel rows, each second pixel row of the pixel array is turned off. Then, during even frames, the timing control circuit controls the gate driving circuit to send row scanning signals to the scanning lines corresponding to the second pixel rows, so that each second pixel row is turned on. Similarly, since the gate driving circuit does not send row scanning signals to the scanning lines corresponding to the first pixel rows, each first pixel row of the pixel array is turned off.

[0144] Thus, in the first driving mode, odd-numbered rows display the picture corresponding to the first picture data in odd-numbered frames, and even-numbered rows display the picture corresponding to the first picture data in even-numbered frames. This is different from the operation of charging the middle value of two adjacent lines of picture data into a certain pixel row in the HSR driving mode in the related art, and can avoid abnormal display problems such as full black, full white or gradient color for special pictures such as interlaced black and white pictures and checkerboard pictures.

[0145] Optionally, the gate driving circuit includes a plurality of gate driving terminals, each gate driving terminal being electrically connected to a corresponding pixel row via a scanning line;

[0146] The timing control circuit is configured to control multiple gate driving ends in a first driving mode to send row scanning signals to the scanning lines corresponding to each first pixel row in turn, so that the first pixel rows are turned on row by row along the column direction, or to control multiple gate driving ends to send row scanning signals to the scanning lines corresponding to each second pixel row in turn, so that the second pixel rows are turned on row by row along the column direction.

[0147] In some embodiments, the timing control circuit controls the gate driving circuit to scan the multiple first pixel rows of the pixel array row by row, that is, controls the multiple gate driving ends of the gate driving circuit to send row scanning signals to the scanning lines corresponding to each first pixel row in turn, so that the multiple first pixel rows are turned on row by row along the column direction, and then the pixels in the first pixel rows can receive the data signals transmitted by the data lines. Alternatively, the timing control circuit controls the gate driving circuit to scan the multiple second pixel rows of the pixel array row by row, that is, controls the multiple gate driving ends of the gate driving circuit to send row scanning signals to the scanning lines corresponding to each second pixel row in turn, so that the multiple second pixel rows are turned on row by row along the column direction, and then the pixels in the second pixel rows can receive the data signals transmitted by the data lines.

[0148] by Figure 2 For example, in this embodiment, in an odd frame, a row scanning signal is sent to odd rows (1, 3, 5 ... 4319), then the valid signal interval of the first sub-data corresponding to any odd row can cover the opening interval of the odd row, such as Figure 2 In the example, signal data(1) can cover the opening interval of odd-numbered rows G1. Even-numbered rows (2, 4, 6…4320) are closed, and even-numbered row pixels will not be charged with data. Therefore, it can be avoided that even-numbered rows are charged with the middle value of the data of two adjacent odd-numbered rows, causing abnormal display problems such as full black, full white or gradient colors. The same is true for even-numbered frames, which will not be repeated here.

[0149] Optionally, the gate driving circuit includes a plurality of cascaded gate driving units, and the gate driving units are electrically connected to the scanning lines corresponding to the pixel rows;

[0150] The display panel 10 further includes at least two frame start signal lines; the frame start signal line is electrically connected to at least one gate driving unit, and the frame start signal line is also electrically connected to the timing control circuit;

[0151] The at least two frame start signal lines include a first frame start signal line and a second frame start signal line; wherein the gate drive unit corresponding to the first pixel row is controlled by the frame start signal transmitted by the first frame start signal line, and the gate drive unit corresponding to the second pixel row is controlled by the frame start signal transmitted by the second frame start signal line;

[0152] The timing control circuit is configured to, in a first driving mode, send a frame start signal to the first frame start signal line so that the gate driving unit corresponding to the first pixel row controls the first pixel row to turn on, or to send a frame start signal to the second frame start signal line so that the gate driving unit corresponding to the second pixel row controls the second pixel row to turn on.

[0153] In some embodiments, a plurality of gate driving units may be provided on the display panel 10, the gate driving units are cascaded with each other, each gate driving unit is electrically connected to a scan line of a corresponding pixel row, and the gate driving unit may send a row scanning signal to the corresponding pixel row through the scan line, so that the corresponding pixel row is turned on. For example, the gate driving circuit includes a plurality of cascaded GOA units, each GOA unit is electrically connected to a scan line of a corresponding pixel row.

[0154] In some embodiments, the display panel 10 further includes at least two frame start signal lines, namely a first frame start signal line and a second frame start signal line, each of which is electrically connected to at least one gate drive unit. The frame start signal line is also electrically connected to a timing control circuit, and the timing control circuit can control a plurality of cascaded gate drive units by sending a frame start signal to the frame start signal line. In this way, the difficulty of timing control of the timing control circuit can be reduced.

[0155] Specifically, the gate driving unit corresponding to the first pixel row is controlled by the frame start signal transmitted by the first frame start signal line. The timing control circuit can send a frame start signal to the first frame start signal line in the first driving mode. The first frame start signal line transmits the frame start signal line to the connected gate driving unit to control the cascaded gate driving unit to send a row scan signal to the scan line, thereby turning on the first pixel row.

[0156] Specifically, the gate driving unit corresponding to the second pixel row is controlled by the frame start signal transmitted by the second frame start signal line. The timing control circuit can send a frame start signal to the second frame start signal line in the first driving mode. The second frame start signal line transmits the frame start signal line to the connected gate driving unit to control the cascaded gate driving unit to send a row scan signal to the scan line, thereby turning on the second pixel row.

[0157] In some embodiments, the first pixel row is an odd row of a pixel array, and the second pixel row is an even row of a pixel array. The first frame start signal line can be used to control the gate drive unit corresponding to the odd row, and the second frame start signal line can be used to control the gate drive unit corresponding to the even row. In the first driving mode, the timing control circuit sends a frame start signal line to the first frame start signal line in an odd frame to control the gate drive unit corresponding to the odd row to send a gate drive signal to the scan line corresponding to the odd row, so that each odd row is turned on and the even row is turned off. In an even frame, the frame start signal line is sent to the second frame start signal line to control the gate drive unit corresponding to the even row to send a gate drive signal to the scan line corresponding to the even row, so that each even row is turned on and the odd row is turned off. This is only an example, and the embodiments of the present application are not limited to this.

[0158] Fig. 9FIG. 1 is a schematic diagram of the structure of another display panel 10 in a display module provided in an embodiment of the present application. The pixel array of the display panel 10 includes a plurality of pixel rows, such as Fig. 9 As shown, it includes at least 1 to 12 rows of pixels, and each pixel row corresponds to a scanning line. A plurality of cascaded GOA units are also provided on the left and right sides of the pixel array, and the output signal of the previous GOA unit can be used as the input signal of the next GOA unit, and the output signal of the next GOA unit can be used as the reset signal of the previous GOA unit. Fig. 9 As shown, GOA1L~GOA12L are arranged on the left side, GOA1R~GOA12R are arranged on the right side, the output signal of GOA1R unit is used as the input signal (Input) of GOA7R unit, and the output signal of GOA9R unit is used as the reset signal (Reset) of GOA1R unit. A pixel row is driven by GOA units on both sides, that is, each GOA unit is electrically connected to the scan line of the corresponding pixel row.

[0159] The timing control circuit is electrically connected to the cascaded multiple GOA units through two frame start signal lines, namely, a first frame start signal line STV1A and a second frame start signal line STV1B. Fig. 9 As shown, the first frame start signal line STV1A is electrically connected to GOA1L, GOA3L and GOA5L respectively, and the first frame start signal line STV1B is electrically connected to GOA2L, GOA4L and GOA6L respectively.

[0160] Optionally, the first sub-data represents that the pixel row displays a black picture, and the second sub-data represents that the pixel row displays a white picture;

[0161] Alternatively, the first sub-data represents a pixel row displaying a first black and white grid picture, and the second sub-data represents a pixel row displaying a second black and white grid picture, wherein the first pixel in the pixel row displays black grids in the first black and white grid picture, and the first pixel in the pixel row displays white grids in the second black and white grid picture.

[0162] In some embodiments, the first sub-data represents that the pixel row displays a black picture, and the second sub-data represents that the pixel row displays a white picture, so that the display picture corresponding to the first picture data includes at most a black picture and a white picture. Since the data charged into the pixel row in the first driving mode is the first sub-data or the second sub-data, the pixel row charged with the data in the pixel array displays a black picture or a white picture.

[0163] Specifically, in the first driving mode, the display driving circuit 20 drives the pixel rows in the first sub-array 101 to display a black picture corresponding to the first sub-data, and drives the pixel rows in the second sub-array 102 to display a white picture corresponding to the second sub-data. In this way, the black and white row pictures corresponding to the first picture data can be displayed through the first sub-array 101 and the second sub-array 102 arranged in a column direction in the pixel array.

[0164] In some embodiments, the first picture data includes first sub-data corresponding to the black line picture and second sub-data corresponding to the white line picture. The timing control circuit can control each pixel row in the first sub-array 101 to be turned on and the second sub-array 102 to be turned off through the gate driving circuit, and the pixel row of the first sub-array 101 displays the white line picture corresponding to the second sub-data, so that the pixel array can also present the display effect of black and white lines. Alternatively, each pixel row in the second sub-array 102 is turned on and the first sub-array 101 is turned off, and the pixel row of the second sub-array 102 displays the white line picture corresponding to the second sub-data. The same is true, which will not be repeated here.

[0165] Fig.10 is a timing diagram of another first driving mode provided in an embodiment of the present application, such as Fig.10 As shown, the timing control circuit sends a frame start signal to the first frame start signal line STV1A, while the frame start signal of the second frame start signal line STV1B is invalid. The GOA units corresponding to the odd rows are controlled to send row scan signals to the scan lines G1, G3, etc. corresponding to the pixel rows, while the row scan signals of the scan lines corresponding to the even rows of pixels are invalid. The data signal sent by the source drive circuit through the data line can be called the second sub-data, i.e., the data signal corresponding to the white row picture data, such as a high level signal (H), so as to obtain a display effect of white pictures for odd rows and black pictures for even rows.

[0166] In some embodiments, the first sub-data represents that the pixel row displays a first black-and-white checkered picture, and the second sub-data represents that the pixel row displays a second black-and-white checkered picture, so that the display picture corresponding to the first picture data includes at most two different black-and-white checkered pictures. Since the data charged into the pixel row in the first driving mode is the first sub-data or the second sub-data, the pixel row charged with the data in the pixel array displays the first black-and-white checkered picture or the second black-and-white checkered picture.

[0167] Specifically, the first sub-data may be a row of black and white grid data starting with a black grid, so the first pixel in the pixel row displays the black grid in the first black and white grid picture. The second sub-data may be a row of black and white grid data starting with a white grid, so the first pixel in the pixel row displays the white grid in the second black and white grid picture. That is, the grid color sequence of the first black and white grid picture is different from that of the second black and white grid picture. For example, for a black and white chessboard picture, the first black and white grid picture may be a row of black and white grid pictures displayed in the order of black grid / white grid / black grid / white grid, and the second black and white grid picture may be a row of black and white grid pictures displayed in the order of white grid / black grid / white grid / black grid. This is merely an example, and the embodiments of the present application are not limited thereto.

[0168] An embodiment of the present application provides a display device, which includes a display module as described in the aforementioned embodiment.

[0169] A display device provided in an embodiment of the present application can achieve the same technical effect as the display module in the aforementioned embodiment, and will not be described again here to avoid repetition.

[0170] The embodiment of the present application provides a display driving method for driving a display module as in the above embodiment, and the display driving method includes:

[0171] Step S1, when the display data is first picture data, the display driving circuit 20 drives the first sub-array 101 of the pixel array to display a picture corresponding to the first sub-data by using a first driving mode, and drives the second sub-array 102 of the pixel array to display a picture corresponding to the second sub-data, and, when the display data is second picture data, drives the pixel array to display a picture corresponding to the second picture data by using a second driving mode;

[0172] Among them, the first picture data includes at most the first sub-data and the second sub-data, and the first sub-data and the second sub-data are different data; in the first driving mode, the data charged into the pixel row is the first sub-data or the second sub-data, and in the second driving mode, the data charged into at least one pixel row is obtained based on the data charged into the adjacent pixel row.

[0173] Optionally, step S1 may include the following sub-steps:

[0174] In sub-step A1, the timing control circuit controls the gate driving circuit to send a row scanning signal to the scanning line corresponding to each pixel row in the first driving mode, so that each pixel row is turned on, each pixel row of the first sub-array 101 is charged with the first sub-data, and each pixel row of the second sub-array 102 is charged with the second sub-data.

[0175] Optionally, sub-step A1 includes the following sub-steps:

[0176] Sub-step B1: In the first driving mode, the timing control circuit controls the source driving circuit to send a data signal to the data line, so that the valid signal interval of the first sub-data corresponding to the first sub-array 101 covers the turn-on interval of multiple pixel rows in the first sub-array 101, and the valid signal interval of the second sub-data corresponding to the second sub-array 102 covers the turn-on interval of multiple pixel rows in the second sub-array 102.

[0177] Optionally, sub-step B1 includes the following sub-steps:

[0178] In the first driving mode, the timing control circuit controls multiple gate driving terminals of the gate driving circuit to send row scanning signals to the scanning lines corresponding to each pixel row in turn, so that the pixel array is turned on row by row along the column direction, and the turn-on intervals of different pixel rows do not overlap.

[0179] Optionally, the duration of the open interval of each pixel row in the first subarray 101 is equal to the row scanning duration, and the duration of the open interval of each pixel row in the second subarray 102 is equal to the row scanning duration;

[0180] The duration of the valid signal interval of the first sub-data corresponding to the first sub-array 101 is substantially equal to N times the row scanning duration, and the duration of the valid signal interval of the second sub-data corresponding to the second sub-array 102 is substantially equal to M times the row scanning duration; wherein N and M are positive integers respectively.

[0181] Optionally, sub-step B1 includes the following sub-steps:

[0182] In the first driving mode, the timing control circuit controls the multiple gate driving terminals of the gate driving circuit to sequentially send row scanning signals to the scanning lines corresponding to the first sub-array 101 and the scanning lines corresponding to the second sub-array 102, so that the multiple first sub-arrays 101 and the multiple second sub-arrays 102 are turned on one by one along the column direction, the multiple pixel rows in the first sub-array 101 are turned on at the same time, and the multiple pixel rows in the second sub-array 102 are turned on at the same time.

[0183] Optionally, the duration of the open interval of each pixel row in the first subarray 101 is equal to N times the row scanning duration, and the duration of the open interval of each pixel row in the second subarray 102 is equal to M times the row scanning duration;

[0184] The duration of the valid signal interval of the first sub-data corresponding to the first sub-array 101 is substantially equal to N times the row scanning duration, and the duration of the valid signal interval of the second sub-data corresponding to the second sub-array 102 is substantially equal to M times the row scanning duration; wherein N and M are positive integers respectively.

[0185] Optionally, step S1 may include the following sub-steps:

[0186] In sub-step A2, in the first driving mode, the timing control circuit controls the gate driving circuit to send row scanning signals to the scanning lines corresponding to the first pixel rows, so that each first pixel row is turned on, the first pixel row of the first sub-array 101 is charged with the first sub-data, and the first pixel row of the second sub-array 102 is charged with the second sub-data, or controls the gate driving circuit to send row scanning signals to the scanning lines corresponding to the second pixel rows, so that each second pixel row is turned on, the second pixel row of the first sub-array 101 is charged with the first sub-data, and the second pixel row of the second sub-array 102 is charged with the second sub-data.

[0187] Optionally, sub-step A2 may include the following sub-steps:

[0188] Sub-step B2: in the first driving mode, the timing control circuit controls the source driving circuit to send a data signal to the data line, so that the valid signal interval of the first sub-data corresponding to the first sub-array 101 covers the turn-on interval of the first pixel row in the first sub-array 101, and the valid signal interval of the second sub-data corresponding to the second sub-array 102 covers the turn-on interval of the first pixel row in the second sub-array 102, or the valid signal interval of the first sub-data corresponding to the first sub-array 101 covers the turn-on interval of the second pixel row in the first sub-array 101, and the valid signal interval of the second sub-data corresponding to the second sub-array 102 covers the turn-on interval of the second pixel row in the second sub-array 102.

[0189] Optionally, sub-step B2 may include the following sub-steps:

[0190] When in an odd frame, the timing control circuit controls the gate drive circuit in the first drive mode to send row scan signals to the scan lines corresponding to the first pixel rows, so that each first pixel row is turned on and each second pixel row is turned off for display;

[0191] In even frames, the timing control circuit controls the gate drive circuit in the first drive mode to send row scan signals to the scan lines corresponding to the second pixel rows, so that each second pixel row is turned on and each first pixel row is turned off.

[0192] Optionally, sub-step A2 may include the following sub-steps:

[0193] Sub-step B3, in the first driving mode, the timing control circuit controls multiple gate driving ends to send row scanning signals to the scanning lines corresponding to each first pixel row in turn, so that the first pixel rows are turned on row by row along the column direction, or controls multiple gate driving ends to send row scanning signals to the scanning lines corresponding to each second pixel row in turn, so that the second pixel rows are turned on row by row along the column direction.

[0194] Optionally, sub-step A2 may include the following sub-steps:

[0195] Sub-step B4, in the first driving mode, the timing control circuit sends a frame start signal to the first frame start signal line so that the gate driving unit corresponding to the first pixel row controls the first pixel row to turn on, or sends a frame start signal to the second frame start signal line so that the gate driving unit corresponding to the second pixel row controls the second pixel row to turn on.

[0196] Optionally, the first sub-data represents that the pixel row displays a black picture, and the second sub-data represents that the pixel row displays a white picture;

[0197] Alternatively, the first sub-data represents a pixel row displaying a first black and white grid picture, and the second sub-data represents a pixel row displaying a second black and white grid picture, wherein the first pixel in the pixel row displays black grids in the first black and white grid picture, and the first pixel in the pixel row displays white grids in the second black and white grid picture.

[0198] A display driving method provided in an embodiment of the present application can achieve the same technical effect as the display module in the aforementioned embodiment, and will not be described again here to avoid repetition.

[0199] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0200] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0201] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0202] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0203] The display module, display device and display driving method provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display module, characterized in that: The display module comprises: The display panel comprises a pixel array, wherein the pixel array comprises a plurality of first sub-arrays and a plurality of second sub-arrays, wherein the first sub-arrays and the second sub-arrays are arranged at intervals at least along a column direction; and the first sub-arrays and the second sub-arrays respectively comprise a plurality of pixel rows; a display driving circuit, electrically connected to the display panel, configured to, when the display data is first picture data, drive the first sub-array to display a picture corresponding to the first sub-data using a first driving mode, and drive the second sub-array to display a picture corresponding to the second sub-data, and, when the display data is second picture data, drive the pixel array to display a picture corresponding to the second picture data using a second driving mode; Among them, the first picture data includes at most the first sub-data and the second sub-data, and the first sub-data and the second sub-data are different data; in the first driving mode, the data charged into the pixel row is the first sub-data or the second sub-data, and in the second driving mode, the data charged into at least one of the pixel rows is obtained based on the data charged into the adjacent pixel rows.

2. The display module according to claim 1, characterized in that: The display driving circuit comprises a timing control circuit and a gate driving circuit, wherein the timing control circuit is electrically connected to the gate driving circuit; each pixel row of the pixel array is provided with at least one scanning line, wherein the gate driving circuit is electrically connected to the scanning line; The timing control circuit is configured to control the gate driving circuit to send a row scanning signal to the scanning line corresponding to each pixel row in the first driving mode, so that each pixel row is turned on, each pixel row of the first sub-array is charged with the first sub-data, and each pixel row of the second sub-array is charged with the second sub-data.

3. The display module according to claim 2, characterized in that: The display driving circuit further comprises a source driving circuit, and the timing control circuit is electrically connected to the source driving circuit; each pixel column of the pixel array is provided with at least one data line, and the source driving circuit is electrically connected to the data line; The timing control circuit is configured to control the source driving circuit to send a data signal to the data line in the first driving mode, so that the valid signal interval of the first sub-data corresponding to the first sub-array covers the turn-on interval of the multiple pixel rows in the first sub-array, and the valid signal interval of the second sub-data corresponding to the second sub-array covers the turn-on interval of the multiple pixel rows in the second sub-array.

4. The display module according to claim 3, characterized in that: The gate driving circuit comprises a plurality of gate driving terminals, each of which is electrically connected to the corresponding pixel row through the scanning line; The timing control circuit is configured to control the multiple gate driving ends of the gate driving circuit in the first driving mode, and send the row scanning signal to the scanning line corresponding to each pixel row in turn, so that the pixel array is turned on row by row along the column direction, and the turn-on intervals of different pixel rows do not overlap with each other.

5. The display module according to claim 4, characterized in that: The first sub-array includes N pixel rows; the second sub-array includes M pixel rows; The duration of the open interval of each pixel row in the first subarray is equal to the row scanning duration, and the duration of the open interval of each pixel row in the second subarray is equal to the row scanning duration; The duration of the valid signal interval of the first sub-data corresponding to the first sub-array is substantially equal to N times the row scanning duration, and the duration of the valid signal interval of the second sub-data corresponding to the second sub-array is substantially equal to M times the row scanning duration; wherein N and M are positive integers respectively.

6. The display module according to claim 3, characterized in that: The gate driving circuit comprises a plurality of gate driving terminals, each of which is electrically connected to the corresponding pixel row through the scanning line; The timing control circuit is configured to control the multiple gate driving terminals of the gate driving circuit in the first driving mode, and sequentially send the row scanning signals to the scanning lines corresponding to the first subarray and the scanning lines corresponding to the second subarray, so that the multiple first subarrays and the multiple second subarrays are turned on one by one along the column direction, the multiple pixel rows in the first subarray are turned on at the same time, and the multiple pixel rows in the second subarray are turned on at the same time.

7. The display module according to claim 6, characterized in that: The first sub-array includes N pixel rows; the second sub-array includes M pixel rows; The duration of the open interval of each pixel row in the first subarray is equal to N times the row scanning duration, and the duration of the open interval of each pixel row in the second subarray is equal to M times the row scanning duration; The duration of the valid signal interval of the first sub-data corresponding to the first sub-array is substantially equal to N times the row scanning duration, and the duration of the valid signal interval of the second sub-data corresponding to the second sub-array is substantially equal to M times the row scanning duration; wherein N and M are positive integers respectively.

8. The display module according to claim 1, characterized in that: The display driving circuit comprises a timing control circuit and a gate driving circuit, wherein the timing control circuit is electrically connected to the gate driving circuit; each pixel row of the pixel array is provided with at least one scanning line, wherein the gate driving circuit is electrically connected to the scanning line; The plurality of pixel rows include at least one first pixel row and at least one second pixel row; the first pixel row and the second pixel row are arranged at intervals along the column direction; The timing control circuit is configured to control the gate driving circuit to send row scanning signals to the scanning lines corresponding to the first pixel rows respectively in the first driving mode, so that each of the first pixel rows is turned on, the first pixel rows of the first sub-array are charged with the first sub-data, and the first pixel rows of the second sub-array are charged with the second sub-data, Alternatively, the gate driving circuit is controlled to send the row scanning signal to the scanning lines corresponding to the second pixel rows respectively, so that each second pixel row is turned on, the second pixel rows of the first sub-array are charged with the first sub-data, and the second pixel rows of the second sub-array are charged with the second sub-data.

9. The display module according to claim 8, characterized in that: The display driving circuit further comprises a source driving circuit, and the timing control circuit is electrically connected to the source driving circuit; each pixel column of the pixel array is provided with at least one data line, and the source driving circuit is electrically connected to the data line; The timing control circuit is configured to control the source driving circuit to send a data signal to the data line in the first driving mode, so that the valid signal interval of the first sub-data corresponding to the first sub-array covers the open interval of the first pixel row in the first sub-array, and the valid signal interval of the second sub-data corresponding to the second sub-array covers the open interval of the first pixel row in the second sub-array, Alternatively, the valid signal interval of the first sub-data corresponding to the first sub-array covers the on-interval of the second pixel row in the first sub-array, and the valid signal interval of the second sub-data corresponding to the second sub-array covers the on-interval of the second pixel row in the second sub-array.

10. The display module according to claim 9, characterized in that: The first pixel row is an odd-numbered row of the pixel array, and the second pixel row is an even-numbered row of the pixel array; the timing control circuit is configured as follows: In an odd frame, in the first driving mode, the gate driving circuit is controlled to send row scanning signals to the scanning lines corresponding to the first pixel rows respectively, so that each of the first pixel rows is turned on and each of the second pixel rows is turned off for display; In an even frame, under the first driving mode, the gate driving circuit is controlled to send the row scanning signal to the scanning lines corresponding to the second pixel rows respectively, so that each second pixel row is turned on and each first pixel row is turned off for display.

11. The display module according to claim 8, characterized in that: The gate driving circuit comprises a plurality of gate driving terminals, each of which is electrically connected to the corresponding pixel row through the scanning line; The timing control circuit is configured to control the multiple gate driving ends in the first driving mode to send the row scanning signal to the scanning line corresponding to each of the first pixel rows in turn, so that the first pixel rows are turned on row by row along the column direction, or to control the multiple gate driving ends to send the row scanning signal to the scanning line corresponding to each of the second pixel rows in turn, so that the second pixel rows are turned on row by row along the column direction.

12. The display module according to claim 8, characterized in that: The gate driving circuit includes a plurality of cascaded gate driving units, and the gate driving units are electrically connected to the scanning lines corresponding to the pixel rows; The display panel further comprises at least two frame start signal lines; the frame start signal lines are electrically connected to at least one of the gate driving units, and the frame start signal lines are also electrically connected to the timing control circuit; The at least two frame start signal lines include a first frame start signal line and a second frame start signal line; wherein the gate driving unit corresponding to the first pixel row is controlled by a frame start signal transmitted by the first frame start signal line, and the gate driving unit corresponding to the second pixel row is controlled by the frame start signal transmitted by the second frame start signal line; The timing control circuit is configured to, in the first driving mode, send the frame start signal to the first frame start signal line so that the gate driving unit corresponding to the first pixel row controls the first pixel row to turn on, or to send the frame start signal to the second frame start signal line so that the gate driving unit corresponding to the second pixel row controls the second pixel row to turn on.

13. The display module according to any one of claims 1 to 12, characterized in that: The first sub-data indicates that the pixel row displays a black picture, and the second sub-data indicates that the pixel row displays a white picture; Alternatively, the first sub-data represents that the pixel row displays a first black and white checkered picture, and the second sub-data represents that the pixel row displays a second black and white checkered picture, wherein in the first black and white checkered picture, the first pixel in the pixel row displays black checkered pictures, and in the second black and white checkered pictures, the first pixel in the pixel row displays white checkered pictures.

14. A display device, characterized in that: The display device comprises a display module as described in any one of claims 1-13.

15. A display driving method, characterized in that: Used to drive the display module as described in any one of claims 1 to 13, the display driving method comprising: The display driving circuit, when the display data is first picture data, drives the first sub-array of the pixel array to display a picture corresponding to the first sub-data by using a first driving mode, and drives the second sub-array of the pixel array to display a picture corresponding to the second sub-data, and, when the display data is second picture data, drives the pixel array to display a picture corresponding to the second picture data by using a second driving mode; Among them, the first picture data includes at most the first sub-data and the second sub-data, and the first sub-data and the second sub-data are different data; in the first driving mode, the data charged into the pixel row is the first sub-data or the second sub-data, and in the second driving mode, the data charged into at least one of the pixel rows is obtained based on the data charged into the adjacent pixel rows.

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